1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_CANXL_MSG_DESCRIPTORS.h 10 * @version 1.8 11 * @date 2022-07-13 12 * @brief Peripheral Access Layer for S32Z2_CANXL_MSG_DESCRIPTORS 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_CANXL_MSG_DESCRIPTORS_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_CANXL_MSG_DESCRIPTORS_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- CANXL_MSG_DESCRIPTORS Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup CANXL_MSG_DESCRIPTORS_Peripheral_Access_Layer CANXL_MSG_DESCRIPTORS Peripheral Access Layer 68 * @{ 69 */ 70 71 /** CANXL_MSG_DESCRIPTORS - Size of Registers Arrays */ 72 #define CANXL_MSG_DESCRIPTORS_MSGDSC_COUNT 128u 73 74 /** CANXL_MSG_DESCRIPTORS - Register Layout Typedef */ 75 typedef struct { 76 struct { /* offset: 0x0, array step: 0x20 */ 77 union { /* offset: 0x0, array step: 0x20 */ 78 __IO uint32_t RXCTRL; /**< Message Descriptor Control (In Rx Mode), array offset: 0x0, array step: 0x20 */ 79 } CTRL; 80 union { /* offset: 0x4, array step: 0x20 */ 81 __IO uint32_t MDFLT1FD; /**< Message Descriptor Filter Configuration 1 (In Rx Mode/In FD Mode), array offset: 0x4, array step: 0x20 */ 82 __IO uint32_t MDFLT1XL; /**< Message Descriptor Filter Configuration 1 (In Rx Mode/In XL Mode), array offset: 0x4, array step: 0x20 */ 83 } CFG1; 84 union { /* offset: 0x8, array step: 0x20 */ 85 __IO uint32_t MDFLT2FD; /**< Message Descriptor Filter Configuration 2 (In Rx Mode/In FD Mode), array offset: 0x8, array step: 0x20 */ 86 __IO uint32_t MDFLT2XL; /**< Message Descriptor Filter Configuration 2 (In Rx Mode/In XL Mode), array offset: 0x8, array step: 0x20 */ 87 } CFG2; 88 union { /* offset: 0xC, array step: 0x20 */ 89 __IO uint32_t RXLSTPTR; /**< Message List Pointer (In Rx Mode), array offset: 0xC, array step: 0x20 */ 90 __IO uint32_t TXLSTPTR; /**< Message List Pointer (In Tx Mode), array offset: 0xC, array step: 0x20 */ 91 } LSTPNT; 92 uint8_t RESERVED_0[16]; 93 } MSGDSC[CANXL_MSG_DESCRIPTORS_MSGDSC_COUNT]; 94 } CANXL_MSG_DESCRIPTORS_Type, *CANXL_MSG_DESCRIPTORS_MemMapPtr; 95 96 /** Number of instances of the CANXL_MSG_DESCRIPTORS module. */ 97 #define CANXL_MSG_DESCRIPTORS_INSTANCE_COUNT (2u) 98 99 /* CANXL_MSG_DESCRIPTORS - Peripheral instance base addresses */ 100 /** Peripheral CANXL_0__MSG_DESCRIPTORS base address */ 101 #define IP_CANXL_0__MSG_DESCRIPTORS_BASE (0x47420000u) 102 /** Peripheral CANXL_0__MSG_DESCRIPTORS base pointer */ 103 #define IP_CANXL_0__MSG_DESCRIPTORS ((CANXL_MSG_DESCRIPTORS_Type *)IP_CANXL_0__MSG_DESCRIPTORS_BASE) 104 /** Peripheral CANXL_1__MSG_DESCRIPTORS base address */ 105 #define IP_CANXL_1__MSG_DESCRIPTORS_BASE (0x47520000u) 106 /** Peripheral CANXL_1__MSG_DESCRIPTORS base pointer */ 107 #define IP_CANXL_1__MSG_DESCRIPTORS ((CANXL_MSG_DESCRIPTORS_Type *)IP_CANXL_1__MSG_DESCRIPTORS_BASE) 108 /** Array initializer of CANXL_MSG_DESCRIPTORS peripheral base addresses */ 109 #define IP_CANXL_MSG_DESCRIPTORS_BASE_ADDRS { IP_CANXL_0__MSG_DESCRIPTORS_BASE, IP_CANXL_1__MSG_DESCRIPTORS_BASE } 110 /** Array initializer of CANXL_MSG_DESCRIPTORS peripheral base pointers */ 111 #define IP_CANXL_MSG_DESCRIPTORS_BASE_PTRS { IP_CANXL_0__MSG_DESCRIPTORS, IP_CANXL_1__MSG_DESCRIPTORS } 112 113 /* ---------------------------------------------------------------------------- 114 -- CANXL_MSG_DESCRIPTORS Register Masks 115 ---------------------------------------------------------------------------- */ 116 117 /*! 118 * @addtogroup CANXL_MSG_DESCRIPTORS_Register_Masks CANXL_MSG_DESCRIPTORS Register Masks 119 * @{ 120 */ 121 122 /*! @name RXCTRL - Message Descriptor Control (In Rx Mode) */ 123 /*! @{ */ 124 125 #define CANXL_MSG_DESCRIPTORS_RXCTRL_MBSIZE_MASK (0x7FF00U) 126 #define CANXL_MSG_DESCRIPTORS_RXCTRL_MBSIZE_SHIFT (8U) 127 #define CANXL_MSG_DESCRIPTORS_RXCTRL_MBSIZE_WIDTH (11U) 128 #define CANXL_MSG_DESCRIPTORS_RXCTRL_MBSIZE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_RXCTRL_MBSIZE_SHIFT)) & CANXL_MSG_DESCRIPTORS_RXCTRL_MBSIZE_MASK) 129 130 #define CANXL_MSG_DESCRIPTORS_RXCTRL_ADDRROA_MASK (0x100000U) 131 #define CANXL_MSG_DESCRIPTORS_RXCTRL_ADDRROA_SHIFT (20U) 132 #define CANXL_MSG_DESCRIPTORS_RXCTRL_ADDRROA_WIDTH (1U) 133 #define CANXL_MSG_DESCRIPTORS_RXCTRL_ADDRROA(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_RXCTRL_ADDRROA_SHIFT)) & CANXL_MSG_DESCRIPTORS_RXCTRL_ADDRROA_MASK) 134 135 #define CANXL_MSG_DESCRIPTORS_RXCTRL_SDUROA_MASK (0x200000U) 136 #define CANXL_MSG_DESCRIPTORS_RXCTRL_SDUROA_SHIFT (21U) 137 #define CANXL_MSG_DESCRIPTORS_RXCTRL_SDUROA_WIDTH (1U) 138 #define CANXL_MSG_DESCRIPTORS_RXCTRL_SDUROA(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_RXCTRL_SDUROA_SHIFT)) & CANXL_MSG_DESCRIPTORS_RXCTRL_SDUROA_MASK) 139 140 #define CANXL_MSG_DESCRIPTORS_RXCTRL_VCANROA_MASK (0x400000U) 141 #define CANXL_MSG_DESCRIPTORS_RXCTRL_VCANROA_SHIFT (22U) 142 #define CANXL_MSG_DESCRIPTORS_RXCTRL_VCANROA_WIDTH (1U) 143 #define CANXL_MSG_DESCRIPTORS_RXCTRL_VCANROA(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_RXCTRL_VCANROA_SHIFT)) & CANXL_MSG_DESCRIPTORS_RXCTRL_VCANROA_MASK) 144 145 #define CANXL_MSG_DESCRIPTORS_RXCTRL_KEEPLST_MASK (0x1000000U) 146 #define CANXL_MSG_DESCRIPTORS_RXCTRL_KEEPLST_SHIFT (24U) 147 #define CANXL_MSG_DESCRIPTORS_RXCTRL_KEEPLST_WIDTH (1U) 148 #define CANXL_MSG_DESCRIPTORS_RXCTRL_KEEPLST(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_RXCTRL_KEEPLST_SHIFT)) & CANXL_MSG_DESCRIPTORS_RXCTRL_KEEPLST_MASK) 149 150 #define CANXL_MSG_DESCRIPTORS_RXCTRL_RXFDFRM_MASK (0x20000000U) 151 #define CANXL_MSG_DESCRIPTORS_RXCTRL_RXFDFRM_SHIFT (29U) 152 #define CANXL_MSG_DESCRIPTORS_RXCTRL_RXFDFRM_WIDTH (1U) 153 #define CANXL_MSG_DESCRIPTORS_RXCTRL_RXFDFRM(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_RXCTRL_RXFDFRM_SHIFT)) & CANXL_MSG_DESCRIPTORS_RXCTRL_RXFDFRM_MASK) 154 155 #define CANXL_MSG_DESCRIPTORS_RXCTRL_RXXLFRM_MASK (0x40000000U) 156 #define CANXL_MSG_DESCRIPTORS_RXCTRL_RXXLFRM_SHIFT (30U) 157 #define CANXL_MSG_DESCRIPTORS_RXCTRL_RXXLFRM_WIDTH (1U) 158 #define CANXL_MSG_DESCRIPTORS_RXCTRL_RXXLFRM(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_RXCTRL_RXXLFRM_SHIFT)) & CANXL_MSG_DESCRIPTORS_RXCTRL_RXXLFRM_MASK) 159 160 #define CANXL_MSG_DESCRIPTORS_RXCTRL_MODE_MASK (0x80000000U) 161 #define CANXL_MSG_DESCRIPTORS_RXCTRL_MODE_SHIFT (31U) 162 #define CANXL_MSG_DESCRIPTORS_RXCTRL_MODE_WIDTH (1U) 163 #define CANXL_MSG_DESCRIPTORS_RXCTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_RXCTRL_MODE_SHIFT)) & CANXL_MSG_DESCRIPTORS_RXCTRL_MODE_MASK) 164 /*! @} */ 165 166 /*! @name MDFLT1FD - Message Descriptor Filter Configuration 1 (In Rx Mode/In FD Mode) */ 167 /*! @{ */ 168 169 #define CANXL_MSG_DESCRIPTORS_MDFLT1FD_IDEXTa_L_MASK (0x3FFFFU) 170 #define CANXL_MSG_DESCRIPTORS_MDFLT1FD_IDEXTa_L_SHIFT (0U) 171 #define CANXL_MSG_DESCRIPTORS_MDFLT1FD_IDEXTa_L_WIDTH (18U) 172 #define CANXL_MSG_DESCRIPTORS_MDFLT1FD_IDEXTa_L(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_MDFLT1FD_IDEXTa_L_SHIFT)) & CANXL_MSG_DESCRIPTORS_MDFLT1FD_IDEXTa_L_MASK) 173 174 #define CANXL_MSG_DESCRIPTORS_MDFLT1FD_IDSTDa_L_MASK (0x1FFC0000U) 175 #define CANXL_MSG_DESCRIPTORS_MDFLT1FD_IDSTDa_L_SHIFT (18U) 176 #define CANXL_MSG_DESCRIPTORS_MDFLT1FD_IDSTDa_L_WIDTH (11U) 177 #define CANXL_MSG_DESCRIPTORS_MDFLT1FD_IDSTDa_L(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_MDFLT1FD_IDSTDa_L_SHIFT)) & CANXL_MSG_DESCRIPTORS_MDFLT1FD_IDSTDa_L_MASK) 178 179 #define CANXL_MSG_DESCRIPTORS_MDFLT1FD_MSKRNG_MASK (0x20000000U) 180 #define CANXL_MSG_DESCRIPTORS_MDFLT1FD_MSKRNG_SHIFT (29U) 181 #define CANXL_MSG_DESCRIPTORS_MDFLT1FD_MSKRNG_WIDTH (1U) 182 #define CANXL_MSG_DESCRIPTORS_MDFLT1FD_MSKRNG(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_MDFLT1FD_MSKRNG_SHIFT)) & CANXL_MSG_DESCRIPTORS_MDFLT1FD_MSKRNG_MASK) 183 184 #define CANXL_MSG_DESCRIPTORS_MDFLT1FD_IDEMSK_MASK (0x40000000U) 185 #define CANXL_MSG_DESCRIPTORS_MDFLT1FD_IDEMSK_SHIFT (30U) 186 #define CANXL_MSG_DESCRIPTORS_MDFLT1FD_IDEMSK_WIDTH (1U) 187 #define CANXL_MSG_DESCRIPTORS_MDFLT1FD_IDEMSK(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_MDFLT1FD_IDEMSK_SHIFT)) & CANXL_MSG_DESCRIPTORS_MDFLT1FD_IDEMSK_MASK) 188 189 #define CANXL_MSG_DESCRIPTORS_MDFLT1FD_RTRMSK_MASK (0x80000000U) 190 #define CANXL_MSG_DESCRIPTORS_MDFLT1FD_RTRMSK_SHIFT (31U) 191 #define CANXL_MSG_DESCRIPTORS_MDFLT1FD_RTRMSK_WIDTH (1U) 192 #define CANXL_MSG_DESCRIPTORS_MDFLT1FD_RTRMSK(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_MDFLT1FD_RTRMSK_SHIFT)) & CANXL_MSG_DESCRIPTORS_MDFLT1FD_RTRMSK_MASK) 193 /*! @} */ 194 195 /*! @name MDFLT1XL - Message Descriptor Filter Configuration 1 (In Rx Mode/In XL Mode) */ 196 /*! @{ */ 197 198 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_ACCPT_VCAN_MASK (0x1FU) 199 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_ACCPT_VCAN_SHIFT (0U) 200 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_ACCPT_VCAN_WIDTH (5U) 201 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_ACCPT_VCAN(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_MDFLT1XL_ACCPT_VCAN_SHIFT)) & CANXL_MSG_DESCRIPTORS_MDFLT1XL_ACCPT_VCAN_MASK) 202 203 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_ACCPT_SDU_MASK (0x3E0U) 204 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_ACCPT_SDU_SHIFT (5U) 205 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_ACCPT_SDU_WIDTH (5U) 206 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_ACCPT_SDU(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_MDFLT1XL_ACCPT_SDU_SHIFT)) & CANXL_MSG_DESCRIPTORS_MDFLT1XL_ACCPT_SDU_MASK) 207 208 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_ACCPT_ADDR_MASK (0x7C00U) 209 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_ACCPT_ADDR_SHIFT (10U) 210 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_ACCPT_ADDR_WIDTH (5U) 211 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_ACCPT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_MDFLT1XL_ACCPT_ADDR_SHIFT)) & CANXL_MSG_DESCRIPTORS_MDFLT1XL_ACCPT_ADDR_MASK) 212 213 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_FBSEL_MASK (0x10000U) 214 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_FBSEL_SHIFT (16U) 215 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_FBSEL_WIDTH (1U) 216 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_FBSEL(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_MDFLT1XL_FBSEL_SHIFT)) & CANXL_MSG_DESCRIPTORS_MDFLT1XL_FBSEL_MASK) 217 218 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_SECMSK_MASK (0x20000U) 219 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_SECMSK_SHIFT (17U) 220 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_SECMSK_WIDTH (1U) 221 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_SECMSK(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_MDFLT1XL_SECMSK_SHIFT)) & CANXL_MSG_DESCRIPTORS_MDFLT1XL_SECMSK_MASK) 222 223 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_IDSTDa_L_MASK (0x1FFC0000U) 224 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_IDSTDa_L_SHIFT (18U) 225 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_IDSTDa_L_WIDTH (11U) 226 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_IDSTDa_L(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_MDFLT1XL_IDSTDa_L_SHIFT)) & CANXL_MSG_DESCRIPTORS_MDFLT1XL_IDSTDa_L_MASK) 227 228 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_MSKRNG_MASK (0x20000000U) 229 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_MSKRNG_SHIFT (29U) 230 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_MSKRNG_WIDTH (1U) 231 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_MSKRNG(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_MDFLT1XL_MSKRNG_SHIFT)) & CANXL_MSG_DESCRIPTORS_MDFLT1XL_MSKRNG_MASK) 232 233 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_IDEMSK_MASK (0x40000000U) 234 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_IDEMSK_SHIFT (30U) 235 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_IDEMSK_WIDTH (1U) 236 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_IDEMSK(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_MDFLT1XL_IDEMSK_SHIFT)) & CANXL_MSG_DESCRIPTORS_MDFLT1XL_IDEMSK_MASK) 237 238 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_RRSMSK_MASK (0x80000000U) 239 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_RRSMSK_SHIFT (31U) 240 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_RRSMSK_WIDTH (1U) 241 #define CANXL_MSG_DESCRIPTORS_MDFLT1XL_RRSMSK(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_MDFLT1XL_RRSMSK_SHIFT)) & CANXL_MSG_DESCRIPTORS_MDFLT1XL_RRSMSK_MASK) 242 /*! @} */ 243 244 /*! @name MDFLT2FD - Message Descriptor Filter Configuration 2 (In Rx Mode/In FD Mode) */ 245 /*! @{ */ 246 247 #define CANXL_MSG_DESCRIPTORS_MDFLT2FD_IDEXTa_H_MASK (0x3FFFFU) 248 #define CANXL_MSG_DESCRIPTORS_MDFLT2FD_IDEXTa_H_SHIFT (0U) 249 #define CANXL_MSG_DESCRIPTORS_MDFLT2FD_IDEXTa_H_WIDTH (18U) 250 #define CANXL_MSG_DESCRIPTORS_MDFLT2FD_IDEXTa_H(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_MDFLT2FD_IDEXTa_H_SHIFT)) & CANXL_MSG_DESCRIPTORS_MDFLT2FD_IDEXTa_H_MASK) 251 252 #define CANXL_MSG_DESCRIPTORS_MDFLT2FD_IDSTDa_H_MASK (0x1FFC0000U) 253 #define CANXL_MSG_DESCRIPTORS_MDFLT2FD_IDSTDa_H_SHIFT (18U) 254 #define CANXL_MSG_DESCRIPTORS_MDFLT2FD_IDSTDa_H_WIDTH (11U) 255 #define CANXL_MSG_DESCRIPTORS_MDFLT2FD_IDSTDa_H(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_MDFLT2FD_IDSTDa_H_SHIFT)) & CANXL_MSG_DESCRIPTORS_MDFLT2FD_IDSTDa_H_MASK) 256 257 #define CANXL_MSG_DESCRIPTORS_MDFLT2FD_IDE_MASK (0x40000000U) 258 #define CANXL_MSG_DESCRIPTORS_MDFLT2FD_IDE_SHIFT (30U) 259 #define CANXL_MSG_DESCRIPTORS_MDFLT2FD_IDE_WIDTH (1U) 260 #define CANXL_MSG_DESCRIPTORS_MDFLT2FD_IDE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_MDFLT2FD_IDE_SHIFT)) & CANXL_MSG_DESCRIPTORS_MDFLT2FD_IDE_MASK) 261 262 #define CANXL_MSG_DESCRIPTORS_MDFLT2FD_RTR_MASK (0x80000000U) 263 #define CANXL_MSG_DESCRIPTORS_MDFLT2FD_RTR_SHIFT (31U) 264 #define CANXL_MSG_DESCRIPTORS_MDFLT2FD_RTR_WIDTH (1U) 265 #define CANXL_MSG_DESCRIPTORS_MDFLT2FD_RTR(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_MDFLT2FD_RTR_SHIFT)) & CANXL_MSG_DESCRIPTORS_MDFLT2FD_RTR_MASK) 266 /*! @} */ 267 268 /*! @name MDFLT2XL - Message Descriptor Filter Configuration 2 (In Rx Mode/In XL Mode) */ 269 /*! @{ */ 270 271 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_RJCT_VCAN_MASK (0x1FU) 272 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_RJCT_VCAN_SHIFT (0U) 273 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_RJCT_VCAN_WIDTH (5U) 274 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_RJCT_VCAN(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_MDFLT2XL_RJCT_VCAN_SHIFT)) & CANXL_MSG_DESCRIPTORS_MDFLT2XL_RJCT_VCAN_MASK) 275 276 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_RJCT_SDU_MASK (0x3E0U) 277 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_RJCT_SDU_SHIFT (5U) 278 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_RJCT_SDU_WIDTH (5U) 279 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_RJCT_SDU(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_MDFLT2XL_RJCT_SDU_SHIFT)) & CANXL_MSG_DESCRIPTORS_MDFLT2XL_RJCT_SDU_MASK) 280 281 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_RJCT_ADDR_MASK (0x7C00U) 282 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_RJCT_ADDR_SHIFT (10U) 283 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_RJCT_ADDR_WIDTH (5U) 284 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_RJCT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_MDFLT2XL_RJCT_ADDR_SHIFT)) & CANXL_MSG_DESCRIPTORS_MDFLT2XL_RJCT_ADDR_MASK) 285 286 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_SEC_MASK (0x20000U) 287 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_SEC_SHIFT (17U) 288 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_SEC_WIDTH (1U) 289 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_SEC(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_MDFLT2XL_SEC_SHIFT)) & CANXL_MSG_DESCRIPTORS_MDFLT2XL_SEC_MASK) 290 291 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_IDSTDa_H_MASK (0x1FFC0000U) 292 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_IDSTDa_H_SHIFT (18U) 293 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_IDSTDa_H_WIDTH (11U) 294 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_IDSTDa_H(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_MDFLT2XL_IDSTDa_H_SHIFT)) & CANXL_MSG_DESCRIPTORS_MDFLT2XL_IDSTDa_H_MASK) 295 296 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_IDE_MASK (0x40000000U) 297 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_IDE_SHIFT (30U) 298 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_IDE_WIDTH (1U) 299 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_IDE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_MDFLT2XL_IDE_SHIFT)) & CANXL_MSG_DESCRIPTORS_MDFLT2XL_IDE_MASK) 300 301 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_RRS_MASK (0x80000000U) 302 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_RRS_SHIFT (31U) 303 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_RRS_WIDTH (1U) 304 #define CANXL_MSG_DESCRIPTORS_MDFLT2XL_RRS(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_MDFLT2XL_RRS_SHIFT)) & CANXL_MSG_DESCRIPTORS_MDFLT2XL_RRS_MASK) 305 /*! @} */ 306 307 /*! @name RXLSTPTR - Message List Pointer (In Rx Mode) */ 308 /*! @{ */ 309 310 #define CANXL_MSG_DESCRIPTORS_RXLSTPTR_RXLST_POINTER_MASK (0xFFFFFFFFU) 311 #define CANXL_MSG_DESCRIPTORS_RXLSTPTR_RXLST_POINTER_SHIFT (0U) 312 #define CANXL_MSG_DESCRIPTORS_RXLSTPTR_RXLST_POINTER_WIDTH (32U) 313 #define CANXL_MSG_DESCRIPTORS_RXLSTPTR_RXLST_POINTER(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_RXLSTPTR_RXLST_POINTER_SHIFT)) & CANXL_MSG_DESCRIPTORS_RXLSTPTR_RXLST_POINTER_MASK) 314 /*! @} */ 315 316 /*! @name TXLSTPTR - Message List Pointer (In Tx Mode) */ 317 /*! @{ */ 318 319 #define CANXL_MSG_DESCRIPTORS_TXLSTPTR_TXLST_POINTER_MASK (0xFFFFFFFFU) 320 #define CANXL_MSG_DESCRIPTORS_TXLSTPTR_TXLST_POINTER_SHIFT (0U) 321 #define CANXL_MSG_DESCRIPTORS_TXLSTPTR_TXLST_POINTER_WIDTH (32U) 322 #define CANXL_MSG_DESCRIPTORS_TXLSTPTR_TXLST_POINTER(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MSG_DESCRIPTORS_TXLSTPTR_TXLST_POINTER_SHIFT)) & CANXL_MSG_DESCRIPTORS_TXLSTPTR_TXLST_POINTER_MASK) 323 /*! @} */ 324 325 /*! 326 * @} 327 */ /* end of group CANXL_MSG_DESCRIPTORS_Register_Masks */ 328 329 /*! 330 * @} 331 */ /* end of group CANXL_MSG_DESCRIPTORS_Peripheral_Access_Layer */ 332 333 #endif /* #if !defined(S32Z2_CANXL_MSG_DESCRIPTORS_H_) */ 334
