1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_CANXL_MRU.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_CANXL_MRU 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_CANXL_MRU_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_CANXL_MRU_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- CANXL_MRU Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup CANXL_MRU_Peripheral_Access_Layer CANXL_MRU Peripheral Access Layer 68 * @{ 69 */ 70 71 /** CANXL_MRU - Size of Registers Arrays */ 72 #define CANXL_MRU_CHXCONFIG_COUNT 1u 73 #define CANXL_MRU_NOTIFY_COUNT 2u 74 75 /** CANXL_MRU - Register Layout Typedef */ 76 typedef struct { 77 struct { /* offset: 0x0, array step: 0xC */ 78 __IO uint32_t CH_CFG0; /**< Channel (x) Configuration 0, array offset: 0x0, array step: 0xC */ 79 __IO uint32_t CH_CFG1; /**< Channel (x) Configuration 1, array offset: 0x4, array step: 0xC */ 80 __IO uint32_t CH_MBSTAT; /**< Channel (x) Mailbox Status, array offset: 0x8, array step: 0xC */ 81 } CHXCONFIG[CANXL_MRU_CHXCONFIG_COUNT]; 82 uint8_t RESERVED_0[500]; 83 __I uint32_t NOTIFY[CANXL_MRU_NOTIFY_COUNT]; /**< Notification 0 Status..Notification 1 Status, array offset: 0x200, array step: 0x4 */ 84 uint8_t RESERVED_1[3576]; 85 __IO uint32_t CH1_MB0; /**< Channel (x) Mailbox (n), offset: 0x1000 */ 86 __IO uint32_t CH1_MB1; /**< Channel (x) Mailbox (n), offset: 0x1004 */ 87 __IO uint32_t CH1_MB2; /**< Channel (x) Mailbox (n), offset: 0x1008 */ 88 __IO uint32_t CH1_MB3; /**< Channel (x) Mailbox (n), offset: 0x100C */ 89 } CANXL_MRU_Type, *CANXL_MRU_MemMapPtr; 90 91 /** Number of instances of the CANXL_MRU module. */ 92 #define CANXL_MRU_INSTANCE_COUNT (2u) 93 94 /* CANXL_MRU - Peripheral instance base addresses */ 95 /** Peripheral CANXL_0__MRU base address */ 96 #define IP_CANXL_0__MRU_BASE (0x47427000u) 97 /** Peripheral CANXL_0__MRU base pointer */ 98 #define IP_CANXL_0__MRU ((CANXL_MRU_Type *)IP_CANXL_0__MRU_BASE) 99 /** Peripheral CANXL_1__MRU base address */ 100 #define IP_CANXL_1__MRU_BASE (0x47527000u) 101 /** Peripheral CANXL_1__MRU base pointer */ 102 #define IP_CANXL_1__MRU ((CANXL_MRU_Type *)IP_CANXL_1__MRU_BASE) 103 /** Array initializer of CANXL_MRU peripheral base addresses */ 104 #define IP_CANXL_MRU_BASE_ADDRS { IP_CANXL_0__MRU_BASE, IP_CANXL_1__MRU_BASE } 105 /** Array initializer of CANXL_MRU peripheral base pointers */ 106 #define IP_CANXL_MRU_BASE_PTRS { IP_CANXL_0__MRU, IP_CANXL_1__MRU } 107 108 /* ---------------------------------------------------------------------------- 109 -- CANXL_MRU Register Masks 110 ---------------------------------------------------------------------------- */ 111 112 /*! 113 * @addtogroup CANXL_MRU_Register_Masks CANXL_MRU Register Masks 114 * @{ 115 */ 116 117 /*! @name CH_CFG0 - Channel (x) Configuration 0 */ 118 /*! @{ */ 119 120 #define CANXL_MRU_CH_CFG0_CHE_MASK (0x1U) 121 #define CANXL_MRU_CH_CFG0_CHE_SHIFT (0U) 122 #define CANXL_MRU_CH_CFG0_CHE_WIDTH (1U) 123 #define CANXL_MRU_CH_CFG0_CHE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MRU_CH_CFG0_CHE_SHIFT)) & CANXL_MRU_CH_CFG0_CHE_MASK) 124 125 #define CANXL_MRU_CH_CFG0_CHR_MASK (0x2U) 126 #define CANXL_MRU_CH_CFG0_CHR_SHIFT (1U) 127 #define CANXL_MRU_CH_CFG0_CHR_WIDTH (1U) 128 #define CANXL_MRU_CH_CFG0_CHR(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MRU_CH_CFG0_CHR_SHIFT)) & CANXL_MRU_CH_CFG0_CHR_MASK) 129 130 #define CANXL_MRU_CH_CFG0_IE_MASK (0x4U) 131 #define CANXL_MRU_CH_CFG0_IE_SHIFT (2U) 132 #define CANXL_MRU_CH_CFG0_IE_WIDTH (1U) 133 #define CANXL_MRU_CH_CFG0_IE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MRU_CH_CFG0_IE_SHIFT)) & CANXL_MRU_CH_CFG0_IE_MASK) 134 135 #define CANXL_MRU_CH_CFG0_MBE0_MASK (0x10000U) 136 #define CANXL_MRU_CH_CFG0_MBE0_SHIFT (16U) 137 #define CANXL_MRU_CH_CFG0_MBE0_WIDTH (1U) 138 #define CANXL_MRU_CH_CFG0_MBE0(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MRU_CH_CFG0_MBE0_SHIFT)) & CANXL_MRU_CH_CFG0_MBE0_MASK) 139 140 #define CANXL_MRU_CH_CFG0_MBE1_MASK (0x20000U) 141 #define CANXL_MRU_CH_CFG0_MBE1_SHIFT (17U) 142 #define CANXL_MRU_CH_CFG0_MBE1_WIDTH (1U) 143 #define CANXL_MRU_CH_CFG0_MBE1(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MRU_CH_CFG0_MBE1_SHIFT)) & CANXL_MRU_CH_CFG0_MBE1_MASK) 144 145 #define CANXL_MRU_CH_CFG0_MBE2_MASK (0x40000U) 146 #define CANXL_MRU_CH_CFG0_MBE2_SHIFT (18U) 147 #define CANXL_MRU_CH_CFG0_MBE2_WIDTH (1U) 148 #define CANXL_MRU_CH_CFG0_MBE2(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MRU_CH_CFG0_MBE2_SHIFT)) & CANXL_MRU_CH_CFG0_MBE2_MASK) 149 150 #define CANXL_MRU_CH_CFG0_MBE3_MASK (0x80000U) 151 #define CANXL_MRU_CH_CFG0_MBE3_SHIFT (19U) 152 #define CANXL_MRU_CH_CFG0_MBE3_WIDTH (1U) 153 #define CANXL_MRU_CH_CFG0_MBE3(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MRU_CH_CFG0_MBE3_SHIFT)) & CANXL_MRU_CH_CFG0_MBE3_MASK) 154 /*! @} */ 155 156 /*! @name CH_CFG1 - Channel (x) Configuration 1 */ 157 /*! @{ */ 158 159 #define CANXL_MRU_CH_CFG1_MBIC0_MASK (0x10000U) 160 #define CANXL_MRU_CH_CFG1_MBIC0_SHIFT (16U) 161 #define CANXL_MRU_CH_CFG1_MBIC0_WIDTH (1U) 162 #define CANXL_MRU_CH_CFG1_MBIC0(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MRU_CH_CFG1_MBIC0_SHIFT)) & CANXL_MRU_CH_CFG1_MBIC0_MASK) 163 164 #define CANXL_MRU_CH_CFG1_MBIC1_MASK (0x20000U) 165 #define CANXL_MRU_CH_CFG1_MBIC1_SHIFT (17U) 166 #define CANXL_MRU_CH_CFG1_MBIC1_WIDTH (1U) 167 #define CANXL_MRU_CH_CFG1_MBIC1(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MRU_CH_CFG1_MBIC1_SHIFT)) & CANXL_MRU_CH_CFG1_MBIC1_MASK) 168 169 #define CANXL_MRU_CH_CFG1_MBIC2_MASK (0x40000U) 170 #define CANXL_MRU_CH_CFG1_MBIC2_SHIFT (18U) 171 #define CANXL_MRU_CH_CFG1_MBIC2_WIDTH (1U) 172 #define CANXL_MRU_CH_CFG1_MBIC2(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MRU_CH_CFG1_MBIC2_SHIFT)) & CANXL_MRU_CH_CFG1_MBIC2_MASK) 173 174 #define CANXL_MRU_CH_CFG1_MBIC3_MASK (0x80000U) 175 #define CANXL_MRU_CH_CFG1_MBIC3_SHIFT (19U) 176 #define CANXL_MRU_CH_CFG1_MBIC3_WIDTH (1U) 177 #define CANXL_MRU_CH_CFG1_MBIC3(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MRU_CH_CFG1_MBIC3_SHIFT)) & CANXL_MRU_CH_CFG1_MBIC3_MASK) 178 /*! @} */ 179 180 /*! @name CH_MBSTAT - Channel (x) Mailbox Status */ 181 /*! @{ */ 182 183 #define CANXL_MRU_CH_MBSTAT_MBS0_MASK (0x10000U) 184 #define CANXL_MRU_CH_MBSTAT_MBS0_SHIFT (16U) 185 #define CANXL_MRU_CH_MBSTAT_MBS0_WIDTH (1U) 186 #define CANXL_MRU_CH_MBSTAT_MBS0(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MRU_CH_MBSTAT_MBS0_SHIFT)) & CANXL_MRU_CH_MBSTAT_MBS0_MASK) 187 188 #define CANXL_MRU_CH_MBSTAT_MBS1_MASK (0x20000U) 189 #define CANXL_MRU_CH_MBSTAT_MBS1_SHIFT (17U) 190 #define CANXL_MRU_CH_MBSTAT_MBS1_WIDTH (1U) 191 #define CANXL_MRU_CH_MBSTAT_MBS1(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MRU_CH_MBSTAT_MBS1_SHIFT)) & CANXL_MRU_CH_MBSTAT_MBS1_MASK) 192 193 #define CANXL_MRU_CH_MBSTAT_MBS2_MASK (0x40000U) 194 #define CANXL_MRU_CH_MBSTAT_MBS2_SHIFT (18U) 195 #define CANXL_MRU_CH_MBSTAT_MBS2_WIDTH (1U) 196 #define CANXL_MRU_CH_MBSTAT_MBS2(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MRU_CH_MBSTAT_MBS2_SHIFT)) & CANXL_MRU_CH_MBSTAT_MBS2_MASK) 197 198 #define CANXL_MRU_CH_MBSTAT_MBS3_MASK (0x80000U) 199 #define CANXL_MRU_CH_MBSTAT_MBS3_SHIFT (19U) 200 #define CANXL_MRU_CH_MBSTAT_MBS3_WIDTH (1U) 201 #define CANXL_MRU_CH_MBSTAT_MBS3(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MRU_CH_MBSTAT_MBS3_SHIFT)) & CANXL_MRU_CH_MBSTAT_MBS3_MASK) 202 /*! @} */ 203 204 /*! @name NOTIFY - Notification 0 Status..Notification 1 Status */ 205 /*! @{ */ 206 207 #define CANXL_MRU_NOTIFY_CH1_IS0_MASK (0x1U) 208 #define CANXL_MRU_NOTIFY_CH1_IS0_SHIFT (0U) 209 #define CANXL_MRU_NOTIFY_CH1_IS0_WIDTH (1U) 210 #define CANXL_MRU_NOTIFY_CH1_IS0(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MRU_NOTIFY_CH1_IS0_SHIFT)) & CANXL_MRU_NOTIFY_CH1_IS0_MASK) 211 212 #define CANXL_MRU_NOTIFY_CH1_IS1_MASK (0x1U) 213 #define CANXL_MRU_NOTIFY_CH1_IS1_SHIFT (0U) 214 #define CANXL_MRU_NOTIFY_CH1_IS1_WIDTH (1U) 215 #define CANXL_MRU_NOTIFY_CH1_IS1(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MRU_NOTIFY_CH1_IS1_SHIFT)) & CANXL_MRU_NOTIFY_CH1_IS1_MASK) 216 /*! @} */ 217 218 /*! @name CH1_MB0 - Channel (x) Mailbox (n) */ 219 /*! @{ */ 220 221 #define CANXL_MRU_CH1_MB0_MBD_MASK (0xFFFFFFFFU) 222 #define CANXL_MRU_CH1_MB0_MBD_SHIFT (0U) 223 #define CANXL_MRU_CH1_MB0_MBD_WIDTH (32U) 224 #define CANXL_MRU_CH1_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MRU_CH1_MB0_MBD_SHIFT)) & CANXL_MRU_CH1_MB0_MBD_MASK) 225 /*! @} */ 226 227 /*! @name CH1_MB1 - Channel (x) Mailbox (n) */ 228 /*! @{ */ 229 230 #define CANXL_MRU_CH1_MB1_MBD_MASK (0xFFFFFFFFU) 231 #define CANXL_MRU_CH1_MB1_MBD_SHIFT (0U) 232 #define CANXL_MRU_CH1_MB1_MBD_WIDTH (32U) 233 #define CANXL_MRU_CH1_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MRU_CH1_MB1_MBD_SHIFT)) & CANXL_MRU_CH1_MB1_MBD_MASK) 234 /*! @} */ 235 236 /*! @name CH1_MB2 - Channel (x) Mailbox (n) */ 237 /*! @{ */ 238 239 #define CANXL_MRU_CH1_MB2_MBD_MASK (0xFFFFFFFFU) 240 #define CANXL_MRU_CH1_MB2_MBD_SHIFT (0U) 241 #define CANXL_MRU_CH1_MB2_MBD_WIDTH (32U) 242 #define CANXL_MRU_CH1_MB2_MBD(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MRU_CH1_MB2_MBD_SHIFT)) & CANXL_MRU_CH1_MB2_MBD_MASK) 243 /*! @} */ 244 245 /*! @name CH1_MB3 - Channel (x) Mailbox (n) */ 246 /*! @{ */ 247 248 #define CANXL_MRU_CH1_MB3_MBD_MASK (0xFFFFFFFFU) 249 #define CANXL_MRU_CH1_MB3_MBD_SHIFT (0U) 250 #define CANXL_MRU_CH1_MB3_MBD_WIDTH (32U) 251 #define CANXL_MRU_CH1_MB3_MBD(x) (((uint32_t)(((uint32_t)(x)) << CANXL_MRU_CH1_MB3_MBD_SHIFT)) & CANXL_MRU_CH1_MB3_MBD_MASK) 252 /*! @} */ 253 254 /*! 255 * @} 256 */ /* end of group CANXL_MRU_Register_Masks */ 257 258 /*! 259 * @} 260 */ /* end of group CANXL_MRU_Peripheral_Access_Layer */ 261 262 #endif /* #if !defined(S32Z2_CANXL_MRU_H_) */ 263
