1 /**************************************************************************//** 2 * @file canfd_reg.h 3 * @version V1.00 4 * @brief CANFD register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2023 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __CANFD_REG_H__ 10 #define __CANFD_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** @addtogroup REGISTER Control Register 17 18 @{ 19 20 */ 21 22 23 /*---------------------- Controller Area Network with Flexible DataRate -------------------------*/ 24 /** 25 @addtogroup CANFD Controller Area Network with Flexible DataRate(CANFD) 26 Memory Mapped Structure for CANFD Controller 27 @{ */ 28 29 typedef struct 30 { 31 32 33 /** 34 * @var CANFD_T::DBTP 35 * Offset: 0x0C Data Bit Timing & Prescaler Register 36 * --------------------------------------------------------------------------------------------------- 37 * |Bits |Field |Descriptions 38 * | :----: | :----: | :---- | 39 * |[3:0] |DSJW |Data Re-Synchronization Jump Width 40 * | | |Valid values are 0 to 15 41 * | | |The actual interpretation by the hardware of this value is such that one more than the programmed value is used 42 * | | |tSJW = (DSJW + 1) x tq. 43 * |[7:4] |DTSEG2 |Data time segment after sample point 44 * | | |Valid values are 0 to 15 45 * | | |The actual interpretation by the hardware of this value is such that one more than the programmed value is used 46 * | | |tBS2 = (DTSEG2 + 1) x tq. 47 * |[12:8] |DTSEG1 |Data time segment before sample point 48 * | | |Valid values are 0 to 31 49 * | | |The actual interpretation by the hardware of this value is such that one more than the programmed value is used 50 * | | |tBS1 = (DTSEG1 + 1) x tq. 51 * |[20:16] |DBRP |Data Bit Rate Prescaler 52 * | | |The value by which the oscillator frequency is divided for generating the bit time quanta 53 * | | |The bit time is built up from a multiple of this quanta 54 * | | |Valid values for the Bit Rate Prescaler are 0 to 31 55 * | | |When TDC = '1', the range is limited to 0,1 56 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. 57 * |[23] |TDC |Transmitter Delay Compensation 58 * | | |0=Transmitter Delay Compensation disabled. 59 * | | |1=Transmitter Delay Compensation enabled. 60 * @var CANFD_T::TEST 61 * Offset: 0x10 Test Register 62 * --------------------------------------------------------------------------------------------------- 63 * |Bits |Field |Descriptions 64 * | :----: | :----: | :---- | 65 * |[4] |LBCK |Loop Back Mode 66 * | | |0 = Reset value, Loop Back Mode is disabled. 67 * | | |1 = Loop Back Mode is enabled (refer to 6.36.5.1 TEST Mode). 68 * |[6:5] |TX |Control of Transmit Pin 69 * | | |00 = Reset value, CANx_TXD controlled by the CAN Core, updated at the end of the CAN bit time. 70 * | | |01 = Sample Point can be monitored at pin CANx_TXD. 71 * | | |10 = Dominant ('0') level at pin CANx_TXD. 72 * | | |11 = Recessive ('1') level at pin CANx_TXD. 73 * |[7] |RX |Receive Pin 74 * | | |Monitors the actual value of pin CANx_RXD 75 * | | |0 = The CAN bus is dominant (CANx_RXD = 0). 76 * | | |1 = The CAN bus is recessive (CANx_RXD = 1). 77 * @var CANFD_T::RWD 78 * Offset: 0x14 RAM Watchdog 79 * --------------------------------------------------------------------------------------------------- 80 * |Bits |Field |Descriptions 81 * | :----: | :----: | :---- | 82 * |[7:0] |WDC |Watchdog Configuration 83 * | | |Start value of the Message RAM Watchdog Counter. With the reset value of 00 the counter is disabled. 84 * |[15:8] |WDV |Watchdog Value 85 * | | |Actual Message RAM Watchdog Counter Value. 86 * @var CANFD_T::CCCR 87 * Offset: 0x18 CC Control Register 88 * --------------------------------------------------------------------------------------------------- 89 * |Bits |Field |Descriptions 90 * | :----: | :----: | :---- | 91 * |[0] |INIT |Initialization 92 * | | |0 = Normal Operation. 93 * | | |1 = Initialization is started. 94 * | | |Note: Due to the synchronization mechanism between the two clock domains, there may be a delay until the value written to INIT can be read back 95 * | | |Therefore the programmer has to assure that the previous value written to INIT has been accepted by reading INIT before setting INIT to a new value. 96 * |[1] |CCE |Configuration Change Enable 97 * | | |0 = The CPU has no write access to the protected configuration registers. 98 * | | |1 = The CPU has write access to the protected configuration registers (while INIT (CANFD_CCCR[0]) = 1). 99 * |[2] |ASM |Restricted Operation Mode 100 * | | |Bit ASM can only be set by the Host when both CCE and INIT are set to 1 101 * | | |The bit can be reset by the software at any time 102 * | | |This bit will be set automatically set to 1 when the Tx handler was not able to read data from the message RAM in time 103 * | | |For a description of the Restricted Operation Mode refer to Restricted Operation Mode. 104 * | | |0 = Normal CAN operation. 105 * | | |1 = Restricted Operation Mode active. 106 * |[3] |CSA |Clock Stop Acknowledge 107 * | | |0 = No clock stop acknowledged. 108 * | | |1 = The Controller may be set in power down by stopping AHB clock and CAN Core clock. 109 * |[4] |CSR |Clock Stop Request 110 * | | |0 = No clock stop is requested. 111 * | | |1 = Clock stop requested 112 * | | |When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. 113 * |[5] |MON |Bus Monitoring Mode 114 * | | |Bit MON can only be set by the Host when both CCE and INIT are set to 1 115 * | | |The bit can be reset by the Host at any time. 116 * | | |0 = Bus Monitoring Mode is disabled. 117 * | | |1 = Bus Monitoring Mode is enabled. 118 * |[6] |DAR |Disable Automatic Retransmission 119 * | | |0 = Automatic retransmission of messages not transmitted successfully enabled. 120 * | | |1 = Automatic retransmission disabled. 121 * |[7] |TEST |Test Mode Enable 122 * | | |0 = Normal operation, register TEST holds reset values. 123 * | | |1 = Test Mode, write access to register TEST enabled. 124 * |[8] |FDOE |FD Operation Enable 125 * | | |0 = FD operation disabled. 126 * | | |1 = FD operation enabled. 127 * |[9] |BRSE |Bit Rate Switch Enable 128 * | | |0 = Bit rate switching for transmissions disabled. 129 * | | |1 = Bit rate switching for transmissions enabled. 130 * | | |Note: When CAN FD operation is disabled FDOE = 0, BRSE is not evaluated. 131 * |[12] |PXHD |Protocol Exception Handling Disable 132 * | | |0 = Protocol exception handling enabled. 133 * | | |1 = Protocol exception handling disabled. 134 * | | |Note: When protocol exception handling is disabled, the controller will transmit an error frame when it detects a protocol exception condition. 135 * |[13] |EFBI |Edge Filtering during Bus Integration 136 * | | |0 = Edge filtering disabled. 137 * | | |1 = Two consecutive dominant tq required to detect an edge f or hard synchronization. 138 * |[14] |TXP |Transmit Pause 139 * | | |If this bit is set, the CAN FD controller pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (refer to 1.1.5.5). 140 * | | |0 = Transmit pause disabled. 141 * | | |1 = Transmit pause enabled. 142 * |[15] |NISO |Non ISO Operation 143 * | | |If this bit is set, the CAN FD controller uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0. 144 * | | |0 = CAN FD frame format according to ISO 11898-1:2015. 145 * | | |1 = CAN FD frame format according to Bosch CAN FD Specification V1.0. 146 * @var CANFD_T::NBTP 147 * Offset: 0x1C Nominal Bit Timing & Prescaler Register 148 * --------------------------------------------------------------------------------------------------- 149 * |Bits |Field |Descriptions 150 * | :----: | :----: | :---- | 151 * |[6:0] |NTSEG2 |Nominal Time segment after sample point 152 * | | |0x01-0x7F Valid values are 1 to 127 153 * | | |The actual interpretation by the hardware of this value is such that one more than the programmed value is used 154 * | | |tBS2 = (NTSEG2 + 1) x tq. 155 * | | |Note: With a CAN Core clock (cclk) of 8 MHz, the reset value of 0x06000A03 configures the controller for a bit rate of 500 kBit/s. 156 * |[15:8] |NTSEG1 |Nominal Time segment before sample point 157 * | | |Valid values are 1 to 255 158 * | | |The actual interpretation by the hardware of this value is such that one more than the programmed value is used 159 * | | |tBS1 = (NTSEG1 + 1) x tq. 160 * |[24:16] |NBRP |Nominal Bit Rate Prescaler 161 * | | |The value by which the oscillator frequency is divided for generating the bit time quanta 162 * | | |The bit time is built up from a multiple of this quanta 163 * | | |Valid values for the Bit Rate Prescaler are 0 to 511 164 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used 165 * |[31:25] |NSJW |Nominal Re-Synchronization Jump Width 166 * | | |Valid values are 0 to 127 167 * | | |Should be smaller than NTSEG2 168 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used 169 * | | |tSJW = (NSJW + 1) x tq. 170 * @var CANFD_T::TSCC 171 * Offset: 0x20 Timestamp Counter Configuration 172 * --------------------------------------------------------------------------------------------------- 173 * |Bits |Field |Descriptions 174 * | :----: | :----: | :---- | 175 * |[1:0] |TSS |Timestamp Select 176 * | | |00 = Timestamp counter value always 0x0000. 177 * | | |01 = Timestamp counter value incremented according to TCP. 178 * | | |10 = Reserved 179 * | | |11 = Same as "00". 180 * |[19:16] |TCP |Timestamp Counter Prescaler 181 * | | |Configures the timestamp and timeout counters time unit in multiples of CAN bit times [ 1...16 ] 182 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. 183 * @var CANFD_T::TSCV 184 * Offset: 0x24 Timestamp Counter Value 185 * --------------------------------------------------------------------------------------------------- 186 * |Bits |Field |Descriptions 187 * | :----: | :----: | :---- | 188 * |[15:0] |TSC |Timestamp Counter 189 * | | |The internal Timestamp Counter value is captured on start of frame (both Rx and Tx) 190 * | | |When TSS (CANFD_TSCC[[1:0]) = 2'b01, the Timestamp Counter is incremented in multiples of CAN bit times [ 1...16 ] depending on the configuration of TCP (CANFD_TSCC[19:16]) 191 * | | |A wrap around sets interrupt flag TSW (CANFD_IR[16]) 192 * | | |Write access resets the counter to zero. 193 * | | |Note: A "wrap around" is a change of the Timestamp Counter value from non-zero to zero not caused by write access to CANFD_TSCV. 194 * @var CANFD_T::TOCC 195 * Offset: 0x28 Timeout Counter Configuration 196 * --------------------------------------------------------------------------------------------------- 197 * |Bits |Field |Descriptions 198 * | :----: | :----: | :---- | 199 * |[0] |ETOC |Enable Timeout Counter 200 * | | |0 = Timeout Counter disabled. 201 * | | |1 = Timeout Counter enabled. 202 * | | |Note: For use of timeout function with CAN FD refer to 6.36.5.3. 203 * |[2:1] |TOS |Timeout Select 204 * | | |When operating in Continuous mode, a write to CANFD_TOCV presets the counter to the value configured by TOP (CANFD_TOCC[31:16]) and continues down-counting 205 * | | |When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOP (CANFD_TOCC[31:16]) 206 * | | |Down-counting is started when the first FIFO element is stored. 207 * | | |00 = Continuous operation. 208 * | | |01 = Timeout controlled by Tx Event FIFO. 209 * | | |10 = Timeout controlled by Rx FIFO 0. 210 * | | |11 = Timeout controlled by Rx FIFO 1. 211 * |[31:16] |TOP |Timeout Period 212 * | | |Start value of the Timeout Counter (down-counter). Configures the Timeout Period. 213 * @var CANFD_T::TOCV 214 * Offset: 0x2C Timeout Counter Value 215 * --------------------------------------------------------------------------------------------------- 216 * |Bits |Field |Descriptions 217 * | :----: | :----: | :---- | 218 * |[15:0] |TOC |Timeout Counter 219 * | | |The filed is decremented in multiples of CAN bit times [ 1...16 ] depending on the configuration of TCP (CANFD_TSCC[19:16]) 220 * | | |When decremented to zero, interrupt flag TOO (CANFD_IR[18]) is set and the timeout counter is stopped 221 * | | |Start and reset/restart conditions are configured via TOS (CANFD_TOCC[1:0]). 222 * @var CANFD_T::ECR 223 * Offset: 0x40 Error Counter Register 224 * --------------------------------------------------------------------------------------------------- 225 * |Bits |Field |Descriptions 226 * | :----: | :----: | :---- | 227 * |[7:0] |TEC |Transmit Error Counter 228 * | | |Actual state of the Transmit Error Counter, values between 0 and 255. 229 * | | |Note: When ASM (CANFD_CCCR[2]) is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. 230 * |[14:8] |REC |Receive Error Counter 231 * | | |Actual state of the Receive Error Counter, values between 0 and 127. 232 * |[15] |RP |Receive Error Passive 233 * | | |0 = The Receive Error Counter is below the error passive level of 128. 234 * | | |1 = The Receive Error Counter has reached the error passive level of 128. 235 * |[23:16] |CEL |CAN Error Logging 236 * | | |The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented 237 * | | |The counter is also incremented when the Bus_Off limit is reached 238 * | | |It is not incremented when only RP is set without changing REC 239 * | | |The increment of CEL follows after the increment of REC or TEC. 240 * | | |The counter is reset by read access to CEL 241 * | | |The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag ELO (CANFD_IR[22]). 242 * @var CANFD_T::PSR 243 * Offset: 0x44 Protocol Status Register 244 * --------------------------------------------------------------------------------------------------- 245 * |Bits |Field |Descriptions 246 * | :----: | :----: | :---- | 247 * |[2:0] |LEC |Last Error Code 248 * | | |The LEC indicates the type of the last error to occur on the CAN bus 249 * | | |This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. 250 * | | |000 = No Error: No error occurred since LEC has been reset by successful reception or transmission. 251 * | | |001 = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 252 * | | |010 = Form Error: A fixed format part of a received frame has the wrong format. 253 * | | |011 = AckError: The message transmitted by the CANFD CONTROLLER was not acknowledged by another node. 254 * | | |100 = Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant. 255 * | | |101 = Bit0Error : During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive 256 * | | |During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored 257 * | | |This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 258 * | | |110 = CRCError: The CRC check sum of a received message was incorrect 259 * | | |The CRC of an incoming message does not match with the CRC calculated from the received data. 260 * | | |111 = NoChange: Any read access to the Protocol Status Register re-initializes the LEC to 7.When the LEC shows the value 7, no CAN bus event was detected since the last CPU read access to the Protocol Status Register. 261 * |[4:3] |ACT |Activity 262 * | | |Monitors the module's CAN communication state. 263 * | | |00 = Synchronizing - node is synchronizing on CAN communication. 264 * | | |01 = Idle - node is neither receiver nor transmitter. 265 * | | |10 = Receiver - node is operating as receiver. 266 * | | |11 = Transmitter - node is operating as transmitter. 267 * |[5] |EP |Error Passive 268 * | | |0 = The CAN FD controller is in the Error_Active state 269 * | | |It normally takes part in bus communication and sends an active error flag when an error has been detected. 270 * | | |1 = The CAN FD controller is in the Error_Passive state. 271 * |[6] |EW |Warning Status 272 * | | |0 = Both error counters are below the Error_Warning limit of 96. 273 * | | |1 = At least one of error counter has reached the Error_Warning limit of 96. 274 * |[7] |BO |Bus_Off Status 275 * | | |0 = The CAN FD controller is not Bus_Off. 276 * | | |1 = The CAN FD controller is in Bus_Off state. 277 * |[10:8] |DLEC |Data Phase Last Error Code 278 * | | |Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set 279 * | | |Coding is the same as for LEC 280 * | | |This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error. 281 * |[11] |RESI |ESI flag of last received CAN FD Message 282 * | | |This bit is set together with RFDF, independent of acceptance filtering. 283 * | | |0 = Last received CAN FD message did not have its ESI flag set. 284 * | | |1 = Last received CAN FD message had its ESI flag set. 285 * |[12] |RBRS |BRS flag of last received CAN FD Message 286 * | | |This bit is set together with RFDF, independent of acceptance filtering. 287 * | | |0 = Last received CAN FD message did not have its BRS flag set. 288 * | | |1 = Last received CAN FD message had its BRS flag set. 289 * | | |Note: Byte access: Reading byte 0 will reset RBRS, reading bytes 3/2/1 has no impact. 290 * |[13] |RFDF |Received a CAN FD Message 291 * | | |This bit is set independent of acceptance filtering. 292 * | | |0 = Since this bit was reset by the CPU, no CAN FD message has been received. 293 * | | |1 = Message in CAN FD format with FDF flag set has been received. 294 * | | |Note: Byte access: Reading byte 0 will reset RFDF, reading bytes 3/2/1 has no impact. 295 * |[14] |PXE |Protocol Exception Event 296 * | | |0 = No protocol exception event occurred since last read access. 297 * | | |1 = Protocol exception event occurred. 298 * |[22:16] |TDCV |Transmitter Delay Compensation Value 299 * | | |Position of the secondary sample point, defined by the sum of the measured delay from CANx_TXD to CANx_RXD and TDCO (CANFD_TDCR[[14:8]) 300 * | | |The SSP position is, in the data phase, the number of minimum time quata (mtq) between the start of the transmitted bit and the secondary sample point 301 * | | |Valid values are 0 to 127 mtq. 302 * @var CANFD_T::TDCR 303 * Offset: 0x48 Transmitter Delay Compensation Register 304 * --------------------------------------------------------------------------------------------------- 305 * |Bits |Field |Descriptions 306 * | :----: | :----: | :---- | 307 * |[6:0] |TDCF |Transmitter Delay Compensation Filter Window Length 308 * | | |Defines the minimum value for the SSP position, dominant edges on CANx_RXD that would result in an earlier SSP position are ignored for transmitter delay measurement 309 * | | |The feature is enabled when TDCF is configured to a value greater than TDCO 310 * | | |Valid values are 0 to 127 mtq. 311 * |[14:8] |TDCO |Transmitter Delay Compensation SSP Offset 312 * | | |Offset value defining the distance between the measured delay from CANx_TXD to CANx_RXD and the secondary sample point 313 * | | |Valid values are 0 to 127 mtq. 314 * @var CANFD_T::IR 315 * Offset: 0x50 Interrupt Register 316 * --------------------------------------------------------------------------------------------------- 317 * |Bits |Field |Descriptions 318 * | :----: | :----: | :---- | 319 * |[0] |RF0N |Rx FIFO 0 New Message 320 * | | |0 = No new message written to Rx FIFO 0. 321 * | | |1 = New message written to Rx FIFO 0. 322 * |[1] |RF0W |Rx FIFO 0 Watermark Reached 323 * | | |0 = Rx FIFO 0 fill level below watermark. 324 * | | |1 = Rx FIFO 0 fill level reached watermark. 325 * |[2] |RF0F |Rx FIFO 0 Full 326 * | | |0 = Rx FIFO 0 is not full. 327 * | | |1 = Rx FIFO 0 is full. 328 * |[3] |RF0L |Rx FIFO 0 Message Lost 329 * | | |0 = No Rx FIFO 0 message lost. 330 * | | |1 = Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero. 331 * |[4] |RF1N |Rx FIFO 1 New Message 332 * | | |0 = No new message written to Rx FIFO 1. 333 * | | |1 = New message written to Rx FIFO 1. 334 * |[5] |RF1W |Rx FIFO 1 Watermark Reached 335 * | | |0 = Rx FIFO 1 fill level below watermark. 336 * | | |1 = Rx FIFO 1 fill level reached watermark. 337 * |[6] |RF1F |Rx FIFO 1 Full 338 * | | |0 = Rx FIFO 1 is not full. 339 * | | |1 = Rx FIFO 1 is full. 340 * |[7] |RF1L |Rx FIFO 1 Message Lost 341 * | | |0 = No Rx FIFO 1 message lost. 342 * | | |1 = Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero. 343 * |[8] |HPM |High Priority Message 344 * | | |0 = No high priority message received. 345 * | | |1 = High priority message received. 346 * |[9] |TC |Transmission Completed 347 * | | |0 = No transmission completed. 348 * | | |1 = Transmission completed. 349 * |[10] |TCF |Transmission Cancellation Finished 350 * | | |0 = No transmission cancellation finished. 351 * | | |1 = Transmission cancellation finished. 352 * |[11] |TFE |Tx FIFO Empty 353 * | | |0 = Tx FIFO non-empty. 354 * | | |1 = Tx FIFO empty. 355 * |[12] |TEFN |Tx Event FIFO New Entry 356 * | | |0 = Tx Event FIFO unchanged. 357 * | | |1 = Tx Handler wrote Tx Event FIFO element. 358 * |[13] |TEFW |Tx Event FIFO Watermark Reached 359 * | | |0 = Tx Event FIFO fill level below watermark. 360 * | | |1 = Tx Event FIFO fill level reached watermark. 361 * |[14] |TEFF |Tx Event FIFO Full 362 * | | |0 = Tx Event FIFO is not full. 363 * | | |1 = Tx Event FIFO is full. 364 * |[15] |TEFL |Tx Event FIFO Element Lost 365 * | | |0 = No Tx Event FIFO element lost. 366 * | | |1 = Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. 367 * |[16] |TSW |Timestamp Wraparound 368 * | | |0 = No timestamp counter wrap-around. 369 * | | |1 = Timestamp counter wrapped around. 370 * |[17] |MRAF |Message RAM Access Failure 371 * | | |The flag is set, when the Rx Handler 372 * | | |�EHas not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received 373 * | | |In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message. 374 * | | |�EWas not able to write a message to the Message RAM. In this case message storage is aborted. 375 * | | |In both cases the FIFO put index is not updated resp 376 * | | |The New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. 377 * | | |The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time 378 * | | |In this case message transmission is aborted 379 * | | |In case of a Tx Handler access failure the CAN FD controller is switched into Restricted Operation Mode (refer to Restricted Operation Mode) 380 * | | |To leave Restricted Operation Mode, the Host CPU has to reset ASM (CANFD_CCCR[2]). 381 * | | |0 = No Message RAM access failure occurred. 382 * | | |1 = Message RAM access failure occurred. 383 * |[18] |TOO |Timeout Occurred 384 * | | |0 = No timeout. 385 * | | |1 = Timeout reached. 386 * |[19] |DRX |Message stored to Dedicated Rx Buffer 387 * | | |The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 388 * | | |0 = No Rx Buffer updated. 389 * | | |1 = At least one received message stored into an Rx Buffer. 390 * |[22] |ELO |Error Logging Overflow 391 * | | |0 = CAN Error Logging Counter did not overflow. 392 * | | |1 = Overflow of CAN Error Logging Counter occurred. 393 * |[23] |EP |Error Passive 394 * | | |0 = Error_Passive status unchanged. 395 * | | |1 = Error_Passive status changed. 396 * |[24] |EW |Warning Status 397 * | | |0 = Error_Warning status unchanged. 398 * | | |1 = Error_Warning status changed. 399 * |[25] |BO |Bus_Off Status 400 * | | |0 = Bus_Off status unchanged. 401 * | | |1 = Bus_Off status changed. 402 * |[26] |WDI |Watchdog Interrupt 403 * | | |0 = No Message RAM Watchdog event occurred. 404 * | | |1 = Message RAM Watchdog event due to missing READY. 405 * |[27] |PEA |Protocol Error in Arbitration Phase 406 * | | |0 = No protocol error in arbitration phase. 407 * | | |1 = Protocol error in arbitration phase detected (LEC (CANFD_PSR[2:0]) no equal 0 or 7). 408 * | | |Note: Nominal bit time is used 409 * |[28] |PED |Protocol Error in Data Phase 410 * | | |0 = No protocol error in data phase. 411 * | | |1= Protocol error in data phase detected (DLEC (CANFD_PSR[10:8]) no equal 0 or 7). 412 * | | |Note: Data bit time is used 413 * |[29] |ARA |Access to Reserved Address 414 * | | |0 = No access to reserved address occurred. 415 * | | |1 = Access to reserved address occurred. 416 * @var CANFD_T::IE 417 * Offset: 0x54 Interrupt Enable 418 * --------------------------------------------------------------------------------------------------- 419 * |Bits |Field |Descriptions 420 * | :----: | :----: | :---- | 421 * |[0] |RF0NE |Rx FIFO 0 New Message Interrupt Enable 422 * | | |0 = Interrupt is Disabled. 423 * | | |1 = Interrupt is Enabled. 424 * |[1] |RF0WE |Rx FIFO 0 Watermark Reached Interrupt Enable 425 * | | |0 = Interrupt is Disabled. 426 * | | |1 = Interrupt is Enabled. 427 * |[2] |RF0FE |Rx FIFO 0 Full Interrupt Enable 428 * | | |0 = Interrupt is Disabled. 429 * | | |1 = Interrupt is Enabled. 430 * |[3] |RF0LE |Rx FIFO 0 Message Lost Interrupt Enable 431 * | | |0 = Interrupt is Disabled. 432 * | | |1 = Interrupt is Enabled. 433 * |[4] |RF1NE |Rx FIFO 1 New Message Interrupt Enable 434 * | | |0 = Interrupt is Disabled. 435 * | | |1 = Interrupt is Enabled. 436 * |[5] |RF1WE |Rx FIFO 1 Watermark Reached Interrupt Enable 437 * | | |0 = Interrupt is Disabled. 438 * | | |1 = Interrupt is Enabled. 439 * |[6] |RF1FE |Rx FIFO 1 Full Interrupt Enable 440 * | | |0 = Interrupt is Disabled. 441 * | | |1 = Interrupt is Enabled. 442 * |[7] |RF1LE |Rx FIFO 1 Message Lost Interrupt Enable 443 * | | |0 = Interrupt is Disabled. 444 * | | |1 = Interrupt is Enabled. 445 * |[8] |HPME |High Priority Message Interrupt Enable 446 * | | |0 = Interrupt is Disabled. 447 * | | |1 = Interrupt is Enabled. 448 * |[9] |TCE |Transmission Completed Interrupt Enable 449 * | | |0 = Interrupt is Disabled. 450 * | | |1 = Interrupt is Enabled. 451 * |[10] |TCFE |Transmission Cancellation Finished Interrupt Enable 452 * | | |0 = Interrupt is Disabled. 453 * | | |1 = Interrupt is Enabled. 454 * |[11] |TFEE |Tx FIFO Empty Interrupt Enable 455 * | | |0 = Interrupt is Disabled. 456 * | | |1 = Interrupt is Enabled. 457 * |[12] |TEFNE |Tx Event FIFO New Entry Interrupt Enable 458 * | | |0 = Interrupt is Disabled. 459 * | | |1 = Interrupt is Enabled. 460 * |[13] |TEFWE |Tx Event FIFO Watermark Reached Interrupt Enable 461 * | | |0 = Interrupt is Disabled. 462 * | | |1 = Interrupt is Enabled. 463 * |[14] |TEFFE |Tx Event FIFO Full Interrupt Enable 464 * | | |0 = Interrupt is Disabled. 465 * | | |1 = Interrupt is Enabled. 466 * |[15] |TEFLE |Tx Event FIFO Event Lost Interrupt Enable 467 * | | |0 = Interrupt is Disabled. 468 * | | |1 = Interrupt is Enabled. 469 * |[16] |TSWE |Timestamp Wraparound Interrupt Enable 470 * | | |0 = Interrupt is Disabled. 471 * | | |1 = Interrupt is Enabled. 472 * |[17] |MRAFE |Message RAM Access Failure Interrupt Enable 473 * | | |0 = Interrupt is Disabled. 474 * | | |1 = Interrupt is Enabled. 475 * |[18] |TOOE |Timeout Occurred Interrupt Enable 476 * | | |0 = Interrupt is Disabled. 477 * | | |1 = Interrupt is Enabled. 478 * |[19] |DRXE |Message stored to Dedicated Rx Buffer Interrupt Enable 479 * | | |0 = Interrupt is Disabled. 480 * | | |1 = Interrupt is Enabled. 481 * |[20] |BECE |Bit Error Corrected Interrupt Enable 482 * | | |0 = Interrupt is Disabled. 483 * | | |1 = Interrupt is Enabled. 484 * |[21] |BEUE |Bit Error Uncorrected Interrupt Enable 485 * | | |0 = Interrupt is Disabled. 486 * | | |1 = Interrupt is Enabled. 487 * |[22] |ELOE |Error Logging Overflow Interrupt Enable 488 * | | |0 = Interrupt is Disabled. 489 * | | |1 = Interrupt is Enabled. 490 * |[23] |EPE |Error Passive Interrupt Enable 491 * | | |0 = Interrupt is Disabled. 492 * | | |1 = Interrupt is Enabled. 493 * |[24] |EWE |Warning Status Interrupt Enable 494 * | | |0 = Interrupt is Disabled. 495 * | | |1 = Interrupt is Enabled. 496 * |[25] |BOE |Bus_Off Status Interrupt Enable 497 * | | |0 = Interrupt is Disabled. 498 * | | |1 = Interrupt is Enabled. 499 * |[26] |WDIE |Watchdog Interrupt Enable 500 * | | |0 = Interrupt is Disabled. 501 * | | |1 = Interrupt is Enabled. 502 * |[27] |PEAE |Protocol Error in Arbitration Phase Enable 503 * | | |0 = Interrupt is Disabled. 504 * | | |1 = Interrupt is Enabled. 505 * |[28] |PEDE |Protocol Error in Data Phase Enable 506 * | | |0 = Interrupt is Disabled. 507 * | | |1 = Interrupt is Enabled. 508 * |[29] |ARAE |Access to Reserved Address Enable 509 * | | |0 = Interrupt is Disabled. 510 * | | |1 = Interrupt is Enabled. 511 * @var CANFD_T::ILS 512 * Offset: 0x58 Interrupt Line Select 513 * --------------------------------------------------------------------------------------------------- 514 * |Bits |Field |Descriptions 515 * | :----: | :----: | :---- | 516 * |[0] |RF0NL |Rx FIFO 0 New Message Interrupt Line 517 * | | |0 = Interrupt assigned to CAN interrupt line 0. 518 * | | |1 = Interrupt assigned to CAN interrupt line 1. 519 * |[1] |RF0WL |Rx FIFO 0 Watermark Reached Interrupt Line 520 * |[2] |RF0FL |Rx FIFO 0 Full Interrupt Line 521 * |[3] |RF0LL |Rx FIFO 0 Message Lost Interrupt Line 522 * |[4] |RF1NL |Rx FIFO 1 New Message Interrupt Line 523 * |[5] |RF1WL |Rx FIFO 1 Watermark Reached Interrupt Line 524 * |[6] |RF1FL |Rx FIFO 1 Full Interrupt Line 525 * |[7] |RF1LL |Rx FIFO 1 Message Lost Interrupt Line 526 * |[8] |HPML |High Priority Message Interrupt Line 527 * |[9] |TCL |Transmission Completed Interrupt Line 528 * |[10] |TCFL |Transmission Cancellation Finished Interrupt Line 529 * |[11] |TFEL |Tx FIFO Empty Interrupt Line 530 * |[12] |TEFNL |Tx Event FIFO New Entry Interrupt Line 531 * |[13] |TEFWL |Tx Event FIFO Watermark Reached Interrupt Line 532 * |[14] |TEFFL |Tx Event FIFO Full Interrupt Line 533 * |[15] |TEFLL |Tx Event FIFO Event Lost Interrupt Line 534 * |[16] |TSWL |Timestamp Wraparound Interrupt Line 535 * |[17] |MRAFL |Message RAM Access Failure Interrupt Line 536 * |[18] |TOOL |Timeout Occurred Interrupt Line 537 * |[19] |DRXL |Message stored to Dedicated Rx Buffer Interrupt Line 538 * |[20] |BECL |Bit Error Corrected Interrupt Line . 539 * |[21] |BEUL |Bit Error Uncorrected Interrupt Line . 540 * |[22] |ELOL |Error Logging Overflow Interrupt Line 541 * |[23] |EPL |Error Passive Interrupt Line 542 * |[24] |EWL |Warning Status Interrupt Line 543 * |[25] |BOL |Bus_Off Status Interrupt Line 544 * |[26] |WDIL |Watchdog Interrupt Line 545 * |[27] |PEAL |Protocol Error in Arbitration Phase Line 546 * |[28] |PEDL |Protocol Error in Data Phase Line 547 * |[29] |ARAL |Access to Reserved Address Line 548 * @var CANFD_T::ILE 549 * Offset: 0x5C Interrupt Line Enable 550 * --------------------------------------------------------------------------------------------------- 551 * |Bits |Field |Descriptions 552 * | :----: | :----: | :---- | 553 * |[0] |EINT0 |Enable Interrupt Line 0 554 * | | |0 = Interrupt line m_can_int0 disabled. 555 * | | |1 = Interrupt line m_can_int0 enabled. 556 * |[1] |EINT1 |Enable Interrupt Line 1 557 * | | |0 = Interrupt line m_can_int1 disabled. 558 * | | |1 = Interrupt line m_can_int1 enabled. 559 * @var CANFD_T::GFC 560 * Offset: 0x80 Global Filter Configuration 561 * --------------------------------------------------------------------------------------------------- 562 * |Bits |Field |Descriptions 563 * | :----: | :----: | :---- | 564 * |[0] |RRFE |Reject Remote Frames Extended 565 * | | |0= Filter remote frames with 29-bit extended IDs. 566 * | | |1= Reject all remote frames with 29-bit extended IDs. 567 * |[1] |RRFS |Reject Remote Frames Standard 568 * | | |0= Filter remote frames with 11-bit standard IDs. 569 * | | |1= Reject all remote frames with 11-bit standard IDs. 570 * |[3:2] |ANFE |Accept Non-matching Frames Extended 571 * | | |Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 572 * | | |00 = Accept in Rx FIFO 0. 573 * | | |01 = Accept in Rx FIFO 1. 574 * | | |10 = Reject. 575 * | | |11 = Reject. 576 * |[5:4] |ANFS |Accept Non-matching Frames Standard 577 * | | |Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 578 * | | |00 = Accept in Rx FIFO 0. 579 * | | |01 = Accept in Rx FIFO 1. 580 * | | |10 = Reject. 581 * | | |11 = Reject. 582 * @var CANFD_T::SIDFC 583 * Offset: 0x84 Standard ID Filter Configuration 584 * --------------------------------------------------------------------------------------------------- 585 * |Bits |Field |Descriptions 586 * | :----: | :----: | :---- | 587 * |[15:2] |FLSSA |Filter List Standard Start Address 588 * | | |Start address of standard Message ID filter list (32-bit word address, refer to Figure 1.1-11Figure 0-11). 589 * |[23:16] |LSS |List Size Standard 590 * | | |0= No standard Message ID filter. 591 * | | |1-128 = Number of standard Message ID filter elements. 592 * | | |>128= Values greater than 128 are interpreted as 128. 593 * @var CANFD_T::XIDFC 594 * Offset: 0x88 Extended ID Filter Configuration 595 * --------------------------------------------------------------------------------------------------- 596 * |Bits |Field |Descriptions 597 * | :----: | :----: | :---- | 598 * |[15:2] |FLESA |Filter List Extended Start Address 599 * | | |Start address of extended Message ID filter list (32-bit word address, refer to Figure 1.1-11Figure 0-11) 600 * |[22:16] |LSE |List Size Extended 601 * | | |0= No extended Message ID filter. 602 * | | |1-64= Number of extended Message ID filter elements. 603 * | | |>64= Values greater than 64 are interpreted as 64. 604 * @var CANFD_T::XIDAM 605 * Offset: 0x90 Extended ID AND Mask 606 * --------------------------------------------------------------------------------------------------- 607 * |Bits |Field |Descriptions 608 * | :----: | :----: | :---- | 609 * |[28:0] |EIDM |Extended ID Mask 610 * | | |For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame 611 * | | |Intended for masking of 29-bit IDs in SAE J1939 612 * | | |With the reset value of all bits set to one the mask is not active. 613 * @var CANFD_T::HPMS 614 * Offset: 0x94 High Priority Message Status 615 * --------------------------------------------------------------------------------------------------- 616 * |Bits |Field |Descriptions 617 * | :----: | :----: | :---- | 618 * |[5:0] |BIDX |Buffer Index 619 * | | |Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = 1. 620 * |[7:6] |MSI |Message Storage Indicator 621 * | | |00 = No FIFO selected. 622 * | | |01 = FIFO message lost. 623 * | | |10 = Message stored in FIFO 0. 624 * | | |11 = Message stored in FIFO 1. 625 * |[14:8] |FIDX |Filter Index 626 * | | |Index of matching filter element 627 * | | |Range is 0 to LSS (CANFD_SIDFC[23:16]) - 1 or LSE (CANFD_XIDFC[22:16]) - 1 628 * |[15] |FLST |Filter List 629 * | | |Indicates the filter list of the matching filter element. 630 * | | |0 = Standard Filter List. 631 * | | |1 = Extended Filter List. 632 * @var CANFD_T::NDAT1 633 * Offset: 0x98 New Data 1 634 * --------------------------------------------------------------------------------------------------- 635 * |Bits |Field |Descriptions 636 * | :----: | :----: | :---- | 637 * |[31:0] |NDn |New Data 638 * | | |The register holds the New Data flags of Rx Buffers 0 to 31 639 * | | |The flags are set when the respective Rx Buffer has been updated from a received frame 640 * | | |The flags remain set until the Host clears them 641 * | | |A flag is cleared by writing a 1 to the corresponding bit position 642 * | | |Writing a 0 has no effect 643 * | | |A hard reset will clear the register. 644 * | | |0 = Rx Buffer not updated. 645 * | | |1 = Rx Buffer updated from new message. 646 * @var CANFD_T::NDAT2 647 * Offset: 0x9C New Data 2 648 * --------------------------------------------------------------------------------------------------- 649 * |Bits |Field |Descriptions 650 * | :----: | :----: | :---- | 651 * |[31:0] |NDn |New Data 652 * | | |The register holds the New Data flags of Rx Buffers 32 to 63 653 * | | |The flags are set when the respective Rx Buffer has been updated from a received frame 654 * | | |The flags remain set until the Host clears them 655 * | | |A flag is cleared by writing a 1 to the corresponding bit position 656 * | | |Writing a 0 has no effect 657 * | | |A hard reset will clear the register. 658 * | | |0 = Rx Buffer not updated. 659 * | | |1 = Rx Buffer updated from new message. 660 * @var CANFD_T::RXF0C 661 * Offset: 0xA0 Rx FIFO 0 Configuration 662 * --------------------------------------------------------------------------------------------------- 663 * |Bits |Field |Descriptions 664 * | :----: | :----: | :---- | 665 * |[15:2] |F0SA |Rx FIFO 0 Start Address 666 * | | |Start address of Rx FIFO 0 in Message RAM (32-bit word address). 667 * |[22:16] |F0S |Rx FIFO 0 Size 668 * | | |0= No Rx FIFO 0. 669 * | | |1-64= Number of Rx FIFO 0 elements. 670 * | | |>64= Values greater than 64 are interpreted as 64. 671 * | | |The Rx FIFO 0 elements are indexed from 0 to F0S-1 672 * |[30:24] |F0WM |Rx FIFO 0 Watermark 673 * | | |0= Watermark interrupt disabled. 674 * | | |1-64 = Level for Rx FIFO 0 watermark interrupt (RF0W(CANFD_IR[1]). 675 * | | |>64 = Watermark interrupt disabled. 676 * |[31] |F0OM |FIFO 0 Operation Mode 677 * | | |FIFO 0 can be operated in blocking or in overwrite mode (refer to Rx FIFOs). 678 * | | |0 = FIFO 0 blocking mode. 679 * | | |1 = FIFO 0 overwrite mode. 680 * @var CANFD_T::RXF0S 681 * Offset: 0xA4 Rx FIFO 0 Status 682 * --------------------------------------------------------------------------------------------------- 683 * |Bits |Field |Descriptions 684 * | :----: | :----: | :---- | 685 * |[6:0] |F0FL |Rx FIFO 0 Fill Level 686 * | | |Number of elements stored in Rx FIFO 0, range 0 to 64 687 * |[13:8] |F0GI |Rx FIFO 0 Get Index 688 * | | |Rx FIFO 0 read index pointer, range 0 to 63. 689 * |[21:16] |F0PI |Rx FIFO 0 Put Index 690 * | | |Rx FIFO 0 write index pointer, range 0 to 63. 691 * |[24] |F0F |Rx FIFO 0 Full 692 * | | |0= Rx FIFO 0 is not full. 693 * | | |1= Rx FIFO 0 is full. 694 * |[25] |RF0L |Rx FIFO 0 Message Lost 695 * | | |This bit is a copy of interrupt flagRF0L (CANFD_IR[3]) 696 * | | |When CANFD_IR.RF0L is reset, this bit is also reset 697 * | | |0 = No Rx FIFO 0 message lost. 698 * | | |1 = Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero. 699 * | | |Note: Overwriting the oldest message when F0OM (CANFD_RXF0C[31]) = 1 will not set this flag. 700 * @var CANFD_T::RXF0A 701 * Offset: 0xA8 Rx FIFO 0 Acknowledge 702 * --------------------------------------------------------------------------------------------------- 703 * |Bits |Field |Descriptions 704 * | :----: | :----: | :---- | 705 * |[5:0] |F0A |Rx FIFO 0 Acknowledge Index 706 * | | |After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI 707 * | | |This will set the Rx FIFO 0 Get Index F0GI (CANFD_RXF0S[13:8]) to F0AI (CANFD_RXF0A[5:0]) + 1 and update the FIFO 0 Fill Level F0FL(CANFD_RXF0S[6:0]). 708 * @var CANFD_T::RXBC 709 * Offset: 0xAC Rx Buffer Configuration 710 * --------------------------------------------------------------------------------------------------- 711 * |Bits |Field |Descriptions 712 * | :----: | :----: | :---- | 713 * |[15:2] |RBSA |Rx Buffer Start Address 714 * | | |Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address). 715 * @var CANFD_T::RXF1C 716 * Offset: 0xB0 Rx FIFO 1 Configuration 717 * --------------------------------------------------------------------------------------------------- 718 * |Bits |Field |Descriptions 719 * | :----: | :----: | :---- | 720 * |[15:2] |F1SA |Rx FIFO 1 Start Address 721 * | | |Start address of Rx FIFO 1 in Message RAM (32-bit word address, refer to Figure 6.36 11). 722 * |[22:16] |F1S |Rx FIFO 1 Size 723 * | | |0= No Rx FIFO 1. 724 * | | |1-64 = Number of Rx FIFO 1 elements. 725 * | | |>64 = Values greater than 64 are interpreted as 64. 726 * | | |The Rx FIFO 1 elements are indexed from 0 to F1S - 1 727 * |[30:24] |F1WM |Rx FIFO 1 Watermark 728 * | | |0= Watermark interrupt disabled. 729 * | | |1-64 = Level for Rx FIFO 1 watermark interrupt (RF1W(CANFD_IR[5])). 730 * | | |>64 = Watermark interrupt disabled. 731 * |[31] |F1OM |FIFO 1 Operation Mode 732 * | | |FIFO 1 can be operated in blocking or in overwrite mode (refer to Rx FIFOs). 733 * | | |0= FIFO 1 blocking mode. 734 * | | |1= FIFO 1 overwrite mode. 735 * @var CANFD_T::RXF1S 736 * Offset: 0xB4 Rx FIFO 1 Status 737 * --------------------------------------------------------------------------------------------------- 738 * |Bits |Field |Descriptions 739 * | :----: | :----: | :---- | 740 * |[6:0] |F1FL |Rx FIFO 1 Fill Level 741 * | | |Number of elements stored in Rx FIFO 1, range 0 to 64 742 * |[13:8] |F1GI |Rx FIFO 1 Get Index 743 * | | |Rx FIFO 1 read index pointer, range 0 to 63. 744 * |[21:16] |F1PI |Rx FIFO 1 Fill Level 745 * | | |Number of elements stored in Rx FIFO 1, range 0 to 64. 746 * |[24] |F1F |Rx FIFO 1 Full 747 * | | |0 = Rx FIFO 1 is not full. 748 * | | |1 = Rx FIFO 1 is full. 749 * |[25] |RF1L |Rx FIFO 1 Message Lost 750 * | | |This bit is a copy of interrupt flag RF1L(CANFD_IR[7]) 751 * | | |When RF1L(CANFD_IR[7]) is reset, this bit is also reset 752 * | | |0= No Rx FIFO 1 message lost. 753 * | | |1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero. 754 * | | |Note: Overwriting the oldest message when F1OM (CANFD_RXF1C[31]) = 1 will not set this flag. 755 * @var CANFD_T::RXF1A 756 * Offset: 0xB8 Rx FIFO 1 Acknowledge 757 * --------------------------------------------------------------------------------------------------- 758 * |Bits |Field |Descriptions 759 * | :----: | :----: | :---- | 760 * |[5:0] |F1AI |Rx FIFO 1 Acknowledge Index 761 * | | |After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI 762 * | | |This will set the Rx FIFO 1 Get Index F1GI (CANFD_RXF1S[13:8]) to F1AI (CANFD_RXF1A[5:0]) + 1 and update the FIFO 1 Fill Level F1FL (CANFD_RXF1S[6:0]). 763 * @var CANFD_T::RXESC 764 * Offset: 0xBC Rx Buffer / FIFO Element Size Configuration 765 * --------------------------------------------------------------------------------------------------- 766 * |Bits |Field |Descriptions 767 * | :----: | :----: | :---- | 768 * |[2:0] |F0DS |Rx FIFO 0 Data Field Size 769 * | | |000 = 8 byte data field. 770 * | | |001 = 12 byte data field. 771 * | | |010 = 16 byte data field. 772 * | | |011 = 20 byte data field. 773 * | | |100 = 24 byte data field. 774 * | | |101 = 32 byte data field. 775 * | | |110 = 48 byte data field. 776 * | | |111 = 64 byte data field. 777 * | | |Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by CANFD_RXESC are stored to the Rx Buffer resp 778 * | | |Rx FIFO element 779 * | | |The rest of the frame data field is ignored. 780 * |[6:4] |F1DS |Rx FIFO 1 Data Field Size 781 * | | |000 = 8 byte data field. 782 * | | |001 = 12 byte data field. 783 * | | |010 = 16 byte data field. 784 * | | |011 = 20 byte data field. 785 * | | |100 = 24 byte data field. 786 * | | |101 = 32 byte data field. 787 * | | |110 = 48 byte data field. 788 * | | |111 = 64 byte data field. 789 * |[10:8] |RBDS |Rx Buffer Data Field Size 790 * | | |000 = 8 byte data field. 791 * | | |001 = 12 byte data field. 792 * | | |010 = 16 byte data field. 793 * | | |011 = 20 byte data field. 794 * | | |100 = 24 byte data field. 795 * | | |101 = 32 byte data field. 796 * | | |110 = 48 byte data field. 797 * | | |111 = 64 byte data field. 798 * @var CANFD_T::TXBC 799 * Offset: 0xC0 Tx Buffer Configuration 800 * --------------------------------------------------------------------------------------------------- 801 * |Bits |Field |Descriptions 802 * | :----: | :----: | :---- | 803 * |[15:2] |TBSA |Tx Buffers Start Address 804 * | | |Start address of Tx Buffers section in Message RAM (32-bit word address, refer to Figure 1.1-11). 805 * | | |Note: The sum of TFQS and NDTB may be not greater than 32 806 * | | |There is no check for erroneous configurations 807 * | | |The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers 808 * |[21:16] |NDTB |Number of Dedicated Transmit Buffers 809 * | | |0= No Dedicated Tx Buffers. 810 * | | |1-32= Number of Dedicated Tx Buffers. 811 * | | |>32= Values greater than 32 are interpreted as 32. 812 * |[29:24] |TFQS |Transmit FIFO/Queue Size 813 * | | |0= No Tx FIFO/Queue. 814 * | | |1-32= Number of Tx Buffers used for Tx FIFO/Queue. 815 * | | |>32= Values greater than 32 are interpreted as 32. 816 * |[30] |TFQM |Tx FIFO/Queue Mode 817 * | | |0= Tx FIFO operation. 818 * | | |1= Tx Queue operation. 819 * @var CANFD_T::TXFQS 820 * Offset: 0xC4 Tx FIFO/Queue Status 821 * --------------------------------------------------------------------------------------------------- 822 * |Bits |Field |Descriptions 823 * | :----: | :----: | :---- | 824 * |[5:0] |TFFL |Tx FIFO Free Level 825 * | | |Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32 826 * | | |Read as zero when Tx Queue operation is configured (TFQM (CANFD_TXBC[30]) = 1). 827 * | | |Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. 828 * | | |Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. 829 * |[12:8] |TFGI |Tx FIFO Get Index 830 * | | |Tx FIFO read index pointer, range 0 to 31 831 * | | |Read as zero when Tx Queue operation is configured (TFQM (CANFD_TXBC[30]) = 1). 832 * |[20:16] |TFQPI |Tx FIFO/Queue Put Index 833 * | | |Tx FIFO/Queue write index pointer, range 0 to 31. 834 * |[21] |TFQF |Tx FIFO/Queue Full 835 * | | |0= Tx FIFO/Queue is not full. 836 * | | |1= Tx FIFO/Queue is full. 837 * @var CANFD_T::TXESC 838 * Offset: 0xC8 Tx Buffer Element Size Configuration 839 * --------------------------------------------------------------------------------------------------- 840 * |Bits |Field |Descriptions 841 * | :----: | :----: | :---- | 842 * |[2:0] |TBDS |Tx Buffer Data Field Size 843 * | | |000 = 8 byte data field. 844 * | | |001 = 12 byte data field. 845 * | | |010 = 16 byte data field. 846 * | | |011 = 20 byte data field. 847 * | | |100 = 24 byte data field. 848 * | | |101 = 32 byte data field. 849 * | | |110 = 48 byte data field. 850 * | | |111 = 64 byte data field. 851 * | | |Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TBDS(CANFD_TXESC[2:0]), the bytes not defined by the Tx Buffer are transmitted as 0xCC (padding bytes). 852 * @var CANFD_T::TXBRP 853 * Offset: 0xCC Tx Buffer Request Pending 854 * --------------------------------------------------------------------------------------------------- 855 * |Bits |Field |Descriptions 856 * | :----: | :----: | :---- | 857 * |[31:0] |TRPn |Transmission Request Pending Each Tx Buffer has its own Transmission Request Pending bit The bits are set via register CANFD_TXBAR The bits are reset after a requested transmission has completed or has been cancelled via register CANFD_TXBCR 858 * | | |CANFD_TXBRP bits are set only for those Tx Buffers configured via CANFD_TXBC 859 * | | |After a CANFD_TXBRP bit has been set, a Tx scan (refer to 6.36.5.5, Tx Handling) is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID). 860 * | | |A cancellation request resets the corresponding transmission request pending bit of register CANFD_TXBRP 861 * | | |In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not 862 * | | |The cancellation request bits are reset directly after the corresponding CANFD_TXBRP bit has been reset. 863 * | | |After a cancellation has been requested, a finished cancellation is signaled via CANFD_TXBCF 864 * | | |�Eafter successful transmission together with the corresponding CANFD_TXBTO bit 865 * | | |�Ewhen the transmission has not yet been started at the point of cancellation 866 * | | |�Ewhen the transmission has been aborted due to lost arbitration 867 * | | |�Ewhen an error occurred during frame transmission 868 * | | |In DAR mode all transmissions are automatically cancelled if they are not successful 869 * | | |The corresponding CANFD_TXBCF bit is set for all unsuccessful transmissions. 870 * | | |0 = No transmission request pending. 871 * | | |1 = Transmission request pending. 872 * | | |Note: CANFD_TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan 873 * | | |In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding CANFD_TXBRP bit is reset. 874 * @var CANFD_T::TXBAR 875 * Offset: 0xD0 Tx Buffer Add Request 876 * --------------------------------------------------------------------------------------------------- 877 * |Bits |Field |Descriptions 878 * | :----: | :----: | :---- | 879 * |[31:0] |ARn |Add Request Each Tx Buffer has its own Add Request bit Writing a 1 will set the corresponding Add Request bit; writing a 0 has no impact This enables the Host to set transmission requests for multiple Tx Buffers with one write to CANFD_TXBAR CANFD_TXBAR bits are set only for those Tx Buffers configured via CANFD_TXBC When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed 880 * | | |0 = No transmission request added. 881 * | | |1 = Transmission requested added. 882 * | | |Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding CANFD_TXBRP bit already set), this add request is ignored. 883 * @var CANFD_T::TXBCR 884 * Offset: 0xD4 Tx Buffer Cancellation Request 885 * --------------------------------------------------------------------------------------------------- 886 * |Bits |Field |Descriptions 887 * | :----: | :----: | :---- | 888 * |[31:0] |CRn |Cancellation Request 889 * | | |Each Tx Buffer has its own Cancellation Request bit 890 * | | |Writing a 1 will set the corresponding Cancellation Request bit; writing a 0 has no impact 891 * | | |This enables the Host to set cancellation requests for multiple Tx Buffers with one write to CANFD_TXBCR 892 * | | |CANFD_TXBCR bits are set only for those Tx Buffers configured via CANFD_TXBC 893 * | | |The bits remain set until the corresponding bit of CANFD_TXBRP is reset. 894 * | | |0 = No cancellation pending. 895 * | | |1 = Cancellation pending. 896 * @var CANFD_T::TXBTO 897 * Offset: 0xD8 Tx Buffer Transmission Occurred 898 * --------------------------------------------------------------------------------------------------- 899 * |Bits |Field |Descriptions 900 * | :----: | :----: | :---- | 901 * |[31:0] |TOn |Transmission Occurred 902 * | | |Each Tx Buffer has its own Transmission Occurred bit 903 * | | |The bits are set when the corresponding CANFD_TXBRP bit is cleared after a successful transmission 904 * | | |The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register CANFD_TXBAR. 905 * | | |0 = No transmission occurred. 906 * | | |1 = Transmission occurred. 907 * @var CANFD_T::TXBCF 908 * Offset: 0xDC Tx Buffer Cancellation Finished 909 * --------------------------------------------------------------------------------------------------- 910 * |Bits |Field |Descriptions 911 * | :----: | :----: | :---- | 912 * |[31:0] |CFn |Cancellation Finished 913 * | | |Each Tx Buffer has its own Cancellation Finished bit 914 * | | |The bits are set when the corresponding CANFD_TXBRP bit is cleared after a cancellation was requested via CANFD_TXBCR 915 * | | |In case the corresponding CANFD_TXBRP bit was not set at the point of cancellation, CF is set immediately 916 * | | |The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register CANFD_TXBAR. 917 * | | |0 = No transmit buffer cancellation. 918 * | | |1 = Transmit buffer cancellation finished. 919 * @var CANFD_T::TXBTIE 920 * Offset: 0xE0 Tx Buffer Transmission Interrupt Enable 921 * --------------------------------------------------------------------------------------------------- 922 * |Bits |Field |Descriptions 923 * | :----: | :----: | :---- | 924 * |[31:0] |TIEn |Transmission Interrupt Enable 925 * | | |Each Tx Buffer has its own Transmission Interrupt enable bit. 926 * | | |0 = Transmission interrupt disabled. 927 * | | |1 = Transmission interrupt enable. 928 * @var CANFD_T::TXBCIE 929 * Offset: 0xE4 Tx Buffer Cancellation Finished Interrupt Enable 930 * --------------------------------------------------------------------------------------------------- 931 * |Bits |Field |Descriptions 932 * | :----: | :----: | :---- | 933 * |[31:0] |CFIEn |Cancellation Finished Interrupt Enable 934 * | | |Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 935 * | | |0 = Cancellation finished interrupt disabled. 936 * | | |1 = Cancellation finished interrupt enabled. 937 * @var CANFD_T::TXEFC 938 * Offset: 0xF0 Tx Event FIFO Configuration 939 * --------------------------------------------------------------------------------------------------- 940 * |Bits |Field |Descriptions 941 * | :----: | :----: | :---- | 942 * |[15:2] |EFSA |Event FIFO Start Address 943 * | | |Start address of Tx Event FIFO in Message RAM (32-bit word address, refer to Figure 6.36 11). 944 * |[21:16] |EFS |Event FIFO Size 945 * | | |0= Tx Event FIFO disabled. 946 * | | |1-32= Number of Tx Event FIFO elements. 947 * | | |>32= Values greater than 32 are interpreted as 32. 948 * | | |The Tx Event FIFO elements are indexed from 0 to EFS - 1 949 * |[29:24] |EFWM |Event FIFO Watermark 950 * | | |0 = Watermark interrupt disabled. 951 * | | |1-32= Level for Tx Event FIFO watermark interrupt (TEFW (CANFD_IR[13])). 952 * | | |>32= Watermark interrupt disabled. 953 * @var CANFD_T::TXEFS 954 * Offset: 0xF4 Tx Event FIFO Status 955 * --------------------------------------------------------------------------------------------------- 956 * |Bits |Field |Descriptions 957 * | :----: | :----: | :---- | 958 * |[5:0] |EFFL |Event FIFO Fill Level 959 * | | |Number of elements stored in Tx Event FIFO, range 0 to 32 960 * |[12:8] |EFGI |Event FIFO Get Index 961 * | | |Tx Event FIFO read index pointer, range 0 to 31 962 * |[20:16] |EFPI |Event FIFO Put Index 963 * | | |Tx Event FIFO write index pointer, range 0 to 31 964 * |[24] |EFF |Event FIFO Full 965 * | | |0= Tx Event FIFO is not full. 966 * | | |1= Tx Event FIFO is full. 967 * |[25] |TEFL |Tx Event FIFO Element Lost 968 * | | |This bit is a copy of interrupt flag TEFL (CANFD_IR[15]) 969 * | | |When TEFL is reset, this bit is also reset. 970 * | | |0= No Tx Event FIFO element lost. 971 * | | |1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. 972 * @var CANFD_T::TXEFA 973 * Offset: 0xF8 Tx Event FIFO Acknowledge 974 * --------------------------------------------------------------------------------------------------- 975 * |Bits |Field |Descriptions 976 * | :----: | :----: | :---- | 977 * |[4:0] |EFAI |Event FIFO Acknowledge Index 978 * | | |After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI 979 * | | |This will set the Tx Event FIFO Get Index EFGI (CANFD_TXEFS[12:8]) to EFAI + 1 and update the Event FIFO Fill Level EFFL (CANFD_TXEFS[5:0]) 980 */ 981 __I uint32_t RESERVE0[3]; 982 __IO uint32_t DBTP; /*!< [0x000c] Data Bit Timing & Prescaler Register */ 983 __IO uint32_t TEST; /*!< [0x0010] Test Register */ 984 __IO uint32_t RWD; /*!< [0x0014] RAM Watchdog */ 985 __IO uint32_t CCCR; /*!< [0x0018] CC Control Register */ 986 __IO uint32_t NBTP; /*!< [0x001c] Nominal Bit Timing & Prescaler Register */ 987 __IO uint32_t TSCC; /*!< [0x0020] Timestamp Counter Configuration */ 988 __IO uint32_t TSCV; /*!< [0x0024] Timestamp Counter Value */ 989 __IO uint32_t TOCC; /*!< [0x0028] Timeout Counter Configuration */ 990 __IO uint32_t TOCV; /*!< [0x002c] Timeout Counter Value */ 991 __I uint32_t RESERVE1[4]; 992 __I uint32_t ECR; /*!< [0x0040] Error Counter Register */ 993 __I uint32_t PSR; /*!< [0x0044] Protocol Status Register */ 994 __IO uint32_t TDCR; /*!< [0x0048] Transmitter Delay Compensation Register */ 995 __I uint32_t RESERVE2[1]; 996 __IO uint32_t IR; /*!< [0x0050] Interrupt Register */ 997 __IO uint32_t IE; /*!< [0x0054] Interrupt Enable */ 998 __IO uint32_t ILS; /*!< [0x0058] Interrupt Line Select */ 999 __IO uint32_t ILE; /*!< [0x005c] Interrupt Line Enable */ 1000 __I uint32_t RESERVE3[8]; 1001 __IO uint32_t GFC; /*!< [0x0080] Global Filter Configuration */ 1002 __IO uint32_t SIDFC; /*!< [0x0084] Standard ID Filter Configuration */ 1003 __IO uint32_t XIDFC; /*!< [0x0088] Extended ID Filter Configuration */ 1004 __I uint32_t RESERVE4[1]; 1005 __IO uint32_t XIDAM; /*!< [0x0090] Extended ID AND Mask */ 1006 __I uint32_t HPMS; /*!< [0x0094] High Priority Message Status */ 1007 __IO uint32_t NDAT1; /*!< [0x0098] New Data 1 */ 1008 __IO uint32_t NDAT2; /*!< [0x009c] New Data 2 */ 1009 __IO uint32_t RXF0C; /*!< [0x00a0] Rx FIFO 0 Configuration */ 1010 __IO uint32_t RXF0S; /*!< [0x00a4] Rx FIFO 0 Status */ 1011 __IO uint32_t RXF0A; /*!< [0x00a8] Rx FIFO 0 Acknowledge */ 1012 __IO uint32_t RXBC; /*!< [0x00ac] Rx Buffer Configuration */ 1013 __IO uint32_t RXF1C; /*!< [0x00b0] Rx FIFO 1 Configuration */ 1014 __IO uint32_t RXF1S; /*!< [0x00b4] Rx FIFO 1 Status */ 1015 __IO uint32_t RXF1A; /*!< [0x00b8] Rx FIFO 1 Acknowledge */ 1016 __IO uint32_t RXESC; /*!< [0x00bc] Rx Buffer / FIFO Element Size Configuration */ 1017 __IO uint32_t TXBC; /*!< [0x00c0] Tx Buffer Configuration */ 1018 __IO uint32_t TXFQS; /*!< [0x00c4] Tx FIFO/Queue Status */ 1019 __IO uint32_t TXESC; /*!< [0x00c8] Tx Buffer Element Size Configuration */ 1020 __IO uint32_t TXBRP; /*!< [0x00cc] Tx Buffer Request Pending */ 1021 __IO uint32_t TXBAR; /*!< [0x00d0] Tx Buffer Add Request */ 1022 __IO uint32_t TXBCR; /*!< [0x00d4] Tx Buffer Cancellation Request */ 1023 __IO uint32_t TXBTO; /*!< [0x00d8] Tx Buffer Transmission Occurred */ 1024 __IO uint32_t TXBCF; /*!< [0x00dc] Tx Buffer Cancellation Finished */ 1025 __IO uint32_t TXBTIE; /*!< [0x00e0] Tx Buffer Transmission Interrupt Enable */ 1026 __IO uint32_t TXBCIE; /*!< [0x00e4] Tx Buffer Cancellation Finished Interrupt Enable */ 1027 __I uint32_t RESERVE5[2]; 1028 __IO uint32_t TXEFC; /*!< [0x00f0] Tx Event FIFO Configuration */ 1029 __IO uint32_t TXEFS; /*!< [0x00f4] Tx Event FIFO Status */ 1030 __IO uint32_t TXEFA; /*!< [0x00f8] Tx Event FIFO Acknowledge */ 1031 1032 } CANFD_T; 1033 1034 /** 1035 @addtogroup CANFD_CONST CANFD Bit Field Definition 1036 Constant Definitions for CANFD Controller 1037 @{ */ 1038 1039 #define CANFD_DBTP_DSJW_Pos (0) /*!< CANFD_T::DBTP: DSJW Position */ 1040 #define CANFD_DBTP_DSJW_Msk (0xful << CANFD_DBTP_DSJW_Pos) /*!< CANFD_T::DBTP: DSJW Mask */ 1041 1042 #define CANFD_DBTP_DTSEG2_Pos (4) /*!< CANFD_T::DBTP: DTSEG2 Position */ 1043 #define CANFD_DBTP_DTSEG2_Msk (0xful << CANFD_DBTP_DTSEG2_Pos) /*!< CANFD_T::DBTP: DTSEG2 Mask */ 1044 1045 #define CANFD_DBTP_DTSEG1_Pos (8) /*!< CANFD_T::DBTP: DTSEG1 Position */ 1046 #define CANFD_DBTP_DTSEG1_Msk (0x1ful << CANFD_DBTP_DTSEG1_Pos) /*!< CANFD_T::DBTP: DTSEG1 Mask */ 1047 1048 #define CANFD_DBTP_DBRP_Pos (16) /*!< CANFD_T::DBTP: DBRP Position */ 1049 #define CANFD_DBTP_DBRP_Msk (0x1ful << CANFD_DBTP_DBRP_Pos) /*!< CANFD_T::DBTP: DBRP Mask */ 1050 1051 #define CANFD_DBTP_TDC_Pos (23) /*!< CANFD_T::DBTP: TDC Position */ 1052 #define CANFD_DBTP_TDC_Msk (0x1ul << CANFD_DBTP_TDC_Pos) /*!< CANFD_T::DBTP: TDC Mask */ 1053 1054 #define CANFD_TEST_LBCK_Pos (4) /*!< CANFD_T::TEST: LBCK Position */ 1055 #define CANFD_TEST_LBCK_Msk (0x1ul << CANFD_TEST_LBCK_Pos) /*!< CANFD_T::TEST: LBCK Mask */ 1056 1057 #define CANFD_TEST_TX_Pos (5) /*!< CANFD_T::TEST: TX Position */ 1058 #define CANFD_TEST_TX_Msk (0x3ul << CANFD_TEST_TX_Pos) /*!< CANFD_T::TEST: TX Mask */ 1059 1060 #define CANFD_TEST_RX_Pos (7) /*!< CANFD_T::TEST: RX Position */ 1061 #define CANFD_TEST_RX_Msk (0x1ul << CANFD_TEST_RX_Pos) /*!< CANFD_T::TEST: RX Mask */ 1062 1063 #define CANFD_RWD_WDC_Pos (0) /*!< CANFD_T::RWD: WDC Position */ 1064 #define CANFD_RWD_WDC_Msk (0xfful << CANFD_RWD_WDC_Pos) /*!< CANFD_T::RWD: WDC Mask */ 1065 1066 #define CANFD_RWD_WDV_Pos (8) /*!< CANFD_T::RWD: WDV Position */ 1067 #define CANFD_RWD_WDV_Msk (0xfful << CANFD_RWD_WDV_Pos) /*!< CANFD_T::RWD: WDV Mask */ 1068 1069 #define CANFD_CCCR_INIT_Pos (0) /*!< CANFD_T::CCCR: INIT Position */ 1070 #define CANFD_CCCR_INIT_Msk (0x1ul << CANFD_CCCR_INIT_Pos) /*!< CANFD_T::CCCR: INIT Mask */ 1071 1072 #define CANFD_CCCR_CCE_Pos (1) /*!< CANFD_T::CCCR: CCE Position */ 1073 #define CANFD_CCCR_CCE_Msk (0x1ul << CANFD_CCCR_CCE_Pos) /*!< CANFD_T::CCCR: CCE Mask */ 1074 1075 #define CANFD_CCCR_ASM_Pos (2) /*!< CANFD_T::CCCR: ASM Position */ 1076 #define CANFD_CCCR_ASM_Msk (0x1ul << CANFD_CCCR_ASM_Pos) /*!< CANFD_T::CCCR: ASM Mask */ 1077 1078 #define CANFD_CCCR_CSA_Pos (3) /*!< CANFD_T::CCCR: CSA Position */ 1079 #define CANFD_CCCR_CSA_Msk (0x1ul << CANFD_CCCR_CSA_Pos) /*!< CANFD_T::CCCR: CSA Mask */ 1080 1081 #define CANFD_CCCR_CSR_Pos (4) /*!< CANFD_T::CCCR: CSR Position */ 1082 #define CANFD_CCCR_CSR_Msk (0x1ul << CANFD_CCCR_CSR_Pos) /*!< CANFD_T::CCCR: CSR Mask */ 1083 1084 #define CANFD_CCCR_MON_Pos (5) /*!< CANFD_T::CCCR: MON Position */ 1085 #define CANFD_CCCR_MON_Msk (0x1ul << CANFD_CCCR_MON_Pos) /*!< CANFD_T::CCCR: MON Mask */ 1086 1087 #define CANFD_CCCR_DAR_Pos (6) /*!< CANFD_T::CCCR: DAR Position */ 1088 #define CANFD_CCCR_DAR_Msk (0x1ul << CANFD_CCCR_DAR_Pos) /*!< CANFD_T::CCCR: DAR Mask */ 1089 1090 #define CANFD_CCCR_TEST_Pos (7) /*!< CANFD_T::CCCR: TEST Position */ 1091 #define CANFD_CCCR_TEST_Msk (0x1ul << CANFD_CCCR_TEST_Pos) /*!< CANFD_T::CCCR: TEST Mask */ 1092 1093 #define CANFD_CCCR_FDOE_Pos (8) /*!< CANFD_T::CCCR: FDOE Position */ 1094 #define CANFD_CCCR_FDOE_Msk (0x1ul << CANFD_CCCR_FDOE_Pos) /*!< CANFD_T::CCCR: FDOE Mask */ 1095 1096 #define CANFD_CCCR_BRSE_Pos (9) /*!< CANFD_T::CCCR: BRSE Position */ 1097 #define CANFD_CCCR_BRSE_Msk (0x1ul << CANFD_CCCR_BRSE_Pos) /*!< CANFD_T::CCCR: BRSE Mask */ 1098 1099 #define CANFD_CCCR_PXHD_Pos (12) /*!< CANFD_T::CCCR: PXHD Position */ 1100 #define CANFD_CCCR_PXHD_Msk (0x1ul << CANFD_CCCR_PXHD_Pos) /*!< CANFD_T::CCCR: PXHD Mask */ 1101 1102 #define CANFD_CCCR_EFBI_Pos (13) /*!< CANFD_T::CCCR: EFBI Position */ 1103 #define CANFD_CCCR_EFBI_Msk (0x1ul << CANFD_CCCR_EFBI_Pos) /*!< CANFD_T::CCCR: EFBI Mask */ 1104 1105 #define CANFD_CCCR_TXP_Pos (14) /*!< CANFD_T::CCCR: TXP Position */ 1106 #define CANFD_CCCR_TXP_Msk (0x1ul << CANFD_CCCR_TXP_Pos) /*!< CANFD_T::CCCR: TXP Mask */ 1107 1108 #define CANFD_CCCR_NISO_Pos (15) /*!< CANFD_T::CCCR: NISO Position */ 1109 #define CANFD_CCCR_NISO_Msk (0x1ul << CANFD_CCCR_NISO_Pos) /*!< CANFD_T::CCCR: NISO Mask */ 1110 1111 #define CANFD_NBTP_NTSEG2_Pos (0) /*!< CANFD_T::NBTP: NTSEG2 Position */ 1112 #define CANFD_NBTP_NTSEG2_Msk (0x7ful << CANFD_NBTP_NTSEG2_Pos) /*!< CANFD_T::NBTP: NTSEG2 Mask */ 1113 1114 #define CANFD_NBTP_NTSEG1_Pos (8) /*!< CANFD_T::NBTP: NTSEG1 Position */ 1115 #define CANFD_NBTP_NTSEG1_Msk (0xfful << CANFD_NBTP_NTSEG1_Pos) /*!< CANFD_T::NBTP: NTSEG1 Mask */ 1116 1117 #define CANFD_NBTP_NBRP_Pos (16) /*!< CANFD_T::NBTP: NBRP Position */ 1118 #define CANFD_NBTP_NBRP_Msk (0x1fful << CANFD_NBTP_NBRP_Pos) /*!< CANFD_T::NBTP: NBRP Mask */ 1119 1120 #define CANFD_NBTP_NSJW_Pos (25) /*!< CANFD_T::NBTP: NSJW Position */ 1121 #define CANFD_NBTP_NSJW_Msk (0x7ful << CANFD_NBTP_NSJW_Pos) /*!< CANFD_T::NBTP: NSJW Mask */ 1122 1123 #define CANFD_TSCC_TSS_Pos (0) /*!< CANFD_T::TSCC: TSS Position */ 1124 #define CANFD_TSCC_TSS_Msk (0x3ul << CANFD_TSCC_TSS_Pos) /*!< CANFD_T::TSCC: TSS Mask */ 1125 1126 #define CANFD_TSCC_TCP_Pos (16) /*!< CANFD_T::TSCC: TCP Position */ 1127 #define CANFD_TSCC_TCP_Msk (0xful << CANFD_TSCC_TCP_Pos) /*!< CANFD_T::TSCC: TCP Mask */ 1128 1129 #define CANFD_TSCV_TSC_Pos (0) /*!< CANFD_T::TSCV: TSC Position */ 1130 #define CANFD_TSCV_TSC_Msk (0xfffful << CANFD_TSCV_TSC_Pos) /*!< CANFD_T::TSCV: TSC Mask */ 1131 1132 #define CANFD_TOCC_ETOC_Pos (0) /*!< CANFD_T::TOCC: ETOC Position */ 1133 #define CANFD_TOCC_ETOC_Msk (0x1ul << CANFD_TOCC_ETOC_Pos) /*!< CANFD_T::TOCC: ETOC Mask */ 1134 1135 #define CANFD_TOCC_TOS_Pos (1) /*!< CANFD_T::TOCC: TOS Position */ 1136 #define CANFD_TOCC_TOS_Msk (0x3ul << CANFD_TOCC_TOS_Pos) /*!< CANFD_T::TOCC: TOS Mask */ 1137 1138 #define CANFD_TOCC_TOP_Pos (16) /*!< CANFD_T::TOCC: TOP Position */ 1139 #define CANFD_TOCC_TOP_Msk (0xfffful << CANFD_TOCC_TOP_Pos) /*!< CANFD_T::TOCC: TOP Mask */ 1140 1141 #define CANFD_TOCV_TOC_Pos (0) /*!< CANFD_T::TOCV: TOC Position */ 1142 #define CANFD_TOCV_TOC_Msk (0xfffful << CANFD_TOCV_TOC_Pos) /*!< CANFD_T::TOCV: TOC Mask */ 1143 1144 #define CANFD_ECR_TEC_Pos (0) /*!< CANFD_T::ECR: TEC Position */ 1145 #define CANFD_ECR_TEC_Msk (0xfful << CANFD_ECR_TEC_Pos) /*!< CANFD_T::ECR: TEC Mask */ 1146 1147 #define CANFD_ECR_REC_Pos (8) /*!< CANFD_T::ECR: REC Position */ 1148 #define CANFD_ECR_REC_Msk (0x7ful << CANFD_ECR_REC_Pos) /*!< CANFD_T::ECR: REC Mask */ 1149 1150 #define CANFD_ECR_RP_Pos (15) /*!< CANFD_T::ECR: RP Position */ 1151 #define CANFD_ECR_RP_Msk (0x1ul << CANFD_ECR_RP_Pos) /*!< CANFD_T::ECR: RP Mask */ 1152 1153 #define CANFD_ECR_CEL_Pos (16) /*!< CANFD_T::ECR: CEL Position */ 1154 #define CANFD_ECR_CEL_Msk (0xfful << CANFD_ECR_CEL_Pos) /*!< CANFD_T::ECR: CEL Mask */ 1155 1156 #define CANFD_PSR_LEC_Pos (0) /*!< CANFD_T::PSR: LEC Position */ 1157 #define CANFD_PSR_LEC_Msk (0x7ul << CANFD_PSR_LEC_Pos) /*!< CANFD_T::PSR: LEC Mask */ 1158 1159 #define CANFD_PSR_ACT_Pos (3) /*!< CANFD_T::PSR: ACT Position */ 1160 #define CANFD_PSR_ACT_Msk (0x3ul << CANFD_PSR_ACT_Pos) /*!< CANFD_T::PSR: ACT Mask */ 1161 1162 #define CANFD_PSR_EP_Pos (5) /*!< CANFD_T::PSR: EP Position */ 1163 #define CANFD_PSR_EP_Msk (0x1ul << CANFD_PSR_EP_Pos) /*!< CANFD_T::PSR: EP Mask */ 1164 1165 #define CANFD_PSR_EW_Pos (6) /*!< CANFD_T::PSR: EW Position */ 1166 #define CANFD_PSR_EW_Msk (0x1ul << CANFD_PSR_EW_Pos) /*!< CANFD_T::PSR: EW Mask */ 1167 1168 #define CANFD_PSR_BO_Pos (7) /*!< CANFD_T::PSR: BO Position */ 1169 #define CANFD_PSR_BO_Msk (0x1ul << CANFD_PSR_BO_Pos) /*!< CANFD_T::PSR: BO Mask */ 1170 1171 #define CANFD_PSR_DLEC_Pos (8) /*!< CANFD_T::PSR: DLEC Position */ 1172 #define CANFD_PSR_DLEC_Msk (0x7ul << CANFD_PSR_DLEC_Pos) /*!< CANFD_T::PSR: DLEC Mask */ 1173 1174 #define CANFD_PSR_RESI_Pos (11) /*!< CANFD_T::PSR: RESI Position */ 1175 #define CANFD_PSR_RESI_Msk (0x1ul << CANFD_PSR_RESI_Pos) /*!< CANFD_T::PSR: RESI Mask */ 1176 1177 #define CANFD_PSR_RBRS_Pos (12) /*!< CANFD_T::PSR: RBRS Position */ 1178 #define CANFD_PSR_RBRS_Msk (0x1ul << CANFD_PSR_RBRS_Pos) /*!< CANFD_T::PSR: RBRS Mask */ 1179 1180 #define CANFD_PSR_RFDF_Pos (13) /*!< CANFD_T::PSR: RFDF Position */ 1181 #define CANFD_PSR_RFDF_Msk (0x1ul << CANFD_PSR_RFDF_Pos) /*!< CANFD_T::PSR: RFDF Mask */ 1182 1183 #define CANFD_PSR_PXE_Pos (14) /*!< CANFD_T::PSR: PXE Position */ 1184 #define CANFD_PSR_PXE_Msk (0x1ul << CANFD_PSR_PXE_Pos) /*!< CANFD_T::PSR: PXE Mask */ 1185 1186 #define CANFD_PSR_TDCV_Pos (16) /*!< CANFD_T::PSR: TDCV Position */ 1187 #define CANFD_PSR_TDCV_Msk (0x7ful << CANFD_PSR_TDCV_Pos) /*!< CANFD_T::PSR: TDCV Mask */ 1188 1189 #define CANFD_TDCR_TDCF_Pos (0) /*!< CANFD_T::TDCR: TDCF Position */ 1190 #define CANFD_TDCR_TDCF_Msk (0x7ful << CANFD_TDCR_TDCF_Pos) /*!< CANFD_T::TDCR: TDCF Mask */ 1191 1192 #define CANFD_TDCR_TDCO_Pos (8) /*!< CANFD_T::TDCR: TDCO Position */ 1193 #define CANFD_TDCR_TDCO_Msk (0x7ful << CANFD_TDCR_TDCO_Pos) /*!< CANFD_T::TDCR: TDCO Mask */ 1194 1195 #define CANFD_IR_RF0N_Pos (0) /*!< CANFD_T::IR: RF0N Position */ 1196 #define CANFD_IR_RF0N_Msk (0x1ul << CANFD_IR_RF0N_Pos) /*!< CANFD_T::IR: RF0N Mask */ 1197 1198 #define CANFD_IR_RF0W_Pos (1) /*!< CANFD_T::IR: RF0W Position */ 1199 #define CANFD_IR_RF0W_Msk (0x1ul << CANFD_IR_RF0W_Pos) /*!< CANFD_T::IR: RF0W Mask */ 1200 1201 #define CANFD_IR_RF0F_Pos (2) /*!< CANFD_T::IR: RF0F Position */ 1202 #define CANFD_IR_RF0F_Msk (0x1ul << CANFD_IR_RF0F_Pos) /*!< CANFD_T::IR: RF0F Mask */ 1203 1204 #define CANFD_IR_RF0L_Pos (3) /*!< CANFD_T::IR: RF0L Position */ 1205 #define CANFD_IR_RF0L_Msk (0x1ul << CANFD_IR_RF0L_Pos) /*!< CANFD_T::IR: RF0L Mask */ 1206 1207 #define CANFD_IR_RF1N_Pos (4) /*!< CANFD_T::IR: RF1N Position */ 1208 #define CANFD_IR_RF1N_Msk (0x1ul << CANFD_IR_RF1N_Pos) /*!< CANFD_T::IR: RF1N Mask */ 1209 1210 #define CANFD_IR_RF1W_Pos (5) /*!< CANFD_T::IR: RF1W Position */ 1211 #define CANFD_IR_RF1W_Msk (0x1ul << CANFD_IR_RF1W_Pos) /*!< CANFD_T::IR: RF1W Mask */ 1212 1213 #define CANFD_IR_RF1F_Pos (6) /*!< CANFD_T::IR: RF1F Position */ 1214 #define CANFD_IR_RF1F_Msk (0x1ul << CANFD_IR_RF1F_Pos) /*!< CANFD_T::IR: RF1F Mask */ 1215 1216 #define CANFD_IR_RF1L_Pos (7) /*!< CANFD_T::IR: RF1L Position */ 1217 #define CANFD_IR_RF1L_Msk (0x1ul << CANFD_IR_RF1L_Pos) /*!< CANFD_T::IR: RF1L Mask */ 1218 1219 #define CANFD_IR_HPM_Pos (8) /*!< CANFD_T::IR: HPM Position */ 1220 #define CANFD_IR_HPM_Msk (0x1ul << CANFD_IR_HPM_Pos) /*!< CANFD_T::IR: HPM Mask */ 1221 1222 #define CANFD_IR_TC_Pos (9) /*!< CANFD_T::IR: TC Position */ 1223 #define CANFD_IR_TC_Msk (0x1ul << CANFD_IR_TC_Pos) /*!< CANFD_T::IR: TC Mask */ 1224 1225 #define CANFD_IR_TCF_Pos (10) /*!< CANFD_T::IR: TCF Position */ 1226 #define CANFD_IR_TCF_Msk (0x1ul << CANFD_IR_TCF_Pos) /*!< CANFD_T::IR: TCF Mask */ 1227 1228 #define CANFD_IR_TFE_Pos (11) /*!< CANFD_T::IR: TFE Position */ 1229 #define CANFD_IR_TFE_Msk (0x1ul << CANFD_IR_TFE_Pos) /*!< CANFD_T::IR: TFE Mask */ 1230 1231 #define CANFD_IR_TEFN_Pos (12) /*!< CANFD_T::IR: TEFN Position */ 1232 #define CANFD_IR_TEFN_Msk (0x1ul << CANFD_IR_TEFN_Pos) /*!< CANFD_T::IR: TEFN Mask */ 1233 1234 #define CANFD_IR_TEFW_Pos (13) /*!< CANFD_T::IR: TEFW Position */ 1235 #define CANFD_IR_TEFW_Msk (0x1ul << CANFD_IR_TEFW_Pos) /*!< CANFD_T::IR: TEFW Mask */ 1236 1237 #define CANFD_IR_TEFF_Pos (14) /*!< CANFD_T::IR: TEFF Position */ 1238 #define CANFD_IR_TEFF_Msk (0x1ul << CANFD_IR_TEFF_Pos) /*!< CANFD_T::IR: TEFF Mask */ 1239 1240 #define CANFD_IR_TEFL_Pos (15) /*!< CANFD_T::IR: TEFL Position */ 1241 #define CANFD_IR_TEFL_Msk (0x1ul << CANFD_IR_TEFL_Pos) /*!< CANFD_T::IR: TEFL Mask */ 1242 1243 #define CANFD_IR_TSW_Pos (16) /*!< CANFD_T::IR: TSW Position */ 1244 #define CANFD_IR_TSW_Msk (0x1ul << CANFD_IR_TSW_Pos) /*!< CANFD_T::IR: TSW Mask */ 1245 1246 #define CANFD_IR_MRAF_Pos (17) /*!< CANFD_T::IR: MRAF Position */ 1247 #define CANFD_IR_MRAF_Msk (0x1ul << CANFD_IR_MRAF_Pos) /*!< CANFD_T::IR: MRAF Mask */ 1248 1249 #define CANFD_IR_TOO_Pos (18) /*!< CANFD_T::IR: TOO Position */ 1250 #define CANFD_IR_TOO_Msk (0x1ul << CANFD_IR_TOO_Pos) /*!< CANFD_T::IR: TOO Mask */ 1251 1252 #define CANFD_IR_DRX_Pos (19) /*!< CANFD_T::IR: DRX Position */ 1253 #define CANFD_IR_DRX_Msk (0x1ul << CANFD_IR_DRX_Pos) /*!< CANFD_T::IR: DRX Mask */ 1254 1255 #define CANFD_IR_ELO_Pos (22) /*!< CANFD_T::IR: ELO Position */ 1256 #define CANFD_IR_ELO_Msk (0x1ul << CANFD_IR_ELO_Pos) /*!< CANFD_T::IR: ELO Mask */ 1257 1258 #define CANFD_IR_EP_Pos (23) /*!< CANFD_T::IR: EP Position */ 1259 #define CANFD_IR_EP_Msk (0x1ul << CANFD_IR_EP_Pos) /*!< CANFD_T::IR: EP Mask */ 1260 1261 #define CANFD_IR_EW_Pos (24) /*!< CANFD_T::IR: EW Position */ 1262 #define CANFD_IR_EW_Msk (0x1ul << CANFD_IR_EW_Pos) /*!< CANFD_T::IR: EW Mask */ 1263 1264 #define CANFD_IR_BO_Pos (25) /*!< CANFD_T::IR: BO Position */ 1265 #define CANFD_IR_BO_Msk (0x1ul << CANFD_IR_BO_Pos) /*!< CANFD_T::IR: BO Mask */ 1266 1267 #define CANFD_IR_WDI_Pos (26) /*!< CANFD_T::IR: WDI Position */ 1268 #define CANFD_IR_WDI_Msk (0x1ul << CANFD_IR_WDI_Pos) /*!< CANFD_T::IR: WDI Mask */ 1269 1270 #define CANFD_IR_PEA_Pos (27) /*!< CANFD_T::IR: PEA Position */ 1271 #define CANFD_IR_PEA_Msk (0x1ul << CANFD_IR_PEA_Pos) /*!< CANFD_T::IR: PEA Mask */ 1272 1273 #define CANFD_IR_PED_Pos (28) /*!< CANFD_T::IR: PED Position */ 1274 #define CANFD_IR_PED_Msk (0x1ul << CANFD_IR_PED_Pos) /*!< CANFD_T::IR: PED Mask */ 1275 1276 #define CANFD_IR_ARA_Pos (29) /*!< CANFD_T::IR: ARA Position */ 1277 #define CANFD_IR_ARA_Msk (0x1ul << CANFD_IR_ARA_Pos) /*!< CANFD_T::IR: ARA Mask */ 1278 1279 #define CANFD_IE_RF0NE_Pos (0) /*!< CANFD_T::IE: RF0NE Position */ 1280 #define CANFD_IE_RF0NE_Msk (0x1ul << CANFD_IE_RF0NE_Pos) /*!< CANFD_T::IE: RF0NE Mask */ 1281 1282 #define CANFD_IE_RF0WE_Pos (1) /*!< CANFD_T::IE: RF0WE Position */ 1283 #define CANFD_IE_RF0WE_Msk (0x1ul << CANFD_IE_RF0WE_Pos) /*!< CANFD_T::IE: RF0WE Mask */ 1284 1285 #define CANFD_IE_RF0FE_Pos (2) /*!< CANFD_T::IE: RF0FE Position */ 1286 #define CANFD_IE_RF0FE_Msk (0x1ul << CANFD_IE_RF0FE_Pos) /*!< CANFD_T::IE: RF0FE Mask */ 1287 1288 #define CANFD_IE_RF0LE_Pos (3) /*!< CANFD_T::IE: RF0LE Position */ 1289 #define CANFD_IE_RF0LE_Msk (0x1ul << CANFD_IE_RF0LE_Pos) /*!< CANFD_T::IE: RF0LE Mask */ 1290 1291 #define CANFD_IE_RF1NE_Pos (4) /*!< CANFD_T::IE: RF1NE Position */ 1292 #define CANFD_IE_RF1NE_Msk (0x1ul << CANFD_IE_RF1NE_Pos) /*!< CANFD_T::IE: RF1NE Mask */ 1293 1294 #define CANFD_IE_RF1WE_Pos (5) /*!< CANFD_T::IE: RF1WE Position */ 1295 #define CANFD_IE_RF1WE_Msk (0x1ul << CANFD_IE_RF1WE_Pos) /*!< CANFD_T::IE: RF1WE Mask */ 1296 1297 #define CANFD_IE_RF1FE_Pos (6) /*!< CANFD_T::IE: RF1FE Position */ 1298 #define CANFD_IE_RF1FE_Msk (0x1ul << CANFD_IE_RF1FE_Pos) /*!< CANFD_T::IE: RF1FE Mask */ 1299 1300 #define CANFD_IE_RF1LE_Pos (7) /*!< CANFD_T::IE: RF1LE Position */ 1301 #define CANFD_IE_RF1LE_Msk (0x1ul << CANFD_IE_RF1LE_Pos) /*!< CANFD_T::IE: RF1LE Mask */ 1302 1303 #define CANFD_IE_HPME_Pos (8) /*!< CANFD_T::IE: HPME Position */ 1304 #define CANFD_IE_HPME_Msk (0x1ul << CANFD_IE_HPME_Pos) /*!< CANFD_T::IE: HPME Mask */ 1305 1306 #define CANFD_IE_TCE_Pos (9) /*!< CANFD_T::IE: TCE Position */ 1307 #define CANFD_IE_TCE_Msk (0x1ul << CANFD_IE_TCE_Pos) /*!< CANFD_T::IE: TCE Mask */ 1308 1309 #define CANFD_IE_TCFE_Pos (10) /*!< CANFD_T::IE: TCFE Position */ 1310 #define CANFD_IE_TCFE_Msk (0x1ul << CANFD_IE_TCFE_Pos) /*!< CANFD_T::IE: TCFE Mask */ 1311 1312 #define CANFD_IE_TFEE_Pos (11) /*!< CANFD_T::IE: TFEE Position */ 1313 #define CANFD_IE_TFEE_Msk (0x1ul << CANFD_IE_TFEE_Pos) /*!< CANFD_T::IE: TFEE Mask */ 1314 1315 #define CANFD_IE_TEFNE_Pos (12) /*!< CANFD_T::IE: TEFNE Position */ 1316 #define CANFD_IE_TEFNE_Msk (0x1ul << CANFD_IE_TEFNE_Pos) /*!< CANFD_T::IE: TEFNE Mask */ 1317 1318 #define CANFD_IE_TEFWE_Pos (13) /*!< CANFD_T::IE: TEFWE Position */ 1319 #define CANFD_IE_TEFWE_Msk (0x1ul << CANFD_IE_TEFWE_Pos) /*!< CANFD_T::IE: TEFWE Mask */ 1320 1321 #define CANFD_IE_TEFFE_Pos (14) /*!< CANFD_T::IE: TEFFE Position */ 1322 #define CANFD_IE_TEFFE_Msk (0x1ul << CANFD_IE_TEFFE_Pos) /*!< CANFD_T::IE: TEFFE Mask */ 1323 1324 #define CANFD_IE_TEFLE_Pos (15) /*!< CANFD_T::IE: TEFLE Position */ 1325 #define CANFD_IE_TEFLE_Msk (0x1ul << CANFD_IE_TEFLE_Pos) /*!< CANFD_T::IE: TEFLE Mask */ 1326 1327 #define CANFD_IE_TSWE_Pos (16) /*!< CANFD_T::IE: TSWE Position */ 1328 #define CANFD_IE_TSWE_Msk (0x1ul << CANFD_IE_TSWE_Pos) /*!< CANFD_T::IE: TSWE Mask */ 1329 1330 #define CANFD_IE_MRAFE_Pos (17) /*!< CANFD_T::IE: MRAFE Position */ 1331 #define CANFD_IE_MRAFE_Msk (0x1ul << CANFD_IE_MRAFE_Pos) /*!< CANFD_T::IE: MRAFE Mask */ 1332 1333 #define CANFD_IE_TOOE_Pos (18) /*!< CANFD_T::IE: TOOE Position */ 1334 #define CANFD_IE_TOOE_Msk (0x1ul << CANFD_IE_TOOE_Pos) /*!< CANFD_T::IE: TOOE Mask */ 1335 1336 #define CANFD_IE_DRXE_Pos (19) /*!< CANFD_T::IE: DRXE Position */ 1337 #define CANFD_IE_DRXE_Msk (0x1ul << CANFD_IE_DRXE_Pos) /*!< CANFD_T::IE: DRXE Mask */ 1338 1339 #define CANFD_IE_BECE_Pos (20) /*!< CANFD_T::IE: BECE Position */ 1340 #define CANFD_IE_BECE_Msk (0x1ul << CANFD_IE_BECE_Pos) /*!< CANFD_T::IE: BECE Mask */ 1341 1342 #define CANFD_IE_BEUE_Pos (21) /*!< CANFD_T::IE: BEUE Position */ 1343 #define CANFD_IE_BEUE_Msk (0x1ul << CANFD_IE_BEUE_Pos) /*!< CANFD_T::IE: BEUE Mask */ 1344 1345 #define CANFD_IE_ELOE_Pos (22) /*!< CANFD_T::IE: ELOE Position */ 1346 #define CANFD_IE_ELOE_Msk (0x1ul << CANFD_IE_ELOE_Pos) /*!< CANFD_T::IE: ELOE Mask */ 1347 1348 #define CANFD_IE_EPE_Pos (23) /*!< CANFD_T::IE: EPE Position */ 1349 #define CANFD_IE_EPE_Msk (0x1ul << CANFD_IE_EPE_Pos) /*!< CANFD_T::IE: EPE Mask */ 1350 1351 #define CANFD_IE_EWE_Pos (24) /*!< CANFD_T::IE: EWE Position */ 1352 #define CANFD_IE_EWE_Msk (0x1ul << CANFD_IE_EWE_Pos) /*!< CANFD_T::IE: EWE Mask */ 1353 1354 #define CANFD_IE_BOE_Pos (25) /*!< CANFD_T::IE: BOE Position */ 1355 #define CANFD_IE_BOE_Msk (0x1ul << CANFD_IE_BOE_Pos) /*!< CANFD_T::IE: BOE Mask */ 1356 1357 #define CANFD_IE_WDIE_Pos (26) /*!< CANFD_T::IE: WDIE Position */ 1358 #define CANFD_IE_WDIE_Msk (0x1ul << CANFD_IE_WDIE_Pos) /*!< CANFD_T::IE: WDIE Mask */ 1359 1360 #define CANFD_IE_PEAE_Pos (27) /*!< CANFD_T::IE: PEAE Position */ 1361 #define CANFD_IE_PEAE_Msk (0x1ul << CANFD_IE_PEAE_Pos) /*!< CANFD_T::IE: PEAE Mask */ 1362 1363 #define CANFD_IE_PEDE_Pos (28) /*!< CANFD_T::IE: PEDE Position */ 1364 #define CANFD_IE_PEDE_Msk (0x1ul << CANFD_IE_PEDE_Pos) /*!< CANFD_T::IE: PEDE Mask */ 1365 1366 #define CANFD_IE_ARAE_Pos (29) /*!< CANFD_T::IE: ARAE Position */ 1367 #define CANFD_IE_ARAE_Msk (0x1ul << CANFD_IE_ARAE_Pos) /*!< CANFD_T::IE: ARAE Mask */ 1368 1369 #define CANFD_ILS_RF0NL_Pos (0) /*!< CANFD_T::ILS: RF0NL Position */ 1370 #define CANFD_ILS_RF0NL_Msk (0x1ul << CANFD_ILS_RF0NL_Pos) /*!< CANFD_T::ILS: RF0NL Mask */ 1371 1372 #define CANFD_ILS_RF0WL_Pos (1) /*!< CANFD_T::ILS: RF0WL Position */ 1373 #define CANFD_ILS_RF0WL_Msk (0x1ul << CANFD_ILS_RF0WL_Pos) /*!< CANFD_T::ILS: RF0WL Mask */ 1374 1375 #define CANFD_ILS_RF0FL_Pos (2) /*!< CANFD_T::ILS: RF0FL Position */ 1376 #define CANFD_ILS_RF0FL_Msk (0x1ul << CANFD_ILS_RF0FL_Pos) /*!< CANFD_T::ILS: RF0FL Mask */ 1377 1378 #define CANFD_ILS_RF0LL_Pos (3) /*!< CANFD_T::ILS: RF0LL Position */ 1379 #define CANFD_ILS_RF0LL_Msk (0x1ul << CANFD_ILS_RF0LL_Pos) /*!< CANFD_T::ILS: RF0LL Mask */ 1380 1381 #define CANFD_ILS_RF1NL_Pos (4) /*!< CANFD_T::ILS: RF1NL Position */ 1382 #define CANFD_ILS_RF1NL_Msk (0x1ul << CANFD_ILS_RF1NL_Pos) /*!< CANFD_T::ILS: RF1NL Mask */ 1383 1384 #define CANFD_ILS_RF1WL_Pos (5) /*!< CANFD_T::ILS: RF1WL Position */ 1385 #define CANFD_ILS_RF1WL_Msk (0x1ul << CANFD_ILS_RF1WL_Pos) /*!< CANFD_T::ILS: RF1WL Mask */ 1386 1387 #define CANFD_ILS_RF1FL_Pos (6) /*!< CANFD_T::ILS: RF1FL Position */ 1388 #define CANFD_ILS_RF1FL_Msk (0x1ul << CANFD_ILS_RF1FL_Pos) /*!< CANFD_T::ILS: RF1FL Mask */ 1389 1390 #define CANFD_ILS_RF1LL_Pos (7) /*!< CANFD_T::ILS: RF1LL Position */ 1391 #define CANFD_ILS_RF1LL_Msk (0x1ul << CANFD_ILS_RF1LL_Pos) /*!< CANFD_T::ILS: RF1LL Mask */ 1392 1393 #define CANFD_ILS_HPML_Pos (8) /*!< CANFD_T::ILS: HPML Position */ 1394 #define CANFD_ILS_HPML_Msk (0x1ul << CANFD_ILS_HPML_Pos) /*!< CANFD_T::ILS: HPML Mask */ 1395 1396 #define CANFD_ILS_TCL_Pos (9) /*!< CANFD_T::ILS: TCL Position */ 1397 #define CANFD_ILS_TCL_Msk (0x1ul << CANFD_ILS_TCL_Pos) /*!< CANFD_T::ILS: TCL Mask */ 1398 1399 #define CANFD_ILS_TCFL_Pos (10) /*!< CANFD_T::ILS: TCFL Position */ 1400 #define CANFD_ILS_TCFL_Msk (0x1ul << CANFD_ILS_TCFL_Pos) /*!< CANFD_T::ILS: TCFL Mask */ 1401 1402 #define CANFD_ILS_TFEL_Pos (11) /*!< CANFD_T::ILS: TFEL Position */ 1403 #define CANFD_ILS_TFEL_Msk (0x1ul << CANFD_ILS_TFEL_Pos) /*!< CANFD_T::ILS: TFEL Mask */ 1404 1405 #define CANFD_ILS_TEFNL_Pos (12) /*!< CANFD_T::ILS: TEFNL Position */ 1406 #define CANFD_ILS_TEFNL_Msk (0x1ul << CANFD_ILS_TEFNL_Pos) /*!< CANFD_T::ILS: TEFNL Mask */ 1407 1408 #define CANFD_ILS_TEFWL_Pos (13) /*!< CANFD_T::ILS: TEFWL Position */ 1409 #define CANFD_ILS_TEFWL_Msk (0x1ul << CANFD_ILS_TEFWL_Pos) /*!< CANFD_T::ILS: TEFWL Mask */ 1410 1411 #define CANFD_ILS_TEFFL_Pos (14) /*!< CANFD_T::ILS: TEFFL Position */ 1412 #define CANFD_ILS_TEFFL_Msk (0x1ul << CANFD_ILS_TEFFL_Pos) /*!< CANFD_T::ILS: TEFFL Mask */ 1413 1414 #define CANFD_ILS_TEFLL_Pos (15) /*!< CANFD_T::ILS: TEFLL Position */ 1415 #define CANFD_ILS_TEFLL_Msk (0x1ul << CANFD_ILS_TEFLL_Pos) /*!< CANFD_T::ILS: TEFLL Mask */ 1416 1417 #define CANFD_ILS_TSWL_Pos (16) /*!< CANFD_T::ILS: TSWL Position */ 1418 #define CANFD_ILS_TSWL_Msk (0x1ul << CANFD_ILS_TSWL_Pos) /*!< CANFD_T::ILS: TSWL Mask */ 1419 1420 #define CANFD_ILS_MRAFL_Pos (17) /*!< CANFD_T::ILS: MRAFL Position */ 1421 #define CANFD_ILS_MRAFL_Msk (0x1ul << CANFD_ILS_MRAFL_Pos) /*!< CANFD_T::ILS: MRAFL Mask */ 1422 1423 #define CANFD_ILS_TOOL_Pos (18) /*!< CANFD_T::ILS: TOOL Position */ 1424 #define CANFD_ILS_TOOL_Msk (0x1ul << CANFD_ILS_TOOL_Pos) /*!< CANFD_T::ILS: TOOL Mask */ 1425 1426 #define CANFD_ILS_DRXL_Pos (19) /*!< CANFD_T::ILS: DRXL Position */ 1427 #define CANFD_ILS_DRXL_Msk (0x1ul << CANFD_ILS_DRXL_Pos) /*!< CANFD_T::ILS: DRXL Mask */ 1428 1429 #define CANFD_ILS_BECL_Pos (20) /*!< CANFD_T::ILS: BECL Position */ 1430 #define CANFD_ILS_BECL_Msk (0x1ul << CANFD_ILS_BECL_Pos) /*!< CANFD_T::ILS: BECL Mask */ 1431 1432 #define CANFD_ILS_BEUL_Pos (21) /*!< CANFD_T::ILS: BEUL Position */ 1433 #define CANFD_ILS_BEUL_Msk (0x1ul << CANFD_ILS_BEUL_Pos) /*!< CANFD_T::ILS: BEUL Mask */ 1434 1435 #define CANFD_ILS_ELOL_Pos (22) /*!< CANFD_T::ILS: ELOL Position */ 1436 #define CANFD_ILS_ELOL_Msk (0x1ul << CANFD_ILS_ELOL_Pos) /*!< CANFD_T::ILS: ELOL Mask */ 1437 1438 #define CANFD_ILS_EPL_Pos (23) /*!< CANFD_T::ILS: EPL Position */ 1439 #define CANFD_ILS_EPL_Msk (0x1ul << CANFD_ILS_EPL_Pos) /*!< CANFD_T::ILS: EPL Mask */ 1440 1441 #define CANFD_ILS_EWL_Pos (24) /*!< CANFD_T::ILS: EWL Position */ 1442 #define CANFD_ILS_EWL_Msk (0x1ul << CANFD_ILS_EWL_Pos) /*!< CANFD_T::ILS: EWL Mask */ 1443 1444 #define CANFD_ILS_BOL_Pos (25) /*!< CANFD_T::ILS: BOL Position */ 1445 #define CANFD_ILS_BOL_Msk (0x1ul << CANFD_ILS_BOL_Pos) /*!< CANFD_T::ILS: BOL Mask */ 1446 1447 #define CANFD_ILS_WDIL_Pos (26) /*!< CANFD_T::ILS: WDIL Position */ 1448 #define CANFD_ILS_WDIL_Msk (0x1ul << CANFD_ILS_WDIL_Pos) /*!< CANFD_T::ILS: WDIL Mask */ 1449 1450 #define CANFD_ILS_PEAL_Pos (27) /*!< CANFD_T::ILS: PEAL Position */ 1451 #define CANFD_ILS_PEAL_Msk (0x1ul << CANFD_ILS_PEAL_Pos) /*!< CANFD_T::ILS: PEAL Mask */ 1452 1453 #define CANFD_ILS_PEDL_Pos (28) /*!< CANFD_T::ILS: PEDL Position */ 1454 #define CANFD_ILS_PEDL_Msk (0x1ul << CANFD_ILS_PEDL_Pos) /*!< CANFD_T::ILS: PEDL Mask */ 1455 1456 #define CANFD_ILS_ARAL_Pos (29) /*!< CANFD_T::ILS: ARAL Position */ 1457 #define CANFD_ILS_ARAL_Msk (0x1ul << CANFD_ILS_ARAL_Pos) /*!< CANFD_T::ILS: ARAL Mask */ 1458 1459 #define CANFD_ILE_EINT0_Pos (0) /*!< CANFD_T::ILE: EINT0 Position */ 1460 #define CANFD_ILE_EINT0_Msk (0x1ul << CANFD_ILE_EINT0_Pos) /*!< CANFD_T::ILE: EINT0 Mask */ 1461 1462 #define CANFD_ILE_EINT1_Pos (1) /*!< CANFD_T::ILE: EINT1 Position */ 1463 #define CANFD_ILE_EINT1_Msk (0x1ul << CANFD_ILE_EINT1_Pos) /*!< CANFD_T::ILE: EINT1 Mask */ 1464 1465 #define CANFD_GFC_RRFE_Pos (0) /*!< CANFD_T::GFC: RRFE Position */ 1466 #define CANFD_GFC_RRFE_Msk (0x1ul << CANFD_GFC_RRFE_Pos) /*!< CANFD_T::GFC: RRFE Mask */ 1467 1468 #define CANFD_GFC_RRFS_Pos (1) /*!< CANFD_T::GFC: RRFS Position */ 1469 #define CANFD_GFC_RRFS_Msk (0x1ul << CANFD_GFC_RRFS_Pos) /*!< CANFD_T::GFC: RRFS Mask */ 1470 1471 #define CANFD_GFC_ANFE_Pos (2) /*!< CANFD_T::GFC: ANFE Position */ 1472 #define CANFD_GFC_ANFE_Msk (0x3ul << CANFD_GFC_ANFE_Pos) /*!< CANFD_T::GFC: ANFE Mask */ 1473 1474 #define CANFD_GFC_ANFS_Pos (4) /*!< CANFD_T::GFC: ANFS Position */ 1475 #define CANFD_GFC_ANFS_Msk (0x3ul << CANFD_GFC_ANFS_Pos) /*!< CANFD_T::GFC: ANFS Mask */ 1476 1477 #define CANFD_SIDFC_FLSSA_Pos (2) /*!< CANFD_T::SIDFC: FLSSA Position */ 1478 #define CANFD_SIDFC_FLSSA_Msk (0x3ffful << CANFD_SIDFC_FLSSA_Pos) /*!< CANFD_T::SIDFC: FLSSA Mask */ 1479 1480 #define CANFD_SIDFC_LSS_Pos (16) /*!< CANFD_T::SIDFC: LSS Position */ 1481 #define CANFD_SIDFC_LSS_Msk (0xfful << CANFD_SIDFC_LSS_Pos) /*!< CANFD_T::SIDFC: LSS Mask */ 1482 1483 #define CANFD_XIDFC_FLESA_Pos (2) /*!< CANFD_T::XIDFC: FLESA Position */ 1484 #define CANFD_XIDFC_FLESA_Msk (0x3ffful << CANFD_XIDFC_FLESA_Pos) /*!< CANFD_T::XIDFC: FLESA Mask */ 1485 1486 #define CANFD_XIDFC_LSE_Pos (16) /*!< CANFD_T::XIDFC: LSE Position */ 1487 #define CANFD_XIDFC_LSE_Msk (0x7ful << CANFD_XIDFC_LSE_Pos) /*!< CANFD_T::XIDFC: LSE Mask */ 1488 1489 #define CANFD_XIDAM_EIDM_Pos (0) /*!< CANFD_T::XIDAM: EIDM Position */ 1490 #define CANFD_XIDAM_EIDM_Msk (0x1ffffffful << CANFD_XIDAM_EIDM_Pos) /*!< CANFD_T::XIDAM: EIDM Mask */ 1491 1492 #define CANFD_HPMS_BIDX_Pos (0) /*!< CANFD_T::HPMS: BIDX Position */ 1493 #define CANFD_HPMS_BIDX_Msk (0x3ful << CANFD_HPMS_BIDX_Pos) /*!< CANFD_T::HPMS: BIDX Mask */ 1494 1495 #define CANFD_HPMS_MSI_Pos (6) /*!< CANFD_T::HPMS: MSI Position */ 1496 #define CANFD_HPMS_MSI_Msk (0x3ul << CANFD_HPMS_MSI_Pos) /*!< CANFD_T::HPMS: MSI Mask */ 1497 1498 #define CANFD_HPMS_FIDX_Pos (8) /*!< CANFD_T::HPMS: FIDX Position */ 1499 #define CANFD_HPMS_FIDX_Msk (0x7ful << CANFD_HPMS_FIDX_Pos) /*!< CANFD_T::HPMS: FIDX Mask */ 1500 1501 #define CANFD_HPMS_FLST_Pos (15) /*!< CANFD_T::HPMS: FLST Position */ 1502 #define CANFD_HPMS_FLST_Msk (0x1ul << CANFD_HPMS_FLST_Pos) /*!< CANFD_T::HPMS: FLST Mask */ 1503 1504 #define CANFD_NDAT1_NDn_Pos (0) /*!< CANFD_T::NDAT1: NDn Position */ 1505 #define CANFD_NDAT1_NDn_Msk (0xfffffffful << CANFD_NDAT1_NDn_Pos) /*!< CANFD_T::NDAT1: NDn Mask */ 1506 1507 #define CANFD_NDAT2_NDn_Pos (0) /*!< CANFD_T::NDAT2: NDn Position */ 1508 #define CANFD_NDAT2_NDn_Msk (0xfffffffful << CANFD_NDAT2_NDn_Pos) /*!< CANFD_T::NDAT2: NDn Mask */ 1509 1510 #define CANFD_RXF0C_F0SA_Pos (2) /*!< CANFD_T::RXF0C: F0SA Position */ 1511 #define CANFD_RXF0C_F0SA_Msk (0x3ffful << CANFD_RXF0C_F0SA_Pos) /*!< CANFD_T::RXF0C: F0SA Mask */ 1512 1513 #define CANFD_RXF0C_F0S_Pos (16) /*!< CANFD_T::RXF0C: F0S Position */ 1514 #define CANFD_RXF0C_F0S_Msk (0x7ful << CANFD_RXF0C_F0S_Pos) /*!< CANFD_T::RXF0C: F0S Mask */ 1515 1516 #define CANFD_RXF0C_F0WM_Pos (24) /*!< CANFD_T::RXF0C: F0WM Position */ 1517 #define CANFD_RXF0C_F0WM_Msk (0x7ful << CANFD_RXF0C_F0WM_Pos) /*!< CANFD_T::RXF0C: F0WM Mask */ 1518 1519 #define CANFD_RXF0C_F0OM_Pos (31) /*!< CANFD_T::RXF0C: F0OM Position */ 1520 #define CANFD_RXF0C_F0OM_Msk (0x1ul << CANFD_RXF0C_F0OM_Pos) /*!< CANFD_T::RXF0C: F0OM Mask */ 1521 1522 #define CANFD_RXF0S_F0FL_Pos (0) /*!< CANFD_T::RXF0S: F0FL Position */ 1523 #define CANFD_RXF0S_F0FL_Msk (0x7ful << CANFD_RXF0S_F0FL_Pos) /*!< CANFD_T::RXF0S: F0FL Mask */ 1524 1525 #define CANFD_RXF0S_F0GI_Pos (8) /*!< CANFD_T::RXF0S: F0GI Position */ 1526 #define CANFD_RXF0S_F0GI_Msk (0x3ful << CANFD_RXF0S_F0GI_Pos) /*!< CANFD_T::RXF0S: F0GI Mask */ 1527 1528 #define CANFD_RXF0S_F0PI_Pos (16) /*!< CANFD_T::RXF0S: F0PI Position */ 1529 #define CANFD_RXF0S_F0PI_Msk (0x3ful << CANFD_RXF0S_F0PI_Pos) /*!< CANFD_T::RXF0S: F0PI Mask */ 1530 1531 #define CANFD_RXF0S_F0F_Pos (24) /*!< CANFD_T::RXF0S: F0F Position */ 1532 #define CANFD_RXF0S_F0F_Msk (0x1ul << CANFD_RXF0S_F0F_Pos) /*!< CANFD_T::RXF0S: F0F Mask */ 1533 1534 #define CANFD_RXF0S_RF0L_Pos (25) /*!< CANFD_T::RXF0S: RF0L Position */ 1535 #define CANFD_RXF0S_RF0L_Msk (0x1ul << CANFD_RXF0S_RF0L_Pos) /*!< CANFD_T::RXF0S: RF0L Mask */ 1536 1537 #define CANFD_RXF0A_F0A_Pos (0) /*!< CANFD_T::RXF0A: F0A Position */ 1538 #define CANFD_RXF0A_F0A_Msk (0x3ful << CANFD_RXF0A_F0A_Pos) /*!< CANFD_T::RXF0A: F0A Mask */ 1539 1540 #define CANFD_RXBC_RBSA_Pos (2) /*!< CANFD_T::RXBC: RBSA Position */ 1541 #define CANFD_RXBC_RBSA_Msk (0x3ffful << CANFD_RXBC_RBSA_Pos) /*!< CANFD_T::RXBC: RBSA Mask */ 1542 1543 #define CANFD_RXF1C_F1SA_Pos (2) /*!< CANFD_T::RXF1C: F1SA Position */ 1544 #define CANFD_RXF1C_F1SA_Msk (0x3ffful << CANFD_RXF1C_F1SA_Pos) /*!< CANFD_T::RXF1C: F1SA Mask */ 1545 1546 #define CANFD_RXF1C_F1S_Pos (16) /*!< CANFD_T::RXF1C: F1S Position */ 1547 #define CANFD_RXF1C_F1S_Msk (0x7ful << CANFD_RXF1C_F1S_Pos) /*!< CANFD_T::RXF1C: F1S Mask */ 1548 1549 #define CANFD_RXF1C_F1WM_Pos (24) /*!< CANFD_T::RXF1C: F1WM Position */ 1550 #define CANFD_RXF1C_F1WM_Msk (0x7ful << CANFD_RXF1C_F1WM_Pos) /*!< CANFD_T::RXF1C: F1WM Mask */ 1551 1552 #define CANFD_RXF1C_F1OM_Pos (31) /*!< CANFD_T::RXF1C: F1OM Position */ 1553 #define CANFD_RXF1C_F1OM_Msk (0x1ul << CANFD_RXF1C_F1OM_Pos) /*!< CANFD_T::RXF1C: F1OM Mask */ 1554 1555 #define CANFD_RXF1S_F1FL_Pos (0) /*!< CANFD_T::RXF1S: F1FL Position */ 1556 #define CANFD_RXF1S_F1FL_Msk (0x7ful << CANFD_RXF1S_F1FL_Pos) /*!< CANFD_T::RXF1S: F1FL Mask */ 1557 1558 #define CANFD_RXF1S_F1GI_Pos (8) /*!< CANFD_T::RXF1S: F1GI Position */ 1559 #define CANFD_RXF1S_F1GI_Msk (0x3ful << CANFD_RXF1S_F1GI_Pos) /*!< CANFD_T::RXF1S: F1GI Mask */ 1560 1561 #define CANFD_RXF1S_F1PI_Pos (16) /*!< CANFD_T::RXF1S: F1PI Position */ 1562 #define CANFD_RXF1S_F1PI_Msk (0x3ful << CANFD_RXF1S_F1PI_Pos) /*!< CANFD_T::RXF1S: F1PI Mask */ 1563 1564 #define CANFD_RXF1S_F1F_Pos (24) /*!< CANFD_T::RXF1S: F1F Position */ 1565 #define CANFD_RXF1S_F1F_Msk (0x1ul << CANFD_RXF1S_F1F_Pos) /*!< CANFD_T::RXF1S: F1F Mask */ 1566 1567 #define CANFD_RXF1S_RF1L_Pos (25) /*!< CANFD_T::RXF1S: RF1L Position */ 1568 #define CANFD_RXF1S_RF1L_Msk (0x1ul << CANFD_RXF1S_RF1L_Pos) /*!< CANFD_T::RXF1S: RF1L Mask */ 1569 1570 #define CANFD_RXF1A_F1AI_Pos (0) /*!< CANFD_T::RXF1A: F1AI Position */ 1571 #define CANFD_RXF1A_F1AI_Msk (0x3ful << CANFD_RXF1A_F1AI_Pos) /*!< CANFD_T::RXF1A: F1AI Mask */ 1572 1573 #define CANFD_RXESC_F0DS_Pos (0) /*!< CANFD_T::RXESC: F0DS Position */ 1574 #define CANFD_RXESC_F0DS_Msk (0x7ul << CANFD_RXESC_F0DS_Pos) /*!< CANFD_T::RXESC: F0DS Mask */ 1575 1576 #define CANFD_RXESC_F1DS_Pos (4) /*!< CANFD_T::RXESC: F1DS Position */ 1577 #define CANFD_RXESC_F1DS_Msk (0x7ul << CANFD_RXESC_F1DS_Pos) /*!< CANFD_T::RXESC: F1DS Mask */ 1578 1579 #define CANFD_RXESC_RBDS_Pos (8) /*!< CANFD_T::RXESC: RBDS Position */ 1580 #define CANFD_RXESC_RBDS_Msk (0x7ul << CANFD_RXESC_RBDS_Pos) /*!< CANFD_T::RXESC: RBDS Mask */ 1581 1582 #define CANFD_TXBC_TBSA_Pos (2) /*!< CANFD_T::TXBC: TBSA Position */ 1583 #define CANFD_TXBC_TBSA_Msk (0x3ffful << CANFD_TXBC_TBSA_Pos) /*!< CANFD_T::TXBC: TBSA Mask */ 1584 1585 #define CANFD_TXBC_NDTB_Pos (16) /*!< CANFD_T::TXBC: NDTB Position */ 1586 #define CANFD_TXBC_NDTB_Msk (0x3ful << CANFD_TXBC_NDTB_Pos) /*!< CANFD_T::TXBC: NDTB Mask */ 1587 1588 #define CANFD_TXBC_TFQS_Pos (24) /*!< CANFD_T::TXBC: TFQS Position */ 1589 #define CANFD_TXBC_TFQS_Msk (0x3ful << CANFD_TXBC_TFQS_Pos) /*!< CANFD_T::TXBC: TFQS Mask */ 1590 1591 #define CANFD_TXBC_TFQM_Pos (30) /*!< CANFD_T::TXBC: TFQM Position */ 1592 #define CANFD_TXBC_TFQM_Msk (0x1ul << CANFD_TXBC_TFQM_Pos) /*!< CANFD_T::TXBC: TFQM Mask */ 1593 1594 #define CANFD_TXFQS_TFFL_Pos (0) /*!< CANFD_T::TXFQS: TFFL Position */ 1595 #define CANFD_TXFQS_TFFL_Msk (0x3ful << CANFD_TXFQS_TFFL_Pos) /*!< CANFD_T::TXFQS: TFFL Mask */ 1596 1597 #define CANFD_TXFQS_TFGI_Pos (8) /*!< CANFD_T::TXFQS: TFGI Position */ 1598 #define CANFD_TXFQS_TFGI_Msk (0x1ful << CANFD_TXFQS_TFGI_Pos) /*!< CANFD_T::TXFQS: TFGI Mask */ 1599 1600 #define CANFD_TXFQS_TFQPI_Pos (16) /*!< CANFD_T::TXFQS: TFQPI Position */ 1601 #define CANFD_TXFQS_TFQPI_Msk (0x1ful << CANFD_TXFQS_TFQPI_Pos) /*!< CANFD_T::TXFQS: TFQPI Mask */ 1602 1603 #define CANFD_TXFQS_TFQF_Pos (21) /*!< CANFD_T::TXFQS: TFQF Position */ 1604 #define CANFD_TXFQS_TFQF_Msk (0x1ul << CANFD_TXFQS_TFQF_Pos) /*!< CANFD_T::TXFQS: TFQF Mask */ 1605 1606 #define CANFD_TXESC_TBDS_Pos (0) /*!< CANFD_T::TXESC: TBDS Position */ 1607 #define CANFD_TXESC_TBDS_Msk (0x7ul << CANFD_TXESC_TBDS_Pos) /*!< CANFD_T::TXESC: TBDS Mask */ 1608 1609 #define CANFD_TXBRP_TRPn_Pos (0) /*!< CANFD_T::TXBRP: TRPn Position */ 1610 #define CANFD_TXBRP_TRPn_Msk (0xfffffffful << CANFD_TXBRP_TRPn_Pos) /*!< CANFD_T::TXBRP: TRPn Mask */ 1611 1612 #define CANFD_TXBAR_ARn_Pos (0) /*!< CANFD_T::TXBAR: ARn Position */ 1613 #define CANFD_TXBAR_ARn_Msk (0xfffffffful << CANFD_TXBAR_ARn_Pos) /*!< CANFD_T::TXBAR: ARn Mask */ 1614 1615 #define CANFD_TXBCR_CRn_Pos (0) /*!< CANFD_T::TXBCR: CRn Position */ 1616 #define CANFD_TXBCR_CRn_Msk (0xfffffffful << CANFD_TXBCR_CRn_Pos) /*!< CANFD_T::TXBCR: CRn Mask */ 1617 1618 #define CANFD_TXBTO_TOn_Pos (0) /*!< CANFD_T::TXBTO: TOn Position */ 1619 #define CANFD_TXBTO_TOn_Msk (0xfffffffful << CANFD_TXBTO_TOn_Pos) /*!< CANFD_T::TXBTO: TOn Mask */ 1620 1621 #define CANFD_TXBCF_CFn_Pos (0) /*!< CANFD_T::TXBCF: CFn Position */ 1622 #define CANFD_TXBCF_CFn_Msk (0xfffffffful << CANFD_TXBCF_CFn_Pos) /*!< CANFD_T::TXBCF: CFn Mask */ 1623 1624 #define CANFD_TXBTIE_TIEn_Pos (0) /*!< CANFD_T::TXBTIE: TIEn Position */ 1625 #define CANFD_TXBTIE_TIEn_Msk (0xfffffffful << CANFD_TXBTIE_TIEn_Pos) /*!< CANFD_T::TXBTIE: TIEn Mask */ 1626 1627 #define CANFD_TXBCIE_CFIEn_Pos (0) /*!< CANFD_T::TXBCIE: CFIEn Position */ 1628 #define CANFD_TXBCIE_CFIEn_Msk (0xfffffffful << CANFD_TXBCIE_CFIEn_Pos) /*!< CANFD_T::TXBCIE: CFIEn Mask */ 1629 1630 #define CANFD_TXEFC_EFSA_Pos (2) /*!< CANFD_T::TXEFC: EFSA Position */ 1631 #define CANFD_TXEFC_EFSA_Msk (0x3ffful << CANFD_TXEFC_EFSA_Pos) /*!< CANFD_T::TXEFC: EFSA Mask */ 1632 1633 #define CANFD_TXEFC_EFS_Pos (16) /*!< CANFD_T::TXEFC: EFS Position */ 1634 #define CANFD_TXEFC_EFS_Msk (0x3ful << CANFD_TXEFC_EFS_Pos) /*!< CANFD_T::TXEFC: EFS Mask */ 1635 1636 #define CANFD_TXEFC_EFWM_Pos (24) /*!< CANFD_T::TXEFC: EFWM Position */ 1637 #define CANFD_TXEFC_EFWM_Msk (0x3ful << CANFD_TXEFC_EFWM_Pos) /*!< CANFD_T::TXEFC: EFWM Mask */ 1638 1639 #define CANFD_TXEFS_EFFL_Pos (0) /*!< CANFD_T::TXEFS: EFFL Position */ 1640 #define CANFD_TXEFS_EFFL_Msk (0x3ful << CANFD_TXEFS_EFFL_Pos) /*!< CANFD_T::TXEFS: EFFL Mask */ 1641 1642 #define CANFD_TXEFS_EFGI_Pos (8) /*!< CANFD_T::TXEFS: EFGI Position */ 1643 #define CANFD_TXEFS_EFGI_Msk (0x1ful << CANFD_TXEFS_EFGI_Pos) /*!< CANFD_T::TXEFS: EFGI Mask */ 1644 1645 #define CANFD_TXEFS_EFPI_Pos (16) /*!< CANFD_T::TXEFS: EFPI Position */ 1646 #define CANFD_TXEFS_EFPI_Msk (0x1ful << CANFD_TXEFS_EFPI_Pos) /*!< CANFD_T::TXEFS: EFPI Mask */ 1647 1648 #define CANFD_TXEFS_EFF_Pos (24) /*!< CANFD_T::TXEFS: EFF Position */ 1649 #define CANFD_TXEFS_EFF_Msk (0x1ul << CANFD_TXEFS_EFF_Pos) /*!< CANFD_T::TXEFS: EFF Mask */ 1650 1651 #define CANFD_TXEFS_TEFL_Pos (25) /*!< CANFD_T::TXEFS: TEFL Position */ 1652 #define CANFD_TXEFS_TEFL_Msk (0x1ul << CANFD_TXEFS_TEFL_Pos) /*!< CANFD_T::TXEFS: TEFL Mask */ 1653 1654 #define CANFD_TXEFA_EFAI_Pos (0) /*!< CANFD_T::TXEFA: EFAI Position */ 1655 #define CANFD_TXEFA_EFAI_Msk (0x1ful << CANFD_TXEFA_EFAI_Pos) /*!< CANFD_T::TXEFA: EFAI Mask */ 1656 1657 /**@}*/ /* CANFD_CONST */ 1658 /**@}*/ /* end of CANFD register group */ 1659 /**@}*/ /* end of REGISTER group */ 1660 1661 #if defined ( __CC_ARM ) 1662 #pragma no_anon_unions 1663 #endif 1664 1665 #endif /* __CANFD_REG_H__ */
