1 /* 2 * Copyright 2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef _S32K344_GLUE_MCUX_H_ 8 #define _S32K344_GLUE_MCUX_H_ 9 10 #include "S32K344_device.h" 11 12 /* LPUART - Peripheral instance base addresses */ 13 /** Peripheral LPUART_0 base address */ 14 #define LPUART0_BASE IP_LPUART_0_BASE 15 /** Peripheral LPUART_0 base pointer */ 16 #define LPUART0 IP_LPUART_0 17 /** Peripheral LPUART_1 base address */ 18 #define LPUART1_BASE IP_LPUART_1_BASE 19 /** Peripheral LPUART_1 base pointer */ 20 #define LPUART1 IP_LPUART_1 21 /** Peripheral LPUART_2 base address */ 22 #define LPUART2_BASE IP_LPUART_2_BASE 23 /** Peripheral LPUART_2 base pointer */ 24 #define LPUART2 IP_LPUART_2 25 /** Peripheral LPUART_3 base address */ 26 #define LPUART3_BASE IP_LPUART_3_BASE 27 /** Peripheral LPUART_3 base pointer */ 28 #define LPUART3 IP_LPUART_3 29 /** Peripheral LPUART_4 base address */ 30 #define LPUART4_BASE IP_LPUART_4_BASE 31 /** Peripheral LPUART_4 base pointer */ 32 #define LPUART4 IP_LPUART_4 33 /** Peripheral LPUART_5 base address */ 34 #define LPUART5_BASE IP_LPUART_5_BASE 35 /** Peripheral LPUART_5 base pointer */ 36 #define LPUART5 IP_LPUART_5 37 /** Peripheral LPUART_6 base address */ 38 #define LPUART6_BASE IP_LPUART_6_BASE 39 /** Peripheral LPUART_6 base pointer */ 40 #define LPUART6 IP_LPUART_6 41 /** Peripheral LPUART_7 base address */ 42 #define LPUART7_BASE IP_LPUART_7_BASE 43 /** Peripheral LPUART_7 base pointer */ 44 #define LPUART7 IP_LPUART_7 45 /** Peripheral LPUART_8 base address */ 46 #define LPUART8_BASE IP_LPUART_8_BASE 47 /** Peripheral LPUART_8 base pointer */ 48 #define LPUART8 IP_LPUART_8 49 /** Peripheral LPUART_9 base address */ 50 #define LPUART9_BASE IP_LPUART_9_BASE 51 /** Peripheral LPUART_9 base pointer */ 52 #define LPUART9 IP_LPUART_9 53 /** Peripheral LPUART_10 base address */ 54 #define LPUART10_BASE IP_LPUART_10_BASE 55 /** Peripheral LPUART_10 base pointer */ 56 #define LPUART10 IP_LPUART_10 57 /** Peripheral LPUART_11 base address */ 58 #define LPUART11_BASE IP_LPUART_11_BASE 59 /** Peripheral LPUART_11 base pointer */ 60 #define LPUART11 IP_LPUART_11 61 /** Peripheral LPUART_12 base address */ 62 #define LPUART12_BASE IP_LPUART_12_BASE 63 /** Peripheral LPUART_12 base pointer */ 64 #define LPUART12 IP_LPUART_12 65 /** Peripheral LPUART_13 base address */ 66 #define LPUART13_BASE IP_LPUART_13_BASE 67 /** Peripheral LPUART_13 base pointer */ 68 #define LPUART13 IP_LPUART_13 69 /** Peripheral LPUART_14 base address */ 70 #define LPUART14_BASE IP_LPUART_14_BASE 71 /** Peripheral LPUART_14 base pointer */ 72 #define LPUART14 IP_LPUART_14 73 /** Peripheral LPUART_15 base address */ 74 #define LPUART15_BASE IP_LPUART_15_BASE 75 /** Peripheral LPUART_15 base pointer */ 76 #define LPUART15 IP_LPUART_15 77 /** Array initializer of LPUART peripheral base addresses */ 78 #define LPUART_BASE_ADDRS IP_LPUART_BASE_ADDRS 79 /** Array initializer of LPUART peripheral base pointers */ 80 #define LPUART_BASE_PTRS IP_LPUART_BASE_PTRS 81 /** Interrupt vectors for the LPUART peripheral type */ 82 #define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn, LPUART9_IRQn, LPUART10_IRQn, LPUART11_IRQn, LPUART12_IRQn, LPUART13_IRQn, LPUART14_IRQn, LPUART15_IRQn } 83 84 /* CAN - Peripheral instance base addresses */ 85 /** Peripheral CAN_0 base address */ 86 #define CAN0_BASE IP_CAN_0_BASE 87 /** Peripheral CAN_0 base pointer */ 88 #define CAN0 ((CAN_Type *)CAN0_BASE) 89 /** Peripheral CAN_1 base address */ 90 #define CAN1_BASE IP_CAN_1_BASE 91 /** Peripheral CAN_1 base pointer */ 92 #define CAN1 ((CAN_Type *)CAN1_BASE) 93 /** Peripheral CAN_2 base address */ 94 #define CAN2_BASE IP_CAN_2_BASE 95 /** Peripheral CAN_2 base pointer */ 96 #define CAN2 ((CAN_Type *)CAN2_BASE) 97 /** Peripheral CAN_3 base address */ 98 #define CAN3_BASE IP_CAN_3_BASE 99 /** Peripheral CAN_3 base pointer */ 100 #define CAN3 ((CAN_Type *)CAN3_BASE) 101 /** Peripheral CAN_4 base address */ 102 #define CAN4_BASE IP_CAN_4_BASE 103 /** Peripheral CAN_4 base pointer */ 104 #define CAN4 ((CAN_Type *)CAN4_BASE) 105 /** Peripheral CAN_5 base address */ 106 #define CAN5_BASE IP_CAN_5_BASE 107 /** Peripheral CAN_5 base pointer */ 108 #define CAN5 ((CAN_Type *)CAN5_BASE) 109 /** Array initializer of CAN peripheral base addresses */ 110 #define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE, CAN2_BASE, CAN3_BASE, CAN4_BASE, CAN5_BASE } 111 /** Array initializer of CAN peripheral base pointers */ 112 #define CAN_BASE_PTRS { CAN0, CAN1, CAN2, CAN3, CAN4, CAN5 } 113 /** Interrupt vectors for the CAN peripheral type */ 114 #define CAN_Rx_Warning_IRQS { FlexCAN0_0_IRQn, FlexCAN1_0_IRQn, FlexCAN2_0_IRQn, FlexCAN3_0_IRQn, FlexCAN4_0_IRQn, FlexCAN5_0_IRQn} 115 #define CAN_Tx_Warning_IRQS { FlexCAN0_0_IRQn, FlexCAN1_0_IRQn, FlexCAN2_0_IRQn, FlexCAN3_0_IRQn, FlexCAN4_0_IRQn, FlexCAN5_0_IRQn} 116 #define CAN_Wake_Up_IRQS { FlexCAN0_0_IRQn, FlexCAN1_0_IRQn, FlexCAN2_0_IRQn, FlexCAN3_0_IRQn, FlexCAN4_0_IRQn, FlexCAN5_0_IRQn} 117 #define CAN_Error_IRQS { FlexCAN0_0_IRQn, FlexCAN1_0_IRQn, FlexCAN2_0_IRQn, FlexCAN3_0_IRQn, FlexCAN4_0_IRQn, FlexCAN5_0_IRQn} 118 #define CAN_Bus_Off_IRQS { FlexCAN0_0_IRQn, FlexCAN1_0_IRQn, FlexCAN2_0_IRQn, FlexCAN3_0_IRQn, FlexCAN4_0_IRQn, FlexCAN5_0_IRQn} 119 #define CAN_ORed_Message_buffer_0_31_IRQS { FlexCAN0_1_IRQn, FlexCAN1_1_IRQn, FlexCAN2_1_IRQn, FlexCAN3_1_IRQn, FlexCAN4_1_IRQn, FlexCAN5_1_IRQn} 120 #define CAN_ORed_Message_buffer_32_63_IRQS { FlexCAN0_2_IRQn, FlexCAN1_2_IRQn, FlexCAN2_2_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn} 121 #define CAN_ORed_Message_buffer_64_95_IRQS { FlexCAN0_1_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn} 122 #define CAN_ORed_Message_buffer_IRQS CAN_ORed_Message_buffer_0_31_IRQS 123 124 /* LPI2C - Peripheral instance base addresses */ 125 /** Peripheral LPI2C0 base address */ 126 #define LPI2C0_BASE IP_LPI2C_0_BASE 127 /** Peripheral LPI2C0 base pointer */ 128 #define LPI2C0 IP_LPI2C_0 129 /** Peripheral LPI2C1 base address */ 130 #define LPI2C1_BASE IP_LPI2C_1_BASE 131 /** Peripheral LPI2C1 base pointer */ 132 #define LPI2C1 IP_LPI2C_1 133 /** Array initializer of LPI2C peripheral base addresses */ 134 #define LPI2C_BASE_ADDRS IP_LPI2C_BASE_ADDRS 135 /** Array initializer of LPI2C peripheral base pointers */ 136 #define LPI2C_BASE_PTRS IP_LPI2C_BASE_PTRS 137 /** Interrupt vectors for the LPI2C peripheral type */ 138 #define LPI2C_IRQS { LPI2C0_IRQn, LPI2C1_IRQn } 139 140 /* LPSPI - Peripheral instance base addresses */ 141 /** Peripheral LPSPI0 base address */ 142 #define LPSPI0_BASE IP_LPSPI_0_BASE 143 /** Peripheral LPSPI0 base pointer */ 144 #define LPSPI0 IP_LPSPI_0 145 /** Peripheral LPSPI1 base address */ 146 #define LPSPI1_BASE IP_LPSPI_1_BASE 147 /** Peripheral LPSPI1 base pointer */ 148 #define LPSPI1 IP_LPSPI_1 149 /** Peripheral LPSPI2 base address */ 150 #define LPSPI2_BASE IP_LPSPI_2_BASE 151 /** Peripheral LPSPI2 base pointer */ 152 #define LPSPI2 IP_LPSPI_2 153 /** Peripheral LPSPI3 base address */ 154 #define LPSPI3_BASE IP_LPSPI_3_BASE 155 /** Peripheral LPSPI3 base pointer */ 156 #define LPSPI3 IP_LPSPI_3 157 /** Peripheral LPSPI4 base address */ 158 #define LPSPI4_BASE IP_LPSPI_4_BASE 159 /** Peripheral LPSPI4 base pointer */ 160 #define LPSPI4 IP_LPSPI_4 161 /** Peripheral LPSPI5 base address */ 162 #define LPSPI5_BASE IP_LPSPI_5_BASE 163 /** Peripheral LPSPI5 base pointer */ 164 #define LPSPI5 IP_LPSPI_5 165 /** Array initializer of LPSPI peripheral base addresses */ 166 #define LPSPI_BASE_ADDRS IP_LPSPI_BASE_ADDRS 167 /** Array initializer of LPSPI peripheral base pointers */ 168 #define LPSPI_BASE_PTRS IP_LPSPI_BASE_PTRS 169 /** Interrupt vectors for the LPSPI peripheral type */ 170 #define LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn, LPSPI5_IRQn } 171 172 /* DMA - Peripheral instance base addresses */ 173 #define DMA_BASE IP_EDMA_BASE 174 #define DMA ((DMA_Type*)DMA_BASE) 175 #define DMA_BASE_PTRS {DMA} 176 177 /** Interrupt vectors for the DMA peripheral type, there is no interrupt id for offset channels */ 178 #define DMA_IRQS { {DMATCD0_IRQn, DMATCD1_IRQn, DMATCD2_IRQn, DMATCD3_IRQn, DMATCD4_IRQn, DMATCD5_IRQn, \ 179 DMATCD6_IRQn, DMATCD7_IRQn, DMATCD8_IRQn, DMATCD9_IRQn, DMATCD10_IRQn, DMATCD11_IRQn, \ 180 [12 ... 127] = NotAvail_IRQn, \ 181 DMATCD12_IRQn, DMATCD13_IRQn, DMATCD14_IRQn, DMATCD15_IRQn, DMATCD16_IRQn, DMATCD17_IRQn, \ 182 DMATCD18_IRQn, DMATCD19_IRQn, DMATCD20_IRQn, DMATCD21_IRQn, DMATCD22_IRQn, DMATCD23_IRQn, \ 183 DMATCD24_IRQn, DMATCD25_IRQn, DMATCD26_IRQn, DMATCD27_IRQn, DMATCD28_IRQn, DMATCD29_IRQn, \ 184 DMATCD30_IRQn, DMATCD31_IRQn} } 185 186 /* DMAMUX - Peripheral instance base addresses */ 187 /** Peripheral DMAMUX0 base address */ 188 #define DMAMUX0_BASE IP_DMAMUX_0_BASE 189 /** Peripheral DMAMUX0 base pointer */ 190 #define DMAMUX0 IP_DMAMUX_0 191 /** Peripheral DMAMUX1 base address */ 192 #define DMAMUX1_BASE IP_DMAMUX_1_BASE 193 /** Peripheral DMAMUX1 base pointer */ 194 #define DMAMUX1 IP_DMAMUX_1 195 /** Array initializer of DMAMUX peripheral base addresses */ 196 #define DMAMUX_BASE_ADDRS IP_DMAMUX_BASE_ADDRS 197 /** Array initializer of DMAMUX peripheral base pointers */ 198 #define DMAMUX_BASE_PTRS IP_DMAMUX_BASE_PTRS 199 200 /* FLEXIO - Peripheral instance base addresses */ 201 /** Peripheral FLEXIO base address */ 202 #define FLEXIO_BASE IP_FLEXIO_BASE 203 /** Peripheral FLEXIO base pointer */ 204 #define FLEXIO IP_FLEXIO 205 /** Array initializer of FLEXIO peripheral base addresses */ 206 #define FLEXIO_BASE_ADDRS IP_FLEXIO_BASE_ADDRS 207 /** Array initializer of FLEXIO peripheral base pointers */ 208 #define FLEXIO_BASE_PTRS IP_FLEXIO_BASE_PTRS 209 /** Interrupt vectors for the FLEXIO peripheral type */ 210 #define FLEXIO_IRQS { FLEXIO_IRQn } 211 #endif /* _S32K344_GLUE_MCUX_H_ */ 212
