1 /* 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the 14 * distribution. 15 * 16 * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 #ifndef __HW_CAMERA_H__ 35 #define __HW_CAMERA_H__ 36 37 //***************************************************************************** 38 // 39 // The following are defines for the CAMERA register offsets. 40 // 41 //***************************************************************************** 42 #define CAMERA_O_CC_REVISION 0x00000000 // This register contains the IP 43 // revision code ( Parallel Mode) 44 #define CAMERA_O_CC_SYSCONFIG 0x00000010 // This register controls the 45 // various parameters of the OCP 46 // interface (CCP and Parallel Mode) 47 #define CAMERA_O_CC_SYSSTATUS 0x00000014 // This register provides status 48 // information about the module 49 // excluding the interrupt status 50 // information (CCP and Parallel 51 // Mode) 52 #define CAMERA_O_CC_IRQSTATUS 0x00000018 // The interrupt status regroups 53 // all the status of the module 54 // internal events that can generate 55 // an interrupt (CCP & Parallel 56 // Mode) 57 #define CAMERA_O_CC_IRQENABLE 0x0000001C // The interrupt enable register 58 // allows to enable/disable the 59 // module internal sources of 60 // interrupt on an event-by-event 61 // basis (CCP & Parallel Mode) 62 #define CAMERA_O_CC_CTRL 0x00000040 // This register controls the 63 // various parameters of the Camera 64 // Core block (CCP & Parallel Mode) 65 #define CAMERA_O_CC_CTRL_DMA 0x00000044 // This register controls the DMA 66 // interface of the Camera Core 67 // block (CCP & Parallel Mode) 68 #define CAMERA_O_CC_CTRL_XCLK 0x00000048 // This register control the value 69 // of the clock divisor used to 70 // generate the external clock 71 // (Parallel Mode) 72 #define CAMERA_O_CC_FIFO_DATA 0x0000004C // This register allows to write to 73 // the FIFO and read from the FIFO 74 // (CCP & Parallel Mode) 75 #define CAMERA_O_CC_TEST 0x00000050 // This register shows the status 76 // of some important variables of 77 // the camera core module (CCP & 78 // Parallel Mode) 79 #define CAMERA_O_CC_GEN_PAR 0x00000054 // This register shows the values 80 // of the generic parameters of the 81 // module 82 83 84 85 //****************************************************************************** 86 // 87 // The following are defines for the bit fields in the 88 // CAMERA_O_CC_REVISION register. 89 // 90 //****************************************************************************** 91 #define CAMERA_CC_REVISION_REV_M \ 92 0x000000FF // IP revision [7:4] Major revision 93 // [3:0] Minor revision Examples: 94 // 0x10 for 1.0 0x21 for 2.1 95 96 #define CAMERA_CC_REVISION_REV_S 0 97 //****************************************************************************** 98 // 99 // The following are defines for the bit fields in the 100 // CAMERA_O_CC_SYSCONFIG register. 101 // 102 //****************************************************************************** 103 #define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_M \ 104 0x00000018 // Slave interface power management 105 // req/ack control """00"" 106 // Force-idle. An idle request is 107 // acknoledged unconditionally" 108 // """01"" No-idle. An idle request 109 // is never acknowledged" """10"" 110 // reserved (Smart-idle not 111 // implemented)" 112 113 #define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_S 3 114 #define CAMERA_CC_SYSCONFIG_SOFT_RESET \ 115 0x00000002 // Software reset. Set this bit to 116 // 1 to trigger a module reset. The 117 // bit is automatically reset by the 118 // hardware. During reset it always 119 // returns 0. 0 Normal mode 1 The 120 // module is reset 121 122 #define CAMERA_CC_SYSCONFIG_AUTO_IDLE \ 123 0x00000001 // Internal OCP clock gating 124 // strategy 0 OCP clock is 125 // free-running 1 Automatic OCP 126 // clock gating strategy is applied 127 // based on the OCP interface 128 // activity 129 130 //****************************************************************************** 131 // 132 // The following are defines for the bit fields in the 133 // CAMERA_O_CC_SYSSTATUS register. 134 // 135 //****************************************************************************** 136 #define CAMERA_CC_SYSSTATUS_RESET_DONE2 \ 137 0x00000001 // Internal Reset Monitoring 0 138 // Internal module reset is on-going 139 // 1 Reset completed 140 141 //****************************************************************************** 142 // 143 // The following are defines for the bit fields in the 144 // CAMERA_O_CC_IRQSTATUS register. 145 // 146 //****************************************************************************** 147 #define CAMERA_CC_IRQSTATUS_FS_IRQ \ 148 0x00080000 // Frame Start has occurred 0 Event 149 // false "1 Event is true 150 // (""pending"")" 0 Event status bit 151 // unchanged 1 Event status bit is 152 // reset 153 154 #define CAMERA_CC_IRQSTATUS_LE_IRQ \ 155 0x00040000 // Line End has occurred 0 Event 156 // false "1 Event is true 157 // (""pending"")" 0 Event status bit 158 // unchanged 1 Event status bit is 159 // reset 160 161 #define CAMERA_CC_IRQSTATUS_LS_IRQ \ 162 0x00020000 // Line Start has occurred 0 Event 163 // false "1 Event is true 164 // (""pending"")" 0 Event status bit 165 // unchanged 1 Event status bit is 166 // reset 167 168 #define CAMERA_CC_IRQSTATUS_FE_IRQ \ 169 0x00010000 // Frame End has occurred 0 Event 170 // false "1 Event is true 171 // (""pending"")" 0 Event status bit 172 // unchanged 1 Event status bit is 173 // reset 174 175 #define CAMERA_CC_IRQSTATUS_FSP_ERR_IRQ \ 176 0x00000800 // FSP code error 0 Event false "1 177 // Event is true (""pending"")" 0 178 // Event status bit unchanged 1 179 // Event status bit is reset 180 181 #define CAMERA_CC_IRQSTATUS_FW_ERR_IRQ \ 182 0x00000400 // Frame Height Error 0 Event false 183 // "1 Event is true (""pending"")" 0 184 // Event status bit unchanged 1 185 // Event status bit is reset 186 187 #define CAMERA_CC_IRQSTATUS_FSC_ERR_IRQ \ 188 0x00000200 // False Synchronization Code 0 189 // Event false "1 Event is true 190 // (""pending"")" 0 Event status bit 191 // unchanged 1 Event status bit is 192 // reset 193 194 #define CAMERA_CC_IRQSTATUS_SSC_ERR_IRQ \ 195 0x00000100 // Shifted Synchronization Code 0 196 // Event false "1 Event is true 197 // (""pending"")" 0 Event status bit 198 // unchanged 1 Event status bit is 199 // reset 200 201 #define CAMERA_CC_IRQSTATUS_FIFO_NONEMPTY_IRQ \ 202 0x00000010 // FIFO is not empty 0 Event false 203 // "1 Event is true (""pending"")" 0 204 // Event status bit unchanged 1 205 // Event status bit is reset 206 207 #define CAMERA_CC_IRQSTATUS_FIFO_FULL_IRQ \ 208 0x00000008 // FIFO is full 0 Event false "1 209 // Event is true (""pending"")" 0 210 // Event status bit unchanged 1 211 // Event status bit is reset 212 213 #define CAMERA_CC_IRQSTATUS_FIFO_THR_IRQ \ 214 0x00000004 // FIFO threshold has been reached 215 // 0 Event false "1 Event is true 216 // (""pending"")" 0 Event status bit 217 // unchanged 1 Event status bit is 218 // reset 219 220 #define CAMERA_CC_IRQSTATUS_FIFO_OF_IRQ \ 221 0x00000002 // FIFO overflow has occurred 0 222 // Event false "1 Event is true 223 // (""pending"")" 0 Event status bit 224 // unchanged 1 Event status bit is 225 // reset 226 227 #define CAMERA_CC_IRQSTATUS_FIFO_UF_IRQ \ 228 0x00000001 // FIFO underflow has occurred 0 229 // Event false "1 Event is true 230 // (""pending"")" 0 Event status bit 231 // unchanged 1 Event status bit is 232 // reset 233 234 //****************************************************************************** 235 // 236 // The following are defines for the bit fields in the 237 // CAMERA_O_CC_IRQENABLE register. 238 // 239 //****************************************************************************** 240 #define CAMERA_CC_IRQENABLE_FS_IRQ_EN \ 241 0x00080000 // Frame Start Interrupt Enable 0 242 // Event is masked 1 Event generates 243 // an interrupt when it occurs 244 245 #define CAMERA_CC_IRQENABLE_LE_IRQ_EN \ 246 0x00040000 // Line End Interrupt Enable 0 247 // Event is masked 1 Event generates 248 // an interrupt when it occurs 249 250 #define CAMERA_CC_IRQENABLE_LS_IRQ_EN \ 251 0x00020000 // Line Start Interrupt Enable 0 252 // Event is masked 1 Event generates 253 // an interrupt when it occurs 254 255 #define CAMERA_CC_IRQENABLE_FE_IRQ_EN \ 256 0x00010000 // Frame End Interrupt Enable 0 257 // Event is masked 1 Event generates 258 // an interrupt when it occurs 259 260 #define CAMERA_CC_IRQENABLE_FSP_IRQ_EN \ 261 0x00000800 // FSP code Interrupt Enable 0 262 // Event is masked 1 Event generates 263 // an interrupt when it occurs 264 265 #define CAMERA_CC_IRQENABLE_FW_ERR_IRQ_EN \ 266 0x00000400 // Frame Height Error Interrupt 267 // Enable 0 Event is masked 1 Event 268 // generates an interrupt when it 269 // occurs 270 271 #define CAMERA_CC_IRQENABLE_FSC_ERR_IRQ_EN \ 272 0x00000200 // False Synchronization Code 273 // Interrupt Enable 0 Event is 274 // masked 1 Event generates an 275 // interrupt when it occurs 276 277 #define CAMERA_CC_IRQENABLE_SSC_ERR_IRQ_EN \ 278 0x00000100 // False Synchronization Code 279 // Interrupt Enable 0 Event is 280 // masked 1 Event generates an 281 // interrupt when it occurs 282 283 #define CAMERA_CC_IRQENABLE_FIFO_NONEMPTY_IRQ_EN \ 284 0x00000010 // FIFO Threshold Interrupt Enable 285 // 0 Event is masked 1 Event 286 // generates an interrupt when it 287 // occurs 288 289 #define CAMERA_CC_IRQENABLE_FIFO_FULL_IRQ_EN \ 290 0x00000008 // FIFO Threshold Interrupt Enable 291 // 0 Event is masked 1 Event 292 // generates an interrupt when it 293 // occurs 294 295 #define CAMERA_CC_IRQENABLE_FIFO_THR_IRQ_EN \ 296 0x00000004 // FIFO Threshold Interrupt Enable 297 // 0 Event is masked 1 Event 298 // generates an interrupt when it 299 // occurs 300 301 #define CAMERA_CC_IRQENABLE_FIFO_OF_IRQ_EN \ 302 0x00000002 // FIFO Overflow Interrupt Enable 0 303 // Event is masked 1 Event generates 304 // an interrupt when it occurs 305 306 #define CAMERA_CC_IRQENABLE_FIFO_UF_IRQ_EN \ 307 0x00000001 // FIFO Underflow Interrupt Enable 308 // 0 Event is masked 1 Event 309 // generates an interrupt when it 310 // occurs 311 312 //****************************************************************************** 313 // 314 // The following are defines for the bit fields in the CAMERA_O_CC_CTRL register. 315 // 316 //****************************************************************************** 317 #define CAMERA_CC_CTRL_CC_IF_SYNCHRO \ 318 0x00080000 // Synchronize all camera sensor 319 // inputs This must be set during 320 // the configuration phase before 321 // CC_EN set to '1'. This can be 322 // used in very high frequency to 323 // avoid dependancy to the IO 324 // timings. 0 No synchro (most of 325 // applications) 1 Synchro enabled 326 // (should never be required) 327 328 #define CAMERA_CC_CTRL_CC_RST 0x00040000 // Resets all the internal finite 329 // states machines of the camera 330 // core module - by writing a 1 to 331 // this bit. must be applied when 332 // CC_EN = 0 Reads returns 0 333 #define CAMERA_CC_CTRL_CC_FRAME_TRIG \ 334 0x00020000 // Set the modality in which CC_EN 335 // works when a disabling of the 336 // sensor camera core is wanted "If 337 // CC_FRAME_TRIG = 1 by writing 338 // ""0"" to CC_EN" the module is 339 // disabled at the end of the frame 340 // "If CC_FRAME_TRIG = 0 by writing 341 // ""0"" to CC_EN" the module is 342 // disabled immediately 343 344 #define CAMERA_CC_CTRL_CC_EN 0x00010000 // Enables the sensor interface of 345 // the camera core module "By 346 // writing ""1"" to this field the 347 // module is enabled." "By writing 348 // ""0"" to this field the module is 349 // disabled at" the end of the frame 350 // if CC_FRAM_TRIG =1 and is 351 // disabled immediately if 352 // CC_FRAM_TRIG = 0 353 #define CAMERA_CC_CTRL_NOBT_SYNCHRO \ 354 0x00002000 // Enables to start at the 355 // beginning of the frame or not in 356 // NoBT 0 Acquisition starts when 357 // Vertical synchro is high 1 358 // Acquisition starts when Vertical 359 // synchro goes from low to high 360 // (beginning of the frame) - 361 // Recommended. 362 363 #define CAMERA_CC_CTRL_BT_CORRECT \ 364 0x00001000 // Enables the correction within 365 // the sync codes in BT mode 0 366 // correction is not enabled 1 367 // correction is enabled 368 369 #define CAMERA_CC_CTRL_PAR_ORDERCAM \ 370 0x00000800 // Enables swap between image-data 371 // in parallel mode 0 swap is not 372 // enabled 1 swap is enabled 373 374 #define CAMERA_CC_CTRL_PAR_CLK_POL \ 375 0x00000400 // Inverts the clock coming from 376 // the sensor in parallel mode 0 377 // clock not inverted - data sampled 378 // on rising edge 1 clock inverted - 379 // data sampled on falling edge 380 381 #define CAMERA_CC_CTRL_NOBT_HS_POL \ 382 0x00000200 // Sets the polarity of the 383 // synchronization signals in NOBT 384 // parallel mode 0 CAM_P_HS is 385 // active high 1 CAM_P_HS is active 386 // low 387 388 #define CAMERA_CC_CTRL_NOBT_VS_POL \ 389 0x00000100 // Sets the polarity of the 390 // synchronization signals in NOBT 391 // parallel mode 0 CAM_P_VS is 392 // active high 1 CAM_P_VS is active 393 // low 394 395 #define CAMERA_CC_CTRL_PAR_MODE_M \ 396 0x0000000E // Sets the Protocol Mode of the 397 // Camera Core module in parallel 398 // mode (when CCP_MODE = 0) """000"" 399 // Parallel NOBT 8-bit" """001"" 400 // Parallel NOBT 10-bit" """010"" 401 // Parallel NOBT 12-bit" """011"" 402 // reserved" """100"" Parallet BT 403 // 8-bit" """101"" Parallel BT 404 // 10-bit" """110"" reserved" 405 // """111"" FIFO test mode. Refer to 406 // Table 12 - FIFO Write and Read 407 // access" 408 409 #define CAMERA_CC_CTRL_PAR_MODE_S 1 410 #define CAMERA_CC_CTRL_CCP_MODE 0x00000001 // Set the Camera Core in CCP mode 411 // 0 CCP mode disabled 1 CCP mode 412 // enabled 413 //****************************************************************************** 414 // 415 // The following are defines for the bit fields in the 416 // CAMERA_O_CC_CTRL_DMA register. 417 // 418 //****************************************************************************** 419 #define CAMERA_CC_CTRL_DMA_DMA_EN \ 420 0x00000100 // Sets the number of dma request 421 // lines 0 DMA interface disabled 422 // The DMA request line stays 423 // inactive 1 DMA interface enabled 424 // The DMA request line is 425 // operational 426 427 #define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_M \ 428 0x0000007F // Sets the threshold of the FIFO 429 // the assertion of the dmarequest 430 // line takes place when the 431 // threshold is reached. 432 // """0000000"" threshold set to 1" 433 // """0000001"" threshold set to 2" 434 // … """1111111"" threshold set to 435 // 128" 436 437 #define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_S 0 438 //****************************************************************************** 439 // 440 // The following are defines for the bit fields in the 441 // CAMERA_O_CC_CTRL_XCLK register. 442 // 443 //****************************************************************************** 444 #define CAMERA_CC_CTRL_XCLK_XCLK_DIV_M \ 445 0x0000001F // Sets the clock divisor value for 446 // CAM_XCLK generation. based on 447 // CAM_MCK (value of CAM_MCLK is 448 // 96MHz) """00000"" CAM_XCLK Stable 449 // Low Level" Divider not enabled 450 // """00001"" CAM_XCLK Stable High 451 // Level" Divider not enabled from 2 452 // to 30 CAM_XCLK = CAM_MCLK / 453 // XCLK_DIV """11111"" Bypass - 454 // CAM_XCLK = CAM_MCLK" 455 456 #define CAMERA_CC_CTRL_XCLK_XCLK_DIV_S 0 457 //****************************************************************************** 458 // 459 // The following are defines for the bit fields in the 460 // CAMERA_O_CC_FIFO_DATA register. 461 // 462 //****************************************************************************** 463 #define CAMERA_CC_FIFO_DATA_FIFO_DATA_M \ 464 0xFFFFFFFF // Writes the 32-bit word into the 465 // FIFO Reads the 32-bit word from 466 // the FIFO 467 468 #define CAMERA_CC_FIFO_DATA_FIFO_DATA_S 0 469 //****************************************************************************** 470 // 471 // The following are defines for the bit fields in the CAMERA_O_CC_TEST register. 472 // 473 //****************************************************************************** 474 #define CAMERA_CC_TEST_FIFO_RD_POINTER_M \ 475 0xFF000000 // FIFO READ Pointer This field 476 // shows the value of the FIFO read 477 // pointer Expected value ranges 478 // from 0 to 127 479 480 #define CAMERA_CC_TEST_FIFO_RD_POINTER_S 24 481 #define CAMERA_CC_TEST_FIFO_WR_POINTER_M \ 482 0x00FF0000 // FIFO WRITE pointer This field 483 // shows the value of the FIFO write 484 // pointer Expected value ranges 485 // from 0 to 127 486 487 #define CAMERA_CC_TEST_FIFO_WR_POINTER_S 16 488 #define CAMERA_CC_TEST_FIFO_LEVEL_M \ 489 0x0000FF00 // FIFO level (how many 32-bit 490 // words the FIFO contains) This 491 // field shows the value of the FIFO 492 // level and can assume values from 493 // 0 to 128 494 495 #define CAMERA_CC_TEST_FIFO_LEVEL_S 8 496 #define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_M \ 497 0x000000FF // FIFO level peak This field shows 498 // the max value of the FIFO level 499 // and can assume values from 0 to 500 // 128 501 502 #define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_S 0 503 //****************************************************************************** 504 // 505 // The following are defines for the bit fields in the 506 // CAMERA_O_CC_GEN_PAR register. 507 // 508 //****************************************************************************** 509 #define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_M \ 510 0x00000007 // Camera Core FIFO DEPTH generic 511 // parameter 512 513 #define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_S 0 514 515 516 517 #endif // __HW_CAMERA_H__ 518
