1 /*
2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef BSP_COMMON_H
8 #define BSP_COMMON_H
9
10 /***********************************************************************************************************************
11 * Includes <System Includes> , "Project Includes"
12 **********************************************************************************************************************/
13
14 /* C99 includes. */
15 #include <stdint.h>
16 #include <stddef.h>
17 #include <stdbool.h>
18 #include <assert.h>
19 #include <string.h>
20 #include <stdlib.h>
21
22 /* Different compiler support. */
23 #include "fsp_common_api.h"
24 #include "bsp_compiler_support.h"
25 #include "bsp_cfg.h"
26
27 /* Zephyr includes */
28 #include <zephyr/arch/cpu.h>
29
30 /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
31 FSP_HEADER
32
33 /*******************************************************************************************************************//**
34 * @addtogroup BSP_MCU
35 * @{
36 **********************************************************************************************************************/
37
38 /***********************************************************************************************************************
39 * Macro definitions
40 **********************************************************************************************************************/
41
42 /** Used to signify that an ELC event is not able to be used as an interrupt. */
43 #define BSP_IRQ_DISABLED (0xFFU)
44
45 /* Vector Number offset */
46 #define BSP_VECTOR_NUM_OFFSET (32)
47 #define BSP_INTERRUPT_TYPE_OFFSET (16U)
48
49 #define FSP_CONTEXT_SAVE
50 #define FSP_CONTEXT_RESTORE
51
52 #define BSP_PRV_CPU_FREQ_1000_MHZ (1000000000U) // CPU frequency is 1000 MHz
53 #define BSP_PRV_CPU_FREQ_500_MHZ (500000000U) // CPU frequency is 500 MHz
54 #define BSP_PRV_CPU_FREQ_200_MHZ (200000000U) // CPU frequency is 200 MHz
55 #define BSP_PRV_CPU_FREQ_150_MHZ (150000000U) // CPU frequency is 150 MHz
56
57 #define BSP_PRV_CA55CLK_FREQ_1200_MHZ (1200000000U) // CA55CLK frequency is 1200 MHz
58 #define BSP_PRV_CA55CLK_FREQ_600_MHZ (600000000U) // CA55CLK frequency is 600 MHz
59
60 #define BSP_PRV_CA55SCLK_FREQ_1000_MHZ (1000000000U) // CA55SCLK frequency is 500 MHz
61 #define BSP_PRV_CA55SCLK_FREQ_500_MHZ (500000000U) // CA55SCLK frequency is 500 MHz
62
63 #define BSP_PRV_ICLK_FREQ_200_MHZ (200000000U) // ICLK frequency is 200 MHz
64 #define BSP_PRV_ICLK_FREQ_150_MHZ (150000000U) // ICLK frequency is 150 MHz
65
66 #define BSP_PRV_PCLKH_FREQ_250_MHZ (250000000U) // PCLKH frequency is 250 MHz
67 #define BSP_PRV_PCLKH_FREQ_200_MHZ (200000000U) // PCLKH frequency is 200 MHz
68 #define BSP_PRV_PCLKH_FREQ_150_MHZ (150000000U) // PCLKH frequency is 150 MHz
69
70 #define BSP_PRV_PCLKM_FREQ_125_MHZ (125000000U) // PCLKM frequency is 125 MHz
71 #define BSP_PRV_PCLKM_FREQ_100_MHZ (100000000U) // PCLKM frequency is 100 MHz
72 #define BSP_PRV_PCLKM_FREQ_75_MHZ (75000000U) // PCLKM frequency is 750 MHz
73
74 #define BSP_PRV_PCLKL_FREQ_62_5_MHZ (62500000U) // PCLKL frequency is 62.5 MHz
75 #define BSP_PRV_PCLKL_FREQ_50_MHZ (50000000U) // PCLKL frequency is 50 MHz
76 #define BSP_PRV_PCLKL_FREQ_37_5_MHZ (37500000U) // PCLKL frequency is 37.5 MHz
77
78 #define BSP_PRV_PCLKADC_FREQ_25_MHZ (25000000U) // PCLKADC frequency is 25 MHz
79 #define BSP_PRV_PCLKADC_FREQ_18_75_MHZ (18750000U) // PCLKADC frequency is 18.75 MHz
80
81 #define BSP_PRV_PCLKGPTL_FREQ_500_MHZ (500000000U) // PCLKGPTL frequency is 500 MHz
82 #define BSP_PRV_PCLKGPTL_FREQ_400_MHZ (400000000U) // PCLKGPTL frequency is 400 MHz
83 #define BSP_PRV_PCLKGPTL_FREQ_300_MHZ (300000000U) // PCLKGPTL frequency is 300 MHz
84
85 #define BSP_PRV_PCLKSCI_FREQ_75_MHZ (75000000U) // PCLKSCI frequency is 75 MHz
86 #define BSP_PRV_PCLKSCI_FREQ_80_MHZ (80000000U) // PCLKSCI frequency is 80 MHz
87 #define BSP_PRV_PCLKSCI_FREQ_96_MHZ (96000000U) // PCLKSCI frequency is 96 MHz
88 #define BSP_PRV_PCLKSCI_FREQ_100_MHZ (100000000U) // PCLKSCI frequency is 100 MHz
89
90 #define BSP_PRV_PCLKSPI_FREQ_75_MHZ (75000000U) // PCLKSPI frequency is 75 MHz
91 #define BSP_PRV_PCLKSPI_FREQ_80_MHZ (80000000U) // PCLKSPI frequency is 80 MHz
92 #define BSP_PRV_PCLKSPI_FREQ_96_MHZ (96000000U) // PCLKSPI frequency is 96 MHz
93 #define BSP_PRV_PCLKSPI_FREQ_100_MHZ (100000000U) // PCLKSPI frequency is 100 MHz
94
95 #define BSP_PRV_PCLKENCO_FREQ_20_MHZ (20000000U) // PCLKENCO frequency is 20 MHz
96 #define BSP_PRV_PCLKENCO_FREQ_80_MHZ (80000000U) // PCLKENCO frequency is 80 MHz
97
98 #define BSP_PRV_PCLKCAN_FREQ_80_MHZ (80000000U) // PCLKCAN frequency is 80 MHz
99 #define BSP_PRV_PCLKCAN_FREQ_40_MHZ (40000000U) // PCLKCAN frequency is 40 MHz
100
101 #define BSP_PRV_CKIO_FREQ_125_MHZ (125000000U) // CKIO frequency is 125 MHz
102 #define BSP_PRV_CKIO_FREQ_100_MHZ (100000000U) // CKIO frequency is 100 MHz
103 #define BSP_PRV_CKIO_FREQ_83_3_MHZ (83333333U) // CKIO frequency is 83.3 MHz
104 #define BSP_PRV_CKIO_FREQ_75_MHZ (75000000U) // CKIO frequency is 75 MHz
105 #define BSP_PRV_CKIO_FREQ_66_7_MHZ (66666666U) // CKIO frequency is 66.7 MHz
106 #define BSP_PRV_CKIO_FREQ_62_5_MHZ (62500000U) // CKIO frequency is 62.5 MHz
107 #define BSP_PRV_CKIO_FREQ_50_MHZ (50000000U) // CKIO frequency is 50 MHz
108 #define BSP_PRV_CKIO_FREQ_41_7_MHZ (41666666U) // CKIO frequency is 41.6 MHz
109 #define BSP_PRV_CKIO_FREQ_40_MHZ (40000000U) // CKIO frequency is 40 MHz
110 #define BSP_PRV_CKIO_FREQ_37_5_MHZ (37500000U) // CKIO frequency is 37.5 MHz
111 #define BSP_PRV_CKIO_FREQ_35_7_MHZ (35714285U) // CKIO frequency is 125 MHz
112 #define BSP_PRV_CKIO_FREQ_33_3_MHZ (33333333U) // CKIO frequency is 33.3MHz
113 #define BSP_PRV_CKIO_FREQ_31_25_MHZ (31250000U) // CKIO frequency is 31.25 MHz
114 #define BSP_PRV_CKIO_FREQ_30_MHZ (30000000U) // CKIO frequency is 30 MHz
115 #define BSP_PRV_CKIO_FREQ_28_6_MHZ (28571428U) // CKIO frequency is 28.6 MHz
116 #define BSP_PRV_CKIO_FREQ_25_MHZ (25000000U) // CKIO frequency is 25 MHz
117 #define BSP_PRV_CKIO_FREQ_21_4_MHZ (21428571U) // CKIO frequency is 21.4 MHz
118 #define BSP_PRV_CKIO_FREQ_18_75_MHZ (18750000U) // CKIO frequency is 18.75 MHz
119 #define BSP_PRV_CKIO_FREQ_NOT_SUPPORTED (0xFFFFFFFFU) // CKIO frequency is not supported
120
121 #define BSP_PRV_XSPI_CLK_FREQ_150_MHZ (150000000U) // XSPI_CLK frequency is 150.0 MHz
122 #define BSP_PRV_XSPI_CLK_FREQ_133_3_MHZ (133333333U) // XSPI_CLK frequency is 133.3 MHz
123 #define BSP_PRV_XSPI_CLK_FREQ_100_MHZ (100000000U) // XSPI_CLK frequency is 100.0 MHz
124 #define BSP_PRV_XSPI_CLK_FREQ_75_MHZ (75000000U) // XSPI_CLK frequency is 75.0 MHz
125 #define BSP_PRV_XSPI_CLK_FREQ_50_MHZ (50000000U) // XSPI_CLK frequency is 50.0 MHz
126 #define BSP_PRV_XSPI_CLK_FREQ_37_5_MHZ (37500000U) // XSPI_CLK frequency is 37.5 MHz
127 #define BSP_PRV_XSPI_CLK_FREQ_25_MHZ (25000000U) // XSPI_CLK frequency is 25.0 MHz
128 #define BSP_PRV_XSPI_CLK_FREQ_12_5_MHZ (12500000U) // XSPI_CLK frequency is 12.5 MHz
129 #define BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED (0xFFFFFFFFU) // XSPI_CLK frequency is not supported
130
131 /** Macro to log and return error without an assertion. */
132 #ifndef FSP_RETURN
133
134 #define FSP_RETURN(err) FSP_ERROR_LOG((err)); \
135 return err;
136 #endif
137
138 /** This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in
139 * user code and do required debugging (breakpoints, stack dump, etc) in this function.*/
140 #if (1 == BSP_CFG_ERROR_LOG)
141
142 #ifndef FSP_ERROR_LOG
143 #define FSP_ERROR_LOG(err) \
144 fsp_error_log((err), __FILE__, __LINE__);
145 #endif
146 #else
147
148 #define FSP_ERROR_LOG(err)
149 #endif
150
151 /** Default assertion calls ::FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP
152 * functions. */
153 #if (3 == BSP_CFG_ASSERT)
154 #define FSP_ASSERT(a)
155 #elif (2 == BSP_CFG_ASSERT)
156 #define FSP_ASSERT(a) {assert(a);}
157 #else
158 #define FSP_ASSERT(a) FSP_ERROR_RETURN((a), FSP_ERR_ASSERTION)
159 #endif // ifndef FSP_ASSERT
160
161 /** All FSP error codes are returned using this macro. Calls ::FSP_ERROR_LOG function if condition "a" is false. Used
162 * to identify runtime errors in FSP functions. */
163
164 #define FSP_ERROR_RETURN(a, err) \
165 { \
166 if ((a)) \
167 { \
168 (void) 0; /* Do nothing */ \
169 } \
170 else \
171 { \
172 FSP_ERROR_LOG(err); \
173 return err; \
174 } \
175 }
176
177 /* Function-like macro used to wait for a condition to be met, most often used to wait for hardware register updates.
178 * This macro can be redefined to add a timeout if necessary. */
179 #ifndef FSP_HARDWARE_REGISTER_WAIT
180 #define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */}
181 #endif
182
183 /* Function-like macro used to wait for a condition to be met with timeout,
184 * most often used to wait for hardware register updates. */
185 #define BSP_HARDWARE_REGISTER_WAIT_WTIH_TIMEOUT(reg, required_value, timeout) \
186 while ((timeout)) \
187 { \
188 if ((required_value) == (reg)) \
189 { \
190 break; \
191 } \
192 (timeout)--; \
193 }
194
195 #ifndef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION
196 #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U)
197 #endif
198
199 /* This macro defines a variable for saving previous mask value */
200 #ifndef FSP_CRITICAL_SECTION_DEFINE
201
202 #define FSP_CRITICAL_SECTION_DEFINE uintptr_t old_mask_level = 0U
203 #endif
204
205 /* These macros abstract methods to save and restore the interrupt state. */
206 #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE read_ICC_PMR_EL1
207 #define FSP_CRITICAL_SECTION_SET_STATE write_ICC_PMR_EL1
208 #define FSP_CRITICAL_SECTION_IRQ_MASK_SET ((uint8_t) (BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION << \
209 BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT))
210
211 /** This macro temporarily saves the current interrupt state and disables interrupts. */
212 #ifndef FSP_CRITICAL_SECTION_ENTER
213 #define FSP_CRITICAL_SECTION_ENTER \
214 old_mask_level = FSP_CRITICAL_SECTION_GET_CURRENT_STATE(); \
215 FSP_CRITICAL_SECTION_SET_STATE(FSP_CRITICAL_SECTION_IRQ_MASK_SET)
216 #endif
217
218 /** This macro restores the previously saved interrupt state, reenabling interrupts. */
219 #ifndef FSP_CRITICAL_SECTION_EXIT
220 #define FSP_CRITICAL_SECTION_EXIT FSP_CRITICAL_SECTION_SET_STATE(old_mask_level)
221 #endif
222
223 /* Number of Cortex processor exceptions. */
224 #define FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS (32U)
225
226 /** Used to signify that the requested IRQ vector is not defined in this system. */
227 #define FSP_INVALID_VECTOR ((IRQn_Type) - 33)
228
229 /* This macro Enable or Disable interrupts. */
230 #if defined(BSP_CFG_CORE_CA55)
231 #define BSP_INTERRUPT_ENABLE __enable_fiq()
232
233 #define BSP_INTERRUPT_DISABLE __disable_fiq()
234
235 #elif defined(BSP_CFG_CORE_CR52)
236 #define BSP_INTERRUPT_ENABLE __asm volatile ("cpsie i"); \
237 __asm volatile ("isb");
238
239 #define BSP_INTERRUPT_DISABLE __asm volatile ("cpsid i"); \
240 __asm volatile ("isb");
241 #endif
242
243 /** In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will
244 * alert the user of the error. The user can override this default behavior by defining their own
245 * BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro.
246 */
247 #if !defined(BSP_CFG_HANDLE_UNRECOVERABLE_ERROR)
248
249 #define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x) __BKPT((x))
250 #endif
251
252 /***********************************************************************************************************************
253 * Typedef definitions
254 **********************************************************************************************************************/
255
256 /** Different warm start entry locations in the BSP. */
257 typedef enum e_bsp_warm_start_event
258 {
259 BSP_WARM_START_RESET = 0, ///< Called almost immediately after reset. No C runtime environment, clocks, or IRQs.
260 BSP_WARM_START_POST_CLOCK, ///< Called after clock initialization. No C runtime environment or IRQs.
261 BSP_WARM_START_POST_C, ///< Called after clocks and C runtime environment have been set up
262 } bsp_warm_start_event_t;
263
264 /* Private enum used in R_FSP_SystemClockHzGet. */
265 typedef enum e_fsp_priv_clock
266 {
267 FSP_PRIV_CLOCK_CPU0,
268 FSP_PRIV_CLOCK_CPU1,
269 FSP_PRIV_CLOCK_CA55C0,
270 FSP_PRIV_CLOCK_CA55C1,
271 FSP_PRIV_CLOCK_CA55C2,
272 FSP_PRIV_CLOCK_CA55C3,
273 FSP_PRIV_CLOCK_CA55SCLK,
274 FSP_PRIV_CLOCK_ICLK,
275 FSP_PRIV_CLOCK_PCLKH,
276 FSP_PRIV_CLOCK_PCLKM,
277 FSP_PRIV_CLOCK_PCLKL,
278 FSP_PRIV_CLOCK_PCLKADC,
279 FSP_PRIV_CLOCK_PCLKGPTL,
280 FSP_PRIV_CLOCK_PCLKENCO,
281 FSP_PRIV_CLOCK_PCLKSPI0,
282 FSP_PRIV_CLOCK_PCLKSPI1,
283 FSP_PRIV_CLOCK_PCLKSPI2,
284 FSP_PRIV_CLOCK_PCLKSPI3,
285 FSP_PRIV_CLOCK_PCLKSCI0,
286 FSP_PRIV_CLOCK_PCLKSCI1,
287 FSP_PRIV_CLOCK_PCLKSCI2,
288 FSP_PRIV_CLOCK_PCLKSCI3,
289 FSP_PRIV_CLOCK_PCLKSCI4,
290 FSP_PRIV_CLOCK_PCLKSCI5,
291 FSP_PRIV_CLOCK_PCLKSCIE0,
292 FSP_PRIV_CLOCK_PCLKSCIE1,
293 FSP_PRIV_CLOCK_PCLKSCIE2,
294 FSP_PRIV_CLOCK_PCLKSCIE3,
295 FSP_PRIV_CLOCK_PCLKSCIE4,
296 FSP_PRIV_CLOCK_PCLKSCIE5,
297 FSP_PRIV_CLOCK_PCLKSCIE6,
298 FSP_PRIV_CLOCK_PCLKSCIE7,
299 FSP_PRIV_CLOCK_PCLKSCIE8,
300 FSP_PRIV_CLOCK_PCLKSCIE9,
301 FSP_PRIV_CLOCK_PCLKSCIE10,
302 FSP_PRIV_CLOCK_PCLKSCIE11,
303 FSP_PRIV_CLOCK_PCLKCAN,
304 FSP_PRIV_CLOCK_CKIO,
305 FSP_PRIV_CLOCK_XSPI0_CLK,
306 FSP_PRIV_CLOCK_XSPI1_CLK
307 } fsp_priv_clock_t;
308
309 /***********************************************************************************************************************
310 * Exported global variables
311 **********************************************************************************************************************/
312 #if (1 == BSP_FEATURE_CGC_CKIO_CLOCK_FREQ_TYPE)
313 extern const uint32_t g_bsp_system_clock_select_ckio[][2];
314 #elif (2 == BSP_FEATURE_CGC_CKIO_CLOCK_FREQ_TYPE)
315 extern const uint32_t g_bsp_system_clock_select_ckio[];
316 #endif
317 extern const uint32_t g_bsp_system_clock_select_xspi_clk[][2];
318 extern const uint32_t g_bsp_system_clock_select_spi_clk[];
319 extern const uint32_t g_bsp_system_clock_select_sci_clk[];
320
321 extern IRQn_Type g_current_interrupt_num[];
322 extern uint8_t g_current_interrupt_pointer;
323
324 /***********************************************************************************************************************
325 * Exported global functions (to be accessed by other files)
326 **********************************************************************************************************************/
327
328 /***********************************************************************************************************************
329 * Inline Functions
330 **********************************************************************************************************************/
331
332 /*******************************************************************************************************************//**
333 * Return active interrupt vector number value
334 *
335 * @return Active interrupt vector number value
336 **********************************************************************************************************************/
R_FSP_CurrentIrqGet(void)337 __STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet (void)
338 {
339 /* Return the current interrupt number. */
340 return g_current_interrupt_num[(g_current_interrupt_pointer - 1U)];
341 }
342
343 /*******************************************************************************************************************//**
344 * Gets the frequency of a system clock.
345 *
346 * @return Frequency of requested clock in Hertz.
347 **********************************************************************************************************************/
R_FSP_SystemClockHzGet(fsp_priv_clock_t clock)348 __STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock)
349 {
350 uint32_t clock_hz = 0;
351
352 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
353 uint32_t fselcpu0 = R_SYSC_S->SCKCR2_b.FSELCPU0;
354 uint32_t divselsub = R_SYSC_S->SCKCR2_b.DIVSELSUB;
355 #elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
356 uint32_t cr52cpu0 = R_SYSC_S->SCKCR2_b.CR52CPU0;
357 uint32_t cr52cpu1 = R_SYSC_S->SCKCR2_b.CR52CPU1;
358 #endif
359 switch (clock)
360 {
361 case FSP_PRIV_CLOCK_CPU0:
362 {
363 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
364 clock_hz = (0 == divselsub) ? BSP_PRV_CPU_FREQ_200_MHZ : BSP_PRV_CPU_FREQ_150_MHZ;
365 clock_hz = clock_hz << fselcpu0;
366 #elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
367 clock_hz = (0 == cr52cpu0) ? BSP_PRV_CPU_FREQ_500_MHZ : BSP_PRV_CPU_FREQ_1000_MHZ;
368 #endif
369 break;
370 }
371
372 case FSP_PRIV_CLOCK_CPU1:
373 {
374 #if (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
375 clock_hz = (0 == cr52cpu1) ? BSP_PRV_CPU_FREQ_500_MHZ : BSP_PRV_CPU_FREQ_1000_MHZ;
376 #endif
377 break;
378 }
379
380 #if (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
381 case FSP_PRIV_CLOCK_CA55C0:
382 {
383 uint32_t ca55core0 = R_SYSC_S->SCKCR2_b.CA55CORE0;
384 clock_hz = (0 == ca55core0) ? BSP_PRV_CA55CLK_FREQ_600_MHZ : BSP_PRV_CA55CLK_FREQ_1200_MHZ;
385 break;
386 }
387
388 case FSP_PRIV_CLOCK_CA55C1:
389 {
390 uint32_t ca55core1 = R_SYSC_S->SCKCR2_b.CA55CORE1;
391 clock_hz = (0 == ca55core1) ? BSP_PRV_CA55CLK_FREQ_600_MHZ : BSP_PRV_CA55CLK_FREQ_1200_MHZ;
392 break;
393 }
394
395 case FSP_PRIV_CLOCK_CA55C2:
396 {
397 uint32_t ca55core2 = R_SYSC_S->SCKCR2_b.CA55CORE2;
398 clock_hz = (0 == ca55core2) ? BSP_PRV_CA55CLK_FREQ_600_MHZ : BSP_PRV_CA55CLK_FREQ_1200_MHZ;
399 break;
400 }
401
402 case FSP_PRIV_CLOCK_CA55C3:
403 {
404 uint32_t ca55core3 = R_SYSC_S->SCKCR2_b.CA55CORE3;
405 clock_hz = (0 == ca55core3) ? BSP_PRV_CA55CLK_FREQ_600_MHZ : BSP_PRV_CA55CLK_FREQ_1200_MHZ;
406 break;
407 }
408
409 case FSP_PRIV_CLOCK_CA55SCLK:
410 {
411 uint32_t ca55sclk = R_SYSC_S->SCKCR2_b.CA55SCLK;
412 clock_hz = (0 == ca55sclk) ? BSP_PRV_CA55SCLK_FREQ_500_MHZ : BSP_PRV_CA55SCLK_FREQ_1000_MHZ;
413 break;
414 }
415 #endif
416
417 case FSP_PRIV_CLOCK_ICLK:
418 {
419 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
420 clock_hz = (0 == divselsub) ? BSP_PRV_ICLK_FREQ_200_MHZ : BSP_PRV_ICLK_FREQ_150_MHZ;
421 #endif
422 break;
423 }
424
425 case FSP_PRIV_CLOCK_PCLKH:
426 {
427 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
428 clock_hz = (0 == divselsub) ? BSP_PRV_PCLKH_FREQ_200_MHZ : BSP_PRV_PCLKH_FREQ_150_MHZ;
429 #elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
430 clock_hz = BSP_PRV_PCLKH_FREQ_250_MHZ;
431 #endif
432 break;
433 }
434
435 case FSP_PRIV_CLOCK_PCLKM:
436 {
437 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
438 clock_hz = (0 == divselsub) ? BSP_PRV_PCLKM_FREQ_100_MHZ : BSP_PRV_PCLKM_FREQ_75_MHZ;
439 #elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
440 clock_hz = BSP_PRV_PCLKM_FREQ_125_MHZ;
441 #endif
442 break;
443 }
444
445 case FSP_PRIV_CLOCK_PCLKL:
446 {
447 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
448 clock_hz = (0 == divselsub) ? BSP_PRV_PCLKL_FREQ_50_MHZ : BSP_PRV_PCLKL_FREQ_37_5_MHZ;
449 #elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
450 clock_hz = BSP_PRV_PCLKL_FREQ_62_5_MHZ;
451 #endif
452 break;
453 }
454
455 case FSP_PRIV_CLOCK_PCLKADC:
456 {
457 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
458 clock_hz = (0 == divselsub) ? BSP_PRV_PCLKADC_FREQ_25_MHZ : BSP_PRV_PCLKADC_FREQ_18_75_MHZ;
459 #elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
460 clock_hz = BSP_PRV_PCLKADC_FREQ_25_MHZ;
461 #endif
462 break;
463 }
464
465 case FSP_PRIV_CLOCK_PCLKGPTL:
466 {
467 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
468 clock_hz = (0 == divselsub) ? BSP_PRV_PCLKGPTL_FREQ_400_MHZ : BSP_PRV_PCLKGPTL_FREQ_300_MHZ;
469 #elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
470 clock_hz = BSP_PRV_PCLKGPTL_FREQ_500_MHZ;
471 #endif
472 break;
473 }
474
475 case FSP_PRIV_CLOCK_PCLKSPI0:
476 {
477 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
478 clock_hz = g_bsp_system_clock_select_spi_clk[R_SYSC_NS->SCKCR_b.SPI0ASYNCSEL];
479 #elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
480 clock_hz = g_bsp_system_clock_select_spi_clk[R_SYSC_NS->SCKCR3_b.SPI0ASYNCSEL];
481 #endif
482 break;
483 }
484
485 case FSP_PRIV_CLOCK_PCLKSPI1:
486 {
487 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
488 clock_hz = g_bsp_system_clock_select_spi_clk[R_SYSC_NS->SCKCR_b.SPI1ASYNCSEL];
489 #elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
490 clock_hz = g_bsp_system_clock_select_spi_clk[R_SYSC_NS->SCKCR3_b.SPI1ASYNCSEL];
491 #endif
492 break;
493 }
494
495 case FSP_PRIV_CLOCK_PCLKSPI2:
496 {
497 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
498 clock_hz = g_bsp_system_clock_select_spi_clk[R_SYSC_NS->SCKCR_b.SPI2ASYNCSEL];
499 #elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
500 clock_hz = g_bsp_system_clock_select_spi_clk[R_SYSC_NS->SCKCR3_b.SPI2ASYNCSEL];
501 #endif
502 break;
503 }
504
505 case FSP_PRIV_CLOCK_PCLKSPI3:
506 {
507 clock_hz = g_bsp_system_clock_select_spi_clk[R_SYSC_S->SCKCR2_b.SPI3ASYNCSEL];
508 break;
509 }
510
511 case FSP_PRIV_CLOCK_PCLKSCI0:
512 {
513 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
514 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR_b.SCI0ASYNCSEL];
515 #elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
516 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR3_b.SCI0ASYNCSEL];
517 #endif
518 break;
519 }
520
521 case FSP_PRIV_CLOCK_PCLKSCI1:
522 {
523 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
524 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR_b.SCI1ASYNCSEL];
525 #elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
526 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR3_b.SCI1ASYNCSEL];
527 #endif
528 break;
529 }
530
531 case FSP_PRIV_CLOCK_PCLKSCI2:
532 {
533 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
534 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR_b.SCI2ASYNCSEL];
535 #elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
536 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR3_b.SCI2ASYNCSEL];
537 #endif
538 break;
539 }
540
541 case FSP_PRIV_CLOCK_PCLKSCI3:
542 {
543 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
544 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR_b.SCI3ASYNCSEL];
545 #elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
546 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR3_b.SCI3ASYNCSEL];
547 #endif
548 break;
549 }
550
551 case FSP_PRIV_CLOCK_PCLKSCI4:
552 {
553 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
554 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR_b.SCI4ASYNCSEL];
555 #elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
556 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR3_b.SCI4ASYNCSEL];
557 #endif
558 break;
559 }
560
561 case FSP_PRIV_CLOCK_PCLKSCI5:
562 {
563 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_S->SCKCR2_b.SCI5ASYNCSEL];
564 break;
565 }
566
567 #if (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
568 case FSP_PRIV_CLOCK_PCLKSCIE0:
569 {
570 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR4_b.SCIE0ASYNCSEL];
571 break;
572 }
573
574 case FSP_PRIV_CLOCK_PCLKSCIE1:
575 {
576 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR4_b.SCIE1ASYNCSEL];
577 break;
578 }
579
580 case FSP_PRIV_CLOCK_PCLKSCIE2:
581 {
582 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR4_b.SCIE2ASYNCSEL];
583 break;
584 }
585
586 case FSP_PRIV_CLOCK_PCLKSCIE3:
587 {
588 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR4_b.SCIE3ASYNCSEL];
589 break;
590 }
591
592 case FSP_PRIV_CLOCK_PCLKSCIE4:
593 {
594 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR4_b.SCIE4ASYNCSEL];
595 break;
596 }
597
598 case FSP_PRIV_CLOCK_PCLKSCIE5:
599 {
600 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR4_b.SCIE5ASYNCSEL];
601 break;
602 }
603
604 case FSP_PRIV_CLOCK_PCLKSCIE6:
605 {
606 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR4_b.SCIE6ASYNCSEL];
607 break;
608 }
609
610 case FSP_PRIV_CLOCK_PCLKSCIE7:
611 {
612 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR4_b.SCIE7ASYNCSEL];
613 break;
614 }
615
616 case FSP_PRIV_CLOCK_PCLKSCIE8:
617 {
618 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR4_b.SCIE8ASYNCSEL];
619 break;
620 }
621
622 case FSP_PRIV_CLOCK_PCLKSCIE9:
623 {
624 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR4_b.SCIE9ASYNCSEL];
625 break;
626 }
627
628 case FSP_PRIV_CLOCK_PCLKSCIE10:
629 {
630 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR4_b.SCIE10ASYNCSEL];
631 break;
632 }
633
634 case FSP_PRIV_CLOCK_PCLKSCIE11:
635 {
636 clock_hz = g_bsp_system_clock_select_sci_clk[R_SYSC_NS->SCKCR4_b.SCIE11ASYNCSEL];
637 break;
638 }
639 #endif
640
641 case FSP_PRIV_CLOCK_PCLKCAN:
642 {
643 uint32_t fselcanfd = R_SYSC_NS->SCKCR_b.FSELCANFD;
644 clock_hz = (0 == fselcanfd) ? BSP_PRV_PCLKCAN_FREQ_80_MHZ : BSP_PRV_PCLKCAN_FREQ_40_MHZ;
645 break;
646 }
647
648 case FSP_PRIV_CLOCK_CKIO:
649 {
650 uint32_t ckio = R_SYSC_NS->SCKCR_b.CKIO;
651 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
652 clock_hz = g_bsp_system_clock_select_ckio[ckio][divselsub];
653 #elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
654 clock_hz = g_bsp_system_clock_select_ckio[ckio];
655 #endif
656 break;
657 }
658
659 case FSP_PRIV_CLOCK_XSPI0_CLK:
660 {
661 uint32_t fselxspi0 = R_SYSC_NS->SCKCR_b.FSELXSPI0;
662 clock_hz = g_bsp_system_clock_select_xspi_clk[fselxspi0][R_SYSC_NS->SCKCR_b.DIVSELXSPI0];
663 break;
664 }
665
666 case FSP_PRIV_CLOCK_XSPI1_CLK:
667 {
668 uint32_t fselxspi1 = R_SYSC_NS->SCKCR_b.FSELXSPI1;
669 clock_hz = g_bsp_system_clock_select_xspi_clk[fselxspi1][R_SYSC_NS->SCKCR_b.DIVSELXSPI1];
670 break;
671 }
672
673 #if (BSP_FEATURE_BSP_ENCOUT_SUPPORTED)
674 case FSP_PRIV_CLOCK_PCLKENCO:
675 {
676 #if (1 == BSP_FEATURE_CGC_SCKCR_TYPE)
677 clock_hz = BSP_PRV_PCLKENCO_FREQ_20_MHZ;
678 #elif (2 == BSP_FEATURE_CGC_SCKCR_TYPE)
679 uint32_t encoutclk = R_SYSC_NS->SCKCR4_b.ENCOUTCLK;
680 clock_hz = (0 == encoutclk) ? BSP_PRV_PCLKENCO_FREQ_20_MHZ : BSP_PRV_PCLKENCO_FREQ_80_MHZ;
681 #endif
682 break;
683 }
684 #endif
685
686 default:
687 {
688 break;
689 }
690 }
691
692 return clock_hz;
693 }
694
695 #if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT))
696
697 /** Prototype of default function called before errors are returned in FSP code if BSP_CFG_LOG_ERRORS is set to 1. */
698 void fsp_error_log(fsp_err_t err, const char * file, int32_t line);
699
700 #endif
701
702 /** @} (end addtogroup BSP_MCU) */
703
704 void * bsp_prv_malloc(size_t size);
705 void bsp_prv_free(void * ptr);
706
707 /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
708 FSP_FOOTER
709
710 #endif
711
