1 /*
2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 
7 #ifndef BSP_CLOCKS_H
8 #define BSP_CLOCKS_H
9 
10 /***********************************************************************************************************************
11  * Includes
12  **********************************************************************************************************************/
13 #include "bsp_clock_cfg.h"
14 #include "bsp_api.h"
15 
16 /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
17 FSP_HEADER
18 
19 /***********************************************************************************************************************
20  * Macro definitions
21  **********************************************************************************************************************/
22 
23 /* The following definitions are macros instead of enums because the values are used in preprocessor conditionals. */
24 /* Must match SCKCR.CKSEL values. */
25 #define BSP_CLOCKS_SOURCE_CLOCK_HOCO               (0) // The high speed on chip oscillator.
26 #define BSP_CLOCKS_SOURCE_CLOCK_MOCO               (1) // The middle speed on chip oscillator.
27 #define BSP_CLOCKS_SOURCE_CLOCK_LOCO               (2) // The low speed on chip oscillator.
28 #define BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC           (3) // The main oscillator.
29 #define BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK           (4) // The subclock oscillator.
30 
31 #if !BSP_FEATURE_CGC_REGISTER_SET_B
32  #if 0 < BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS
33   #define BSP_CLOCKS_SOURCE_CLOCK_PLL              (5) // The PLL oscillator.
34  #endif
35  #if 0 < BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS
36   #define BSP_CLOCKS_SOURCE_CLOCK_PLL2             (6) // The PLL2 oscillator.
37  #endif
38  #if (1 < BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS && 1 < BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS)
39   #define BSP_CLOCKS_SOURCE_CLOCK_PLL1P            (BSP_CLOCKS_SOURCE_CLOCK_PLL)
40   #define BSP_CLOCKS_SOURCE_CLOCK_PLL2P            (BSP_CLOCKS_SOURCE_CLOCK_PLL2)
41   #define BSP_CLOCKS_SOURCE_CLOCK_PLL1Q            (7)  // The PLL1Q oscillator.
42   #define BSP_CLOCKS_SOURCE_CLOCK_PLL1R            (8)  // The PLL1R oscillator.
43   #define BSP_CLOCKS_SOURCE_CLOCK_PLL2Q            (9)  // The PLL2Q oscillator.
44   #define BSP_CLOCKS_SOURCE_CLOCK_PLL2R            (10) // The PLL2R oscillator.
45  #endif
46 #else
47  #define BSP_CLOCKS_SOURCE_CLOCK_FSXP              (11) // Subsystem Clock (FSXP) source.
48 
49 /* The following definitions are macros instead of enums because the values are used in preprocessor conditionals. */
50 /* Must match ICLKSCR.CKSEL, FMAINSCR.CKSEL, FOCOSCR.CKSEL, FSUBSCR.CKSEL, OSMC.WUTMMCK0 and CKS0.CSEL values. */
51  #define BSP_CLOCKS_SOURCE_CLOCK_FMAIN             (0)  // Use Main System clock (FMAIN) as System clock (ICLK) source.
52  #define BSP_CLOCKS_SOURCE_CLOCK_FSUB              (1)  // Use Sub System clock (FSUB) as System clock (ICLK) source.
53  #define BSP_CLOCKS_FMAIN_SOURCE_CLOCK_FOCO        (0)  // Use Main on-chip oscillator clock (FOCO) as Main System clock (FMAIN) source.
54  #define BSP_CLOCKS_FMAIN_SOURCE_CLOCK_MAIN_OSC    (1)  // Use Main clock oscillator (MOSC) as Main System clock (FMAIN) source.
55  #define BSP_CLOCKS_FOCO_SOURCE_CLOCK_HOCO         (0)  // Use High-speed on-chip oscillator (HOCO) as Main on-chip oscillator clock (FOCO) source.
56  #define BSP_CLOCKS_FOCO_SOURCE_CLOCK_MOCO         (1)  // Use Middle-speed on-chip oscillator (MOCO) as Main on-chip oscillator clock (FOCO) source.
57  #define BSP_CLOCKS_FSUB_SOURCE_CLOCK_SUBCLOCK     (0)  // Use Sub-clock oscillator (SOSC) as Sub System clock (FSUB) source.
58  #define BSP_CLOCKS_FSUB_SOURCE_CLOCK_LOCO         (1)  // Use Low-speed on-chip oscillator clock (LOCO) as Sub System clock (FSUB) source.
59  #define BSP_CLOCKS_CLKOUT_SOURCE_CLOCK_FMAIN      (0)  // Use Main System clock (FMAIN) as Clock Out (CLKOUT) source.
60  #define BSP_CLOCKS_CLKOUT_SOURCE_CLOCK_FSUB       (1)  // Use Subsystem Clock (FSUB) as Clock Out (CLKOUT) source.
61 
62 /* Offset to convert OSTS setting to OSTC value (OSTC = ~(BSP_PRV_OSTC_OFFSET >> OSTS)) */
63  #define BSP_PRV_OSTC_OFFSET                       (0x7FU)
64 
65 #endif
66 
67 /* PLLs are not supported in the following scenarios:
68  *  - When using low voltage mode
69  *  - When using an MCU that does not have a PLL
70  *  - When the PLL only accepts the main oscillator as a source and XTAL is not used
71  */
72 #if BSP_FEATURE_CGC_HAS_PLL && !BSP_CFG_USE_LOW_VOLTAGE_MODE && \
73     !((1U != BSP_FEATURE_CGC_PLLCCR_TYPE) &&                    \
74     (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) &&                      \
75     (4U != BSP_FEATURE_CGC_PLLCCR_TYPE) &&                      \
76     (5U != BSP_FEATURE_CGC_PLLCCR_TYPE) &&                      \
77     !BSP_CLOCK_CFG_MAIN_OSC_POPULATED)
78  #define BSP_PRV_PLL_SUPPORTED      (1)
79  #if BSP_FEATURE_CGC_HAS_PLL2
80   #define BSP_PRV_PLL2_SUPPORTED    (1)
81  #else
82   #define BSP_PRV_PLL2_SUPPORTED    (0)
83  #endif
84 #else
85  #define BSP_PRV_PLL_SUPPORTED      (0)
86  #define BSP_PRV_PLL2_SUPPORTED     (0)
87 #endif
88 
89 /* The ICLK frequency at startup is used to determine the ideal operating mode to set after startup. The PLL frequency
90  * calculated here is also used to initialize the g_clock_freq array. */
91 #if BSP_PRV_PLL_SUPPORTED
92  #if ((1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE)) && \
93     (BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE)
94   #define BSP_PRV_PLL_SOURCE_FREQ_HZ     (BSP_HOCO_HZ)
95  #else
96   #define BSP_PRV_PLL_SOURCE_FREQ_HZ     (BSP_CFG_XTAL_HZ)
97  #endif
98 #endif
99 #if BSP_PRV_PLL2_SUPPORTED
100  #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL2_SOURCE
101   #define BSP_PRV_PLL2_SOURCE_FREQ_HZ    (BSP_HOCO_HZ)
102  #else
103   #define BSP_PRV_PLL2_SOURCE_FREQ_HZ    (BSP_CFG_XTAL_HZ)
104  #endif
105 #endif
106 
107 #define BSP_MOCO_FREQ_HZ                 (BSP_MOCO_HZ)
108 
109 /* Frequencies of clocks with fixed freqencies. */
110 #define BSP_LOCO_FREQ_HZ                 (32768U) // LOCO frequency is fixed at 32768 Hz
111 #define BSP_SUBCLOCK_FREQ_HZ             (32768U) // Subclock frequency is 32768 Hz
112 
113 #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_CLOCK_SOURCE
114  #define BSP_STARTUP_SOURCE_CLOCK_HZ     (BSP_HOCO_HZ)
115 #elif BSP_CLOCKS_SOURCE_CLOCK_MOCO == BSP_CFG_CLOCK_SOURCE
116  #define BSP_STARTUP_SOURCE_CLOCK_HZ     (BSP_MOCO_FREQ_HZ)
117 #elif BSP_CLOCKS_SOURCE_CLOCK_LOCO == BSP_CFG_CLOCK_SOURCE
118  #define BSP_STARTUP_SOURCE_CLOCK_HZ     (BSP_LOCO_FREQ_HZ)
119 #elif BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE
120  #define BSP_STARTUP_SOURCE_CLOCK_HZ     (BSP_SUBCLOCK_FREQ_HZ)
121 #elif BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_CLOCK_SOURCE
122  #define BSP_STARTUP_SOURCE_CLOCK_HZ     (BSP_CFG_XTAL_HZ)
123 #elif BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE
124  #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) || (5U == BSP_FEATURE_CGC_PLLCCR_TYPE)
125   #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE
126    #define BSP_PRV_PLL_SOURCE_FREQ_HZ    (BSP_CFG_XTAL_HZ)
127   #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE
128    #define BSP_PRV_PLL_SOURCE_FREQ_HZ    (BSP_HOCO_HZ)
129   #endif
130   #define BSP_STARTUP_SOURCE_CLOCK_HZ    (((BSP_PRV_PLL_SOURCE_FREQ_HZ * (BSP_CFG_PLL_MUL + 1U)) >> 1) / \
131                                           (BSP_CFG_PLL_DIV + 1U))
132  #elif (2U == BSP_FEATURE_CGC_PLLCCR_TYPE)
133   #define BSP_PRV_PLL_SOURCE_FREQ_HZ     (BSP_CFG_XTAL_HZ)
134   #define BSP_STARTUP_SOURCE_CLOCK_HZ    ((BSP_PRV_PLL_SOURCE_FREQ_HZ * ((BSP_CFG_PLL_MUL + 1U) >> 1)) >> \
135                                           (BSP_CFG_PLL_DIV))
136  #elif (3U == BSP_FEATURE_CGC_PLLCCR_TYPE)
137   #define BSP_STARTUP_SOURCE_CLOCK_HZ    (BSP_CFG_PLL1P_FREQUENCY_HZ)
138  #endif
139 #endif
140 
141 /* Convert divisor bitfield settings into divisor values to calculate startup clocks */
142 #define BSP_PRV_SCKDIVCR_DIV_VALUE(div)    (((div) & 8U) ? (3U << ((div) & ~8U)) : (1U << (div)))
143 #define BSP_PRV_CPUCLK_DIV_VALUE          BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_CPUCLK_DIV)
144 
145 #if !BSP_FEATURE_CGC_REGISTER_SET_B
146  #define BSP_PRV_ICLK_DIV_VALUE           BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_ICLK_DIV)
147 #else
148  #define BSP_PRV_ICLK_DIV_VALUE           (1U << BSP_CFG_ICLK_DIV)
149 #endif
150 
151 #define BSP_PRV_PCLKA_DIV_VALUE           BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKA_DIV)
152 #define BSP_PRV_PCLKB_DIV_VALUE           BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKB_DIV)
153 #define BSP_PRV_PCLKC_DIV_VALUE           BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKC_DIV)
154 #define BSP_PRV_PCLKD_DIV_VALUE           BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKD_DIV)
155 #define BSP_PRV_PCLKE_DIV_VALUE           BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKE_DIV)
156 #define BSP_PRV_BCLK_DIV_VALUE            BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_BCLK_DIV)
157 #define BSP_PRV_FCLK_DIV_VALUE            BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_FCLK_DIV)
158 
159 /* Startup clock frequency of each system clock. These macros are only helpful if the system clock and dividers have
160  * not changed since startup. These macros are not used in FSP modules except for the clock startup code. */
161 #define BSP_STARTUP_CPUCLK_HZ             (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_CPUCLK_DIV_VALUE)
162 #define BSP_STARTUP_ICLK_HZ               (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_ICLK_DIV_VALUE)
163 #define BSP_STARTUP_PCLKA_HZ              (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKA_DIV_VALUE)
164 #define BSP_STARTUP_PCLKB_HZ              (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKB_DIV_VALUE)
165 #define BSP_STARTUP_PCLKC_HZ              (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKC_DIV_VALUE)
166 #define BSP_STARTUP_PCLKD_HZ              (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKD_DIV_VALUE)
167 #define BSP_STARTUP_PCLKE_HZ              (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_PCLKE_DIV_VALUE)
168 #define BSP_STARTUP_BCLK_HZ               (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_BCLK_DIV_VALUE)
169 #define BSP_STARTUP_FCLK_HZ               (BSP_STARTUP_SOURCE_CLOCK_HZ / BSP_PRV_FCLK_DIV_VALUE)
170 
171 /* System clock divider options. */
172 #define BSP_CLOCKS_SYS_CLOCK_DIV_1        (0)  // System clock divided by 1.
173 #define BSP_CLOCKS_SYS_CLOCK_DIV_2        (1)  // System clock divided by 2.
174 #define BSP_CLOCKS_SYS_CLOCK_DIV_4        (2)  // System clock divided by 4.
175 #define BSP_CLOCKS_SYS_CLOCK_DIV_8        (3)  // System clock divided by 8.
176 #define BSP_CLOCKS_SYS_CLOCK_DIV_16       (4)  // System clock divided by 16.
177 #define BSP_CLOCKS_SYS_CLOCK_DIV_32       (5)  // System clock divided by 32.
178 #define BSP_CLOCKS_SYS_CLOCK_DIV_64       (6)  // System clock divided by 64.
179 #define BSP_CLOCKS_SYS_CLOCK_DIV_128      (7)  // System clock divided by 128 (available for CLKOUT only).
180 #define BSP_CLOCKS_SYS_CLOCK_DIV_3        (8)  // System clock divided by 3.
181 #define BSP_CLOCKS_SYS_CLOCK_DIV_6        (9)  // System clock divided by 6.
182 #define BSP_CLOCKS_SYS_CLOCK_DIV_12       (10) // System clock divided by 12.
183 
184 /* USB clock divider options. */
185 #define BSP_CLOCKS_USB_CLOCK_DIV_1        (0)  // Divide USB source clock by 1
186 #define BSP_CLOCKS_USB_CLOCK_DIV_2        (1)  // Divide USB source clock by 2
187 #define BSP_CLOCKS_USB_CLOCK_DIV_3        (2)  // Divide USB source clock by 3
188 #define BSP_CLOCKS_USB_CLOCK_DIV_4        (3)  // Divide USB source clock by 4
189 #define BSP_CLOCKS_USB_CLOCK_DIV_5        (4)  // Divide USB source clock by 5
190 #define BSP_CLOCKS_USB_CLOCK_DIV_6        (5)  // Divide USB source clock by 6
191 #define BSP_CLOCKS_USB_CLOCK_DIV_8        (7)  // Divide USB source clock by 8
192 
193 /* USB60 clock divider options. */
194 #define BSP_CLOCKS_USB60_CLOCK_DIV_1      (0)  // Divide USB60 source clock by 1
195 #define BSP_CLOCKS_USB60_CLOCK_DIV_2      (1)  // Divide USB60 source clock by 2
196 #define BSP_CLOCKS_USB60_CLOCK_DIV_3      (5)  // Divide USB60 source clock by 3
197 #define BSP_CLOCKS_USB60_CLOCK_DIV_4      (2)  // Divide USB60 source clock by 4
198 #define BSP_CLOCKS_USB60_CLOCK_DIV_5      (6)  // Divide USB60 source clock by 5
199 #define BSP_CLOCKS_USB60_CLOCK_DIV_6      (3)  // Divide USB66 source clock by 6
200 #define BSP_CLOCKS_USB60_CLOCK_DIV_8      (4)  // Divide USB60 source clock by 8
201 
202 /* GLCD clock divider options. */
203 #define BSP_CLOCKS_LCD_CLOCK_DIV_1        (0)  // Divide LCD source clock by 1
204 #define BSP_CLOCKS_LCD_CLOCK_DIV_2        (1)  // Divide LCD source clock by 2
205 #define BSP_CLOCKS_LCD_CLOCK_DIV_3        (5)  // Divide LCD source clock by 3
206 #define BSP_CLOCKS_LCD_CLOCK_DIV_4        (2)  // Divide LCD source clock by 4
207 #define BSP_CLOCKS_LCD_CLOCK_DIV_5        (6)  // Divide LCD source clock by 5
208 #define BSP_CLOCKS_LCD_CLOCK_DIV_6        (3)  // Divide LCD source clock by 6
209 #define BSP_CLOCKS_LCD_CLOCK_DIV_8        (4)  // Divide LCD source clock by 8
210 
211 /* OCTA clock divider options. */
212 #define BSP_CLOCKS_OCTA_CLOCK_DIV_1       (0)  // Divide OCTA source clock by 1
213 #define BSP_CLOCKS_OCTA_CLOCK_DIV_2       (1)  // Divide OCTA source clock by 2
214 #define BSP_CLOCKS_OCTA_CLOCK_DIV_3       (5)  // Divide OCTA source clock by 3
215 #define BSP_CLOCKS_OCTA_CLOCK_DIV_4       (2)  // Divide OCTA source clock by 4
216 #define BSP_CLOCKS_OCTA_CLOCK_DIV_5       (6)  // Divide OCTA source clock by 5
217 #define BSP_CLOCKS_OCTA_CLOCK_DIV_6       (3)  // Divide OCTA source clock by 6
218 #define BSP_CLOCKS_OCTA_CLOCK_DIV_8       (4)  // Divide OCTA source clock by 8
219 
220 /* CANFD clock divider options. */
221 #define BSP_CLOCKS_CANFD_CLOCK_DIV_1      (0)  // Divide CANFD source clock by 1
222 #define BSP_CLOCKS_CANFD_CLOCK_DIV_2      (1)  // Divide CANFD source clock by 2
223 #define BSP_CLOCKS_CANFD_CLOCK_DIV_3      (5)  // Divide CANFD source clock by 3
224 #define BSP_CLOCKS_CANFD_CLOCK_DIV_4      (2)  // Divide CANFD source clock by 4
225 #define BSP_CLOCKS_CANFD_CLOCK_DIV_5      (6)  // Divide CANFD source clock by 5
226 #define BSP_CLOCKS_CANFD_CLOCK_DIV_6      (3)  // Divide CANFD source clock by 6
227 #define BSP_CLOCKS_CANFD_CLOCK_DIV_8      (4)  // Divide CANFD source clock by 8
228 
229 /* SCI clock divider options. */
230 #define BSP_CLOCKS_SCI_CLOCK_DIV_1        (0)  // Divide SCI source clock by 1
231 #define BSP_CLOCKS_SCI_CLOCK_DIV_2        (1)  // Divide SCI source clock by 2
232 #define BSP_CLOCKS_SCI_CLOCK_DIV_3        (5)  // Divide SCI source clock by 3
233 #define BSP_CLOCKS_SCI_CLOCK_DIV_4        (2)  // Divide SCI source clock by 4
234 #define BSP_CLOCKS_SCI_CLOCK_DIV_5        (6)  // Divide SCI source clock by 5
235 #define BSP_CLOCKS_SCI_CLOCK_DIV_6        (3)  // Divide SCI source clock by 6
236 #define BSP_CLOCKS_SCI_CLOCK_DIV_8        (4)  // Divide SCI source clock by 8
237 
238 /* SPI clock divider options. */
239 #define BSP_CLOCKS_SPI_CLOCK_DIV_1        (0)  // Divide SPI source clock by 1
240 #define BSP_CLOCKS_SPI_CLOCK_DIV_2        (1)  // Divide SPI source clock by 2
241 #define BSP_CLOCKS_SPI_CLOCK_DIV_3        (5)  // Divide SPI source clock by 3
242 #define BSP_CLOCKS_SPI_CLOCK_DIV_4        (2)  // Divide SPI source clock by 4
243 #define BSP_CLOCKS_SPI_CLOCK_DIV_5        (6)  // Divide SPI source clock by 5
244 #define BSP_CLOCKS_SPI_CLOCK_DIV_6        (3)  // Divide SPI source clock by 6
245 #define BSP_CLOCKS_SPI_CLOCK_DIV_8        (4)  // Divide SPI source clock by 8
246 
247 /* SCISPI clock divider options. */
248 #define BSP_CLOCKS_SCISPI_CLOCK_DIV_1     (0)  // Divide SCISPI source clock by 1
249 #define BSP_CLOCKS_SCISPI_CLOCK_DIV_2     (1)  // Divide SCISPI source clock by 2
250 #define BSP_CLOCKS_SCISPI_CLOCK_DIV_4     (2)  // Divide SCISPI source clock by 4
251 #define BSP_CLOCKS_SCISPI_CLOCK_DIV_6     (3)  // Divide SCISPI source clock by 6
252 #define BSP_CLOCKS_SCISPI_CLOCK_DIV_8     (4)  // Divide SCISPI source clock by 8
253 
254 /* GPT clock divider options. */
255 #define BSP_CLOCKS_GPT_CLOCK_DIV_1        (0)  // Divide GPT source clock by 1
256 #define BSP_CLOCKS_GPT_CLOCK_DIV_2        (1)  // Divide GPT source clock by 2
257 #define BSP_CLOCKS_GPT_CLOCK_DIV_3        (5)  // Divide GPT source clock by 3
258 #define BSP_CLOCKS_GPT_CLOCK_DIV_4        (2)  // Divide GPT source clock by 4
259 #define BSP_CLOCKS_GPT_CLOCK_DIV_5        (6)  // Divide GPT source clock by 5
260 #define BSP_CLOCKS_GPT_CLOCK_DIV_6        (3)  // Divide GPT source clock by 6
261 #define BSP_CLOCKS_GPT_CLOCK_DIV_8        (4)  // Divide GPT source clock by 8
262 
263 /* IIC clock divider options. */
264 #define BSP_CLOCKS_IIC_CLOCK_DIV_1        (0)  // Divide IIC source clock by 1
265 #define BSP_CLOCKS_IIC_CLOCK_DIV_2        (1)  // Divide IIC source clock by 2
266 #define BSP_CLOCKS_IIC_CLOCK_DIV_4        (2)  // Divide IIC source clock by 4
267 #define BSP_CLOCKS_IIC_CLOCK_DIV_6        (3)  // Divide IIC source clock by 6
268 #define BSP_CLOCKS_IIC_CLOCK_DIV_8        (4)  // Divide IIC source clock by 8
269 
270 /* CEC clock divider options. */
271 #define BSP_CLOCKS_CEC_CLOCK_DIV_1        (0)  // Divide CEC source clock by 1
272 #define BSP_CLOCKS_CEC_CLOCK_DIV_2        (1)  // Divide CEC source clock by 2
273 
274 /* I3C clock divider options. */
275 #define BSP_CLOCKS_I3C_CLOCK_DIV_1        (0)  // Divide I3C source clock by 1
276 #define BSP_CLOCKS_I3C_CLOCK_DIV_2        (1)  // Divide I3C source clock by 2
277 #define BSP_CLOCKS_I3C_CLOCK_DIV_3        (5)  // Divide I3C source clock by 3
278 #define BSP_CLOCKS_I3C_CLOCK_DIV_4        (2)  // Divide I3C source clock by 4
279 #define BSP_CLOCKS_I3C_CLOCK_DIV_5        (6)  // Divide I3C source clock by 5
280 #define BSP_CLOCKS_I3C_CLOCK_DIV_6        (3)  // Divide I3C source clock by 6
281 #define BSP_CLOCKS_I3C_CLOCK_DIV_8        (4)  // Divide I3C source clock by 8
282 
283 /* SAU clock divider options. */
284 #define BSP_CLOCKS_SAU_CLOCK_DIV_1        (0)  // Divide SAU source clock by 1
285 #define BSP_CLOCKS_SAU_CLOCK_DIV_2        (1)  // Divide SAU source clock by 2
286 #define BSP_CLOCKS_SAU_CLOCK_DIV_4        (2)  // Divide SAU source clock by 4
287 #define BSP_CLOCKS_SAU_CLOCK_DIV_8        (3)  // Divide SAU source clock by 8
288 #define BSP_CLOCKS_SAU_CLOCK_DIV_16       (4)  // Divide SAU source clock by 16
289 #define BSP_CLOCKS_SAU_CLOCK_DIV_32       (5)  // Divide SAU source clock by 32
290 #define BSP_CLOCKS_SAU_CLOCK_DIV_64       (6)  // Divide SAU source clock by 64
291 #define BSP_CLOCKS_SAU_CLOCK_DIV_128      (7)  // Divide SAU source clock by 128
292 #define BSP_CLOCKS_SAU_CLOCK_DIV_256      (8)  // Divide SAU source clock by 256
293 #define BSP_CLOCKS_SAU_CLOCK_DIV_512      (9)  // Divide SAU source clock by 512
294 #define BSP_CLOCKS_SAU_CLOCK_DIV_1024     (10) // Divide SAU source clock by 1024
295 #define BSP_CLOCKS_SAU_CLOCK_DIV_2048     (11) // Divide SAU source clock by 2048
296 #define BSP_CLOCKS_SAU_CLOCK_DIV_4096     (12) // Divide SAU source clock by 4096
297 #define BSP_CLOCKS_SAU_CLOCK_DIV_8192     (13) // Divide SAU source clock by 8192
298 #define BSP_CLOCKS_SAU_CLOCK_DIV_16384    (14) // Divide SAU source clock by 16384
299 #define BSP_CLOCKS_SAU_CLOCK_DIV_32768    (15) // Divide SAU source clock by 32768
300 
301 /* PLL divider options. */
302 #define BSP_CLOCKS_PLL_DIV_1              (0)
303 #define BSP_CLOCKS_PLL_DIV_2              (1)
304 #define BSP_CLOCKS_PLL_DIV_3              (2)
305 #define BSP_CLOCKS_PLL_DIV_4              (3)
306 #define BSP_CLOCKS_PLL_DIV_5              (4)
307 #define BSP_CLOCKS_PLL_DIV_6              (5)
308 #define BSP_CLOCKS_PLL_DIV_8              (7)
309 #define BSP_CLOCKS_PLL_DIV_9              (8)
310 #define BSP_CLOCKS_PLL_DIV_16             (15)
311 
312 /* PLL multiplier options. */
313 #if (4U == BSP_FEATURE_CGC_PLLCCR_TYPE)
314 
315 /* Offset from decimal multiplier to register value for PLLCCR type 4. */
316  #define BSP_PRV_CLOCKS_PLL_MUL_INT_OFFSET    (574)
317 
318 /**
319  * X=Integer portion of the multiplier.
320  * Y=Fractional portion of the multiplier. (not used for this PLLCCR type)
321  */
322  #define BSP_CLOCKS_PLL_MUL(X, Y)    (X - BSP_PRV_CLOCKS_PLL_MUL_INT_OFFSET)
323 
324 #elif (3U != BSP_FEATURE_CGC_PLLCCR_TYPE)
325 
326 /**
327  * X=Integer portion of the multiplier.
328  * Y=Fractional portion of the multiplier.
329  */
330  #define BSP_CLOCKS_PLL_MUL(X, Y)    (((X) << 1 | ((Y) >= 50U ? 1 : 0)) - 1U)
331 
332 #else
333 
334  #define BSP_PRV_CLOCKS_PLL_MUL_INT_SHIFT     (2U)
335  #define BSP_PRV_CLOCKS_PLL_MUL_FRAC_MASK     (0x3U)
336  #define BSP_PRV_CLOCKS_PLL_MUL_FRAC_SHIFT    (0U)
337 
338 /**
339  * X=Integer portion of the multiplier.
340  * Y=Fractional portion of the multiplier.
341  */
342  #define BSP_CLOCKS_PLL_MUL(X, Y)    ((((X) -1U) << 2U) | ((Y) == 50U ? 3U : ((Y) / 33U)))
343 
344 #endif
345 
346 /* Configuration option used to disable clock output. */
347 #define BSP_CLOCKS_CLOCK_DISABLED               (0xFFU)
348 
349 /* HOCO cycles per microsecond. */
350 #define BSP_PRV_HOCO_CYCLES_PER_US              (BSP_HOCO_HZ / 1000000U)
351 
352 /* Maximum number of delay cycles required to ensure 1 us passes between setting PLLCCR and clearing PLLCR. */
353 #if BSP_HOCO_HZ < 48000000U
354  #define BSP_PRV_MAX_HOCO_CYCLES_PER_US         (BSP_PRV_HOCO_CYCLES_PER_US)
355 #else
356  #define BSP_PRV_MAX_HOCO_CYCLES_PER_US         (48U)
357 #endif
358 
359 /* Create a mask of valid bits in SCKDIVCR. */
360 #define BSP_PRV_SCKDIVCR_ICLK_MASK              (FSP_PRV_SCKDIVCR_DIV_MASK << 24)
361 #if BSP_FEATURE_CGC_HAS_PCLKD
362  #define BSP_PRV_SCKDIVCR_PCLKD_MASK            (FSP_PRV_SCKDIVCR_DIV_MASK << 0)
363 #else
364  #define BSP_PRV_SCKDIVCR_PCLKD_MASK            (0U)
365 #endif
366 #if BSP_FEATURE_CGC_HAS_PCLKC
367  #define BSP_PRV_SCKDIVCR_PCLKC_MASK            (FSP_PRV_SCKDIVCR_DIV_MASK << 4)
368 #else
369  #define BSP_PRV_SCKDIVCR_PCLKC_MASK            (0U)
370 #endif
371 #if BSP_FEATURE_CGC_HAS_PCLKB
372  #define BSP_PRV_SCKDIVCR_PCLKB_MASK            (FSP_PRV_SCKDIVCR_DIV_MASK << 8)
373 #else
374  #define BSP_PRV_SCKDIVCR_PCLKB_MASK            (0U)
375 #endif
376 #if BSP_FEATURE_CGC_HAS_PCLKA
377  #define BSP_PRV_SCKDIVCR_PCLKA_MASK            (FSP_PRV_SCKDIVCR_DIV_MASK << 12)
378 #else
379  #define BSP_PRV_SCKDIVCR_PCLKA_MASK            (0U)
380 #endif
381 #if BSP_FEATURE_CGC_HAS_BCLK || BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB
382  #define BSP_PRV_SCKDIVCR_BCLK_MASK             (FSP_PRV_SCKDIVCR_DIV_MASK << 16)
383 #else
384  #define BSP_PRV_SCKDIVCR_BCLK_MASK             (0U)
385 #endif
386 #if BSP_FEATURE_CGC_HAS_PCLKE
387  #define BSP_PRV_SCKDIVCR_PCLKE_MASK            (FSP_PRV_SCKDIVCR_DIV_MASK << 24)
388 #else
389  #define BSP_PRV_SCKDIVCR_PCLKE_MASK            (0U)
390 #endif
391 #if BSP_FEATURE_CGC_HAS_FCLK
392  #define BSP_PRV_SCKDIVCR_FCLK_MASK             (FSP_PRV_SCKDIVCR_DIV_MASK << 28)
393 #else
394  #define BSP_PRV_SCKDIVCR_FCLK_MASK             (0U)
395 #endif
396 #define BSP_PRV_SCKDIVCR_MASK                   (BSP_PRV_SCKDIVCR_ICLK_MASK | BSP_PRV_SCKDIVCR_PCLKD_MASK |  \
397                                                  BSP_PRV_SCKDIVCR_PCLKC_MASK | BSP_PRV_SCKDIVCR_PCLKB_MASK | \
398                                                  BSP_PRV_SCKDIVCR_PCLKA_MASK | BSP_PRV_SCKDIVCR_BCLK_MASK |  \
399                                                  BSP_PRV_SCKDIVCR_PCLKE_MASK | BSP_PRV_SCKDIVCR_FCLK_MASK)
400 
401 /* FLL is only used when enabled, present and the subclock is populated. */
402 #if BSP_FEATURE_CGC_HAS_FLL && BSP_CFG_FLL_ENABLE && BSP_CLOCK_CFG_SUBCLOCK_POPULATED
403  #define BSP_PRV_HOCO_USE_FLL                   (1)
404  #ifndef BSP_PRV_FLL_STABILIZATION_TIME_US
405   #define BSP_PRV_FLL_STABILIZATION_TIME_US     (1800)
406  #endif
407 #else
408  #define BSP_PRV_HOCO_USE_FLL                   (0)
409  #define BSP_PRV_FLL_STABILIZATION_TIME_US      (0)
410 #endif
411 
412 #if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_SYSC_HAS_VBTICTLR
413  #define BSP_PRV_RTC_RESET_DELAY_US             (200)
414 #endif
415 
416 /* Operating power control modes. */
417 #if BSP_FEATURE_CGC_REGISTER_SET_B
418  #define BSP_PRV_OPERATING_MODE_LOW_SPEED       (1U) // Should match FLMODE low speed
419  #define BSP_PRV_OPERATING_MODE_MIDDLE_SPEED    (2U) // Should match FLMODE middle speed
420  #define BSP_PRV_OPERATING_MODE_HIGH_SPEED      (3U) // Should match FLMODE high speed
421 #else
422  #define BSP_PRV_OPERATING_MODE_HIGH_SPEED      (0U) // Should match OPCCR OPCM high speed
423  #define BSP_PRV_OPERATING_MODE_MIDDLE_SPEED    (1U) // Should match OPCCR OPCM middle speed
424  #define BSP_PRV_OPERATING_MODE_LOW_VOLTAGE     (2U) // Should match OPCCR OPCM low voltage
425  #define BSP_PRV_OPERATING_MODE_LOW_SPEED       (3U) // Should match OPCCR OPCM low speed
426 #endif
427 #define BSP_PRV_OPERATING_MODE_SUBOSC_SPEED     (4U) // Can be any value not otherwise used
428 
429 /***********************************************************************************************************************
430  * Typedef definitions
431  **********************************************************************************************************************/
432 
433 #if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD
434 typedef struct
435 {
436     uint32_t pll_freq;
437 } bsp_clock_update_callback_args_t;
438 
439  #if defined(__ARMCC_VERSION) || defined(__ICCARM__)
440 typedef void (BSP_CMSE_NONSECURE_CALL * bsp_clock_update_callback_t)(bsp_clock_update_callback_args_t *
441                                                                      p_callback_args);
442  #elif defined(__GNUC__)
443 typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_clock_update_callback_t)(bsp_clock_update_callback_args_t *
444                                                                              p_callback_args);
445  #endif
446 
447 #endif
448 
449 /** PLL multiplier values */
450 typedef enum e_cgc_pll_mul
451 {
452     CGC_PLL_MUL_4_0    = BSP_CLOCKS_PLL_MUL(4U, 0U),    ///< PLL multiplier of 4.00
453     CGC_PLL_MUL_4_5    = BSP_CLOCKS_PLL_MUL(4U, 50U),   ///< PLL multiplier of 4.50
454     CGC_PLL_MUL_5_0    = BSP_CLOCKS_PLL_MUL(5U, 0U),    ///< PLL multiplier of 5.00
455     CGC_PLL_MUL_5_5    = BSP_CLOCKS_PLL_MUL(5U, 50U),   ///< PLL multiplier of 5.50
456     CGC_PLL_MUL_6_0    = BSP_CLOCKS_PLL_MUL(6U, 0U),    ///< PLL multiplier of 6.00
457     CGC_PLL_MUL_6_5    = BSP_CLOCKS_PLL_MUL(6U, 50U),   ///< PLL multiplier of 6.50
458     CGC_PLL_MUL_7_0    = BSP_CLOCKS_PLL_MUL(7U, 0U),    ///< PLL multiplier of 7.00
459     CGC_PLL_MUL_7_5    = BSP_CLOCKS_PLL_MUL(7U, 50U),   ///< PLL multiplier of 7.50
460     CGC_PLL_MUL_8_0    = BSP_CLOCKS_PLL_MUL(8U, 0U),    ///< PLL multiplier of 8.00
461     CGC_PLL_MUL_8_5    = BSP_CLOCKS_PLL_MUL(8U, 50U),   ///< PLL multiplier of 8.50
462     CGC_PLL_MUL_9_0    = BSP_CLOCKS_PLL_MUL(9U, 0U),    ///< PLL multiplier of 9.00
463     CGC_PLL_MUL_9_5    = BSP_CLOCKS_PLL_MUL(9U, 50U),   ///< PLL multiplier of 9.50
464     CGC_PLL_MUL_10_0   = BSP_CLOCKS_PLL_MUL(10U, 0U),   ///< PLL multiplier of 10.00
465     CGC_PLL_MUL_10_5   = BSP_CLOCKS_PLL_MUL(10U, 50U),  ///< PLL multiplier of 10.50
466     CGC_PLL_MUL_11_0   = BSP_CLOCKS_PLL_MUL(11U, 0U),   ///< PLL multiplier of 11.00
467     CGC_PLL_MUL_11_5   = BSP_CLOCKS_PLL_MUL(11U, 50U),  ///< PLL multiplier of 11.50
468     CGC_PLL_MUL_12_0   = BSP_CLOCKS_PLL_MUL(12U, 0U),   ///< PLL multiplier of 12.00
469     CGC_PLL_MUL_12_5   = BSP_CLOCKS_PLL_MUL(12U, 50U),  ///< PLL multiplier of 12.50
470     CGC_PLL_MUL_13_0   = BSP_CLOCKS_PLL_MUL(13U, 0U),   ///< PLL multiplier of 13.00
471     CGC_PLL_MUL_13_5   = BSP_CLOCKS_PLL_MUL(13U, 50U),  ///< PLL multiplier of 13.50
472     CGC_PLL_MUL_14_0   = BSP_CLOCKS_PLL_MUL(14U, 0U),   ///< PLL multiplier of 14.00
473     CGC_PLL_MUL_14_5   = BSP_CLOCKS_PLL_MUL(14U, 50U),  ///< PLL multiplier of 14.50
474     CGC_PLL_MUL_15_0   = BSP_CLOCKS_PLL_MUL(15U, 0U),   ///< PLL multiplier of 15.00
475     CGC_PLL_MUL_15_5   = BSP_CLOCKS_PLL_MUL(15U, 50U),  ///< PLL multiplier of 15.50
476     CGC_PLL_MUL_16_0   = BSP_CLOCKS_PLL_MUL(16U, 0U),   ///< PLL multiplier of 16.00
477     CGC_PLL_MUL_16_5   = BSP_CLOCKS_PLL_MUL(16U, 50U),  ///< PLL multiplier of 16.50
478     CGC_PLL_MUL_17_0   = BSP_CLOCKS_PLL_MUL(17U, 0U),   ///< PLL multiplier of 17.00
479     CGC_PLL_MUL_17_5   = BSP_CLOCKS_PLL_MUL(17U, 50U),  ///< PLL multiplier of 17.50
480     CGC_PLL_MUL_18_0   = BSP_CLOCKS_PLL_MUL(18U, 0U),   ///< PLL multiplier of 18.00
481     CGC_PLL_MUL_18_5   = BSP_CLOCKS_PLL_MUL(18U, 50U),  ///< PLL multiplier of 18.50
482     CGC_PLL_MUL_19_0   = BSP_CLOCKS_PLL_MUL(19U, 0U),   ///< PLL multiplier of 19.00
483     CGC_PLL_MUL_19_5   = BSP_CLOCKS_PLL_MUL(19U, 50U),  ///< PLL multiplier of 19.50
484     CGC_PLL_MUL_20_0   = BSP_CLOCKS_PLL_MUL(20U, 0U),   ///< PLL multiplier of 20.00
485     CGC_PLL_MUL_20_5   = BSP_CLOCKS_PLL_MUL(20U, 50U),  ///< PLL multiplier of 20.50
486     CGC_PLL_MUL_21_0   = BSP_CLOCKS_PLL_MUL(21U, 0U),   ///< PLL multiplier of 21.00
487     CGC_PLL_MUL_21_5   = BSP_CLOCKS_PLL_MUL(21U, 50U),  ///< PLL multiplier of 21.50
488     CGC_PLL_MUL_22_0   = BSP_CLOCKS_PLL_MUL(22U, 0U),   ///< PLL multiplier of 22.00
489     CGC_PLL_MUL_22_5   = BSP_CLOCKS_PLL_MUL(22U, 50U),  ///< PLL multiplier of 22.50
490     CGC_PLL_MUL_23_0   = BSP_CLOCKS_PLL_MUL(23U, 0U),   ///< PLL multiplier of 23.00
491     CGC_PLL_MUL_23_5   = BSP_CLOCKS_PLL_MUL(23U, 50U),  ///< PLL multiplier of 23.50
492     CGC_PLL_MUL_24_0   = BSP_CLOCKS_PLL_MUL(24U, 0U),   ///< PLL multiplier of 24.00
493     CGC_PLL_MUL_24_5   = BSP_CLOCKS_PLL_MUL(24U, 50U),  ///< PLL multiplier of 24.50
494     CGC_PLL_MUL_25_0   = BSP_CLOCKS_PLL_MUL(25U, 0U),   ///< PLL multiplier of 25.00
495     CGC_PLL_MUL_25_5   = BSP_CLOCKS_PLL_MUL(25U, 50U),  ///< PLL multiplier of 25.50
496     CGC_PLL_MUL_26_0   = BSP_CLOCKS_PLL_MUL(26U, 0U),   ///< PLL multiplier of 26.00
497     CGC_PLL_MUL_26_33  = BSP_CLOCKS_PLL_MUL(26U, 33U),  ///< PLL multiplier of 26.33
498     CGC_PLL_MUL_26_5   = BSP_CLOCKS_PLL_MUL(26U, 50U),  ///< PLL multiplier of 26.50
499     CGC_PLL_MUL_26_66  = BSP_CLOCKS_PLL_MUL(26U, 66U),  ///< PLL multiplier of 26.66
500     CGC_PLL_MUL_27_0   = BSP_CLOCKS_PLL_MUL(27U, 0U),   ///< PLL multiplier of 27.00
501     CGC_PLL_MUL_27_33  = BSP_CLOCKS_PLL_MUL(27U, 33U),  ///< PLL multiplier of 27.33
502     CGC_PLL_MUL_27_5   = BSP_CLOCKS_PLL_MUL(27U, 50U),  ///< PLL multiplier of 27.50
503     CGC_PLL_MUL_27_66  = BSP_CLOCKS_PLL_MUL(27U, 66U),  ///< PLL multiplier of 27.66
504     CGC_PLL_MUL_28_0   = BSP_CLOCKS_PLL_MUL(28U, 0U),   ///< PLL multiplier of 28.00
505     CGC_PLL_MUL_28_33  = BSP_CLOCKS_PLL_MUL(28U, 33U),  ///< PLL multiplier of 28.33
506     CGC_PLL_MUL_28_5   = BSP_CLOCKS_PLL_MUL(28U, 50U),  ///< PLL multiplier of 28.50
507     CGC_PLL_MUL_28_66  = BSP_CLOCKS_PLL_MUL(28U, 66U),  ///< PLL multiplier of 28.66
508     CGC_PLL_MUL_29_0   = BSP_CLOCKS_PLL_MUL(29U, 0U),   ///< PLL multiplier of 29.00
509     CGC_PLL_MUL_29_33  = BSP_CLOCKS_PLL_MUL(29U, 33U),  ///< PLL multiplier of 29.33
510     CGC_PLL_MUL_29_5   = BSP_CLOCKS_PLL_MUL(29U, 50U),  ///< PLL multiplier of 29.50
511     CGC_PLL_MUL_29_66  = BSP_CLOCKS_PLL_MUL(29U, 66U),  ///< PLL multiplier of 29.66
512     CGC_PLL_MUL_30_0   = BSP_CLOCKS_PLL_MUL(30U, 0U),   ///< PLL multiplier of 30.00
513     CGC_PLL_MUL_30_33  = BSP_CLOCKS_PLL_MUL(30U, 33U),  ///< PLL multiplier of 30.33
514     CGC_PLL_MUL_30_5   = BSP_CLOCKS_PLL_MUL(30U, 50U),  ///< PLL multiplier of 30.50
515     CGC_PLL_MUL_30_66  = BSP_CLOCKS_PLL_MUL(30U, 66U),  ///< PLL multiplier of 30.66
516     CGC_PLL_MUL_31_0   = BSP_CLOCKS_PLL_MUL(31U, 0U),   ///< PLL multiplier of 31.00
517     CGC_PLL_MUL_31_33  = BSP_CLOCKS_PLL_MUL(31U, 33U),  ///< PLL multiplier of 31.33
518     CGC_PLL_MUL_31_5   = BSP_CLOCKS_PLL_MUL(31U, 50U),  ///< PLL multiplier of 31.50
519     CGC_PLL_MUL_31_66  = BSP_CLOCKS_PLL_MUL(31U, 66U),  ///< PLL multiplier of 31.66
520     CGC_PLL_MUL_32_0   = BSP_CLOCKS_PLL_MUL(32U, 0U),   ///< PLL multiplier of 32.00
521     CGC_PLL_MUL_32_33  = BSP_CLOCKS_PLL_MUL(32U, 33U),  ///< PLL multiplier of 32.33
522     CGC_PLL_MUL_32_5   = BSP_CLOCKS_PLL_MUL(32U, 50U),  ///< PLL multiplier of 32.50
523     CGC_PLL_MUL_32_66  = BSP_CLOCKS_PLL_MUL(32U, 66U),  ///< PLL multiplier of 32.66
524     CGC_PLL_MUL_33_0   = BSP_CLOCKS_PLL_MUL(33U, 0U),   ///< PLL multiplier of 33.00
525     CGC_PLL_MUL_33_33  = BSP_CLOCKS_PLL_MUL(33U, 33U),  ///< PLL multiplier of 33.33
526     CGC_PLL_MUL_33_5   = BSP_CLOCKS_PLL_MUL(33U, 50U),  ///< PLL multiplier of 33.50
527     CGC_PLL_MUL_33_66  = BSP_CLOCKS_PLL_MUL(33U, 66U),  ///< PLL multiplier of 33.66
528     CGC_PLL_MUL_34_0   = BSP_CLOCKS_PLL_MUL(34U, 0U),   ///< PLL multiplier of 34.00
529     CGC_PLL_MUL_34_33  = BSP_CLOCKS_PLL_MUL(34U, 33U),  ///< PLL multiplier of 34.33
530     CGC_PLL_MUL_34_5   = BSP_CLOCKS_PLL_MUL(34U, 50U),  ///< PLL multiplier of 34.50
531     CGC_PLL_MUL_34_66  = BSP_CLOCKS_PLL_MUL(34U, 66U),  ///< PLL multiplier of 34.66
532     CGC_PLL_MUL_35_0   = BSP_CLOCKS_PLL_MUL(35U, 0U),   ///< PLL multiplier of 35.00
533     CGC_PLL_MUL_35_33  = BSP_CLOCKS_PLL_MUL(35U, 33U),  ///< PLL multiplier of 35.33
534     CGC_PLL_MUL_35_5   = BSP_CLOCKS_PLL_MUL(35U, 50U),  ///< PLL multiplier of 35.50
535     CGC_PLL_MUL_35_66  = BSP_CLOCKS_PLL_MUL(35U, 66U),  ///< PLL multiplier of 35.66
536     CGC_PLL_MUL_36_0   = BSP_CLOCKS_PLL_MUL(36U, 0U),   ///< PLL multiplier of 36.00
537     CGC_PLL_MUL_36_33  = BSP_CLOCKS_PLL_MUL(36U, 33U),  ///< PLL multiplier of 36.33
538     CGC_PLL_MUL_36_5   = BSP_CLOCKS_PLL_MUL(36U, 50U),  ///< PLL multiplier of 36.50
539     CGC_PLL_MUL_36_66  = BSP_CLOCKS_PLL_MUL(36U, 66U),  ///< PLL multiplier of 36.66
540     CGC_PLL_MUL_37_0   = BSP_CLOCKS_PLL_MUL(37U, 0U),   ///< PLL multiplier of 37.00
541     CGC_PLL_MUL_37_33  = BSP_CLOCKS_PLL_MUL(37U, 33U),  ///< PLL multiplier of 37.33
542     CGC_PLL_MUL_37_5   = BSP_CLOCKS_PLL_MUL(37U, 50U),  ///< PLL multiplier of 37.50
543     CGC_PLL_MUL_37_66  = BSP_CLOCKS_PLL_MUL(37U, 66U),  ///< PLL multiplier of 37.66
544     CGC_PLL_MUL_38_0   = BSP_CLOCKS_PLL_MUL(38U, 0U),   ///< PLL multiplier of 38.00
545     CGC_PLL_MUL_38_33  = BSP_CLOCKS_PLL_MUL(38U, 33U),  ///< PLL multiplier of 38.33
546     CGC_PLL_MUL_38_5   = BSP_CLOCKS_PLL_MUL(38U, 50U),  ///< PLL multiplier of 38.50
547     CGC_PLL_MUL_38_66  = BSP_CLOCKS_PLL_MUL(38U, 66U),  ///< PLL multiplier of 38.66
548     CGC_PLL_MUL_39_0   = BSP_CLOCKS_PLL_MUL(39U, 0U),   ///< PLL multiplier of 39.00
549     CGC_PLL_MUL_39_33  = BSP_CLOCKS_PLL_MUL(39U, 33U),  ///< PLL multiplier of 39.33
550     CGC_PLL_MUL_39_5   = BSP_CLOCKS_PLL_MUL(39U, 50U),  ///< PLL multiplier of 39.50
551     CGC_PLL_MUL_39_66  = BSP_CLOCKS_PLL_MUL(39U, 66U),  ///< PLL multiplier of 39.66
552     CGC_PLL_MUL_40_0   = BSP_CLOCKS_PLL_MUL(40U, 0U),   ///< PLL multiplier of 40.00
553     CGC_PLL_MUL_40_33  = BSP_CLOCKS_PLL_MUL(40U, 33U),  ///< PLL multiplier of 40.33
554     CGC_PLL_MUL_40_5   = BSP_CLOCKS_PLL_MUL(40U, 50U),  ///< PLL multiplier of 40.50
555     CGC_PLL_MUL_40_66  = BSP_CLOCKS_PLL_MUL(40U, 66U),  ///< PLL multiplier of 40.66
556     CGC_PLL_MUL_41_0   = BSP_CLOCKS_PLL_MUL(41U, 0U),   ///< PLL multiplier of 41.00
557     CGC_PLL_MUL_41_33  = BSP_CLOCKS_PLL_MUL(41U, 33U),  ///< PLL multiplier of 41.33
558     CGC_PLL_MUL_41_5   = BSP_CLOCKS_PLL_MUL(41U, 50U),  ///< PLL multiplier of 41.50
559     CGC_PLL_MUL_41_66  = BSP_CLOCKS_PLL_MUL(41U, 66U),  ///< PLL multiplier of 41.66
560     CGC_PLL_MUL_42_0   = BSP_CLOCKS_PLL_MUL(42U, 0U),   ///< PLL multiplier of 42.00
561     CGC_PLL_MUL_42_33  = BSP_CLOCKS_PLL_MUL(42U, 33U),  ///< PLL multiplier of 42.33
562     CGC_PLL_MUL_42_5   = BSP_CLOCKS_PLL_MUL(42U, 50U),  ///< PLL multiplier of 42.50
563     CGC_PLL_MUL_42_66  = BSP_CLOCKS_PLL_MUL(42U, 66U),  ///< PLL multiplier of 42.66
564     CGC_PLL_MUL_43_0   = BSP_CLOCKS_PLL_MUL(43U, 0U),   ///< PLL multiplier of 43.00
565     CGC_PLL_MUL_43_33  = BSP_CLOCKS_PLL_MUL(43U, 33U),  ///< PLL multiplier of 43.33
566     CGC_PLL_MUL_43_5   = BSP_CLOCKS_PLL_MUL(43U, 50U),  ///< PLL multiplier of 43.50
567     CGC_PLL_MUL_43_66  = BSP_CLOCKS_PLL_MUL(43U, 66U),  ///< PLL multiplier of 43.66
568     CGC_PLL_MUL_44_0   = BSP_CLOCKS_PLL_MUL(44U, 0U),   ///< PLL multiplier of 44.00
569     CGC_PLL_MUL_44_33  = BSP_CLOCKS_PLL_MUL(44U, 33U),  ///< PLL multiplier of 44.33
570     CGC_PLL_MUL_44_5   = BSP_CLOCKS_PLL_MUL(44U, 50U),  ///< PLL multiplier of 44.50
571     CGC_PLL_MUL_44_66  = BSP_CLOCKS_PLL_MUL(44U, 66U),  ///< PLL multiplier of 44.66
572     CGC_PLL_MUL_45_0   = BSP_CLOCKS_PLL_MUL(45U, 0U),   ///< PLL multiplier of 45.00
573     CGC_PLL_MUL_45_33  = BSP_CLOCKS_PLL_MUL(45U, 33U),  ///< PLL multiplier of 45.33
574     CGC_PLL_MUL_45_5   = BSP_CLOCKS_PLL_MUL(45U, 50U),  ///< PLL multiplier of 45.50
575     CGC_PLL_MUL_45_66  = BSP_CLOCKS_PLL_MUL(45U, 66U),  ///< PLL multiplier of 45.66
576     CGC_PLL_MUL_46_0   = BSP_CLOCKS_PLL_MUL(46U, 0U),   ///< PLL multiplier of 46.00
577     CGC_PLL_MUL_46_33  = BSP_CLOCKS_PLL_MUL(46U, 33U),  ///< PLL multiplier of 46.33
578     CGC_PLL_MUL_46_5   = BSP_CLOCKS_PLL_MUL(46U, 50U),  ///< PLL multiplier of 46.50
579     CGC_PLL_MUL_46_66  = BSP_CLOCKS_PLL_MUL(46U, 66U),  ///< PLL multiplier of 46.66
580     CGC_PLL_MUL_47_0   = BSP_CLOCKS_PLL_MUL(47U, 0U),   ///< PLL multiplier of 47.00
581     CGC_PLL_MUL_47_33  = BSP_CLOCKS_PLL_MUL(47U, 33U),  ///< PLL multiplier of 47.33
582     CGC_PLL_MUL_47_5   = BSP_CLOCKS_PLL_MUL(47U, 50U),  ///< PLL multiplier of 47.50
583     CGC_PLL_MUL_47_66  = BSP_CLOCKS_PLL_MUL(47U, 66U),  ///< PLL multiplier of 47.66
584     CGC_PLL_MUL_48_0   = BSP_CLOCKS_PLL_MUL(48U, 0U),   ///< PLL multiplier of 48.00
585     CGC_PLL_MUL_48_33  = BSP_CLOCKS_PLL_MUL(48U, 33U),  ///< PLL multiplier of 48.33
586     CGC_PLL_MUL_48_5   = BSP_CLOCKS_PLL_MUL(48U, 50U),  ///< PLL multiplier of 48.50
587     CGC_PLL_MUL_48_66  = BSP_CLOCKS_PLL_MUL(48U, 66U),  ///< PLL multiplier of 48.66
588     CGC_PLL_MUL_49_0   = BSP_CLOCKS_PLL_MUL(49U, 0U),   ///< PLL multiplier of 49.00
589     CGC_PLL_MUL_49_33  = BSP_CLOCKS_PLL_MUL(49U, 33U),  ///< PLL multiplier of 49.33
590     CGC_PLL_MUL_49_5   = BSP_CLOCKS_PLL_MUL(49U, 50U),  ///< PLL multiplier of 49.50
591     CGC_PLL_MUL_49_66  = BSP_CLOCKS_PLL_MUL(49U, 66U),  ///< PLL multiplier of 49.66
592     CGC_PLL_MUL_50_0   = BSP_CLOCKS_PLL_MUL(50U, 0U),   ///< PLL multiplier of 50.00
593     CGC_PLL_MUL_50_33  = BSP_CLOCKS_PLL_MUL(50U, 33U),  ///< PLL multiplier of 50.33
594     CGC_PLL_MUL_50_5   = BSP_CLOCKS_PLL_MUL(50U, 50U),  ///< PLL multiplier of 50.50
595     CGC_PLL_MUL_50_66  = BSP_CLOCKS_PLL_MUL(50U, 66U),  ///< PLL multiplier of 50.66
596     CGC_PLL_MUL_51_0   = BSP_CLOCKS_PLL_MUL(51U, 0U),   ///< PLL multiplier of 51.00
597     CGC_PLL_MUL_51_33  = BSP_CLOCKS_PLL_MUL(51U, 33U),  ///< PLL multiplier of 51.33
598     CGC_PLL_MUL_51_5   = BSP_CLOCKS_PLL_MUL(51U, 50U),  ///< PLL multiplier of 51.50
599     CGC_PLL_MUL_51_66  = BSP_CLOCKS_PLL_MUL(51U, 66U),  ///< PLL multiplier of 51.66
600     CGC_PLL_MUL_52_0   = BSP_CLOCKS_PLL_MUL(52U, 0U),   ///< PLL multiplier of 52.00
601     CGC_PLL_MUL_52_33  = BSP_CLOCKS_PLL_MUL(52U, 33U),  ///< PLL multiplier of 52.33
602     CGC_PLL_MUL_52_5   = BSP_CLOCKS_PLL_MUL(52U, 50U),  ///< PLL multiplier of 52.50
603     CGC_PLL_MUL_52_66  = BSP_CLOCKS_PLL_MUL(52U, 66U),  ///< PLL multiplier of 52.66
604     CGC_PLL_MUL_53_0   = BSP_CLOCKS_PLL_MUL(53U, 0U),   ///< PLL multiplier of 53.00
605     CGC_PLL_MUL_53_33  = BSP_CLOCKS_PLL_MUL(53U, 33U),  ///< PLL multiplier of 53.33
606     CGC_PLL_MUL_53_5   = BSP_CLOCKS_PLL_MUL(53U, 50U),  ///< PLL multiplier of 53.50
607     CGC_PLL_MUL_53_66  = BSP_CLOCKS_PLL_MUL(53U, 66U),  ///< PLL multiplier of 53.66
608     CGC_PLL_MUL_54_0   = BSP_CLOCKS_PLL_MUL(54U, 0U),   ///< PLL multiplier of 54.00
609     CGC_PLL_MUL_54_33  = BSP_CLOCKS_PLL_MUL(54U, 33U),  ///< PLL multiplier of 54.33
610     CGC_PLL_MUL_54_5   = BSP_CLOCKS_PLL_MUL(54U, 50U),  ///< PLL multiplier of 54.50
611     CGC_PLL_MUL_54_66  = BSP_CLOCKS_PLL_MUL(54U, 66U),  ///< PLL multiplier of 54.66
612     CGC_PLL_MUL_55_0   = BSP_CLOCKS_PLL_MUL(55U, 0U),   ///< PLL multiplier of 55.00
613     CGC_PLL_MUL_55_33  = BSP_CLOCKS_PLL_MUL(55U, 33U),  ///< PLL multiplier of 55.33
614     CGC_PLL_MUL_55_5   = BSP_CLOCKS_PLL_MUL(55U, 50U),  ///< PLL multiplier of 55.50
615     CGC_PLL_MUL_55_66  = BSP_CLOCKS_PLL_MUL(55U, 66U),  ///< PLL multiplier of 55.66
616     CGC_PLL_MUL_56_0   = BSP_CLOCKS_PLL_MUL(56U, 0U),   ///< PLL multiplier of 56.00
617     CGC_PLL_MUL_56_33  = BSP_CLOCKS_PLL_MUL(56U, 33U),  ///< PLL multiplier of 56.33
618     CGC_PLL_MUL_56_5   = BSP_CLOCKS_PLL_MUL(56U, 50U),  ///< PLL multiplier of 56.50
619     CGC_PLL_MUL_56_66  = BSP_CLOCKS_PLL_MUL(56U, 66U),  ///< PLL multiplier of 56.66
620     CGC_PLL_MUL_57_0   = BSP_CLOCKS_PLL_MUL(57U, 0U),   ///< PLL multiplier of 57.00
621     CGC_PLL_MUL_57_33  = BSP_CLOCKS_PLL_MUL(57U, 33U),  ///< PLL multiplier of 57.33
622     CGC_PLL_MUL_57_5   = BSP_CLOCKS_PLL_MUL(57U, 50U),  ///< PLL multiplier of 57.50
623     CGC_PLL_MUL_57_66  = BSP_CLOCKS_PLL_MUL(57U, 66U),  ///< PLL multiplier of 57.66
624     CGC_PLL_MUL_58_0   = BSP_CLOCKS_PLL_MUL(58U, 0U),   ///< PLL multiplier of 58.00
625     CGC_PLL_MUL_58_33  = BSP_CLOCKS_PLL_MUL(58U, 33U),  ///< PLL multiplier of 58.33
626     CGC_PLL_MUL_58_5   = BSP_CLOCKS_PLL_MUL(58U, 50U),  ///< PLL multiplier of 58.50
627     CGC_PLL_MUL_58_66  = BSP_CLOCKS_PLL_MUL(58U, 66U),  ///< PLL multiplier of 58.66
628     CGC_PLL_MUL_59_0   = BSP_CLOCKS_PLL_MUL(59U, 0U),   ///< PLL multiplier of 59.00
629     CGC_PLL_MUL_59_33  = BSP_CLOCKS_PLL_MUL(59U, 33U),  ///< PLL multiplier of 59.33
630     CGC_PLL_MUL_59_5   = BSP_CLOCKS_PLL_MUL(59U, 50U),  ///< PLL multiplier of 59.50
631     CGC_PLL_MUL_59_66  = BSP_CLOCKS_PLL_MUL(59U, 66U),  ///< PLL multiplier of 59.66
632     CGC_PLL_MUL_60_0   = BSP_CLOCKS_PLL_MUL(60U, 0U),   ///< PLL multiplier of 60.00
633     CGC_PLL_MUL_60_33  = BSP_CLOCKS_PLL_MUL(60U, 33U),  ///< PLL multiplier of 60.33
634     CGC_PLL_MUL_60_5   = BSP_CLOCKS_PLL_MUL(60U, 50U),  ///< PLL multiplier of 60.50
635     CGC_PLL_MUL_60_66  = BSP_CLOCKS_PLL_MUL(60U, 66U),  ///< PLL multiplier of 60.66
636     CGC_PLL_MUL_61_0   = BSP_CLOCKS_PLL_MUL(61U, 0U),   ///< PLL multiplier of 61.00
637     CGC_PLL_MUL_61_33  = BSP_CLOCKS_PLL_MUL(61U, 33U),  ///< PLL multiplier of 61.33
638     CGC_PLL_MUL_61_5   = BSP_CLOCKS_PLL_MUL(61U, 50U),  ///< PLL multiplier of 61.50
639     CGC_PLL_MUL_61_66  = BSP_CLOCKS_PLL_MUL(61U, 66U),  ///< PLL multiplier of 61.66
640     CGC_PLL_MUL_62_0   = BSP_CLOCKS_PLL_MUL(62U, 0U),   ///< PLL multiplier of 62.00
641     CGC_PLL_MUL_62_33  = BSP_CLOCKS_PLL_MUL(62U, 33U),  ///< PLL multiplier of 62.33
642     CGC_PLL_MUL_62_5   = BSP_CLOCKS_PLL_MUL(62U, 50U),  ///< PLL multiplier of 62.50
643     CGC_PLL_MUL_62_66  = BSP_CLOCKS_PLL_MUL(62U, 66U),  ///< PLL multiplier of 62.66
644     CGC_PLL_MUL_63_0   = BSP_CLOCKS_PLL_MUL(63U, 0U),   ///< PLL multiplier of 63.00
645     CGC_PLL_MUL_63_33  = BSP_CLOCKS_PLL_MUL(63U, 33U),  ///< PLL multiplier of 63.33
646     CGC_PLL_MUL_63_5   = BSP_CLOCKS_PLL_MUL(63U, 50U),  ///< PLL multiplier of 63.50
647     CGC_PLL_MUL_63_66  = BSP_CLOCKS_PLL_MUL(63U, 66U),  ///< PLL multiplier of 63.66
648     CGC_PLL_MUL_64_0   = BSP_CLOCKS_PLL_MUL(64U, 0U),   ///< PLL multiplier of 64.00
649     CGC_PLL_MUL_64_33  = BSP_CLOCKS_PLL_MUL(64U, 33U),  ///< PLL multiplier of 64.33
650     CGC_PLL_MUL_64_5   = BSP_CLOCKS_PLL_MUL(64U, 50U),  ///< PLL multiplier of 64.50
651     CGC_PLL_MUL_64_66  = BSP_CLOCKS_PLL_MUL(64U, 66U),  ///< PLL multiplier of 64.66
652     CGC_PLL_MUL_65_0   = BSP_CLOCKS_PLL_MUL(65U, 0U),   ///< PLL multiplier of 65.00
653     CGC_PLL_MUL_65_33  = BSP_CLOCKS_PLL_MUL(65U, 33U),  ///< PLL multiplier of 65.33
654     CGC_PLL_MUL_65_5   = BSP_CLOCKS_PLL_MUL(65U, 50U),  ///< PLL multiplier of 65.50
655     CGC_PLL_MUL_65_66  = BSP_CLOCKS_PLL_MUL(65U, 66U),  ///< PLL multiplier of 65.66
656     CGC_PLL_MUL_66_0   = BSP_CLOCKS_PLL_MUL(66U, 0U),   ///< PLL multiplier of 66.00
657     CGC_PLL_MUL_66_33  = BSP_CLOCKS_PLL_MUL(66U, 33U),  ///< PLL multiplier of 66.33
658     CGC_PLL_MUL_66_5   = BSP_CLOCKS_PLL_MUL(66U, 50U),  ///< PLL multiplier of 66.50
659     CGC_PLL_MUL_66_66  = BSP_CLOCKS_PLL_MUL(66U, 66U),  ///< PLL multiplier of 66.66
660     CGC_PLL_MUL_67_0   = BSP_CLOCKS_PLL_MUL(67U, 0U),   ///< PLL multiplier of 67.00
661     CGC_PLL_MUL_67_33  = BSP_CLOCKS_PLL_MUL(67U, 33U),  ///< PLL multiplier of 67.33
662     CGC_PLL_MUL_67_5   = BSP_CLOCKS_PLL_MUL(67U, 50U),  ///< PLL multiplier of 67.50
663     CGC_PLL_MUL_67_66  = BSP_CLOCKS_PLL_MUL(67U, 66U),  ///< PLL multiplier of 67.66
664     CGC_PLL_MUL_68_0   = BSP_CLOCKS_PLL_MUL(68U, 0U),   ///< PLL multiplier of 68.00
665     CGC_PLL_MUL_68_33  = BSP_CLOCKS_PLL_MUL(68U, 33U),  ///< PLL multiplier of 68.33
666     CGC_PLL_MUL_68_5   = BSP_CLOCKS_PLL_MUL(68U, 50U),  ///< PLL multiplier of 68.50
667     CGC_PLL_MUL_68_66  = BSP_CLOCKS_PLL_MUL(68U, 66U),  ///< PLL multiplier of 68.66
668     CGC_PLL_MUL_69_0   = BSP_CLOCKS_PLL_MUL(69U, 0U),   ///< PLL multiplier of 69.00
669     CGC_PLL_MUL_69_33  = BSP_CLOCKS_PLL_MUL(69U, 33U),  ///< PLL multiplier of 69.33
670     CGC_PLL_MUL_69_5   = BSP_CLOCKS_PLL_MUL(69U, 50U),  ///< PLL multiplier of 69.50
671     CGC_PLL_MUL_69_66  = BSP_CLOCKS_PLL_MUL(69U, 66U),  ///< PLL multiplier of 69.66
672     CGC_PLL_MUL_70_0   = BSP_CLOCKS_PLL_MUL(70U, 0U),   ///< PLL multiplier of 70.00
673     CGC_PLL_MUL_70_33  = BSP_CLOCKS_PLL_MUL(70U, 33U),  ///< PLL multiplier of 70.33
674     CGC_PLL_MUL_70_5   = BSP_CLOCKS_PLL_MUL(70U, 50U),  ///< PLL multiplier of 70.50
675     CGC_PLL_MUL_70_66  = BSP_CLOCKS_PLL_MUL(70U, 66U),  ///< PLL multiplier of 70.66
676     CGC_PLL_MUL_71_0   = BSP_CLOCKS_PLL_MUL(71U, 0U),   ///< PLL multiplier of 71.00
677     CGC_PLL_MUL_71_33  = BSP_CLOCKS_PLL_MUL(71U, 33U),  ///< PLL multiplier of 71.33
678     CGC_PLL_MUL_71_5   = BSP_CLOCKS_PLL_MUL(71U, 50U),  ///< PLL multiplier of 71.50
679     CGC_PLL_MUL_71_66  = BSP_CLOCKS_PLL_MUL(71U, 66U),  ///< PLL multiplier of 71.66
680     CGC_PLL_MUL_72_0   = BSP_CLOCKS_PLL_MUL(72U, 0U),   ///< PLL multiplier of 72.00
681     CGC_PLL_MUL_72_33  = BSP_CLOCKS_PLL_MUL(72U, 33U),  ///< PLL multiplier of 72.33
682     CGC_PLL_MUL_72_5   = BSP_CLOCKS_PLL_MUL(72U, 50U),  ///< PLL multiplier of 72.50
683     CGC_PLL_MUL_72_66  = BSP_CLOCKS_PLL_MUL(72U, 66U),  ///< PLL multiplier of 72.66
684     CGC_PLL_MUL_73_0   = BSP_CLOCKS_PLL_MUL(73U, 0U),   ///< PLL multiplier of 73.00
685     CGC_PLL_MUL_73_33  = BSP_CLOCKS_PLL_MUL(73U, 33U),  ///< PLL multiplier of 73.33
686     CGC_PLL_MUL_73_5   = BSP_CLOCKS_PLL_MUL(73U, 50U),  ///< PLL multiplier of 73.50
687     CGC_PLL_MUL_73_66  = BSP_CLOCKS_PLL_MUL(73U, 66U),  ///< PLL multiplier of 73.66
688     CGC_PLL_MUL_74_0   = BSP_CLOCKS_PLL_MUL(74U, 0U),   ///< PLL multiplier of 74.00
689     CGC_PLL_MUL_74_33  = BSP_CLOCKS_PLL_MUL(74U, 33U),  ///< PLL multiplier of 74.33
690     CGC_PLL_MUL_74_5   = BSP_CLOCKS_PLL_MUL(74U, 50U),  ///< PLL multiplier of 74.50
691     CGC_PLL_MUL_74_66  = BSP_CLOCKS_PLL_MUL(74U, 66U),  ///< PLL multiplier of 74.66
692     CGC_PLL_MUL_75_0   = BSP_CLOCKS_PLL_MUL(75U, 0U),   ///< PLL multiplier of 75.00
693     CGC_PLL_MUL_75_33  = BSP_CLOCKS_PLL_MUL(75U, 33U),  ///< PLL multiplier of 75.33
694     CGC_PLL_MUL_75_5   = BSP_CLOCKS_PLL_MUL(75U, 50U),  ///< PLL multiplier of 75.50
695     CGC_PLL_MUL_75_66  = BSP_CLOCKS_PLL_MUL(75U, 66U),  ///< PLL multiplier of 75.66
696     CGC_PLL_MUL_76_0   = BSP_CLOCKS_PLL_MUL(76U, 0U),   ///< PLL multiplier of 76.00
697     CGC_PLL_MUL_76_33  = BSP_CLOCKS_PLL_MUL(76U, 33U),  ///< PLL multiplier of 76.33
698     CGC_PLL_MUL_76_5   = BSP_CLOCKS_PLL_MUL(76U, 50U),  ///< PLL multiplier of 76.50
699     CGC_PLL_MUL_76_66  = BSP_CLOCKS_PLL_MUL(76U, 66U),  ///< PLL multiplier of 76.66
700     CGC_PLL_MUL_77_0   = BSP_CLOCKS_PLL_MUL(77U, 0U),   ///< PLL multiplier of 77.00
701     CGC_PLL_MUL_77_33  = BSP_CLOCKS_PLL_MUL(77U, 33U),  ///< PLL multiplier of 77.33
702     CGC_PLL_MUL_77_5   = BSP_CLOCKS_PLL_MUL(77U, 50U),  ///< PLL multiplier of 77.50
703     CGC_PLL_MUL_77_66  = BSP_CLOCKS_PLL_MUL(77U, 66U),  ///< PLL multiplier of 77.66
704     CGC_PLL_MUL_78_0   = BSP_CLOCKS_PLL_MUL(78U, 0U),   ///< PLL multiplier of 78.00
705     CGC_PLL_MUL_78_33  = BSP_CLOCKS_PLL_MUL(78U, 33U),  ///< PLL multiplier of 78.33
706     CGC_PLL_MUL_78_5   = BSP_CLOCKS_PLL_MUL(78U, 50U),  ///< PLL multiplier of 78.50
707     CGC_PLL_MUL_78_66  = BSP_CLOCKS_PLL_MUL(78U, 66U),  ///< PLL multiplier of 78.66
708     CGC_PLL_MUL_79_0   = BSP_CLOCKS_PLL_MUL(79U, 0U),   ///< PLL multiplier of 79.00
709     CGC_PLL_MUL_79_33  = BSP_CLOCKS_PLL_MUL(79U, 33U),  ///< PLL multiplier of 79.33
710     CGC_PLL_MUL_79_5   = BSP_CLOCKS_PLL_MUL(79U, 50U),  ///< PLL multiplier of 79.50
711     CGC_PLL_MUL_79_66  = BSP_CLOCKS_PLL_MUL(79U, 66U),  ///< PLL multiplier of 79.66
712     CGC_PLL_MUL_80_0   = BSP_CLOCKS_PLL_MUL(80U, 0U),   ///< PLL multiplier of 80.00
713     CGC_PLL_MUL_80_33  = BSP_CLOCKS_PLL_MUL(80U, 33U),  ///< PLL multiplier of 80.33
714     CGC_PLL_MUL_80_5   = BSP_CLOCKS_PLL_MUL(80U, 50U),  ///< PLL multiplier of 80.50
715     CGC_PLL_MUL_80_66  = BSP_CLOCKS_PLL_MUL(80U, 66U),  ///< PLL multiplier of 80.66
716     CGC_PLL_MUL_81_0   = BSP_CLOCKS_PLL_MUL(81U, 0U),   ///< PLL multiplier of 81.00
717     CGC_PLL_MUL_81_33  = BSP_CLOCKS_PLL_MUL(81U, 33U),  ///< PLL multiplier of 81.33
718     CGC_PLL_MUL_81_5   = BSP_CLOCKS_PLL_MUL(81U, 50U),  ///< PLL multiplier of 81.50
719     CGC_PLL_MUL_81_66  = BSP_CLOCKS_PLL_MUL(81U, 66U),  ///< PLL multiplier of 81.66
720     CGC_PLL_MUL_82_0   = BSP_CLOCKS_PLL_MUL(82U, 0U),   ///< PLL multiplier of 82.00
721     CGC_PLL_MUL_82_33  = BSP_CLOCKS_PLL_MUL(82U, 33U),  ///< PLL multiplier of 82.33
722     CGC_PLL_MUL_82_5   = BSP_CLOCKS_PLL_MUL(82U, 50U),  ///< PLL multiplier of 82.50
723     CGC_PLL_MUL_82_66  = BSP_CLOCKS_PLL_MUL(82U, 66U),  ///< PLL multiplier of 82.66
724     CGC_PLL_MUL_83_0   = BSP_CLOCKS_PLL_MUL(83U, 0U),   ///< PLL multiplier of 83.00
725     CGC_PLL_MUL_83_33  = BSP_CLOCKS_PLL_MUL(83U, 33U),  ///< PLL multiplier of 83.33
726     CGC_PLL_MUL_83_5   = BSP_CLOCKS_PLL_MUL(83U, 50U),  ///< PLL multiplier of 83.50
727     CGC_PLL_MUL_83_66  = BSP_CLOCKS_PLL_MUL(83U, 66U),  ///< PLL multiplier of 83.66
728     CGC_PLL_MUL_84_0   = BSP_CLOCKS_PLL_MUL(84U, 0U),   ///< PLL multiplier of 84.00
729     CGC_PLL_MUL_84_33  = BSP_CLOCKS_PLL_MUL(84U, 33U),  ///< PLL multiplier of 84.33
730     CGC_PLL_MUL_84_5   = BSP_CLOCKS_PLL_MUL(84U, 50U),  ///< PLL multiplier of 84.50
731     CGC_PLL_MUL_84_66  = BSP_CLOCKS_PLL_MUL(84U, 66U),  ///< PLL multiplier of 84.66
732     CGC_PLL_MUL_85_0   = BSP_CLOCKS_PLL_MUL(85U, 0U),   ///< PLL multiplier of 85.00
733     CGC_PLL_MUL_85_33  = BSP_CLOCKS_PLL_MUL(85U, 33U),  ///< PLL multiplier of 85.33
734     CGC_PLL_MUL_85_5   = BSP_CLOCKS_PLL_MUL(85U, 50U),  ///< PLL multiplier of 85.50
735     CGC_PLL_MUL_85_66  = BSP_CLOCKS_PLL_MUL(85U, 66U),  ///< PLL multiplier of 85.66
736     CGC_PLL_MUL_86_0   = BSP_CLOCKS_PLL_MUL(86U, 0U),   ///< PLL multiplier of 86.00
737     CGC_PLL_MUL_86_33  = BSP_CLOCKS_PLL_MUL(86U, 33U),  ///< PLL multiplier of 86.33
738     CGC_PLL_MUL_86_5   = BSP_CLOCKS_PLL_MUL(86U, 50U),  ///< PLL multiplier of 86.50
739     CGC_PLL_MUL_86_66  = BSP_CLOCKS_PLL_MUL(86U, 66U),  ///< PLL multiplier of 86.66
740     CGC_PLL_MUL_87_0   = BSP_CLOCKS_PLL_MUL(87U, 0U),   ///< PLL multiplier of 87.00
741     CGC_PLL_MUL_87_33  = BSP_CLOCKS_PLL_MUL(87U, 33U),  ///< PLL multiplier of 87.33
742     CGC_PLL_MUL_87_5   = BSP_CLOCKS_PLL_MUL(87U, 50U),  ///< PLL multiplier of 87.50
743     CGC_PLL_MUL_87_66  = BSP_CLOCKS_PLL_MUL(87U, 66U),  ///< PLL multiplier of 87.66
744     CGC_PLL_MUL_88_0   = BSP_CLOCKS_PLL_MUL(88U, 0U),   ///< PLL multiplier of 88.00
745     CGC_PLL_MUL_88_33  = BSP_CLOCKS_PLL_MUL(88U, 33U),  ///< PLL multiplier of 88.33
746     CGC_PLL_MUL_88_5   = BSP_CLOCKS_PLL_MUL(88U, 50U),  ///< PLL multiplier of 88.50
747     CGC_PLL_MUL_88_66  = BSP_CLOCKS_PLL_MUL(88U, 66U),  ///< PLL multiplier of 88.66
748     CGC_PLL_MUL_89_0   = BSP_CLOCKS_PLL_MUL(89U, 0U),   ///< PLL multiplier of 89.00
749     CGC_PLL_MUL_89_33  = BSP_CLOCKS_PLL_MUL(89U, 33U),  ///< PLL multiplier of 89.33
750     CGC_PLL_MUL_89_5   = BSP_CLOCKS_PLL_MUL(89U, 50U),  ///< PLL multiplier of 89.50
751     CGC_PLL_MUL_89_66  = BSP_CLOCKS_PLL_MUL(89U, 66U),  ///< PLL multiplier of 89.66
752     CGC_PLL_MUL_90_0   = BSP_CLOCKS_PLL_MUL(90U, 0U),   ///< PLL multiplier of 90.00
753     CGC_PLL_MUL_90_33  = BSP_CLOCKS_PLL_MUL(90U, 33U),  ///< PLL multiplier of 90.33
754     CGC_PLL_MUL_90_5   = BSP_CLOCKS_PLL_MUL(90U, 50U),  ///< PLL multiplier of 90.50
755     CGC_PLL_MUL_90_66  = BSP_CLOCKS_PLL_MUL(90U, 66U),  ///< PLL multiplier of 90.66
756     CGC_PLL_MUL_91_0   = BSP_CLOCKS_PLL_MUL(91U, 0U),   ///< PLL multiplier of 91.00
757     CGC_PLL_MUL_91_33  = BSP_CLOCKS_PLL_MUL(91U, 33U),  ///< PLL multiplier of 91.33
758     CGC_PLL_MUL_91_5   = BSP_CLOCKS_PLL_MUL(91U, 50U),  ///< PLL multiplier of 91.50
759     CGC_PLL_MUL_91_66  = BSP_CLOCKS_PLL_MUL(91U, 66U),  ///< PLL multiplier of 91.66
760     CGC_PLL_MUL_92_0   = BSP_CLOCKS_PLL_MUL(92U, 0U),   ///< PLL multiplier of 92.00
761     CGC_PLL_MUL_92_33  = BSP_CLOCKS_PLL_MUL(92U, 33U),  ///< PLL multiplier of 92.33
762     CGC_PLL_MUL_92_5   = BSP_CLOCKS_PLL_MUL(92U, 50U),  ///< PLL multiplier of 92.50
763     CGC_PLL_MUL_92_66  = BSP_CLOCKS_PLL_MUL(92U, 66U),  ///< PLL multiplier of 92.66
764     CGC_PLL_MUL_93_0   = BSP_CLOCKS_PLL_MUL(93U, 0U),   ///< PLL multiplier of 93.00
765     CGC_PLL_MUL_93_33  = BSP_CLOCKS_PLL_MUL(93U, 33U),  ///< PLL multiplier of 93.33
766     CGC_PLL_MUL_93_5   = BSP_CLOCKS_PLL_MUL(93U, 50U),  ///< PLL multiplier of 93.50
767     CGC_PLL_MUL_93_66  = BSP_CLOCKS_PLL_MUL(93U, 66U),  ///< PLL multiplier of 93.66
768     CGC_PLL_MUL_94_0   = BSP_CLOCKS_PLL_MUL(94U, 0U),   ///< PLL multiplier of 94.00
769     CGC_PLL_MUL_94_33  = BSP_CLOCKS_PLL_MUL(94U, 33U),  ///< PLL multiplier of 94.33
770     CGC_PLL_MUL_94_5   = BSP_CLOCKS_PLL_MUL(94U, 50U),  ///< PLL multiplier of 94.50
771     CGC_PLL_MUL_94_66  = BSP_CLOCKS_PLL_MUL(94U, 66U),  ///< PLL multiplier of 94.66
772     CGC_PLL_MUL_95_0   = BSP_CLOCKS_PLL_MUL(95U, 0U),   ///< PLL multiplier of 95.00
773     CGC_PLL_MUL_95_33  = BSP_CLOCKS_PLL_MUL(95U, 33U),  ///< PLL multiplier of 95.33
774     CGC_PLL_MUL_95_5   = BSP_CLOCKS_PLL_MUL(95U, 50U),  ///< PLL multiplier of 95.50
775     CGC_PLL_MUL_95_66  = BSP_CLOCKS_PLL_MUL(95U, 66U),  ///< PLL multiplier of 95.66
776     CGC_PLL_MUL_96_0   = BSP_CLOCKS_PLL_MUL(96U, 0U),   ///< PLL multiplier of 96.00
777     CGC_PLL_MUL_96_33  = BSP_CLOCKS_PLL_MUL(96U, 33U),  ///< PLL multiplier of 96.33
778     CGC_PLL_MUL_96_5   = BSP_CLOCKS_PLL_MUL(96U, 50U),  ///< PLL multiplier of 96.50
779     CGC_PLL_MUL_96_66  = BSP_CLOCKS_PLL_MUL(96U, 66U),  ///< PLL multiplier of 96.66
780     CGC_PLL_MUL_97_0   = BSP_CLOCKS_PLL_MUL(97U, 0U),   ///< PLL multiplier of 97.00
781     CGC_PLL_MUL_97_33  = BSP_CLOCKS_PLL_MUL(97U, 33U),  ///< PLL multiplier of 97.33
782     CGC_PLL_MUL_97_5   = BSP_CLOCKS_PLL_MUL(97U, 50U),  ///< PLL multiplier of 97.50
783     CGC_PLL_MUL_97_66  = BSP_CLOCKS_PLL_MUL(97U, 66U),  ///< PLL multiplier of 97.66
784     CGC_PLL_MUL_98_0   = BSP_CLOCKS_PLL_MUL(98U, 0U),   ///< PLL multiplier of 98.00
785     CGC_PLL_MUL_98_33  = BSP_CLOCKS_PLL_MUL(98U, 33U),  ///< PLL multiplier of 98.33
786     CGC_PLL_MUL_98_5   = BSP_CLOCKS_PLL_MUL(98U, 50U),  ///< PLL multiplier of 98.50
787     CGC_PLL_MUL_98_66  = BSP_CLOCKS_PLL_MUL(98U, 66U),  ///< PLL multiplier of 98.66
788     CGC_PLL_MUL_99_0   = BSP_CLOCKS_PLL_MUL(99U, 0U),   ///< PLL multiplier of 99.00
789     CGC_PLL_MUL_99_33  = BSP_CLOCKS_PLL_MUL(99U, 33U),  ///< PLL multiplier of 99.33
790     CGC_PLL_MUL_99_5   = BSP_CLOCKS_PLL_MUL(99U, 50U),  ///< PLL multiplier of 99.50
791     CGC_PLL_MUL_99_66  = BSP_CLOCKS_PLL_MUL(99U, 66U),  ///< PLL multiplier of 99.66
792     CGC_PLL_MUL_100_0  = BSP_CLOCKS_PLL_MUL(100U, 0U),  ///< PLL multiplier of 100.00
793     CGC_PLL_MUL_100_33 = BSP_CLOCKS_PLL_MUL(100U, 33U), ///< PLL multiplier of 100.33
794     CGC_PLL_MUL_100_5  = BSP_CLOCKS_PLL_MUL(100U, 50U), ///< PLL multiplier of 100.50
795     CGC_PLL_MUL_100_66 = BSP_CLOCKS_PLL_MUL(100U, 66U), ///< PLL multiplier of 100.66
796     CGC_PLL_MUL_101_0  = BSP_CLOCKS_PLL_MUL(101U, 0U),  ///< PLL multiplier of 101.00
797     CGC_PLL_MUL_101_33 = BSP_CLOCKS_PLL_MUL(101U, 33U), ///< PLL multiplier of 101.33
798     CGC_PLL_MUL_101_5  = BSP_CLOCKS_PLL_MUL(101U, 50U), ///< PLL multiplier of 101.50
799     CGC_PLL_MUL_101_66 = BSP_CLOCKS_PLL_MUL(101U, 66U), ///< PLL multiplier of 101.66
800     CGC_PLL_MUL_102_0  = BSP_CLOCKS_PLL_MUL(102U, 0U),  ///< PLL multiplier of 102.00
801     CGC_PLL_MUL_102_33 = BSP_CLOCKS_PLL_MUL(102U, 33U), ///< PLL multiplier of 102.33
802     CGC_PLL_MUL_102_5  = BSP_CLOCKS_PLL_MUL(102U, 50U), ///< PLL multiplier of 102.50
803     CGC_PLL_MUL_102_66 = BSP_CLOCKS_PLL_MUL(102U, 66U), ///< PLL multiplier of 102.66
804     CGC_PLL_MUL_103_0  = BSP_CLOCKS_PLL_MUL(103U, 0U),  ///< PLL multiplier of 103.00
805     CGC_PLL_MUL_103_33 = BSP_CLOCKS_PLL_MUL(103U, 33U), ///< PLL multiplier of 103.33
806     CGC_PLL_MUL_103_5  = BSP_CLOCKS_PLL_MUL(103U, 50U), ///< PLL multiplier of 103.50
807     CGC_PLL_MUL_103_66 = BSP_CLOCKS_PLL_MUL(103U, 66U), ///< PLL multiplier of 103.66
808     CGC_PLL_MUL_104_0  = BSP_CLOCKS_PLL_MUL(104U, 0U),  ///< PLL multiplier of 104.00
809     CGC_PLL_MUL_104_33 = BSP_CLOCKS_PLL_MUL(104U, 33U), ///< PLL multiplier of 104.33
810     CGC_PLL_MUL_104_5  = BSP_CLOCKS_PLL_MUL(104U, 50U), ///< PLL multiplier of 104.50
811     CGC_PLL_MUL_104_66 = BSP_CLOCKS_PLL_MUL(104U, 66U), ///< PLL multiplier of 104.66
812     CGC_PLL_MUL_105_0  = BSP_CLOCKS_PLL_MUL(105U, 0U),  ///< PLL multiplier of 105.00
813     CGC_PLL_MUL_105_33 = BSP_CLOCKS_PLL_MUL(105U, 33U), ///< PLL multiplier of 105.33
814     CGC_PLL_MUL_105_5  = BSP_CLOCKS_PLL_MUL(105U, 50U), ///< PLL multiplier of 105.50
815     CGC_PLL_MUL_105_66 = BSP_CLOCKS_PLL_MUL(105U, 66U), ///< PLL multiplier of 105.66
816     CGC_PLL_MUL_106_0  = BSP_CLOCKS_PLL_MUL(106U, 0U),  ///< PLL multiplier of 106.00
817     CGC_PLL_MUL_106_33 = BSP_CLOCKS_PLL_MUL(106U, 33U), ///< PLL multiplier of 106.33
818     CGC_PLL_MUL_106_5  = BSP_CLOCKS_PLL_MUL(106U, 50U), ///< PLL multiplier of 106.50
819     CGC_PLL_MUL_106_66 = BSP_CLOCKS_PLL_MUL(106U, 66U), ///< PLL multiplier of 106.66
820     CGC_PLL_MUL_107_0  = BSP_CLOCKS_PLL_MUL(107U, 0U),  ///< PLL multiplier of 107.00
821     CGC_PLL_MUL_107_33 = BSP_CLOCKS_PLL_MUL(107U, 33U), ///< PLL multiplier of 107.33
822     CGC_PLL_MUL_107_5  = BSP_CLOCKS_PLL_MUL(107U, 50U), ///< PLL multiplier of 107.50
823     CGC_PLL_MUL_107_66 = BSP_CLOCKS_PLL_MUL(107U, 66U), ///< PLL multiplier of 107.66
824     CGC_PLL_MUL_108_0  = BSP_CLOCKS_PLL_MUL(108U, 0U),  ///< PLL multiplier of 108.00
825     CGC_PLL_MUL_108_33 = BSP_CLOCKS_PLL_MUL(108U, 33U), ///< PLL multiplier of 108.33
826     CGC_PLL_MUL_108_5  = BSP_CLOCKS_PLL_MUL(108U, 50U), ///< PLL multiplier of 108.50
827     CGC_PLL_MUL_108_66 = BSP_CLOCKS_PLL_MUL(108U, 66U), ///< PLL multiplier of 108.66
828     CGC_PLL_MUL_109_0  = BSP_CLOCKS_PLL_MUL(109U, 0U),  ///< PLL multiplier of 109.00
829     CGC_PLL_MUL_109_33 = BSP_CLOCKS_PLL_MUL(109U, 33U), ///< PLL multiplier of 109.33
830     CGC_PLL_MUL_109_5  = BSP_CLOCKS_PLL_MUL(109U, 50U), ///< PLL multiplier of 109.50
831     CGC_PLL_MUL_109_66 = BSP_CLOCKS_PLL_MUL(109U, 66U), ///< PLL multiplier of 109.66
832     CGC_PLL_MUL_110_0  = BSP_CLOCKS_PLL_MUL(110U, 0U),  ///< PLL multiplier of 110.00
833     CGC_PLL_MUL_110_33 = BSP_CLOCKS_PLL_MUL(110U, 33U), ///< PLL multiplier of 110.33
834     CGC_PLL_MUL_110_5  = BSP_CLOCKS_PLL_MUL(110U, 50U), ///< PLL multiplier of 110.50
835     CGC_PLL_MUL_110_66 = BSP_CLOCKS_PLL_MUL(110U, 66U), ///< PLL multiplier of 110.66
836     CGC_PLL_MUL_111_0  = BSP_CLOCKS_PLL_MUL(111U, 0U),  ///< PLL multiplier of 111.00
837     CGC_PLL_MUL_111_33 = BSP_CLOCKS_PLL_MUL(111U, 33U), ///< PLL multiplier of 111.33
838     CGC_PLL_MUL_111_5  = BSP_CLOCKS_PLL_MUL(111U, 50U), ///< PLL multiplier of 111.50
839     CGC_PLL_MUL_111_66 = BSP_CLOCKS_PLL_MUL(111U, 66U), ///< PLL multiplier of 111.66
840     CGC_PLL_MUL_112_0  = BSP_CLOCKS_PLL_MUL(112U, 0U),  ///< PLL multiplier of 112.00
841     CGC_PLL_MUL_112_33 = BSP_CLOCKS_PLL_MUL(112U, 33U), ///< PLL multiplier of 112.33
842     CGC_PLL_MUL_112_5  = BSP_CLOCKS_PLL_MUL(112U, 50U), ///< PLL multiplier of 112.50
843     CGC_PLL_MUL_112_66 = BSP_CLOCKS_PLL_MUL(112U, 66U), ///< PLL multiplier of 112.66
844     CGC_PLL_MUL_113_0  = BSP_CLOCKS_PLL_MUL(113U, 0U),  ///< PLL multiplier of 113.00
845     CGC_PLL_MUL_113_33 = BSP_CLOCKS_PLL_MUL(113U, 33U), ///< PLL multiplier of 113.33
846     CGC_PLL_MUL_113_5  = BSP_CLOCKS_PLL_MUL(113U, 50U), ///< PLL multiplier of 113.50
847     CGC_PLL_MUL_113_66 = BSP_CLOCKS_PLL_MUL(113U, 66U), ///< PLL multiplier of 113.66
848     CGC_PLL_MUL_114_0  = BSP_CLOCKS_PLL_MUL(114U, 0U),  ///< PLL multiplier of 114.00
849     CGC_PLL_MUL_114_33 = BSP_CLOCKS_PLL_MUL(114U, 33U), ///< PLL multiplier of 114.33
850     CGC_PLL_MUL_114_5  = BSP_CLOCKS_PLL_MUL(114U, 50U), ///< PLL multiplier of 114.50
851     CGC_PLL_MUL_114_66 = BSP_CLOCKS_PLL_MUL(114U, 66U), ///< PLL multiplier of 114.66
852     CGC_PLL_MUL_115_0  = BSP_CLOCKS_PLL_MUL(115U, 0U),  ///< PLL multiplier of 115.00
853     CGC_PLL_MUL_115_33 = BSP_CLOCKS_PLL_MUL(115U, 33U), ///< PLL multiplier of 115.33
854     CGC_PLL_MUL_115_5  = BSP_CLOCKS_PLL_MUL(115U, 50U), ///< PLL multiplier of 115.50
855     CGC_PLL_MUL_115_66 = BSP_CLOCKS_PLL_MUL(115U, 66U), ///< PLL multiplier of 115.66
856     CGC_PLL_MUL_116_0  = BSP_CLOCKS_PLL_MUL(116U, 0U),  ///< PLL multiplier of 116.00
857     CGC_PLL_MUL_116_33 = BSP_CLOCKS_PLL_MUL(116U, 33U), ///< PLL multiplier of 116.33
858     CGC_PLL_MUL_116_5  = BSP_CLOCKS_PLL_MUL(116U, 50U), ///< PLL multiplier of 116.50
859     CGC_PLL_MUL_116_66 = BSP_CLOCKS_PLL_MUL(116U, 66U), ///< PLL multiplier of 116.66
860     CGC_PLL_MUL_117_0  = BSP_CLOCKS_PLL_MUL(117U, 0U),  ///< PLL multiplier of 117.00
861     CGC_PLL_MUL_117_33 = BSP_CLOCKS_PLL_MUL(117U, 33U), ///< PLL multiplier of 117.33
862     CGC_PLL_MUL_117_5  = BSP_CLOCKS_PLL_MUL(117U, 50U), ///< PLL multiplier of 117.50
863     CGC_PLL_MUL_117_66 = BSP_CLOCKS_PLL_MUL(117U, 66U), ///< PLL multiplier of 117.66
864     CGC_PLL_MUL_118_0  = BSP_CLOCKS_PLL_MUL(118U, 0U),  ///< PLL multiplier of 118.00
865     CGC_PLL_MUL_118_33 = BSP_CLOCKS_PLL_MUL(118U, 33U), ///< PLL multiplier of 118.33
866     CGC_PLL_MUL_118_5  = BSP_CLOCKS_PLL_MUL(118U, 50U), ///< PLL multiplier of 118.50
867     CGC_PLL_MUL_118_66 = BSP_CLOCKS_PLL_MUL(118U, 66U), ///< PLL multiplier of 118.66
868     CGC_PLL_MUL_119_0  = BSP_CLOCKS_PLL_MUL(119U, 0U),  ///< PLL multiplier of 119.00
869     CGC_PLL_MUL_119_33 = BSP_CLOCKS_PLL_MUL(119U, 33U), ///< PLL multiplier of 119.33
870     CGC_PLL_MUL_119_5  = BSP_CLOCKS_PLL_MUL(119U, 50U), ///< PLL multiplier of 119.50
871     CGC_PLL_MUL_119_66 = BSP_CLOCKS_PLL_MUL(119U, 66U), ///< PLL multiplier of 119.66
872     CGC_PLL_MUL_120_0  = BSP_CLOCKS_PLL_MUL(120U, 0U),  ///< PLL multiplier of 120.00
873     CGC_PLL_MUL_120_33 = BSP_CLOCKS_PLL_MUL(120U, 33U), ///< PLL multiplier of 120.33
874     CGC_PLL_MUL_120_5  = BSP_CLOCKS_PLL_MUL(120U, 50U), ///< PLL multiplier of 120.50
875     CGC_PLL_MUL_120_66 = BSP_CLOCKS_PLL_MUL(120U, 66U), ///< PLL multiplier of 120.66
876     CGC_PLL_MUL_121_0  = BSP_CLOCKS_PLL_MUL(121U, 0U),  ///< PLL multiplier of 121.00
877     CGC_PLL_MUL_121_33 = BSP_CLOCKS_PLL_MUL(121U, 33U), ///< PLL multiplier of 121.33
878     CGC_PLL_MUL_121_5  = BSP_CLOCKS_PLL_MUL(121U, 50U), ///< PLL multiplier of 121.50
879     CGC_PLL_MUL_121_66 = BSP_CLOCKS_PLL_MUL(121U, 66U), ///< PLL multiplier of 121.66
880     CGC_PLL_MUL_122_0  = BSP_CLOCKS_PLL_MUL(122U, 0U),  ///< PLL multiplier of 122.00
881     CGC_PLL_MUL_122_33 = BSP_CLOCKS_PLL_MUL(122U, 33U), ///< PLL multiplier of 122.33
882     CGC_PLL_MUL_122_5  = BSP_CLOCKS_PLL_MUL(122U, 50U), ///< PLL multiplier of 122.50
883     CGC_PLL_MUL_122_66 = BSP_CLOCKS_PLL_MUL(122U, 66U), ///< PLL multiplier of 122.66
884     CGC_PLL_MUL_123_0  = BSP_CLOCKS_PLL_MUL(123U, 0U),  ///< PLL multiplier of 123.00
885     CGC_PLL_MUL_123_33 = BSP_CLOCKS_PLL_MUL(123U, 33U), ///< PLL multiplier of 123.33
886     CGC_PLL_MUL_123_5  = BSP_CLOCKS_PLL_MUL(123U, 50U), ///< PLL multiplier of 123.50
887     CGC_PLL_MUL_123_66 = BSP_CLOCKS_PLL_MUL(123U, 66U), ///< PLL multiplier of 123.66
888     CGC_PLL_MUL_124_0  = BSP_CLOCKS_PLL_MUL(124U, 0U),  ///< PLL multiplier of 124.00
889     CGC_PLL_MUL_124_33 = BSP_CLOCKS_PLL_MUL(124U, 33U), ///< PLL multiplier of 124.33
890     CGC_PLL_MUL_124_5  = BSP_CLOCKS_PLL_MUL(124U, 50U), ///< PLL multiplier of 124.50
891     CGC_PLL_MUL_124_66 = BSP_CLOCKS_PLL_MUL(124U, 66U), ///< PLL multiplier of 124.66
892     CGC_PLL_MUL_125_0  = BSP_CLOCKS_PLL_MUL(125U, 0U),  ///< PLL multiplier of 125.00
893     CGC_PLL_MUL_125_33 = BSP_CLOCKS_PLL_MUL(125U, 33U), ///< PLL multiplier of 125.33
894     CGC_PLL_MUL_125_5  = BSP_CLOCKS_PLL_MUL(125U, 50U), ///< PLL multiplier of 125.50
895     CGC_PLL_MUL_125_66 = BSP_CLOCKS_PLL_MUL(125U, 66U), ///< PLL multiplier of 125.66
896     CGC_PLL_MUL_126_0  = BSP_CLOCKS_PLL_MUL(126U, 0U),  ///< PLL multiplier of 126.00
897     CGC_PLL_MUL_126_33 = BSP_CLOCKS_PLL_MUL(126U, 33U), ///< PLL multiplier of 126.33
898     CGC_PLL_MUL_126_5  = BSP_CLOCKS_PLL_MUL(126U, 50U), ///< PLL multiplier of 126.50
899     CGC_PLL_MUL_126_66 = BSP_CLOCKS_PLL_MUL(126U, 66U), ///< PLL multiplier of 126.66
900     CGC_PLL_MUL_127_0  = BSP_CLOCKS_PLL_MUL(127U, 0U),  ///< PLL multiplier of 127.00
901     CGC_PLL_MUL_127_33 = BSP_CLOCKS_PLL_MUL(127U, 33U), ///< PLL multiplier of 127.33
902     CGC_PLL_MUL_127_5  = BSP_CLOCKS_PLL_MUL(127U, 50U), ///< PLL multiplier of 127.50
903     CGC_PLL_MUL_127_66 = BSP_CLOCKS_PLL_MUL(127U, 66U), ///< PLL multiplier of 127.66
904     CGC_PLL_MUL_128_0  = BSP_CLOCKS_PLL_MUL(128U, 0U),  ///< PLL multiplier of 128.00
905     CGC_PLL_MUL_128_33 = BSP_CLOCKS_PLL_MUL(128U, 33U), ///< PLL multiplier of 128.33
906     CGC_PLL_MUL_128_5  = BSP_CLOCKS_PLL_MUL(128U, 50U), ///< PLL multiplier of 128.50
907     CGC_PLL_MUL_128_66 = BSP_CLOCKS_PLL_MUL(128U, 66U), ///< PLL multiplier of 128.66
908     CGC_PLL_MUL_129_0  = BSP_CLOCKS_PLL_MUL(129U, 0U),  ///< PLL multiplier of 129.00
909     CGC_PLL_MUL_129_33 = BSP_CLOCKS_PLL_MUL(129U, 33U), ///< PLL multiplier of 129.33
910     CGC_PLL_MUL_129_5  = BSP_CLOCKS_PLL_MUL(129U, 50U), ///< PLL multiplier of 129.50
911     CGC_PLL_MUL_129_66 = BSP_CLOCKS_PLL_MUL(129U, 66U), ///< PLL multiplier of 129.66
912     CGC_PLL_MUL_130_0  = BSP_CLOCKS_PLL_MUL(130U, 0U),  ///< PLL multiplier of 130.00
913     CGC_PLL_MUL_130_33 = BSP_CLOCKS_PLL_MUL(130U, 33U), ///< PLL multiplier of 130.33
914     CGC_PLL_MUL_130_5  = BSP_CLOCKS_PLL_MUL(130U, 50U), ///< PLL multiplier of 130.50
915     CGC_PLL_MUL_130_66 = BSP_CLOCKS_PLL_MUL(130U, 66U), ///< PLL multiplier of 130.66
916     CGC_PLL_MUL_131_0  = BSP_CLOCKS_PLL_MUL(131U, 0U),  ///< PLL multiplier of 131.00
917     CGC_PLL_MUL_131_33 = BSP_CLOCKS_PLL_MUL(131U, 33U), ///< PLL multiplier of 131.33
918     CGC_PLL_MUL_131_5  = BSP_CLOCKS_PLL_MUL(131U, 50U), ///< PLL multiplier of 131.50
919     CGC_PLL_MUL_131_66 = BSP_CLOCKS_PLL_MUL(131U, 66U), ///< PLL multiplier of 131.66
920     CGC_PLL_MUL_132_0  = BSP_CLOCKS_PLL_MUL(132U, 0U),  ///< PLL multiplier of 132.00
921     CGC_PLL_MUL_132_33 = BSP_CLOCKS_PLL_MUL(132U, 33U), ///< PLL multiplier of 132.33
922     CGC_PLL_MUL_132_5  = BSP_CLOCKS_PLL_MUL(132U, 50U), ///< PLL multiplier of 132.50
923     CGC_PLL_MUL_132_66 = BSP_CLOCKS_PLL_MUL(132U, 66U), ///< PLL multiplier of 132.66
924     CGC_PLL_MUL_133_0  = BSP_CLOCKS_PLL_MUL(133U, 0U),  ///< PLL multiplier of 133.00
925     CGC_PLL_MUL_133_33 = BSP_CLOCKS_PLL_MUL(133U, 33U), ///< PLL multiplier of 133.33
926     CGC_PLL_MUL_133_5  = BSP_CLOCKS_PLL_MUL(133U, 50U), ///< PLL multiplier of 133.50
927     CGC_PLL_MUL_133_66 = BSP_CLOCKS_PLL_MUL(133U, 66U), ///< PLL multiplier of 133.66
928     CGC_PLL_MUL_134_0  = BSP_CLOCKS_PLL_MUL(134U, 0U),  ///< PLL multiplier of 134.00
929     CGC_PLL_MUL_134_33 = BSP_CLOCKS_PLL_MUL(134U, 33U), ///< PLL multiplier of 134.33
930     CGC_PLL_MUL_134_5  = BSP_CLOCKS_PLL_MUL(134U, 50U), ///< PLL multiplier of 134.50
931     CGC_PLL_MUL_134_66 = BSP_CLOCKS_PLL_MUL(134U, 66U), ///< PLL multiplier of 134.66
932     CGC_PLL_MUL_135_0  = BSP_CLOCKS_PLL_MUL(135U, 0U),  ///< PLL multiplier of 135.00
933     CGC_PLL_MUL_135_33 = BSP_CLOCKS_PLL_MUL(135U, 33U), ///< PLL multiplier of 135.33
934     CGC_PLL_MUL_135_5  = BSP_CLOCKS_PLL_MUL(135U, 50U), ///< PLL multiplier of 135.50
935     CGC_PLL_MUL_135_66 = BSP_CLOCKS_PLL_MUL(135U, 66U), ///< PLL multiplier of 135.66
936     CGC_PLL_MUL_136_0  = BSP_CLOCKS_PLL_MUL(136U, 0U),  ///< PLL multiplier of 136.00
937     CGC_PLL_MUL_136_33 = BSP_CLOCKS_PLL_MUL(136U, 33U), ///< PLL multiplier of 136.33
938     CGC_PLL_MUL_136_5  = BSP_CLOCKS_PLL_MUL(136U, 50U), ///< PLL multiplier of 136.50
939     CGC_PLL_MUL_136_66 = BSP_CLOCKS_PLL_MUL(136U, 66U), ///< PLL multiplier of 136.66
940     CGC_PLL_MUL_137_0  = BSP_CLOCKS_PLL_MUL(137U, 0U),  ///< PLL multiplier of 137.00
941     CGC_PLL_MUL_137_33 = BSP_CLOCKS_PLL_MUL(137U, 33U), ///< PLL multiplier of 137.33
942     CGC_PLL_MUL_137_5  = BSP_CLOCKS_PLL_MUL(137U, 50U), ///< PLL multiplier of 137.50
943     CGC_PLL_MUL_137_66 = BSP_CLOCKS_PLL_MUL(137U, 66U), ///< PLL multiplier of 137.66
944     CGC_PLL_MUL_138_0  = BSP_CLOCKS_PLL_MUL(138U, 0U),  ///< PLL multiplier of 138.00
945     CGC_PLL_MUL_138_33 = BSP_CLOCKS_PLL_MUL(138U, 33U), ///< PLL multiplier of 138.33
946     CGC_PLL_MUL_138_5  = BSP_CLOCKS_PLL_MUL(138U, 50U), ///< PLL multiplier of 138.50
947     CGC_PLL_MUL_138_66 = BSP_CLOCKS_PLL_MUL(138U, 66U), ///< PLL multiplier of 138.66
948     CGC_PLL_MUL_139_0  = BSP_CLOCKS_PLL_MUL(139U, 0U),  ///< PLL multiplier of 139.00
949     CGC_PLL_MUL_139_33 = BSP_CLOCKS_PLL_MUL(139U, 33U), ///< PLL multiplier of 139.33
950     CGC_PLL_MUL_139_5  = BSP_CLOCKS_PLL_MUL(139U, 50U), ///< PLL multiplier of 139.50
951     CGC_PLL_MUL_139_66 = BSP_CLOCKS_PLL_MUL(139U, 66U), ///< PLL multiplier of 139.66
952     CGC_PLL_MUL_140_0  = BSP_CLOCKS_PLL_MUL(140U, 0U),  ///< PLL multiplier of 140.00
953     CGC_PLL_MUL_140_33 = BSP_CLOCKS_PLL_MUL(140U, 33U), ///< PLL multiplier of 140.33
954     CGC_PLL_MUL_140_5  = BSP_CLOCKS_PLL_MUL(140U, 50U), ///< PLL multiplier of 140.50
955     CGC_PLL_MUL_140_66 = BSP_CLOCKS_PLL_MUL(140U, 66U), ///< PLL multiplier of 140.66
956     CGC_PLL_MUL_141_0  = BSP_CLOCKS_PLL_MUL(141U, 0U),  ///< PLL multiplier of 141.00
957     CGC_PLL_MUL_141_33 = BSP_CLOCKS_PLL_MUL(141U, 33U), ///< PLL multiplier of 141.33
958     CGC_PLL_MUL_141_5  = BSP_CLOCKS_PLL_MUL(141U, 50U), ///< PLL multiplier of 141.50
959     CGC_PLL_MUL_141_66 = BSP_CLOCKS_PLL_MUL(141U, 66U), ///< PLL multiplier of 141.66
960     CGC_PLL_MUL_142_0  = BSP_CLOCKS_PLL_MUL(142U, 0U),  ///< PLL multiplier of 142.00
961     CGC_PLL_MUL_142_33 = BSP_CLOCKS_PLL_MUL(142U, 33U), ///< PLL multiplier of 142.33
962     CGC_PLL_MUL_142_5  = BSP_CLOCKS_PLL_MUL(142U, 50U), ///< PLL multiplier of 142.50
963     CGC_PLL_MUL_142_66 = BSP_CLOCKS_PLL_MUL(142U, 66U), ///< PLL multiplier of 142.66
964     CGC_PLL_MUL_143_0  = BSP_CLOCKS_PLL_MUL(143U, 0U),  ///< PLL multiplier of 143.00
965     CGC_PLL_MUL_143_33 = BSP_CLOCKS_PLL_MUL(143U, 33U), ///< PLL multiplier of 143.33
966     CGC_PLL_MUL_143_5  = BSP_CLOCKS_PLL_MUL(143U, 50U), ///< PLL multiplier of 143.50
967     CGC_PLL_MUL_143_66 = BSP_CLOCKS_PLL_MUL(143U, 66U), ///< PLL multiplier of 143.66
968     CGC_PLL_MUL_144_0  = BSP_CLOCKS_PLL_MUL(144U, 0U),  ///< PLL multiplier of 144.00
969     CGC_PLL_MUL_144_33 = BSP_CLOCKS_PLL_MUL(144U, 33U), ///< PLL multiplier of 144.33
970     CGC_PLL_MUL_144_5  = BSP_CLOCKS_PLL_MUL(144U, 50U), ///< PLL multiplier of 144.50
971     CGC_PLL_MUL_144_66 = BSP_CLOCKS_PLL_MUL(144U, 66U), ///< PLL multiplier of 144.66
972     CGC_PLL_MUL_145_0  = BSP_CLOCKS_PLL_MUL(145U, 0U),  ///< PLL multiplier of 145.00
973     CGC_PLL_MUL_145_33 = BSP_CLOCKS_PLL_MUL(145U, 33U), ///< PLL multiplier of 145.33
974     CGC_PLL_MUL_145_5  = BSP_CLOCKS_PLL_MUL(145U, 50U), ///< PLL multiplier of 145.50
975     CGC_PLL_MUL_145_66 = BSP_CLOCKS_PLL_MUL(145U, 66U), ///< PLL multiplier of 145.66
976     CGC_PLL_MUL_146_0  = BSP_CLOCKS_PLL_MUL(146U, 0U),  ///< PLL multiplier of 146.00
977     CGC_PLL_MUL_146_33 = BSP_CLOCKS_PLL_MUL(146U, 33U), ///< PLL multiplier of 146.33
978     CGC_PLL_MUL_146_5  = BSP_CLOCKS_PLL_MUL(146U, 50U), ///< PLL multiplier of 146.50
979     CGC_PLL_MUL_146_66 = BSP_CLOCKS_PLL_MUL(146U, 66U), ///< PLL multiplier of 146.66
980     CGC_PLL_MUL_147_0  = BSP_CLOCKS_PLL_MUL(147U, 0U),  ///< PLL multiplier of 147.00
981     CGC_PLL_MUL_147_33 = BSP_CLOCKS_PLL_MUL(147U, 33U), ///< PLL multiplier of 147.33
982     CGC_PLL_MUL_147_5  = BSP_CLOCKS_PLL_MUL(147U, 50U), ///< PLL multiplier of 147.50
983     CGC_PLL_MUL_147_66 = BSP_CLOCKS_PLL_MUL(147U, 66U), ///< PLL multiplier of 147.66
984     CGC_PLL_MUL_148_0  = BSP_CLOCKS_PLL_MUL(148U, 0U),  ///< PLL multiplier of 148.00
985     CGC_PLL_MUL_148_33 = BSP_CLOCKS_PLL_MUL(148U, 33U), ///< PLL multiplier of 148.33
986     CGC_PLL_MUL_148_5  = BSP_CLOCKS_PLL_MUL(148U, 50U), ///< PLL multiplier of 148.50
987     CGC_PLL_MUL_148_66 = BSP_CLOCKS_PLL_MUL(148U, 66U), ///< PLL multiplier of 148.66
988     CGC_PLL_MUL_149_0  = BSP_CLOCKS_PLL_MUL(149U, 0U),  ///< PLL multiplier of 149.00
989     CGC_PLL_MUL_149_33 = BSP_CLOCKS_PLL_MUL(149U, 33U), ///< PLL multiplier of 149.33
990     CGC_PLL_MUL_149_5  = BSP_CLOCKS_PLL_MUL(149U, 50U), ///< PLL multiplier of 149.50
991     CGC_PLL_MUL_149_66 = BSP_CLOCKS_PLL_MUL(149U, 66U), ///< PLL multiplier of 149.66
992     CGC_PLL_MUL_150_0  = BSP_CLOCKS_PLL_MUL(150U, 0U),  ///< PLL multiplier of 150.00
993     CGC_PLL_MUL_150_33 = BSP_CLOCKS_PLL_MUL(150U, 33U), ///< PLL multiplier of 150.33
994     CGC_PLL_MUL_150_5  = BSP_CLOCKS_PLL_MUL(150U, 50U), ///< PLL multiplier of 150.50
995     CGC_PLL_MUL_150_66 = BSP_CLOCKS_PLL_MUL(150U, 66U), ///< PLL multiplier of 150.66
996     CGC_PLL_MUL_151_0  = BSP_CLOCKS_PLL_MUL(151U, 0U),  ///< PLL multiplier of 151.00
997     CGC_PLL_MUL_151_33 = BSP_CLOCKS_PLL_MUL(151U, 33U), ///< PLL multiplier of 151.33
998     CGC_PLL_MUL_151_5  = BSP_CLOCKS_PLL_MUL(151U, 50U), ///< PLL multiplier of 151.50
999     CGC_PLL_MUL_151_66 = BSP_CLOCKS_PLL_MUL(151U, 66U), ///< PLL multiplier of 151.66
1000     CGC_PLL_MUL_152_0  = BSP_CLOCKS_PLL_MUL(152U, 0U),  ///< PLL multiplier of 152.00
1001     CGC_PLL_MUL_152_33 = BSP_CLOCKS_PLL_MUL(152U, 33U), ///< PLL multiplier of 152.33
1002     CGC_PLL_MUL_152_5  = BSP_CLOCKS_PLL_MUL(152U, 50U), ///< PLL multiplier of 152.50
1003     CGC_PLL_MUL_152_66 = BSP_CLOCKS_PLL_MUL(152U, 66U), ///< PLL multiplier of 152.66
1004     CGC_PLL_MUL_153_0  = BSP_CLOCKS_PLL_MUL(153U, 0U),  ///< PLL multiplier of 153.00
1005     CGC_PLL_MUL_153_33 = BSP_CLOCKS_PLL_MUL(153U, 33U), ///< PLL multiplier of 153.33
1006     CGC_PLL_MUL_153_5  = BSP_CLOCKS_PLL_MUL(153U, 50U), ///< PLL multiplier of 153.50
1007     CGC_PLL_MUL_153_66 = BSP_CLOCKS_PLL_MUL(153U, 66U), ///< PLL multiplier of 153.66
1008     CGC_PLL_MUL_154_0  = BSP_CLOCKS_PLL_MUL(154U, 0U),  ///< PLL multiplier of 154.00
1009     CGC_PLL_MUL_154_33 = BSP_CLOCKS_PLL_MUL(154U, 33U), ///< PLL multiplier of 154.33
1010     CGC_PLL_MUL_154_5  = BSP_CLOCKS_PLL_MUL(154U, 50U), ///< PLL multiplier of 154.50
1011     CGC_PLL_MUL_154_66 = BSP_CLOCKS_PLL_MUL(154U, 66U), ///< PLL multiplier of 154.66
1012     CGC_PLL_MUL_155_0  = BSP_CLOCKS_PLL_MUL(155U, 0U),  ///< PLL multiplier of 155.00
1013     CGC_PLL_MUL_155_33 = BSP_CLOCKS_PLL_MUL(155U, 33U), ///< PLL multiplier of 155.33
1014     CGC_PLL_MUL_155_5  = BSP_CLOCKS_PLL_MUL(155U, 50U), ///< PLL multiplier of 155.50
1015     CGC_PLL_MUL_155_66 = BSP_CLOCKS_PLL_MUL(155U, 66U), ///< PLL multiplier of 155.66
1016     CGC_PLL_MUL_156_0  = BSP_CLOCKS_PLL_MUL(156U, 0U),  ///< PLL multiplier of 156.00
1017     CGC_PLL_MUL_156_33 = BSP_CLOCKS_PLL_MUL(156U, 33U), ///< PLL multiplier of 156.33
1018     CGC_PLL_MUL_156_5  = BSP_CLOCKS_PLL_MUL(156U, 50U), ///< PLL multiplier of 156.50
1019     CGC_PLL_MUL_156_66 = BSP_CLOCKS_PLL_MUL(156U, 66U), ///< PLL multiplier of 156.66
1020     CGC_PLL_MUL_157_0  = BSP_CLOCKS_PLL_MUL(157U, 0U),  ///< PLL multiplier of 157.00
1021     CGC_PLL_MUL_157_33 = BSP_CLOCKS_PLL_MUL(157U, 33U), ///< PLL multiplier of 157.33
1022     CGC_PLL_MUL_157_5  = BSP_CLOCKS_PLL_MUL(157U, 50U), ///< PLL multiplier of 157.50
1023     CGC_PLL_MUL_157_66 = BSP_CLOCKS_PLL_MUL(157U, 66U), ///< PLL multiplier of 157.66
1024     CGC_PLL_MUL_158_0  = BSP_CLOCKS_PLL_MUL(158U, 0U),  ///< PLL multiplier of 158.00
1025     CGC_PLL_MUL_158_33 = BSP_CLOCKS_PLL_MUL(158U, 33U), ///< PLL multiplier of 158.33
1026     CGC_PLL_MUL_158_5  = BSP_CLOCKS_PLL_MUL(158U, 50U), ///< PLL multiplier of 158.50
1027     CGC_PLL_MUL_158_66 = BSP_CLOCKS_PLL_MUL(158U, 66U), ///< PLL multiplier of 158.66
1028     CGC_PLL_MUL_159_0  = BSP_CLOCKS_PLL_MUL(159U, 0U),  ///< PLL multiplier of 159.00
1029     CGC_PLL_MUL_159_33 = BSP_CLOCKS_PLL_MUL(159U, 33U), ///< PLL multiplier of 159.33
1030     CGC_PLL_MUL_159_5  = BSP_CLOCKS_PLL_MUL(159U, 50U), ///< PLL multiplier of 159.50
1031     CGC_PLL_MUL_159_66 = BSP_CLOCKS_PLL_MUL(159U, 66U), ///< PLL multiplier of 159.66
1032     CGC_PLL_MUL_160_0  = BSP_CLOCKS_PLL_MUL(160U, 0U),  ///< PLL multiplier of 160.00
1033     CGC_PLL_MUL_160_33 = BSP_CLOCKS_PLL_MUL(160U, 33U), ///< PLL multiplier of 160.33
1034     CGC_PLL_MUL_160_5  = BSP_CLOCKS_PLL_MUL(160U, 50U), ///< PLL multiplier of 160.50
1035     CGC_PLL_MUL_160_66 = BSP_CLOCKS_PLL_MUL(160U, 66U), ///< PLL multiplier of 160.66
1036     CGC_PLL_MUL_161_0  = BSP_CLOCKS_PLL_MUL(161U, 0U),  ///< PLL multiplier of 161.00
1037     CGC_PLL_MUL_161_33 = BSP_CLOCKS_PLL_MUL(161U, 33U), ///< PLL multiplier of 161.33
1038     CGC_PLL_MUL_161_5  = BSP_CLOCKS_PLL_MUL(161U, 50U), ///< PLL multiplier of 161.50
1039     CGC_PLL_MUL_161_66 = BSP_CLOCKS_PLL_MUL(161U, 66U), ///< PLL multiplier of 161.66
1040     CGC_PLL_MUL_162_0  = BSP_CLOCKS_PLL_MUL(162U, 0U),  ///< PLL multiplier of 162.00
1041     CGC_PLL_MUL_162_33 = BSP_CLOCKS_PLL_MUL(162U, 33U), ///< PLL multiplier of 162.33
1042     CGC_PLL_MUL_162_5  = BSP_CLOCKS_PLL_MUL(162U, 50U), ///< PLL multiplier of 162.50
1043     CGC_PLL_MUL_162_66 = BSP_CLOCKS_PLL_MUL(162U, 66U), ///< PLL multiplier of 162.66
1044     CGC_PLL_MUL_163_0  = BSP_CLOCKS_PLL_MUL(163U, 0U),  ///< PLL multiplier of 163.00
1045     CGC_PLL_MUL_163_33 = BSP_CLOCKS_PLL_MUL(163U, 33U), ///< PLL multiplier of 163.33
1046     CGC_PLL_MUL_163_5  = BSP_CLOCKS_PLL_MUL(163U, 50U), ///< PLL multiplier of 163.50
1047     CGC_PLL_MUL_163_66 = BSP_CLOCKS_PLL_MUL(163U, 66U), ///< PLL multiplier of 163.66
1048     CGC_PLL_MUL_164_0  = BSP_CLOCKS_PLL_MUL(164U, 0U),  ///< PLL multiplier of 164.00
1049     CGC_PLL_MUL_164_33 = BSP_CLOCKS_PLL_MUL(164U, 33U), ///< PLL multiplier of 164.33
1050     CGC_PLL_MUL_164_5  = BSP_CLOCKS_PLL_MUL(164U, 50U), ///< PLL multiplier of 164.50
1051     CGC_PLL_MUL_164_66 = BSP_CLOCKS_PLL_MUL(164U, 66U), ///< PLL multiplier of 164.66
1052     CGC_PLL_MUL_165_0  = BSP_CLOCKS_PLL_MUL(165U, 0U),  ///< PLL multiplier of 165.00
1053     CGC_PLL_MUL_165_33 = BSP_CLOCKS_PLL_MUL(165U, 33U), ///< PLL multiplier of 165.33
1054     CGC_PLL_MUL_165_5  = BSP_CLOCKS_PLL_MUL(165U, 50U), ///< PLL multiplier of 165.50
1055     CGC_PLL_MUL_165_66 = BSP_CLOCKS_PLL_MUL(165U, 66U), ///< PLL multiplier of 165.66
1056     CGC_PLL_MUL_166_0  = BSP_CLOCKS_PLL_MUL(166U, 0U),  ///< PLL multiplier of 166.00
1057     CGC_PLL_MUL_166_33 = BSP_CLOCKS_PLL_MUL(166U, 33U), ///< PLL multiplier of 166.33
1058     CGC_PLL_MUL_166_5  = BSP_CLOCKS_PLL_MUL(166U, 50U), ///< PLL multiplier of 166.50
1059     CGC_PLL_MUL_166_66 = BSP_CLOCKS_PLL_MUL(166U, 66U), ///< PLL multiplier of 166.66
1060     CGC_PLL_MUL_167_0  = BSP_CLOCKS_PLL_MUL(167U, 0U),  ///< PLL multiplier of 167.00
1061     CGC_PLL_MUL_167_33 = BSP_CLOCKS_PLL_MUL(167U, 33U), ///< PLL multiplier of 167.33
1062     CGC_PLL_MUL_167_5  = BSP_CLOCKS_PLL_MUL(167U, 50U), ///< PLL multiplier of 167.50
1063     CGC_PLL_MUL_167_66 = BSP_CLOCKS_PLL_MUL(167U, 66U), ///< PLL multiplier of 167.66
1064     CGC_PLL_MUL_168_0  = BSP_CLOCKS_PLL_MUL(168U, 0U),  ///< PLL multiplier of 168.00
1065     CGC_PLL_MUL_168_33 = BSP_CLOCKS_PLL_MUL(168U, 33U), ///< PLL multiplier of 168.33
1066     CGC_PLL_MUL_168_5  = BSP_CLOCKS_PLL_MUL(168U, 50U), ///< PLL multiplier of 168.50
1067     CGC_PLL_MUL_168_66 = BSP_CLOCKS_PLL_MUL(168U, 66U), ///< PLL multiplier of 168.66
1068     CGC_PLL_MUL_169_0  = BSP_CLOCKS_PLL_MUL(169U, 0U),  ///< PLL multiplier of 169.00
1069     CGC_PLL_MUL_169_33 = BSP_CLOCKS_PLL_MUL(169U, 33U), ///< PLL multiplier of 169.33
1070     CGC_PLL_MUL_169_5  = BSP_CLOCKS_PLL_MUL(169U, 50U), ///< PLL multiplier of 169.50
1071     CGC_PLL_MUL_169_66 = BSP_CLOCKS_PLL_MUL(169U, 66U), ///< PLL multiplier of 169.66
1072     CGC_PLL_MUL_170_0  = BSP_CLOCKS_PLL_MUL(170U, 0U),  ///< PLL multiplier of 170.00
1073     CGC_PLL_MUL_170_33 = BSP_CLOCKS_PLL_MUL(170U, 33U), ///< PLL multiplier of 170.33
1074     CGC_PLL_MUL_170_5  = BSP_CLOCKS_PLL_MUL(170U, 50U), ///< PLL multiplier of 170.50
1075     CGC_PLL_MUL_170_66 = BSP_CLOCKS_PLL_MUL(170U, 66U), ///< PLL multiplier of 170.66
1076     CGC_PLL_MUL_171_0  = BSP_CLOCKS_PLL_MUL(171U, 0U),  ///< PLL multiplier of 171.00
1077     CGC_PLL_MUL_171_33 = BSP_CLOCKS_PLL_MUL(171U, 33U), ///< PLL multiplier of 171.33
1078     CGC_PLL_MUL_171_5  = BSP_CLOCKS_PLL_MUL(171U, 50U), ///< PLL multiplier of 171.50
1079     CGC_PLL_MUL_171_66 = BSP_CLOCKS_PLL_MUL(171U, 66U), ///< PLL multiplier of 171.66
1080     CGC_PLL_MUL_172_0  = BSP_CLOCKS_PLL_MUL(172U, 0U),  ///< PLL multiplier of 172.00
1081     CGC_PLL_MUL_172_33 = BSP_CLOCKS_PLL_MUL(172U, 33U), ///< PLL multiplier of 172.33
1082     CGC_PLL_MUL_172_5  = BSP_CLOCKS_PLL_MUL(172U, 50U), ///< PLL multiplier of 172.50
1083     CGC_PLL_MUL_172_66 = BSP_CLOCKS_PLL_MUL(172U, 66U), ///< PLL multiplier of 172.66
1084     CGC_PLL_MUL_173_0  = BSP_CLOCKS_PLL_MUL(173U, 0U),  ///< PLL multiplier of 173.00
1085     CGC_PLL_MUL_173_33 = BSP_CLOCKS_PLL_MUL(173U, 33U), ///< PLL multiplier of 173.33
1086     CGC_PLL_MUL_173_5  = BSP_CLOCKS_PLL_MUL(173U, 50U), ///< PLL multiplier of 173.50
1087     CGC_PLL_MUL_173_66 = BSP_CLOCKS_PLL_MUL(173U, 66U), ///< PLL multiplier of 173.66
1088     CGC_PLL_MUL_174_0  = BSP_CLOCKS_PLL_MUL(174U, 0U),  ///< PLL multiplier of 174.00
1089     CGC_PLL_MUL_174_33 = BSP_CLOCKS_PLL_MUL(174U, 33U), ///< PLL multiplier of 174.33
1090     CGC_PLL_MUL_174_5  = BSP_CLOCKS_PLL_MUL(174U, 50U), ///< PLL multiplier of 174.50
1091     CGC_PLL_MUL_174_66 = BSP_CLOCKS_PLL_MUL(174U, 66U), ///< PLL multiplier of 174.66
1092     CGC_PLL_MUL_175_0  = BSP_CLOCKS_PLL_MUL(175U, 0U),  ///< PLL multiplier of 175.00
1093     CGC_PLL_MUL_175_33 = BSP_CLOCKS_PLL_MUL(175U, 33U), ///< PLL multiplier of 175.33
1094     CGC_PLL_MUL_175_5  = BSP_CLOCKS_PLL_MUL(175U, 50U), ///< PLL multiplier of 175.50
1095     CGC_PLL_MUL_175_66 = BSP_CLOCKS_PLL_MUL(175U, 66U), ///< PLL multiplier of 175.66
1096     CGC_PLL_MUL_176_0  = BSP_CLOCKS_PLL_MUL(176U, 0U),  ///< PLL multiplier of 176.00
1097     CGC_PLL_MUL_176_33 = BSP_CLOCKS_PLL_MUL(176U, 33U), ///< PLL multiplier of 176.33
1098     CGC_PLL_MUL_176_5  = BSP_CLOCKS_PLL_MUL(176U, 50U), ///< PLL multiplier of 176.50
1099     CGC_PLL_MUL_176_66 = BSP_CLOCKS_PLL_MUL(176U, 66U), ///< PLL multiplier of 176.66
1100     CGC_PLL_MUL_177_0  = BSP_CLOCKS_PLL_MUL(177U, 0U),  ///< PLL multiplier of 177.00
1101     CGC_PLL_MUL_177_33 = BSP_CLOCKS_PLL_MUL(177U, 33U), ///< PLL multiplier of 177.33
1102     CGC_PLL_MUL_177_5  = BSP_CLOCKS_PLL_MUL(177U, 50U), ///< PLL multiplier of 177.50
1103     CGC_PLL_MUL_177_66 = BSP_CLOCKS_PLL_MUL(177U, 66U), ///< PLL multiplier of 177.66
1104     CGC_PLL_MUL_178_0  = BSP_CLOCKS_PLL_MUL(178U, 0U),  ///< PLL multiplier of 178.00
1105     CGC_PLL_MUL_178_33 = BSP_CLOCKS_PLL_MUL(178U, 33U), ///< PLL multiplier of 178.33
1106     CGC_PLL_MUL_178_5  = BSP_CLOCKS_PLL_MUL(178U, 50U), ///< PLL multiplier of 178.50
1107     CGC_PLL_MUL_178_66 = BSP_CLOCKS_PLL_MUL(178U, 66U), ///< PLL multiplier of 178.66
1108     CGC_PLL_MUL_179_0  = BSP_CLOCKS_PLL_MUL(179U, 0U),  ///< PLL multiplier of 179.00
1109     CGC_PLL_MUL_179_33 = BSP_CLOCKS_PLL_MUL(179U, 33U), ///< PLL multiplier of 179.33
1110     CGC_PLL_MUL_179_5  = BSP_CLOCKS_PLL_MUL(179U, 50U), ///< PLL multiplier of 179.50
1111     CGC_PLL_MUL_179_66 = BSP_CLOCKS_PLL_MUL(179U, 66U), ///< PLL multiplier of 179.66
1112     CGC_PLL_MUL_180_0  = BSP_CLOCKS_PLL_MUL(180U, 0U),  ///< PLL multiplier of 180.00
1113     CGC_PLL_MUL_180_33 = BSP_CLOCKS_PLL_MUL(180U, 33U), ///< PLL multiplier of 180.33
1114     CGC_PLL_MUL_180_5  = BSP_CLOCKS_PLL_MUL(180U, 50U), ///< PLL multiplier of 180.50
1115     CGC_PLL_MUL_180_66 = BSP_CLOCKS_PLL_MUL(180U, 66U), ///< PLL multiplier of 180.66
1116     CGC_PLL_MUL_732_0  = BSP_CLOCKS_PLL_MUL(732U, 0U),  ///< PLL multiplier of 732.00
1117     CGC_PLL_MUL_781_0  = BSP_CLOCKS_PLL_MUL(781U, 0U),  ///< PLL multiplier of 781.00
1118 } cgc_pll_mul_t;
1119 
1120 /***********************************************************************************************************************
1121  * Exported global variables
1122  **********************************************************************************************************************/
1123 
1124 /***********************************************************************************************************************
1125  * Exported global functions (to be accessed by other files)
1126  **********************************************************************************************************************/
1127 
1128 /* Public functions defined in bsp.h */
1129 void bsp_clock_init(void);             // Used internally by BSP
1130 
1131 #if BSP_TZ_NONSECURE_BUILD
1132 void bsp_clock_freq_var_init(void);    // Used internally by BSP
1133 
1134 #endif
1135 
1136 #if BSP_TZ_SECURE_BUILD
1137 void r_bsp_clock_update_callback_set(bsp_clock_update_callback_t        p_callback,
1138                                      bsp_clock_update_callback_args_t * p_callback_memory);
1139 
1140 #endif
1141 
1142 /* Used internally by CGC */
1143 
1144 #if !BSP_CFG_USE_LOW_VOLTAGE_MODE
1145 void bsp_prv_operating_mode_set(uint8_t operating_mode);
1146 
1147 #endif
1148 
1149 #if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED
1150 uint32_t bsp_prv_power_change_mstp_set(void);
1151 void     bsp_prv_power_change_mstp_clear(uint32_t mstp_clear_bitmask);
1152 
1153 #endif
1154 
1155 void bsp_prv_prepare_pll(uint32_t clock, uint32_t const * const p_pll_hz);
1156 
1157 #if !BSP_FEATURE_CGC_REGISTER_SET_B
1158 void bsp_prv_clock_set(uint32_t clock, uint32_t sckdivcr, uint8_t sckdivcr2);
1159 
1160 #else
1161 void     bsp_prv_clock_set(uint32_t clock, uint8_t hocodiv, uint8_t mocodiv, uint8_t moscdiv);
1162 uint32_t bsp_prv_clock_source_get(void);
1163 
1164 #endif
1165 
1166 /* RTC Initialization */
1167 #if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_SYSC_HAS_VBTICTLR
1168 void R_BSP_Init_RTC(void);
1169 
1170 #endif
1171 
1172 #if BSP_CFG_SLEEP_MODE_DELAY_ENABLE || BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE
1173 bool bsp_prv_clock_prepare_pre_sleep(void);
1174 void bsp_prv_clock_prepare_post_sleep(bool cpuclk_slowed);
1175 
1176 #endif
1177 
1178 /* The public function is used to get state or initialize the sub-clock. */
1179 #if BSP_FEATURE_RTC_IS_IRTC
1180 fsp_err_t R_BSP_SubclockStatusGet();
1181 fsp_err_t R_BSP_SubclockInitialize();
1182 
1183 #endif
1184 
1185 /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
1186 FSP_FOOTER
1187 
1188 #endif
1189