1 /* 2 * Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /*******************************************************************************************************************//** 8 * @addtogroup BSP_MCU_RA4L1 9 * @{ 10 **********************************************************************************************************************/ 11 12 /** @} (end addtogroup BSP_MCU_RA4L1) */ 13 14 #ifndef BSP_OVERRIDE_H 15 #define BSP_OVERRIDE_H 16 17 /*********************************************************************************************************************** 18 * Includes <System Includes> , "Project Includes" 19 **********************************************************************************************************************/ 20 21 /*********************************************************************************************************************** 22 * Macro definitions 23 **********************************************************************************************************************/ 24 25 /* Define overrides required for this MCU. */ 26 #define BSP_OVERRIDE_LVD_PERIPHERAL_T 27 #define BSP_OVERRIDE_LPM_STANDBY_WAKE_SOURCE_T 28 #define BSP_OVERRIDE_LPM_SNOOZE_REQUEST_T 29 #define BSP_OVERRIDE_LPM_SNOOZE_END_T 30 #define BSP_OVERRIDE_UART_DATA_BITS_T 31 32 /*********************************************************************************************************************** 33 * Typedef definitions 34 **********************************************************************************************************************/ 35 36 /** PLL divider values */ 37 38 /** The thresholds supported by each MCU are in the MCU User's Manual as well as 39 * in the r_lvd module description on the stack tab of the RA project. */ 40 typedef enum 41 { 42 LVD_THRESHOLD_MONITOR_1_LEVEL_3_10V = 0x00UL, ///< 3.10V 43 LVD_THRESHOLD_MONITOR_1_LEVEL_3_00V = 0x01UL, ///< 3.00V 44 LVD_THRESHOLD_MONITOR_1_LEVEL_2_90V = 0x02UL, ///< 2.90V 45 LVD_THRESHOLD_MONITOR_1_LEVEL_2_79V = 0x03UL, ///< 2.79V 46 LVD_THRESHOLD_MONITOR_1_LEVEL_2_68V = 0x04UL, ///< 2.68V 47 LVD_THRESHOLD_MONITOR_1_LEVEL_2_58V = 0x05UL, ///< 2.58V 48 LVD_THRESHOLD_MONITOR_1_LEVEL_2_48V = 0x06UL, ///< 2.48V 49 LVD_THRESHOLD_MONITOR_1_LEVEL_2_20V = 0x07UL, ///< 2.20V 50 LVD_THRESHOLD_MONITOR_1_LEVEL_1_96V = 0x08UL, ///< 1.96V 51 LVD_THRESHOLD_MONITOR_1_LEVEL_1_86V = 0x09UL, ///< 1.86V 52 LVD_THRESHOLD_MONITOR_1_LEVEL_1_75V = 0x0AUL, ///< 1.75V 53 LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V = 0x0BUL, ///< 1.65V 54 LVD_THRESHOLD_MONITOR_2_LEVEL_3_13V = 0x00UL, ///< 3.13V 55 LVD_THRESHOLD_MONITOR_2_LEVEL_2_92V = 0x01UL, ///< 2.92V 56 LVD_THRESHOLD_MONITOR_2_LEVEL_2_71V = 0x02UL, ///< 2.71V 57 LVD_THRESHOLD_MONITOR_2_LEVEL_2_50V = 0x03UL, ///< 2.50V 58 LVD_THRESHOLD_MONITOR_2_LEVEL_2_30V = 0x04UL, ///< 2.30V 59 LVD_THRESHOLD_MONITOR_2_LEVEL_2_09V = 0x05UL, ///< 2.09V 60 LVD_THRESHOLD_MONITOR_2_LEVEL_1_88V = 0x06UL, ///< 1.88V 61 LVD_THRESHOLD_MONITOR_2_LEVEL_1_67V = 0x07UL, ///< 1.67V 62 } lvd_threshold_t; 63 64 /** Wake from deep sleep or standby mode sources, does not apply to sleep or deep standby modes */ 65 typedef enum e_lpm_standby_wake_source 66 { 67 LPM_STANDBY_WAKE_SOURCE_IRQ0 = 0x00000001ULL, ///< IRQ0 68 LPM_STANDBY_WAKE_SOURCE_IRQ1 = 0x00000002ULL, ///< IRQ1 69 LPM_STANDBY_WAKE_SOURCE_IRQ2 = 0x00000004ULL, ///< IRQ2 70 LPM_STANDBY_WAKE_SOURCE_IRQ3 = 0x00000008ULL, ///< IRQ3 71 LPM_STANDBY_WAKE_SOURCE_IRQ4 = 0x00000010ULL, ///< IRQ4 72 LPM_STANDBY_WAKE_SOURCE_IRQ5 = 0x00000020ULL, ///< IRQ5 73 LPM_STANDBY_WAKE_SOURCE_IRQ6 = 0x00000040ULL, ///< IRQ6 74 LPM_STANDBY_WAKE_SOURCE_IRQ7 = 0x00000080ULL, ///< IRQ7 75 LPM_STANDBY_WAKE_SOURCE_IRQ8 = 0x00000100ULL, ///< IRQ8 76 LPM_STANDBY_WAKE_SOURCE_IRQ9 = 0x00000200ULL, ///< IRQ9 77 LPM_STANDBY_WAKE_SOURCE_IRQ10 = 0x00000400ULL, ///< IRQ10 78 LPM_STANDBY_WAKE_SOURCE_IRQ11 = 0x00000800ULL, ///< IRQ11 79 LPM_STANDBY_WAKE_SOURCE_IRQ12 = 0x00001000ULL, ///< IRQ12 80 LPM_STANDBY_WAKE_SOURCE_IRQ13 = 0x00002000ULL, ///< IRQ13 81 LPM_STANDBY_WAKE_SOURCE_IRQ14 = 0x00004000ULL, ///< IRQ14 82 LPM_STANDBY_WAKE_SOURCE_IRQ15 = 0x00008000ULL, ///< IRQ15 83 LPM_STANDBY_WAKE_SOURCE_IWDT = 0x00010000ULL, ///< Independent watchdog interrupt 84 LPM_STANDBY_WAKE_SOURCE_LVD1 = 0x00040000ULL, ///< Low Voltage Detection 1 interrupt 85 LPM_STANDBY_WAKE_SOURCE_LVD2 = 0x00080000ULL, ///< Low Voltage Detection 2 interrupt 86 LPM_STANDBY_WAKE_SOURCE_ACMPLP0 = 0x00800000ULL, ///< Analog Comparator Low-speed 0 interrupt 87 LPM_STANDBY_WAKE_SOURCE_RTCALM = 0x01000000ULL, ///< RTC Alarm interrupt 88 LPM_STANDBY_WAKE_SOURCE_RTCPRD = 0x02000000ULL, ///< RTC Period interrupt 89 LPM_STANDBY_WAKE_SOURCE_USBFS = 0x08000000ULL, ///< USB Full-speed interrupt 90 LPM_STANDBY_WAKE_SOURCE_AGT1UD = 0x10000000ULL, ///< AGT1 Underflow interrupt 91 LPM_STANDBY_WAKE_SOURCE_AGT1CA = 0x20000000ULL, ///< AGT1 Compare Match A interrupt 92 LPM_STANDBY_WAKE_SOURCE_AGT1CB = 0x40000000ULL, ///< AGT1 Compare Match B interrupt 93 LPM_STANDBY_WAKE_SOURCE_IIC0 = 0x80000000ULL, ///< I2C 0 interrupt 94 LPM_STANDBY_WAKE_SOURCE_SOSTD = 0x8000000000ULL, ///< SOSTD interrupt 95 LPM_STANDBY_WAKE_SOURCE_I3C0 = 0x80000000000ULL, ///< I3C0 address match interrupt 96 } lpm_standby_wake_source_t; 97 98 typedef enum e_lpm_standby_wake_source_2 99 { 100 LPM_STANDBY_WAKE_SOURCE_INTUR0 = 0x00000001ULL, ///< UARTA0 INTUR Interrupt 101 LPM_STANDBY_WAKE_SOURCE_INTURE0 = 0x00000002ULL, ///< UARTA0 INTURE Interrupt 102 LPM_STANDBY_WAKE_SOURCE_INTUR1 = 0x00000004ULL, ///< UARTA1 INTUR Interrupt 103 LPM_STANDBY_WAKE_SOURCE_INTURE1 = 0x00000008ULL, ///< UARTA1 INTURE Interrupt 104 LPM_STANDBY_WAKE_SOURCE_USBCCS = 0x00000010ULL, ///< USBCC Status Change Interrupt 105 } lpm_standby_wake_source_2_t; 106 107 typedef uint64_t lpm_standby_wake_source_bits_t; 108 109 /** Snooze request sources */ 110 typedef enum e_lpm_snooze_request 111 { 112 LPM_SNOOZE_REQUEST_RXD0_FALLING = 0x00000000ULL, ///< Enable RXD0 falling edge snooze request 113 LPM_SNOOZE_REQUEST_IRQ0 = 0x00000001ULL, ///< Enable IRQ0 pin snooze request 114 LPM_SNOOZE_REQUEST_IRQ1 = 0x00000002ULL, ///< Enable IRQ1 pin snooze request 115 LPM_SNOOZE_REQUEST_IRQ2 = 0x00000004ULL, ///< Enable IRQ2 pin snooze request 116 LPM_SNOOZE_REQUEST_IRQ3 = 0x00000008ULL, ///< Enable IRQ3 pin snooze request 117 LPM_SNOOZE_REQUEST_IRQ4 = 0x00000010ULL, ///< Enable IRQ4 pin snooze request 118 LPM_SNOOZE_REQUEST_IRQ5 = 0x00000020ULL, ///< Enable IRQ5 pin snooze request 119 LPM_SNOOZE_REQUEST_IRQ6 = 0x00000040ULL, ///< Enable IRQ6 pin snooze request 120 LPM_SNOOZE_REQUEST_IRQ7 = 0x00000080ULL, ///< Enable IRQ7 pin snooze request 121 LPM_SNOOZE_REQUEST_IRQ8 = 0x00000100ULL, ///< Enable IRQ8 pin snooze request 122 LPM_SNOOZE_REQUEST_IRQ9 = 0x00000200ULL, ///< Enable IRQ9 pin snooze request 123 LPM_SNOOZE_REQUEST_IRQ10 = 0x00000400ULL, ///< Enable IRQ10 pin snooze request 124 LPM_SNOOZE_REQUEST_IRQ11 = 0x00000800ULL, ///< Enable IRQ11 pin snooze request 125 LPM_SNOOZE_REQUEST_IRQ12 = 0x00001000ULL, ///< Enable IRQ12 pin snooze request 126 LPM_SNOOZE_REQUEST_IRQ13 = 0x00002000ULL, ///< Enable IRQ13 pin snooze request 127 LPM_SNOOZE_REQUEST_IRQ14 = 0x00004000ULL, ///< Enable IRQ14 pin snooze request 128 LPM_SNOOZE_REQUEST_IRQ15 = 0x00008000ULL, ///< Enable IRQ15 pin snooze request 129 LPM_SNOOZE_REQUEST_ACMPLP0 = 0x00400000ULL, ///< Enable Low-speed analog comparator 0 snooze request 130 LPM_SNOOZE_REQUEST_RTC_ALARM = 0x01000000ULL, ///< Enable RTC alarm snooze request 131 LPM_SNOOZE_REQUEST_RTC_PERIOD = 0x02000000ULL, ///< Enable RTC period snooze request 132 LPM_SNOOZE_REQUEST_AGT1_UNDERFLOW = 0x10000000ULL, ///< Enable AGT1 underflow snooze request 133 LPM_SNOOZE_REQUEST_AGT1_COMPARE_A = 0x20000000ULL, ///< Enable AGT1 compare match A snooze request 134 LPM_SNOOZE_REQUEST_AGT1_COMPARE_B = 0x40000000ULL, ///< Enable AGT1 compare match B snooze request 135 } lpm_snooze_request_t; 136 137 /** Snooze end control */ 138 typedef enum e_lpm_snooze_end 139 { 140 LPM_SNOOZE_END_STANDBY_WAKE_SOURCES = 0x00U, ///< Transition from Snooze to Normal mode directly 141 LPM_SNOOZE_END_AGT1_UNDERFLOW = 0x01U, ///< AGT1 underflow 142 LPM_SNOOZE_END_DTC_TRANS_COMPLETE = 0x02U, ///< Last DTC transmission completion 143 LPM_SNOOZE_END_DTC_TRANS_COMPLETE_NEGATED = 0x04U, ///< Not Last DTC transmission completion 144 LPM_SNOOZE_END_ADC0_COMPARE_MATCH = 0x08U, ///< ADC Channel 0 compare match 145 LPM_SNOOZE_END_ADC0_COMPARE_MISMATCH = 0x10U, ///< ADC Channel 0 compare mismatch 146 LPM_SNOOZE_END_SCI0_ADDRESS_MISMATCH = 0x20U, ///< SCI0 address mismatch 147 LPM_SNOOZE_END_CTSU_NAJED = 0x40U, ///< CTSU2SLa non-touch automatic judgment 148 } lpm_snooze_end_t; 149 150 typedef uint16_t lpm_snooze_end_bits_t; 151 152 /** UART Data bit length definition */ 153 typedef enum e_uart_data_bits 154 { 155 UART_DATA_BITS_5 = 0U, ///< Data bits 5-bit 156 UART_DATA_BITS_9 = 1U, ///< Data bits 9-bit 157 UART_DATA_BITS_7 = 2U, ///< Data bits 7-bit 158 UART_DATA_BITS_8 = 3U, ///< Data bits 8-bit 159 } uart_data_bits_t; 160 161 /*********************************************************************************************************************** 162 * Exported global variables 163 **********************************************************************************************************************/ 164 165 /*********************************************************************************************************************** 166 * Exported global functions (to be accessed by other files) 167 **********************************************************************************************************************/ 168 169 #endif 170
