1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef BSP_MCU_FAMILY_CFG_H_ 8 #define BSP_MCU_FAMILY_CFG_H_ 9 #define BSP_MCU_GROUP_RZG3S (1) 10 #define BSP_CURRENT_CORE (RZG3S_CORE_CM33) 11 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) 12 #define BSP_VECTOR_TABLE_MAX_ENTRIES (496U) 13 #include "bsp_mcu_device_pn_cfg.h" 14 #include "bsp_mcu_device_cfg.h" 15 #include "bsp_multi_core.h" 16 #include "bsp_override.h" 17 #include "bsp_mcu_info.h" 18 #include "bsp_clock_cfg.h" 19 20 #if defined(_RZG3S_TZ_SECURE) 21 #define BSP_TZ_SECURE_BUILD (1) 22 #define BSP_TZ_NONSECURE_BUILD (0) 23 #elif defined(_RZG3S_TZ_NONSECURE) 24 #define BSP_TZ_SECURE_BUILD (0) 25 #define BSP_TZ_NONSECURE_BUILD (1) 26 #else 27 #define BSP_TZ_SECURE_BUILD (0) 28 #define BSP_TZ_NONSECURE_BUILD (0) 29 #endif 30 31 #define BSP_NONSECURE_TRANSITION (0) 32 33 /* TrustZone Settings */ 34 #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) 35 #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) 36 37 #define SCB_SCR_SLEEPDEEPS_VAL (0) 38 #define SCB_SCR_SLEEPDEEP_VAL (0) 39 40 /* CMSIS TrustZone Settings */ 41 #define SCB_CSR_AIRCR_INIT (1) 42 #define SCB_AIRCR_BFHFNMINS_VAL (1) 43 #define SCB_AIRCR_SYSRESETREQS_VAL (0) 44 #define SCB_AIRCR_PRIS_VAL (0) 45 #define TZ_FPU_NS_USAGE (1) 46 #ifndef SCB_NSACR_CP10_11_VAL 47 #define SCB_NSACR_CP10_11_VAL (3U) 48 #endif 49 #define SCB_SHCSR_SECUREFAULTENA_VAL (1) 50 51 #ifndef FPU_FPCCR_TS_VAL 52 #define FPU_FPCCR_TS_VAL (0U) 53 #endif 54 #define FPU_FPCCR_CLRONRETS_VAL (0) 55 56 #ifndef FPU_FPCCR_CLRONRET_VAL 57 #define FPU_FPCCR_CLRONRET_VAL (1) 58 #endif 59 #endif /* BSP_MCU_FAMILY_CFG_H_ */ 60
