1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef BSP_RESET_H 8 #define BSP_RESET_H 9 10 /*********************************************************************************************************************** 11 * Includes <System Includes> , "Project Includes" 12 **********************************************************************************************************************/ 13 14 /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 15 FSP_HEADER 16 17 /*********************************************************************************************************************** 18 * Macro definitions 19 **********************************************************************************************************************/ 20 21 /* Key code for writing reset register. */ 22 #define BSP_PRV_RESET_KEY (0x4321A501U) 23 #define BSP_PRV_RESET_KEY_AUTO_RELEASE (0x4321A502U) 24 #define BSP_PRV_RESET_RELEASE_KEY (0x00000000U) 25 26 /* MRCTL register selection. Bits 16-20 assign values in order for the module control registers (A=0, E=4). 27 * Bit 24 indicates whether MRCTLn register is in the safety region. */ 28 #define BSP_RESET_MRCTLA_SELECT (0x00000000U) 29 #define BSP_RESET_MRCTLE_SELECT (0x00040000U) 30 #define BSP_RESET_MRCTLI_SELECT (0x00480000U) 31 #define BSP_RESET_MRCTLM_SELECT (0x000C0000U) 32 33 /* MRCTL register bit number. */ 34 #define BSP_RESET_MRCTL_BIT0_SHIFT (0x00000000U) 35 #define BSP_RESET_MRCTL_BIT1_SHIFT (0x00000001U) 36 #define BSP_RESET_MRCTL_BIT2_SHIFT (0x00000002U) 37 #define BSP_RESET_MRCTL_BIT3_SHIFT (0x00000003U) 38 #define BSP_RESET_MRCTL_BIT4_SHIFT (0x00000004U) 39 #define BSP_RESET_MRCTL_BIT5_SHIFT (0x00000005U) 40 #define BSP_RESET_MRCTL_BIT6_SHIFT (0x00000006U) 41 #define BSP_RESET_MRCTL_BIT7_SHIFT (0x00000007U) 42 #define BSP_RESET_MRCTL_BIT8_SHIFT (0x00000008U) 43 #define BSP_RESET_MRCTL_BIT9_SHIFT (0x00000009U) 44 #define BSP_RESET_MRCTL_BIT10_SHIFT (0x0000000AU) 45 #define BSP_RESET_MRCTL_BIT11_SHIFT (0x0000000BU) 46 #define BSP_RESET_MRCTL_BIT12_SHIFT (0x0000000CU) 47 #define BSP_RESET_MRCTL_BIT13_SHIFT (0x0000000DU) 48 #define BSP_RESET_MRCTL_BIT14_SHIFT (0x0000000EU) 49 #define BSP_RESET_MRCTL_BIT15_SHIFT (0x0000000FU) 50 #define BSP_RESET_MRCTL_BIT16_SHIFT (0x00000010U) 51 #define BSP_RESET_MRCTL_BIT17_SHIFT (0x00000011U) 52 #define BSP_RESET_MRCTL_BIT18_SHIFT (0x00000012U) 53 #define BSP_RESET_MRCTL_BIT19_SHIFT (0x00000013U) 54 #define BSP_RESET_MRCTL_BIT20_SHIFT (0x00000014U) 55 #define BSP_RESET_MRCTL_BIT21_SHIFT (0x00000015U) 56 #define BSP_RESET_MRCTL_BIT22_SHIFT (0x00000016U) 57 #define BSP_RESET_MRCTL_BIT23_SHIFT (0x00000017U) 58 #define BSP_RESET_MRCTL_BIT24_SHIFT (0x00000018U) 59 #define BSP_RESET_MRCTL_BIT25_SHIFT (0x00000019U) 60 #define BSP_RESET_MRCTL_BIT26_SHIFT (0x0000001AU) 61 #define BSP_RESET_MRCTL_BIT27_SHIFT (0x0000001BU) 62 #define BSP_RESET_MRCTL_BIT28_SHIFT (0x0000001CU) 63 #define BSP_RESET_MRCTL_BIT29_SHIFT (0x0000001DU) 64 #define BSP_RESET_MRCTL_BIT30_SHIFT (0x0000001EU) 65 #define BSP_RESET_MRCTL_BIT31_SHIFT (0x0000001FU) 66 67 /*********************************************************************************************************************** 68 * Typedef definitions 69 **********************************************************************************************************************/ 70 71 /*******************************************************************************************************************//** 72 * @addtogroup BSP_MCU 73 * @{ 74 **********************************************************************************************************************/ 75 76 /** CPU to be reset target.*/ 77 typedef enum e_bsp_reset 78 { 79 BSP_RESET_CR52_0 = 0, ///< Software reset for CR52_0 80 BSP_RESET_CR52_1 = 1, ///< Software reset for CR52_1 81 BSP_RESET_CA55_CLUSTER = 2, ///< Software reset for CA55_CLUSTER 82 BSP_RESET_CA55_0 = 3, ///< Software reset for CA55_0 83 BSP_RESET_CA55_1 = 4, ///< Software reset for CA55_1 84 BSP_RESET_CA55_2 = 5, ///< Software reset for CA55_2 85 BSP_RESET_CA55_3 = 6, ///< Software reset for CA55_3 86 } bsp_reset_t; 87 88 /** CA55 cluster reset auto reset release status. */ 89 typedef enum e_bsp_cluster_reset_auto_release 90 { 91 BSP_CLUSTER_RESET_AUTO_RELEASE_DISABLE = 0, 92 BSP_CLUSTER_RESET_AUTO_RELEASE_ENABLE = 1, 93 } bsp_cluster_reset_auto_release_t; 94 95 /** The different types of registers that can control the reset of peripheral modules related to Ethernet. */ 96 typedef enum e_bsp_module_reset 97 { 98 /** Enables writing to the registers related to xSPI Unit 0 reset control. */ 99 BSP_MODULE_RESET_XSPI0 = (BSP_RESET_MRCTLA_SELECT | BSP_RESET_MRCTL_BIT4_SHIFT), 100 101 /** Enables writing to the registers related to xSPI Unit 1 reset control. */ 102 BSP_MODULE_RESET_XSPI1 = (BSP_RESET_MRCTLA_SELECT | BSP_RESET_MRCTL_BIT5_SHIFT), 103 104 /** Enables writing to the registers related to GMAC (PCLKH clock domain) reset control. */ 105 BSP_MODULE_RESET_GMAC0_PCLKH = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT0_SHIFT), 106 107 /** Enables writing to the registers related to GMAC (PCLKM clock domain) reset control. */ 108 BSP_MODULE_RESET_GMAC0_PCLKM = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT1_SHIFT), 109 110 /** Enables writing to the registers related to ETHSW reset control. */ 111 BSP_MODULE_RESET_ETHSW = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT2_SHIFT), 112 113 /** Enables writing to the registers related to ESC (Bus clock domain) reset control. */ 114 BSP_MODULE_RESET_ESC_BUS = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT3_SHIFT), 115 116 /** Enables writing to the registers related to ESC (IP clock domain) reset control. */ 117 BSP_MODULE_RESET_ESC_IP = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT4_SHIFT), 118 119 /** Enables writing to the registers related to Ethernet subsystem register reset control. */ 120 BSP_MODULE_RESET_ESC_ETH_SUBSYSTEM = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT5_SHIFT), 121 122 /** Enables writing to the registers related to MII converter reset control. */ 123 BSP_MODULE_RESET_MII = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT6_SHIFT), 124 125 /** Enables writing to the registers related to GMAC Unit 1 (PCLKAH clock domain) reset control. */ 126 BSP_MODULE_RESET_GMAC1_ACLK = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT16_SHIFT), 127 128 /** Enables writing to the registers related to GMAC Unit 1 (PCLKAM clock domain) reset control. */ 129 BSP_MODULE_RESET_GMAC1_HCLK = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT17_SHIFT), 130 131 /** Enables writing to the registers related to GMAC Unit 2 (PCLKAH clock domain) reset control. */ 132 BSP_MODULE_RESET_GMAC2_ACLK = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT18_SHIFT), 133 134 /** Enables writing to the registers related to GMAC Unit 2 (PCLKAM clock domain) reset control. */ 135 BSP_MODULE_RESET_GMAC2_HCLK = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT19_SHIFT), 136 137 /** Enables writing to the registers related to PHOSTIF reset control. */ 138 BSP_MODULE_RESET_PHOSTIF = (BSP_RESET_MRCTLI_SELECT | BSP_RESET_MRCTL_BIT0_SHIFT), 139 140 /** Enables writing to the registers related to SHOSTIF (Master bus clock domain) reset control. */ 141 BSP_MODULE_RESET_SHOSTIF_MASTER_BUS_CLOCK = (BSP_RESET_MRCTLI_SELECT | BSP_RESET_MRCTL_BIT1_SHIFT), 142 143 /** Enables writing to the registers related to SHOSTIF (Slave bus clock domain) reset control. */ 144 BSP_MODULE_RESET_SHOSTIF_SLAVE_BUS_CLOCK = (BSP_RESET_MRCTLI_SELECT | BSP_RESET_MRCTL_BIT2_SHIFT), 145 146 /** Enables writing to the registers related to SHOSTIF (IP clock domain) reset control. */ 147 BSP_MODULE_RESET_SHOSTIF_IP_CLOCK = (BSP_RESET_MRCTLI_SELECT | BSP_RESET_MRCTL_BIT3_SHIFT), 148 149 /** Enables writing to the registers related to PCIE reset control. */ 150 BSP_MODULE_RESET_PCIE = (BSP_RESET_MRCTLM_SELECT | BSP_RESET_MRCTL_BIT8_SHIFT), 151 152 /** Enables writing to the registers related to DDRSS rst_n reset control. */ 153 BSP_MODULE_RESET_DDRSS_RST_N = (BSP_RESET_MRCTLM_SELECT | BSP_RESET_MRCTL_BIT16_SHIFT), 154 155 /** Enables writing to the registers related to DDRSS PwrOkln reset control. */ 156 BSP_MODULE_RESET_DDRSS_RST_PWROKLN = (BSP_RESET_MRCTLM_SELECT | BSP_RESET_MRCTL_BIT17_SHIFT), 157 158 /** Enables writing to the registers related to DDRSS Reset reset control. */ 159 BSP_MODULE_RESET_DDRSS_RESET = (BSP_RESET_MRCTLM_SELECT | BSP_RESET_MRCTL_BIT18_SHIFT), 160 161 /** Enables writing to the registers related to DDRSS axi0_ARESETn reset control. */ 162 BSP_MODULE_RESET_DDRSS_AXI0_ARESETN = (BSP_RESET_MRCTLM_SELECT | BSP_RESET_MRCTL_BIT19_SHIFT), 163 164 /** Enables writing to the registers related to DDRSS axi1_ARESETn reset control. */ 165 BSP_MODULE_RESET_DDRSS_AXI1_ARESETN = (BSP_RESET_MRCTLM_SELECT | BSP_RESET_MRCTL_BIT20_SHIFT), 166 167 /** Enables writing to the registers related to DDRSS axi2_ARESETn reset control. */ 168 BSP_MODULE_RESET_DDRSS_AXI2_ARESETN = (BSP_RESET_MRCTLM_SELECT | BSP_RESET_MRCTL_BIT21_SHIFT), 169 170 /** Enables writing to the registers related to DDRSS axi3_ARESETn reset control. */ 171 BSP_MODULE_RESET_DDRSS_AXI3_ARESETN = (BSP_RESET_MRCTLM_SELECT | BSP_RESET_MRCTL_BIT22_SHIFT), 172 173 /** Enables writing to the registers related to DDRSS axi4_ARESETn reset control. */ 174 BSP_MODULE_RESET_DDRSS_AXI4_ARESETN = (BSP_RESET_MRCTLM_SELECT | BSP_RESET_MRCTL_BIT23_SHIFT), 175 176 /** Enables writing to the registers related to DDRSS MC_PRESETn reset control. */ 177 BSP_MODULE_RESET_DDRSS_MC_PRESETN = (BSP_RESET_MRCTLM_SELECT | BSP_RESET_MRCTL_BIT24_SHIFT), 178 179 /** Enables writing to the registers related to DDRSS PHY_PRESETn reset control. */ 180 BSP_MODULE_RESET_DDRSS_PHY_PRESETN = (BSP_RESET_MRCTLM_SELECT | BSP_RESET_MRCTL_BIT25_SHIFT), 181 } bsp_module_reset_t; 182 183 /** @} (end addtogroup BSP_MCU) */ 184 185 /*********************************************************************************************************************** 186 * Exported global variables 187 **********************************************************************************************************************/ 188 189 /*********************************************************************************************************************** 190 * Exported global functions (to be accessed by other files) 191 **********************************************************************************************************************/ 192 193 /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 194 FSP_FOOTER 195 196 #endif 197
