1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef BSP_MCU_FAMILY_CFG_H_ 7 #define BSP_MCU_FAMILY_CFG_H_ 8 #include "bsp_mcu_device_pn_cfg.h" 9 #include "bsp_mcu_device_cfg.h" 10 #include "bsp_override.h" 11 #include "bsp_mcu_info.h" 12 #include "bsp_clock_cfg.h" 13 #define BSP_MCU_GROUP_RA8M1 (1) 14 #define BSP_LOCO_HZ (DT_PROP_OR(DT_NODELABEL(loco), clock_frequency, 0)) 15 #define BSP_MOCO_HZ (DT_PROP_OR(DT_NODELABEL(moco), clock_frequency, 0)) 16 #define BSP_SUB_CLOCK_HZ (0) 17 #if BSP_CFG_HOCO_FREQUENCY == 0 18 #define BSP_HOCO_HZ (16000000) 19 #elif BSP_CFG_HOCO_FREQUENCY == 1 20 #define BSP_HOCO_HZ (18000000) 21 #elif BSP_CFG_HOCO_FREQUENCY == 2 22 #define BSP_HOCO_HZ (20000000) 23 #elif BSP_CFG_HOCO_FREQUENCY == 4 24 #define BSP_HOCO_HZ (32000000) 25 #elif BSP_CFG_HOCO_FREQUENCY == 7 26 #define BSP_HOCO_HZ (48000000) 27 #else 28 #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" 29 #endif 30 31 #define BSP_CFG_FLL_ENABLE (0) 32 33 #define BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE (1) 34 #define BSP_CFG_SLEEP_MODE_DELAY_ENABLE (1) 35 #define BSP_CFG_MSTP_CHANGE_DELAY_ENABLE (1) 36 #define BSP_CFG_RTOS_IDLE_SLEEP (0) 37 #define BSP_CFG_CLOCK_SETTLING_DELAY_US (150) 38 39 #if defined(BSP_PACKAGE_LQFP) && (BSP_PACKAGE_PINS == 100) 40 #define BSP_MAX_CLOCK_CHANGE_THRESHOLD (180000000U) 41 #elif defined(BSP_PACKAGE_LQFP) 42 #define BSP_MAX_CLOCK_CHANGE_THRESHOLD (200000000U) 43 #else 44 #define BSP_MAX_CLOCK_CHANGE_THRESHOLD (240000000U) 45 #endif 46 47 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) 48 #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) 49 #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) 50 51 #if defined(_RA_TZ_SECURE) 52 #define BSP_TZ_SECURE_BUILD (1) 53 #define BSP_TZ_NONSECURE_BUILD (0) 54 #elif defined(_RA_TZ_NONSECURE) 55 #define BSP_TZ_SECURE_BUILD (0) 56 #define BSP_TZ_NONSECURE_BUILD (1) 57 #else 58 #define BSP_TZ_SECURE_BUILD (0) 59 #define BSP_TZ_NONSECURE_BUILD (0) 60 #endif 61 62 /* TrustZone Settings */ 63 #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) 64 #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) 65 #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) 66 67 /* CMSIS TrustZone Settings */ 68 #define SCB_CSR_AIRCR_INIT (1) 69 #define SCB_AIRCR_BFHFNMINS_VAL (0) 70 #define SCB_AIRCR_SYSRESETREQS_VAL (1) 71 #define SCB_AIRCR_PRIS_VAL (0) 72 #define TZ_FPU_NS_USAGE (1) 73 #ifndef SCB_NSACR_CP10_11_VAL 74 #define SCB_NSACR_CP10_11_VAL (3U) 75 #endif 76 77 #ifndef FPU_FPCCR_TS_VAL 78 #define FPU_FPCCR_TS_VAL (1U) 79 #endif 80 #define FPU_FPCCR_CLRONRETS_VAL (1) 81 82 #ifndef FPU_FPCCR_CLRONRET_VAL 83 #define FPU_FPCCR_CLRONRET_VAL (1) 84 #endif 85 86 /* Type 1 Peripheral Security Attribution */ 87 88 /* Peripheral Security Attribution Register (PSAR) Settings */ 89 #ifndef BSP_TZ_CFG_PSARB 90 #define BSP_TZ_CFG_PSARB (\ 91 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4) /* I3C */ | \ 92 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ 93 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ 94 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ 95 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* USBHS */ | \ 96 (1 << 15) /* ETHERC/EDMAC */ | \ 97 (1 << 16) /* OSPI */ | \ 98 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ 99 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ 100 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ 101 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \ 102 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ 103 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \ 104 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ 105 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */) 106 #endif 107 #ifndef BSP_TZ_CFG_PSARC 108 #define BSP_TZ_CFG_PSARC (\ 109 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ 110 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ 111 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7) /* SSIE1 */ | \ 112 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ 113 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* SDHI1 */ | \ 114 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \ 115 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ 116 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* CEU */ | \ 117 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* CANFD1 */ | \ 118 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* CANFD0 */ | \ 119 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* RSIP7 */) 120 #endif 121 #ifndef BSP_TZ_CFG_PSARD 122 #define BSP_TZ_CFG_PSARD (\ 123 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4) /* AGT1 */ | \ 124 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5) /* AGT0 */ | \ 125 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ 126 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ 127 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ 128 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ 129 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC121 */ | \ 130 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC120 */ | \ 131 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC120 */ | \ 132 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ 133 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* ACMPHS1 */ | \ 134 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* ACMPHS0 */) 135 #endif 136 #ifndef BSP_TZ_CFG_PSARE 137 #define BSP_TZ_CFG_PSARE (\ 138 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* WDT */ | \ 139 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* IWDT */ | \ 140 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* RTC */ | \ 141 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* ULPT1 */ | \ 142 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* ULPT0 */ | \ 143 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* GPT13 */ | \ 144 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* GPT12 */ | \ 145 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* GPT11 */ | \ 146 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 21) /* GPT10 */ | \ 147 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ 148 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \ 149 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ 150 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ 151 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ 152 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ 153 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ 154 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ 155 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ 156 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */) 157 #endif 158 #ifndef BSP_TZ_CFG_MSSAR 159 #define BSP_TZ_CFG_MSSAR (\ 160 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* DTC_DMAC */ | \ 161 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* ELC */) 162 #endif 163 164 /* Type 2 Peripheral Security Attribution */ 165 166 /* Security attribution for RSTSRn registers. */ 167 #ifndef BSP_TZ_CFG_RSTSAR 168 #define BSP_TZ_CFG_RSTSAR (0x0000000FU) 169 #endif 170 171 /* Security attribution for registers of LVD channels. */ 172 #ifndef BSP_TZ_CFG_LVDSAR 173 /* The LVD driver needs to access both channels. This means that the security attribution for both channels must be the same. */ 174 #if (RA_NOT_DEFINED > 0) || (RA_NOT_DEFINED > 0) 175 #define BSP_TZ_CFG_LVDSAR (0U) 176 #else 177 #define BSP_TZ_CFG_LVDSAR (3U) 178 #endif 179 #endif 180 181 /* Security attribution for LPM registers. 182 * - OPCCR based on clock security. 183 * - Set remaining registers based on LPM security. 184 */ 185 #ifndef BSP_TZ_CFG_LPMSAR 186 #define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? BSP_CFG_CLOCKS_SECURE == 0 : (\ 187 0x002E0106U | \ 188 (BSP_CFG_CLOCKS_SECURE == 0))) 189 #endif 190 /* Deep Standby Interrupt Factor Security Attribution Register. */ 191 #ifndef BSP_TZ_CFG_DPFSAR 192 #define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0U : 0xAF1FFFFFU) 193 #endif 194 /* RAM Standby Control Security Attribution Register. */ 195 #ifndef BSP_TZ_CFG_RSCSAR 196 #define BSP_TZ_CFG_RSCSAR ((RA_NOT_DEFINED > 0) ? 0U : 0x00037FFFU) 197 #endif 198 199 /* Security attribution for CGC registers. */ 200 #ifndef BSP_TZ_CFG_CGFSAR 201 #if BSP_CFG_CLOCKS_SECURE 202 /* Protect all CGC registers from Non-secure write access. */ 203 #define BSP_TZ_CFG_CGFSAR (0U) 204 #else 205 /* Allow Secure and Non-secure write access. */ 206 #define BSP_TZ_CFG_CGFSAR (0x047F3BFDU) 207 #endif 208 #endif 209 210 /* Security attribution for Battery Backup registers. */ 211 #ifndef BSP_TZ_CFG_BBFSAR 212 #define BSP_TZ_CFG_BBFSAR (0x0000001FU) 213 #endif 214 215 /* Security attribution for registers for IRQ channels. */ 216 #ifndef BSP_TZ_CFG_ICUSARA 217 #define BSP_TZ_CFG_ICUSARA (\ 218 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ 219 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ 220 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ 221 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ 222 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ 223 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ 224 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ 225 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ 226 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ 227 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ 228 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ 229 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ 230 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ 231 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ 232 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ 233 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */) 234 #endif 235 236 /* Security attribution for NMI registers. */ 237 #ifndef BSP_TZ_CFG_ICUSARB 238 #define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ 239 #endif 240 241 /* Security attribution for registers for DMAC channels */ 242 #ifndef BSP_TZ_CFG_DMACCHSAR 243 #define BSP_TZ_CFG_DMACCHSAR (\ 244 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ 245 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ 246 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ 247 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ 248 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ 249 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ 250 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ 251 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */) 252 #endif 253 254 /* Security attribution registers for WUPEN0. */ 255 #ifndef BSP_TZ_CFG_ICUSARE 256 #define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0U : 0xFF1D0000U) 257 #endif 258 259 /* Security attribution registers for WUPEN1. */ 260 #ifndef BSP_TZ_CFG_ICUSARF 261 #define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0U : 0x00007F08U) 262 #endif 263 264 /* Trusted Event Route Control Register for IELSR, DMAC.DELSR and ELC.ELSR. Note that currently Trusted Event Route Control is not supported. */ 265 #ifndef BSP_TZ_CFG_TEVTRCR 266 #define BSP_TZ_CFG_TEVTRCR (0) 267 #endif 268 269 /* Security attribution register for ELCR, ELSEGR0, ELSEGR1 Security Attribution. */ 270 #ifndef BSP_TZ_CFG_ELCSARA 271 #define BSP_TZ_CFG_ELCSARA (0x00000007U) 272 #endif 273 274 /* Set DTCSTSAR if the Secure program uses the DTC. */ 275 #if RA_NOT_DEFINED == RA_NOT_DEFINED 276 #define BSP_TZ_CFG_DTC_USED (0U) 277 #else 278 #define BSP_TZ_CFG_DTC_USED (1U) 279 #endif 280 281 /* Security attribution of FLWT and FCKMHZ registers. */ 282 #ifndef BSP_TZ_CFG_FSAR 283 /* If the CGC registers are only accessible in Secure mode, than there is no 284 * reason for nonsecure applications to access FLWT and FCKMHZ. */ 285 #define BSP_TZ_CFG_FSAR (\ 286 ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 0) : 0U) | /* FLWTSA */\ 287 ((RA_NOT_DEFINED) > 0 ? 0U: (1U << 1)) | /* FCACHESA */\ 288 ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 8) : 0U) | /* FCKMHZSA */ \ 289 ((RA_NOT_DEFINED) > 0 ? 0U : (1U << 9U)) | /* FACICMISA */\ 290 ((RA_NOT_DEFINED) > 0 ? 0U: (1U << 10U)) /* FACICMRSA */) 291 #endif 292 293 /* Security attribution for SRAM registers. */ 294 #ifndef BSP_TZ_CFG_SRAMSAR 295 /* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access 296 * SRAM0WTEN and therefore there is no reason to access PRCR2. */ 297 #define BSP_TZ_CFG_SRAMSAR (\ 298 ((1U) << 0U) | /* SRAMSA0 */\ 299 ((1U) << 1U) | /* SRAMSA1 */\ 300 ((1U) << 7U) | /* STBRAMSA */\ 301 ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 8U) : 0U) /* SRAMWTSA */) 302 #endif 303 304 /* Security attribution for the DMAC Bus Master MPU settings. */ 305 #ifndef BSP_TZ_CFG_MMPUSARA 306 /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ 307 #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_DMACCHSAR) 308 #endif 309 310 /* Security Attribution Register A for BUS Control registers. */ 311 #ifndef BSP_TZ_CFG_BUSSARA 312 #define BSP_TZ_CFG_BUSSARA (1U) 313 #endif 314 /* Security Attribution Register B for BUS Control registers. */ 315 #ifndef BSP_TZ_CFG_BUSSARB 316 #define BSP_TZ_CFG_BUSSARB (1U) 317 #endif 318 /* Security Attribution Register C for BUS Control registers. */ 319 #ifndef BSP_TZ_CFG_BUSSARC 320 #define BSP_TZ_CFG_BUSSARC (1U) 321 #endif 322 323 /* Enable Uninitialized Non-Secure Application Fallback. */ 324 #ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK 325 #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) 326 #endif 327 328 #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) 329 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) 330 #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) 331 #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) 332 #define OFS_SEQ5 (1 << 28) | (1 << 30) 333 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) 334 335 #define BSP_CFG_ROM_REG_OFS2 ((1 << 0) | 0xFFFFFFFEU) 336 337 /* Option Function Select Register 1 Security Attribution */ 338 #ifndef BSP_CFG_ROM_REG_OFS1_SEL 339 #if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) 340 #define BSP_CFG_ROM_REG_OFS1_SEL (0x00000000U | ((0U << 0U)) | ((0U << 3U)) | ((0U << 5U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0xF00U : 0U) | ((0U << 24U)) | ((0U << 25U))) 341 #else 342 #define BSP_CFG_ROM_REG_OFS1_SEL (0x00000000U) 343 #endif 344 #endif 345 #define BSP_CFG_ROM_REG_OFS1_INITECCEN (0 << 25) 346 #define BSP_CFG_ROM_REG_OFS1 (0xFCFFFED0 | (1 << 3) | (7) | (1 << 5) | (1 << 8) | (1 << 24) | (BSP_CFG_ROM_REG_OFS1_INITECCEN)) 347 348 /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ 349 #define BSP_PRV_IELS_ENUM(vector) CONCAT(ELC_, vector) 350 351 /* Dual Mode Select Register */ 352 #ifndef BSP_CFG_ROM_REG_DUALSEL 353 #if CONFIG_DUAL_BANK_MODE 354 #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x0U)) 355 #else 356 #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) 357 #endif 358 #endif 359 360 /* Block Protection Register 0 */ 361 #ifndef BSP_CFG_ROM_REG_BPS0 362 #define BSP_CFG_ROM_REG_BPS0 (~(0U)) 363 #endif 364 /* Block Protection Register 1 */ 365 #ifndef BSP_CFG_ROM_REG_BPS1 366 #define BSP_CFG_ROM_REG_BPS1 (~(0U)) 367 #endif 368 /* Block Protection Register 2 */ 369 #ifndef BSP_CFG_ROM_REG_BPS2 370 #define BSP_CFG_ROM_REG_BPS2 (~(0U)) 371 #endif 372 /* Block Protection Register 3 */ 373 #ifndef BSP_CFG_ROM_REG_BPS3 374 #define BSP_CFG_ROM_REG_BPS3 (~(0U)) 375 #endif 376 /* Permanent Block Protection Register 0 */ 377 #ifndef BSP_CFG_ROM_REG_PBPS0 378 #define BSP_CFG_ROM_REG_PBPS0 (~(0U)) 379 #endif 380 /* Permanent Block Protection Register 1 */ 381 #ifndef BSP_CFG_ROM_REG_PBPS1 382 #define BSP_CFG_ROM_REG_PBPS1 (~(0U)) 383 #endif 384 /* Permanent Block Protection Register 2 */ 385 #ifndef BSP_CFG_ROM_REG_PBPS2 386 #define BSP_CFG_ROM_REG_PBPS2 (~(0U)) 387 #endif 388 /* Permanent Block Protection Register 3 */ 389 #ifndef BSP_CFG_ROM_REG_PBPS3 390 #define BSP_CFG_ROM_REG_PBPS3 (~(0U)) 391 #endif 392 /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ 393 #ifndef BSP_CFG_ROM_REG_BPS_SEL0 394 #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) 395 #endif 396 /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ 397 #ifndef BSP_CFG_ROM_REG_BPS_SEL1 398 #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) 399 #endif 400 /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ 401 #ifndef BSP_CFG_ROM_REG_BPS_SEL2 402 #define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) 403 #endif 404 /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ 405 #ifndef BSP_CFG_ROM_REG_BPS_SEL3 406 #define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) 407 #endif 408 /* Security Attribution for Bank Select Register */ 409 #ifndef BSP_CFG_ROM_REG_BANKSEL_SEL 410 #define BSP_CFG_ROM_REG_BANKSEL_SEL (0xFFFFFFFFU) 411 #endif 412 #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT 413 #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) 414 #endif 415 416 /* FSBL Control Register 0 */ 417 #ifndef BSP_CFG_ROM_REG_FSBLCTRL0 418 #define BSP_CFG_ROM_REG_FSBLCTRL0 ( \ 419 (7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLEN_Pos) | \ 420 (7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPSW_Pos) | \ 421 (7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPDS_Pos) | \ 422 (7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLCLK_Pos) | \ 423 0xFFFFF000) 424 #endif 425 426 /* FSBL Control Register 1 */ 427 #ifndef BSP_CFG_ROM_REG_FSBLCTRL1 428 #define BSP_CFG_ROM_REG_FSBLCTRL1 ( \ 429 (3 << R_OFS_DATAFLASH_FSBLCTRL1_FSBLEXMD_Pos) | \ 430 0xFFFFFFFC) 431 #endif 432 433 /* FSBL Control Register 2 */ 434 #ifndef BSP_CFG_ROM_REG_FSBLCTRL2 435 #define BSP_CFG_ROM_REG_FSBLCTRL2 ( \ 436 (15 << R_OFS_DATAFLASH_FSBLCTRL2_PORTPN_Pos) | \ 437 (0x1F << R_OFS_DATAFLASH_FSBLCTRL2_PORTGN_Pos) | \ 438 0xFFFFFE00) 439 #endif 440 441 /* Start Address of Code Certificate Register 0 */ 442 #ifndef BSP_CFG_ROM_REG_SACC0 443 #define BSP_CFG_ROM_REG_SACC0 (0xFFFFFFFF) 444 #endif 445 446 /* Start Address of Code Certificate Register 1 */ 447 #ifndef BSP_CFG_ROM_REG_SACC1 448 #define BSP_CFG_ROM_REG_SACC1 (0xFFFFFFFF) 449 #endif 450 451 /* Start Address of Measurement Report Register */ 452 #ifndef BSP_CFG_ROM_REG_SAMR 453 #define BSP_CFG_ROM_REG_SAMR (0xFFFFFFFF) 454 #endif 455 456 /* Hash of OEM_ROOT_PK Register */ 457 #ifndef BSP_CFG_ROM_REG_HOEMRTPK 458 #define BSP_CFG_ROM_REG_HOEMRTPK (RA_NOT_DEFINED) 459 #endif 460 461 /* Configuration Data 0 Lock Bit Register 0 */ 462 #ifndef BSP_CFG_ROM_REG_CFGD0LOCK0 463 #define BSP_CFG_ROM_REG_CFGD0LOCK0 (RA_NOT_DEFINED) 464 #endif 465 466 /* Configuration Data 0 Lock Bit Register 1 */ 467 #ifndef BSP_CFG_ROM_REG_CFGD0LOCK1 468 #define BSP_CFG_ROM_REG_CFGD0LOCK1 (RA_NOT_DEFINED) 469 #endif 470 471 /* Configuration Data 1 Lock Bit Register 0 */ 472 #ifndef BSP_CFG_ROM_REG_CFGD1LOCK0 473 #define BSP_CFG_ROM_REG_CFGD1LOCK0 (RA_NOT_DEFINED) 474 #endif 475 476 /* Configuration Data 1 Lock Bit Register 1 */ 477 #ifndef BSP_CFG_ROM_REG_CFGD1LOCK1 478 #define BSP_CFG_ROM_REG_CFGD1LOCK1 (RA_NOT_DEFINED) 479 #endif 480 481 /* Configuration Data 2 Lock Bit Register */ 482 #ifndef BSP_CFG_ROM_REG_CFGD2LOCK 483 #define BSP_CFG_ROM_REG_CFGD2LOCK (RA_NOT_DEFINED) 484 #endif 485 486 /* Anti-Rollback Counter Lock Setting Register */ 487 #ifndef BSP_CFG_ROM_REG_ARCLS 488 #define BSP_CFG_ROM_REG_ARCLS ( \ 489 (RA_NOT_DEFINED << R_OFS_DATAFLASH_ARCLS_ARCS_LK_Pos) | \ 490 (RA_NOT_DEFINED << R_OFS_DATAFLASH_ARCLS_ARCNS_LK_Pos) | \ 491 (RA_NOT_DEFINED << R_OFS_DATAFLASH_ARCLS_ARCBL_LK_Pos) | \ 492 0xFFC0) 493 #endif 494 495 /* Anti-Rollback Counter Configuration Setting for Non-secure Application Register */ 496 #ifndef BSP_CFG_ROM_REG_ARCCS 497 #define BSP_CFG_ROM_REG_ARCCS (RA_NOT_DEFINED | 0xFFFC) 498 #endif 499 500 /* Anti-Rollback Counter for Secure Application 0 Register */ 501 #ifndef BSP_CFG_ROM_REG_ARC_SEC0 502 #define BSP_CFG_ROM_REG_ARC_SEC0 (0U) 503 #endif 504 505 /* Anti-Rollback Counter for Secure Application 1 Register */ 506 #ifndef BSP_CFG_ROM_REG_ARC_SEC1 507 #define BSP_CFG_ROM_REG_ARC_SEC1 (0U) 508 #endif 509 510 /* Anti-Rollback Counter for Non-secure Application 0 Register */ 511 #ifndef BSP_CFG_ROM_REG_ARC_NSEC0 512 #define BSP_CFG_ROM_REG_ARC_NSEC0 (0U) 513 #endif 514 515 /* Anti-Rollback Counter for Non-secure Application 1 Register */ 516 #ifndef BSP_CFG_ROM_REG_ARC_NSEC1 517 #define BSP_CFG_ROM_REG_ARC_NSEC1 (0U) 518 #endif 519 520 /* Anti-Rollback Counter for Non-secure Application 2 Register */ 521 #ifndef BSP_CFG_ROM_REG_ARC_NSEC2 522 #define BSP_CFG_ROM_REG_ARC_NSEC2 (0U) 523 #endif 524 525 /* Anti-Rollback Counter for Non-secure Application 3 Register */ 526 #ifndef BSP_CFG_ROM_REG_ARC_NSEC3 527 #define BSP_CFG_ROM_REG_ARC_NSEC3 (0U) 528 #endif 529 530 /* Anti-Rollback Counter for Non-secure Application 4 Register */ 531 #ifndef BSP_CFG_ROM_REG_ARC_NSEC4 532 #define BSP_CFG_ROM_REG_ARC_NSEC4 (0U) 533 #endif 534 535 /* Anti-Rollback Counter for Non-secure Application 5 Register */ 536 #ifndef BSP_CFG_ROM_REG_ARC_NSEC5 537 #define BSP_CFG_ROM_REG_ARC_NSEC5 (0U) 538 #endif 539 540 /* Anti-Rollback Counter for Non-secure Application 6 Register */ 541 #ifndef BSP_CFG_ROM_REG_ARC_NSEC6 542 #define BSP_CFG_ROM_REG_ARC_NSEC6 (0U) 543 #endif 544 545 /* Anti-Rollback Counter for Non-secure Application 7 Register */ 546 #ifndef BSP_CFG_ROM_REG_ARC_NSEC7 547 #define BSP_CFG_ROM_REG_ARC_NSEC7 (0U) 548 #endif 549 550 /* Anti-Rollback Counter for OEMBL 0 Register */ 551 #ifndef BSP_CFG_ROM_REG_ARC_OEMBL0 552 #define BSP_CFG_ROM_REG_ARC_OEMBL0 (0U) 553 #endif 554 555 /* Anti-Rollback Counter for OEMBL 1 Register */ 556 #ifndef BSP_CFG_ROM_REG_ARC_OEMBL1 557 #define BSP_CFG_ROM_REG_ARC_OEMBL1 (0U) 558 #endif 559 560 #ifndef BSP_CFG_DCACHE_ENABLED 561 #define BSP_CFG_DCACHE_ENABLED (CONFIG_DCACHE) 562 #endif 563 564 /* SDRAM controller configuration */ 565 #if DT_NODE_HAS_STATUS_OKAY(DT_INST(0, renesas_ra_sdram)) 566 #define BSP_CFG_SDRAM_TRAS \ 567 DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 0) 568 #define BSP_CFG_SDRAM_TRCD \ 569 DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 1) 570 #define BSP_CFG_SDRAM_TRP \ 571 DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 2) 572 #define BSP_CFG_SDRAM_TWR \ 573 DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 3) 574 #define BSP_CFG_SDRAM_TCL \ 575 DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 4) 576 #define BSP_CFG_SDRAM_TRFC \ 577 DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 5) 578 #define BSP_CFG_SDRAM_TREFW \ 579 DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 6) 580 #define BSP_CFG_SDRAM_INIT_ARFI DT_PROP(DT_INST(0, renesas_ra_sdram), auto_refresh_interval) 581 #define BSP_CFG_SDRAM_INIT_ARFC DT_PROP(DT_INST(0, renesas_ra_sdram), auto_refresh_count) 582 #define BSP_CFG_SDRAM_INIT_PRC DT_PROP(DT_INST(0, renesas_ra_sdram), precharge_cycle_count) 583 #define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), multiplex_addr_shift) 584 #define BSP_CFG_SDRAM_ENDIAN_MODE DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), edian_mode) 585 #define BSP_CFG_SDRAM_ACCESS_MODE DT_PROP(DT_INST(0, renesas_ra_sdram), continuous_access) 586 #define BSP_CFG_SDRAM_BUS_WIDTH DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), bus_width) 587 #else 588 #define BSP_CFG_SDRAM_TRAS (0) 589 #define BSP_CFG_SDRAM_TRCD (0) 590 #define BSP_CFG_SDRAM_TRP (0) 591 #define BSP_CFG_SDRAM_TWR (0) 592 #define BSP_CFG_SDRAM_TCL (0) 593 #define BSP_CFG_SDRAM_TRFC (0) 594 #define BSP_CFG_SDRAM_TREFW (0) 595 #define BSP_CFG_SDRAM_INIT_ARFI (0) 596 #define BSP_CFG_SDRAM_INIT_ARFC (0) 597 #define BSP_CFG_SDRAM_INIT_PRC (0) 598 #define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT (0) 599 #define BSP_CFG_SDRAM_ENDIAN_MODE (0) 600 #define BSP_CFG_SDRAM_ACCESS_MODE (0) 601 #define BSP_CFG_SDRAM_BUS_WIDTH (0) 602 #endif /* DT_NODE_HAS_STATUS_OKAY(DT_INST(0, renesas_ra_sdram)) */ 603 604 #endif /* BSP_MCU_FAMILY_CFG_H_ */ 605
