1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef BSP_MCU_FAMILY_CFG_H_ 7 #define BSP_MCU_FAMILY_CFG_H_ 8 #include "bsp_mcu_device_pn_cfg.h" 9 #include "bsp_mcu_device_cfg.h" 10 #include "bsp_override.h" 11 #include "bsp_mcu_info.h" 12 #include "bsp_clock_cfg.h" 13 #define BSP_MCU_GROUP_RA8D1 (1) 14 #define BSP_LOCO_HZ (DT_PROP_OR(DT_NODELABEL(loco), clock_frequency, 0)) 15 #define BSP_MOCO_HZ (DT_PROP_OR(DT_NODELABEL(moco), clock_frequency, 0)) 16 #define BSP_SUB_CLOCK_HZ (0) 17 #if BSP_CFG_HOCO_FREQUENCY == 0 18 #define BSP_HOCO_HZ (16000000) 19 #elif BSP_CFG_HOCO_FREQUENCY == 1 20 #define BSP_HOCO_HZ (18000000) 21 #elif BSP_CFG_HOCO_FREQUENCY == 2 22 #define BSP_HOCO_HZ (20000000) 23 #elif BSP_CFG_HOCO_FREQUENCY == 4 24 #define BSP_HOCO_HZ (32000000) 25 #elif BSP_CFG_HOCO_FREQUENCY == 7 26 #define BSP_HOCO_HZ (48000000) 27 #else 28 #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" 29 #endif 30 31 #define BSP_CFG_FLL_ENABLE (0) 32 33 #define BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE (1) 34 #define BSP_CFG_SLEEP_MODE_DELAY_ENABLE (1) 35 #define BSP_CFG_MSTP_CHANGE_DELAY_ENABLE (1) 36 #define BSP_CFG_RTOS_IDLE_SLEEP (0) 37 #define BSP_CFG_CLOCK_SETTLING_DELAY_US (150) 38 39 #if defined(BSP_PACKAGE_LQFP) && (BSP_PACKAGE_PINS == 100) 40 #define BSP_MAX_CLOCK_CHANGE_THRESHOLD (180000000U) 41 #elif defined(BSP_PACKAGE_LQFP) 42 #define BSP_MAX_CLOCK_CHANGE_THRESHOLD (200000000U) 43 #else 44 #define BSP_MAX_CLOCK_CHANGE_THRESHOLD (240000000U) 45 #endif 46 47 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) 48 #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) 49 #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) 50 51 #if defined(_RA_TZ_SECURE) 52 #define BSP_TZ_SECURE_BUILD (1) 53 #define BSP_TZ_NONSECURE_BUILD (0) 54 #elif defined(_RA_TZ_NONSECURE) 55 #define BSP_TZ_SECURE_BUILD (0) 56 #define BSP_TZ_NONSECURE_BUILD (1) 57 #else 58 #define BSP_TZ_SECURE_BUILD (0) 59 #define BSP_TZ_NONSECURE_BUILD (0) 60 #endif 61 62 /* TrustZone Settings */ 63 #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) 64 #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) 65 #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) 66 67 /* CMSIS TrustZone Settings */ 68 #define SCB_CSR_AIRCR_INIT (1) 69 #define SCB_AIRCR_BFHFNMINS_VAL (0) 70 #define SCB_AIRCR_SYSRESETREQS_VAL (1) 71 #define SCB_AIRCR_PRIS_VAL (0) 72 #define TZ_FPU_NS_USAGE (1) 73 #ifndef SCB_NSACR_CP10_11_VAL 74 #define SCB_NSACR_CP10_11_VAL (3U) 75 #endif 76 77 #ifndef FPU_FPCCR_TS_VAL 78 #define FPU_FPCCR_TS_VAL (1U) 79 #endif 80 #define FPU_FPCCR_CLRONRETS_VAL (1) 81 82 #ifndef FPU_FPCCR_CLRONRET_VAL 83 #define FPU_FPCCR_CLRONRET_VAL (1) 84 #endif 85 86 /* Type 1 Peripheral Security Attribution */ 87 88 /* Peripheral Security Attribution Register (PSAR) Settings */ 89 #ifndef BSP_TZ_CFG_PSARB 90 #define BSP_TZ_CFG_PSARB \ 91 ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4) /* I3C */ | \ 92 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ 93 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ 94 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ 95 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* USBHS */ | (1 << 15) /* ETHERC/EDMAC */ | \ 96 (1 << 16) /* OSPI */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ 97 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ 98 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ 99 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \ 100 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ 101 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \ 102 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ 103 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */) 104 #endif 105 #ifndef BSP_TZ_CFG_PSARC 106 #define BSP_TZ_CFG_PSARC \ 107 ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ 108 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ 109 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7) /* SSIE1 */ | \ 110 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ 111 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* SDHI1 */ | \ 112 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \ 113 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ 114 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* GLCDC/MIPI-DSI/DRW */ | \ 115 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* CEU */ | \ 116 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* CANFD1 */ | \ 117 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* CANFD0 */ | \ 118 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* RSIP7 */) 119 #endif 120 #ifndef BSP_TZ_CFG_PSARD 121 #define BSP_TZ_CFG_PSARD \ 122 ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4) /* AGT1 */ | \ 123 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5) /* AGT0 */ | \ 124 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ 125 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ 126 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ 127 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ 128 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC121 */ | \ 129 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC120 */ | \ 130 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC120 */ | \ 131 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ 132 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* ACMPHS1 */ | \ 133 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* ACMPHS0 */) 134 #endif 135 #ifndef BSP_TZ_CFG_PSARE 136 #define BSP_TZ_CFG_PSARE \ 137 ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* WDT */ | \ 138 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* IWDT */ | \ 139 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* RTC */ | \ 140 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* ULPT1 */ | \ 141 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* ULPT0 */ | \ 142 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* GPT13 */ | \ 143 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* GPT12 */ | \ 144 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* GPT11 */ | \ 145 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 21) /* GPT10 */ | \ 146 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ 147 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \ 148 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ 149 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ 150 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ 151 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ 152 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ 153 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ 154 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ 155 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */) 156 #endif 157 #ifndef BSP_TZ_CFG_MSSAR 158 #define BSP_TZ_CFG_MSSAR \ 159 ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* DTC_DMAC */ | \ 160 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* ELC */) 161 #endif 162 163 /* Type 2 Peripheral Security Attribution */ 164 165 /* Security attribution for RSTSRn registers. */ 166 #ifndef BSP_TZ_CFG_RSTSAR 167 #define BSP_TZ_CFG_RSTSAR (0x0000000FU) 168 #endif 169 170 /* Security attribution for registers of LVD channels. */ 171 #ifndef BSP_TZ_CFG_LVDSAR 172 /* The LVD driver needs to access both channels. This means that the security attribution for both 173 * channels must be the same. 174 */ 175 #if (RA_NOT_DEFINED > 0) || (RA_NOT_DEFINED > 0) 176 #define BSP_TZ_CFG_LVDSAR (0U) 177 #else 178 #define BSP_TZ_CFG_LVDSAR (3U) 179 #endif 180 #endif 181 182 /* Security attribution for LPM registers. 183 * - OPCCR based on clock security. 184 * - Set remaining registers based on LPM security. 185 */ 186 #ifndef BSP_TZ_CFG_LPMSAR 187 #define BSP_TZ_CFG_LPMSAR \ 188 ((RA_NOT_DEFINED > 0) ? BSP_CFG_CLOCKS_SECURE == 0 \ 189 : (0x002E0106U | (BSP_CFG_CLOCKS_SECURE == 0))) 190 #endif 191 /* Deep Standby Interrupt Factor Security Attribution Register. */ 192 #ifndef BSP_TZ_CFG_DPFSAR 193 #define BSP_TZ_CFG_DPFSAR ((1 > 0) ? 0U : 0xAF1FFFFFU) 194 #endif 195 /* RAM Standby Control Security Attribution Register. */ 196 #ifndef BSP_TZ_CFG_RSCSAR 197 #define BSP_TZ_CFG_RSCSAR ((1 > 0) ? 0U : 0x00037FFFU) 198 #endif 199 /* Power Gating Control Security Attribution Register */ 200 #ifndef BSP_TZ_CFG_PGCSAR 201 #define BSP_TZ_CFG_PGCSAR 0 202 #endif 203 204 /* Security attribution for CGC registers. */ 205 #ifndef BSP_TZ_CFG_CGFSAR 206 #if BSP_CFG_CLOCKS_SECURE 207 /* Protect all CGC registers from Non-secure write access. */ 208 #define BSP_TZ_CFG_CGFSAR (0U) 209 #else 210 /* Allow Secure and Non-secure write access. */ 211 #define BSP_TZ_CFG_CGFSAR (0x047F3BFDU) 212 #endif 213 #endif 214 215 /* Security attribution for Battery Backup registers. */ 216 #ifndef BSP_TZ_CFG_BBFSAR 217 #define BSP_TZ_CFG_BBFSAR (0x0000001FU) 218 #endif 219 220 /* Security attribution for registers for IRQ channels. */ 221 #ifndef BSP_TZ_CFG_ICUSARA 222 #define BSP_TZ_CFG_ICUSARA \ 223 ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ 224 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ 225 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ 226 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ 227 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ 228 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ 229 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ 230 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ 231 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ 232 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ 233 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ 234 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ 235 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ 236 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ 237 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ 238 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */) 239 #endif 240 241 /* Security attribution for NMI registers. */ 242 #ifndef BSP_TZ_CFG_ICUSARB 243 #define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ 244 #endif 245 246 /* Security attribution for registers for DMAC channels */ 247 #ifndef BSP_TZ_CFG_DMACCHSAR 248 #define BSP_TZ_CFG_DMACCHSAR \ 249 ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ 250 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ 251 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ 252 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ 253 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ 254 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ 255 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ 256 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */) 257 #endif 258 259 /* Security attribution registers for WUPEN0. */ 260 #ifndef BSP_TZ_CFG_ICUSARE 261 #define BSP_TZ_CFG_ICUSARE ((1 > 0) ? 0U : 0xFF1D0000U) 262 #endif 263 264 /* Security attribution registers for WUPEN1. */ 265 #ifndef BSP_TZ_CFG_ICUSARF 266 #define BSP_TZ_CFG_ICUSARF ((1 > 0) ? 0U : 0x00007F08U) 267 #endif 268 269 /* Trusted Event Route Control Register for IELSR, DMAC.DELSR and ELC.ELSR. Note that currently 270 * Trusted Event Route Control is not supported. 271 */ 272 #ifndef BSP_TZ_CFG_TEVTRCR 273 #define BSP_TZ_CFG_TEVTRCR (0) 274 #endif 275 276 /* Security attribution register for ELCR, ELSEGR0, ELSEGR1 Security Attribution. */ 277 #ifndef BSP_TZ_CFG_ELCSARA 278 #define BSP_TZ_CFG_ELCSARA (0x00000007U) 279 #endif 280 281 /* Set DTCSTSAR if the Secure program uses the DTC. */ 282 #if RA_NOT_DEFINED == RA_NOT_DEFINED 283 #define BSP_TZ_CFG_DTC_USED (0U) 284 #else 285 #define BSP_TZ_CFG_DTC_USED (1U) 286 #endif 287 288 /* Security attribution of FLWT and FCKMHZ registers. */ 289 #ifndef BSP_TZ_CFG_FSAR 290 /* If the CGC registers are only accessible in Secure mode, than there is no 291 * reason for nonsecure applications to access FLWT and FCKMHZ. 292 */ 293 #define BSP_TZ_CFG_FSAR \ 294 (((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 0) : 0U) | /* FLWTSA */ \ 295 ((RA_NOT_DEFINED) > 0 ? 0U : (1U << 1)) | /* FCACHESA */ \ 296 ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 8) : 0U) | /* FCKMHZSA */ \ 297 ((RA_NOT_DEFINED) > 0 ? 0U : (1U << 9U)) | /* FACICMISA */ \ 298 ((RA_NOT_DEFINED) > 0 ? 0U : (1U << 10U)) /* FACICMRSA */) 299 #endif 300 301 /* Security attribution for SRAM registers. */ 302 #ifndef BSP_TZ_CFG_SRAMSAR 303 /* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure 304 * applications to access SRAM0WTEN and therefore there is no reason to access PRCR2. 305 */ 306 #define BSP_TZ_CFG_SRAMSAR \ 307 (((1U) << 0U) | /* SRAMSA0 */ \ 308 ((1U) << 1U) | /* SRAMSA1 */ \ 309 ((1U) << 7U) | /* STBRAMSA */ \ 310 ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 8U) : 0U) /* SRAMWTSA */) 311 #endif 312 313 /* Security attribution for the DMAC Bus Master MPU settings. */ 314 #ifndef BSP_TZ_CFG_MMPUSARA 315 /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ 316 #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_DMACCHSAR) 317 #endif 318 319 /* Security Attribution Register A for BUS Control registers. */ 320 #ifndef BSP_TZ_CFG_BUSSARA 321 #define BSP_TZ_CFG_BUSSARA (1U) 322 #endif 323 /* Security Attribution Register B for BUS Control registers. */ 324 #ifndef BSP_TZ_CFG_BUSSARB 325 #define BSP_TZ_CFG_BUSSARB (1U) 326 #endif 327 /* Security Attribution Register C for BUS Control registers. */ 328 #ifndef BSP_TZ_CFG_BUSSARC 329 #define BSP_TZ_CFG_BUSSARC (1U) 330 #endif 331 332 /* Enable Uninitialized Non-Secure Application Fallback. */ 333 #ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK 334 #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) 335 #endif 336 337 #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) 338 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) 339 #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) 340 #define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26) 341 #define OFS_SEQ5 (1 << 28) | (1 << 30) 342 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) 343 344 #define BSP_CFG_ROM_REG_OFS2 ((1 << 0) | 0xFFFFFFFEU) 345 346 /* Option Function Select Register 1 Security Attribution */ 347 #ifndef BSP_CFG_ROM_REG_OFS1_SEL 348 #if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) 349 #define BSP_CFG_ROM_REG_OFS1_SEL \ 350 (0x00000000U | ((0U << 0U)) | ((0U << 3U)) | ((0U << 5U)) | \ 351 ((BSP_CFG_CLOCKS_SECURE == 0) ? 0xF00U : 0U) | ((0U << 24U)) | ((0U << 25U))) 352 #else 353 #define BSP_CFG_ROM_REG_OFS1_SEL (0x00000000U) 354 #endif 355 #endif 356 #define BSP_CFG_ROM_REG_OFS1_INITECCEN (0 << 25) 357 #define BSP_CFG_ROM_REG_OFS1 \ 358 (0xFCFFFED0 | (1 << 3) | (7) | (1 << 5) | (1 << 8) | (1 << 24) | \ 359 (BSP_CFG_ROM_REG_OFS1_INITECCEN)) 360 361 /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. 362 */ 363 #define BSP_PRV_IELS_ENUM(vector) CONCAT(ELC_, vector) 364 365 /* Dual Mode Select Register */ 366 #ifndef BSP_CFG_ROM_REG_DUALSEL 367 #if CONFIG_DUAL_BANK_MODE 368 #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x0U)) 369 #else 370 #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) 371 #endif 372 #endif 373 374 /* Block Protection Register 0 */ 375 #ifndef BSP_CFG_ROM_REG_BPS0 376 #define BSP_CFG_ROM_REG_BPS0 (~(0U)) 377 #endif 378 /* Block Protection Register 1 */ 379 #ifndef BSP_CFG_ROM_REG_BPS1 380 #define BSP_CFG_ROM_REG_BPS1 (~(0U)) 381 #endif 382 /* Block Protection Register 2 */ 383 #ifndef BSP_CFG_ROM_REG_BPS2 384 #define BSP_CFG_ROM_REG_BPS2 (~(0U)) 385 #endif 386 /* Block Protection Register 3 */ 387 #ifndef BSP_CFG_ROM_REG_BPS3 388 #define BSP_CFG_ROM_REG_BPS3 (~(0U)) 389 #endif 390 /* Permanent Block Protection Register 0 */ 391 #ifndef BSP_CFG_ROM_REG_PBPS0 392 #define BSP_CFG_ROM_REG_PBPS0 (~(0U)) 393 #endif 394 /* Permanent Block Protection Register 1 */ 395 #ifndef BSP_CFG_ROM_REG_PBPS1 396 #define BSP_CFG_ROM_REG_PBPS1 (~(0U)) 397 #endif 398 /* Permanent Block Protection Register 2 */ 399 #ifndef BSP_CFG_ROM_REG_PBPS2 400 #define BSP_CFG_ROM_REG_PBPS2 (~(0U)) 401 #endif 402 /* Permanent Block Protection Register 3 */ 403 #ifndef BSP_CFG_ROM_REG_PBPS3 404 #define BSP_CFG_ROM_REG_PBPS3 (~(0U)) 405 #endif 406 /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in 407 * the secure application, then mark them as secure) 408 */ 409 #ifndef BSP_CFG_ROM_REG_BPS_SEL0 410 #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) 411 #endif 412 /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in 413 * the secure application, then mark them as secure) 414 */ 415 #ifndef BSP_CFG_ROM_REG_BPS_SEL1 416 #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) 417 #endif 418 /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in 419 * the secure application, then mark them as secure) 420 */ 421 #ifndef BSP_CFG_ROM_REG_BPS_SEL2 422 #define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) 423 #endif 424 /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in 425 * the secure application, then mark them as secure) 426 */ 427 #ifndef BSP_CFG_ROM_REG_BPS_SEL3 428 #define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) 429 #endif 430 /* Security Attribution for Bank Select Register */ 431 #ifndef BSP_CFG_ROM_REG_BANKSEL_SEL 432 #define BSP_CFG_ROM_REG_BANKSEL_SEL (0xFFFFFFFFU) 433 #endif 434 #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT 435 #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) 436 #endif 437 438 /* FSBL Control Register 0 */ 439 #ifndef BSP_CFG_ROM_REG_FSBLCTRL0 440 #define BSP_CFG_ROM_REG_FSBLCTRL0 \ 441 ((7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLEN_Pos) | \ 442 (7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPSW_Pos) | \ 443 (7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPDS_Pos) | \ 444 (7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLCLK_Pos) | 0xFFFFF000) 445 #endif 446 447 /* FSBL Control Register 1 */ 448 #ifndef BSP_CFG_ROM_REG_FSBLCTRL1 449 #define BSP_CFG_ROM_REG_FSBLCTRL1 ((3 << R_OFS_DATAFLASH_FSBLCTRL1_FSBLEXMD_Pos) | 0xFFFFFFFC) 450 #endif 451 452 /* FSBL Control Register 2 */ 453 #ifndef BSP_CFG_ROM_REG_FSBLCTRL2 454 #define BSP_CFG_ROM_REG_FSBLCTRL2 \ 455 ((15 << R_OFS_DATAFLASH_FSBLCTRL2_PORTPN_Pos) | \ 456 (0x1F << R_OFS_DATAFLASH_FSBLCTRL2_PORTGN_Pos) | 0xFFFFFE00) 457 #endif 458 459 /* Start Address of Code Certificate Register 0 */ 460 #ifndef BSP_CFG_ROM_REG_SACC0 461 #define BSP_CFG_ROM_REG_SACC0 (0xFFFFFFFF) 462 #endif 463 464 /* Start Address of Code Certificate Register 1 */ 465 #ifndef BSP_CFG_ROM_REG_SACC1 466 #define BSP_CFG_ROM_REG_SACC1 (0xFFFFFFFF) 467 #endif 468 469 /* Start Address of Measurement Report Register */ 470 #ifndef BSP_CFG_ROM_REG_SAMR 471 #define BSP_CFG_ROM_REG_SAMR (0xFFFFFFFF) 472 #endif 473 474 /* Hash of OEM_ROOT_PK Register */ 475 #ifndef BSP_CFG_ROM_REG_HOEMRTPK 476 #define BSP_CFG_ROM_REG_HOEMRTPK (RA_NOT_DEFINED) 477 #endif 478 479 /* Configuration Data 0 Lock Bit Register 0 */ 480 #ifndef BSP_CFG_ROM_REG_CFGD0LOCK0 481 #define BSP_CFG_ROM_REG_CFGD0LOCK0 (RA_NOT_DEFINED) 482 #endif 483 484 /* Configuration Data 0 Lock Bit Register 1 */ 485 #ifndef BSP_CFG_ROM_REG_CFGD0LOCK1 486 #define BSP_CFG_ROM_REG_CFGD0LOCK1 (RA_NOT_DEFINED) 487 #endif 488 489 /* Configuration Data 1 Lock Bit Register 0 */ 490 #ifndef BSP_CFG_ROM_REG_CFGD1LOCK0 491 #define BSP_CFG_ROM_REG_CFGD1LOCK0 (RA_NOT_DEFINED) 492 #endif 493 494 /* Configuration Data 1 Lock Bit Register 1 */ 495 #ifndef BSP_CFG_ROM_REG_CFGD1LOCK1 496 #define BSP_CFG_ROM_REG_CFGD1LOCK1 (RA_NOT_DEFINED) 497 #endif 498 499 /* Configuration Data 2 Lock Bit Register */ 500 #ifndef BSP_CFG_ROM_REG_CFGD2LOCK 501 #define BSP_CFG_ROM_REG_CFGD2LOCK (RA_NOT_DEFINED) 502 #endif 503 504 /* Anti-Rollback Counter Lock Setting Register */ 505 #ifndef BSP_CFG_ROM_REG_ARCLS 506 #define BSP_CFG_ROM_REG_ARCLS \ 507 ((RA_NOT_DEFINED << R_OFS_DATAFLASH_ARCLS_ARCS_LK_Pos) | \ 508 (RA_NOT_DEFINED << R_OFS_DATAFLASH_ARCLS_ARCNS_LK_Pos) | \ 509 (RA_NOT_DEFINED << R_OFS_DATAFLASH_ARCLS_ARCBL_LK_Pos) | 0xFFC0) 510 #endif 511 512 /* Anti-Rollback Counter Configuration Setting for Non-secure Application Register */ 513 #ifndef BSP_CFG_ROM_REG_ARCCS 514 #define BSP_CFG_ROM_REG_ARCCS (RA_NOT_DEFINED | 0xFFFC) 515 #endif 516 517 /* Anti-Rollback Counter for Secure Application 0 Register */ 518 #ifndef BSP_CFG_ROM_REG_ARC_SEC0 519 #define BSP_CFG_ROM_REG_ARC_SEC0 (0U) 520 #endif 521 522 /* Anti-Rollback Counter for Secure Application 1 Register */ 523 #ifndef BSP_CFG_ROM_REG_ARC_SEC1 524 #define BSP_CFG_ROM_REG_ARC_SEC1 (0U) 525 #endif 526 527 /* Anti-Rollback Counter for Non-secure Application 0 Register */ 528 #ifndef BSP_CFG_ROM_REG_ARC_NSEC0 529 #define BSP_CFG_ROM_REG_ARC_NSEC0 (0U) 530 #endif 531 532 /* Anti-Rollback Counter for Non-secure Application 1 Register */ 533 #ifndef BSP_CFG_ROM_REG_ARC_NSEC1 534 #define BSP_CFG_ROM_REG_ARC_NSEC1 (0U) 535 #endif 536 537 /* Anti-Rollback Counter for Non-secure Application 2 Register */ 538 #ifndef BSP_CFG_ROM_REG_ARC_NSEC2 539 #define BSP_CFG_ROM_REG_ARC_NSEC2 (0U) 540 #endif 541 542 /* Anti-Rollback Counter for Non-secure Application 3 Register */ 543 #ifndef BSP_CFG_ROM_REG_ARC_NSEC3 544 #define BSP_CFG_ROM_REG_ARC_NSEC3 (0U) 545 #endif 546 547 /* Anti-Rollback Counter for Non-secure Application 4 Register */ 548 #ifndef BSP_CFG_ROM_REG_ARC_NSEC4 549 #define BSP_CFG_ROM_REG_ARC_NSEC4 (0U) 550 #endif 551 552 /* Anti-Rollback Counter for Non-secure Application 5 Register */ 553 #ifndef BSP_CFG_ROM_REG_ARC_NSEC5 554 #define BSP_CFG_ROM_REG_ARC_NSEC5 (0U) 555 #endif 556 557 /* Anti-Rollback Counter for Non-secure Application 6 Register */ 558 #ifndef BSP_CFG_ROM_REG_ARC_NSEC6 559 #define BSP_CFG_ROM_REG_ARC_NSEC6 (0U) 560 #endif 561 562 /* Anti-Rollback Counter for Non-secure Application 7 Register */ 563 #ifndef BSP_CFG_ROM_REG_ARC_NSEC7 564 #define BSP_CFG_ROM_REG_ARC_NSEC7 (0U) 565 #endif 566 567 /* Anti-Rollback Counter for OEMBL 0 Register */ 568 #ifndef BSP_CFG_ROM_REG_ARC_OEMBL0 569 #define BSP_CFG_ROM_REG_ARC_OEMBL0 (0U) 570 #endif 571 572 /* Anti-Rollback Counter for OEMBL 1 Register */ 573 #ifndef BSP_CFG_ROM_REG_ARC_OEMBL1 574 #define BSP_CFG_ROM_REG_ARC_OEMBL1 (0U) 575 #endif 576 577 #ifndef BSP_CFG_DCACHE_ENABLED 578 #define BSP_CFG_DCACHE_ENABLED (CONFIG_DCACHE) 579 #endif 580 581 /* SDRAM controller configuration */ 582 #if DT_NODE_HAS_STATUS_OKAY(DT_INST(0, renesas_ra_sdram)) 583 #define BSP_CFG_SDRAM_TRAS \ 584 DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 0) 585 #define BSP_CFG_SDRAM_TRCD \ 586 DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 1) 587 #define BSP_CFG_SDRAM_TRP \ 588 DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 2) 589 #define BSP_CFG_SDRAM_TWR \ 590 DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 3) 591 #define BSP_CFG_SDRAM_TCL \ 592 DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 4) 593 #define BSP_CFG_SDRAM_TRFC \ 594 DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 5) 595 #define BSP_CFG_SDRAM_TREFW \ 596 DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 6) 597 #define BSP_CFG_SDRAM_INIT_ARFI DT_PROP(DT_INST(0, renesas_ra_sdram), auto_refresh_interval) 598 #define BSP_CFG_SDRAM_INIT_ARFC DT_PROP(DT_INST(0, renesas_ra_sdram), auto_refresh_count) 599 #define BSP_CFG_SDRAM_INIT_PRC DT_PROP(DT_INST(0, renesas_ra_sdram), precharge_cycle_count) 600 #define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), multiplex_addr_shift) 601 #define BSP_CFG_SDRAM_ENDIAN_MODE DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), edian_mode) 602 #define BSP_CFG_SDRAM_ACCESS_MODE DT_PROP(DT_INST(0, renesas_ra_sdram), continuous_access) 603 #define BSP_CFG_SDRAM_BUS_WIDTH DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), bus_width) 604 #else 605 #define BSP_CFG_SDRAM_TRAS (0) 606 #define BSP_CFG_SDRAM_TRCD (0) 607 #define BSP_CFG_SDRAM_TRP (0) 608 #define BSP_CFG_SDRAM_TWR (0) 609 #define BSP_CFG_SDRAM_TCL (0) 610 #define BSP_CFG_SDRAM_TRFC (0) 611 #define BSP_CFG_SDRAM_TREFW (0) 612 #define BSP_CFG_SDRAM_INIT_ARFI (0) 613 #define BSP_CFG_SDRAM_INIT_ARFC (0) 614 #define BSP_CFG_SDRAM_INIT_PRC (0) 615 #define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT (0) 616 #define BSP_CFG_SDRAM_ENDIAN_MODE (0) 617 #define BSP_CFG_SDRAM_ACCESS_MODE (0) 618 #define BSP_CFG_SDRAM_BUS_WIDTH (0) 619 #endif /* DT_NODE_HAS_STATUS_OKAY(DT_INST(0, renesas_ra_sdram)) */ 620 621 #endif /* BSP_MCU_FAMILY_CFG_H_ */ 622
