1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef BSP_MCU_FAMILY_CFG_H_ 8 #define BSP_MCU_FAMILY_CFG_H_ 9 #include "bsp_mcu_device_pn_cfg.h" 10 #include "bsp_mcu_device_cfg.h" 11 #include "bsp_mcu_info.h" 12 #include "bsp_clock_cfg.h" 13 #define BSP_MCU_GROUP_RA6M5 (1) 14 #define BSP_LOCO_HZ (DT_PROP_OR(DT_NODELABEL(loco), clock_frequency, 0)) 15 #define BSP_MOCO_HZ (DT_PROP_OR(DT_NODELABEL(moco), clock_frequency, 0)) 16 #define BSP_SUB_CLOCK_HZ (DT_PROP_OR(DT_NODELABEL(subclk), clock_frequency, 0)) 17 #if BSP_CFG_HOCO_FREQUENCY == 0 18 #define BSP_HOCO_HZ (16000000) 19 #elif BSP_CFG_HOCO_FREQUENCY == 1 20 #define BSP_HOCO_HZ (18000000) 21 #elif BSP_CFG_HOCO_FREQUENCY == 2 22 #define BSP_HOCO_HZ (20000000) 23 #else 24 #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" 25 #endif 26 27 #define BSP_CFG_FLL_ENABLE (0) 28 29 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) 30 #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) 31 32 #if defined(_RA_TZ_SECURE) 33 #define BSP_TZ_SECURE_BUILD (1) 34 #define BSP_TZ_NONSECURE_BUILD (0) 35 #elif defined(_RA_TZ_NONSECURE) 36 #define BSP_TZ_SECURE_BUILD (0) 37 #define BSP_TZ_NONSECURE_BUILD (1) 38 #else 39 #define BSP_TZ_SECURE_BUILD (0) 40 #define BSP_TZ_NONSECURE_BUILD (0) 41 #endif 42 43 /* TrustZone Settings */ 44 #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) 45 #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) 46 #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) 47 48 /* CMSIS TrustZone Settings */ 49 #define SCB_CSR_AIRCR_INIT (1) 50 #define SCB_AIRCR_BFHFNMINS_VAL (0) 51 #define SCB_AIRCR_SYSRESETREQS_VAL (1) 52 #define SCB_AIRCR_PRIS_VAL (0) 53 #define TZ_FPU_NS_USAGE (1) 54 #ifndef SCB_NSACR_CP10_11_VAL 55 #define SCB_NSACR_CP10_11_VAL (3U) 56 #endif 57 58 #ifndef FPU_FPCCR_TS_VAL 59 #define FPU_FPCCR_TS_VAL (1U) 60 #endif 61 #define FPU_FPCCR_CLRONRETS_VAL (1) 62 63 #ifndef FPU_FPCCR_CLRONRET_VAL 64 #define FPU_FPCCR_CLRONRET_VAL (1) 65 #endif 66 67 /* The C-Cache line size that is configured during startup. */ 68 #ifndef BSP_CFG_C_CACHE_LINE_SIZE 69 #define BSP_CFG_C_CACHE_LINE_SIZE (1U) 70 #endif 71 72 /* Type 1 Peripheral Security Attribution */ 73 74 /* Peripheral Security Attribution Register (PSAR) Settings */ 75 #ifndef BSP_TZ_CFG_PSARB 76 #define BSP_TZ_CFG_PSARB \ 77 ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \ 78 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ 79 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ 80 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ 81 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ 82 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ 83 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ 84 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ 85 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \ 86 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ 87 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \ 88 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \ 89 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \ 90 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ 91 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \ 92 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ 93 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | 0x33f4f9) /* Unused */ 94 #endif 95 #ifndef BSP_TZ_CFG_PSARC 96 #define BSP_TZ_CFG_PSARC \ 97 ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ 98 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ 99 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \ 100 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ 101 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \ 102 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ 103 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | 0x7fffcef4) /* Unused */ 104 #endif 105 #ifndef BSP_TZ_CFG_PSARD 106 #define BSP_TZ_CFG_PSARD \ 107 ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \ 108 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \ 109 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \ 110 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ 111 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ 112 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ 113 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ 114 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ 115 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \ 116 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ 117 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \ 118 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | 0xffae07f0) /* Unused */ 119 #endif 120 #ifndef BSP_TZ_CFG_PSARE 121 #define BSP_TZ_CFG_PSARE \ 122 ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \ 123 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ 124 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \ 125 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \ 126 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \ 127 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ 128 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \ 129 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ 130 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ 131 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ 132 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ 133 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ 134 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ 135 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ 136 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | 0x3f3ff8) /* Unused */ 137 #endif 138 #ifndef BSP_TZ_CFG_MSSAR 139 #define BSP_TZ_CFG_MSSAR \ 140 ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \ 141 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | 0xfffffffc) /* Unused */ 142 #endif 143 144 /* Type 2 Peripheral Security Attribution */ 145 /* Security attribution for Cache registers. */ 146 #ifndef BSP_TZ_CFG_CSAR 147 #define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) 148 #endif 149 150 /* Security attribution for RSTSRn registers. */ 151 #ifndef BSP_TZ_CFG_RSTSAR 152 #define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) 153 #endif 154 155 /* Security attribution for registers of LVD channels. */ 156 #ifndef BSP_TZ_CFG_LVDSAR 157 #define BSP_TZ_CFG_LVDSAR \ 158 ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ 159 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \ 160 0xFFFFFFFCU) 161 #endif 162 163 /* Security attribution for LPM registers. */ 164 #ifndef BSP_TZ_CFG_LPMSAR 165 #define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) 166 #endif 167 /* Deep Standby Interrupt Factor Security Attribution Register. */ 168 #ifndef BSP_TZ_CFG_DPFSAR 169 #define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) 170 #endif 171 172 /* Security attribution for CGC registers. */ 173 #ifndef BSP_TZ_CFG_CGFSAR 174 #if BSP_CFG_CLOCKS_SECURE 175 /* Protect all CGC registers from Non-secure write access. */ 176 #define BSP_TZ_CFG_CGFSAR (0xFFFCE402U) 177 #else 178 /* Allow Secure and Non-secure write access. */ 179 #define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU) 180 #endif 181 #endif 182 183 /* Security attribution for Battery Backup registers. */ 184 #ifndef BSP_TZ_CFG_BBFSAR 185 #define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) 186 #endif 187 188 /* Security attribution for registers for IRQ channels. */ 189 #ifndef BSP_TZ_CFG_ICUSARA 190 #define BSP_TZ_CFG_ICUSARA \ 191 ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ 192 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ 193 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ 194 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ 195 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ 196 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ 197 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ 198 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ 199 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ 200 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ 201 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ 202 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ 203 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ 204 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ 205 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ 206 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | 0xFFFF0000U) 207 #endif 208 209 /* Security attribution for NMI registers. */ 210 #ifndef BSP_TZ_CFG_ICUSARB 211 #define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ 212 #endif 213 214 /* Security attribution for registers for DMAC channels */ 215 #ifndef BSP_TZ_CFG_ICUSARC 216 #define BSP_TZ_CFG_ICUSARC \ 217 ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ 218 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ 219 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ 220 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ 221 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ 222 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ 223 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ 224 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | 0xFFFFFF00U) 225 #endif 226 227 /* Security attribution registers for SELSR0. */ 228 #ifndef BSP_TZ_CFG_ICUSARD 229 #define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) 230 #endif 231 232 /* Security attribution registers for WUPEN0. */ 233 #ifndef BSP_TZ_CFG_ICUSARE 234 #define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) 235 #endif 236 237 /* Security attribution registers for WUPEN1. */ 238 #ifndef BSP_TZ_CFG_ICUSARF 239 #define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) 240 #endif 241 242 /* Set DTCSTSAR if the Secure program uses the DTC. */ 243 #if RA_NOT_DEFINED == RA_NOT_DEFINED 244 #define BSP_TZ_CFG_DTC_USED (0U) 245 #else 246 #define BSP_TZ_CFG_DTC_USED (1U) 247 #endif 248 249 /* Security attribution of FLWT and FCKMHZ registers. */ 250 #ifndef BSP_TZ_CFG_FSAR 251 /* If the CGC registers are only accessible in Secure mode, than there is no 252 * reason for nonsecure applications to access FLWT and FCKMHZ. 253 */ 254 #if BSP_CFG_CLOCKS_SECURE 255 /* Protect FLWT and FCKMHZ registers from nonsecure write access. */ 256 #define BSP_TZ_CFG_FSAR (0xFEFEU) 257 #else 258 /* Allow Secure and Non-secure write access. */ 259 #define BSP_TZ_CFG_FSAR (0xFFFFU) 260 #endif 261 #endif 262 263 /* Security attribution for SRAM registers. */ 264 #ifndef BSP_TZ_CFG_SRAMSAR 265 /* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure 266 * applications to access SRAM0WTEN and therefore there is no reason to access PRCR2. 267 */ 268 #define BSP_TZ_CFG_SRAMSAR (1 | ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | 4 | 0xFFFFFFF8U) 269 #endif 270 271 /* Security attribution for Standby RAM registers. */ 272 #ifndef BSP_TZ_CFG_STBRAMSAR 273 #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) 274 #endif 275 276 /* Security attribution for the DMAC Bus Master MPU settings. */ 277 #ifndef BSP_TZ_CFG_MMPUSARA 278 /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ 279 #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) 280 #endif 281 282 /* Security Attribution Register A for BUS Control registers. */ 283 #ifndef BSP_TZ_CFG_BUSSARA 284 #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) 285 #endif 286 /* Security Attribution Register B for BUS Control registers. */ 287 #ifndef BSP_TZ_CFG_BUSSARB 288 #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) 289 #endif 290 291 /* Enable Uninitialized Non-Secure Application Fallback. */ 292 #ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK 293 #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) 294 #endif 295 296 #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) 297 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) 298 #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) 299 #define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26) 300 #define OFS_SEQ5 (1 << 28) | (1 << 30) 301 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) 302 303 /* Option Function Select Register 1 Security Attribution */ 304 #ifndef BSP_CFG_ROM_REG_OFS1_SEL 305 #if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) 306 #define BSP_CFG_ROM_REG_OFS1_SEL \ 307 (0xFFFFF8F8U | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U)) 308 #else 309 #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) 310 #endif 311 #endif 312 313 #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) 314 315 /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. 316 */ 317 #define BSP_PRV_IELS_ENUM(vector) CONCAT(ELC_, vector) 318 319 /* Dual Mode Select Register */ 320 #ifndef BSP_CFG_ROM_REG_DUALSEL 321 #if CONFIG_DUAL_BANK_MODE 322 #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x0U)) 323 #else 324 #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) 325 #endif 326 #endif 327 328 /* Block Protection Register 0 */ 329 #ifndef BSP_CFG_ROM_REG_BPS0 330 #define BSP_CFG_ROM_REG_BPS0 (~(0U)) 331 #endif 332 /* Block Protection Register 1 */ 333 #ifndef BSP_CFG_ROM_REG_BPS1 334 #define BSP_CFG_ROM_REG_BPS1 (~(0U)) 335 #endif 336 /* Block Protection Register 2 */ 337 #ifndef BSP_CFG_ROM_REG_BPS2 338 #define BSP_CFG_ROM_REG_BPS2 (~(0U)) 339 #endif 340 /* Block Protection Register 3 */ 341 #ifndef BSP_CFG_ROM_REG_BPS3 342 #define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) 343 #endif 344 /* Permanent Block Protection Register 0 */ 345 #ifndef BSP_CFG_ROM_REG_PBPS0 346 #define BSP_CFG_ROM_REG_PBPS0 (~(0U)) 347 #endif 348 /* Permanent Block Protection Register 1 */ 349 #ifndef BSP_CFG_ROM_REG_PBPS1 350 #define BSP_CFG_ROM_REG_PBPS1 (~(0U)) 351 #endif 352 /* Permanent Block Protection Register 2 */ 353 #ifndef BSP_CFG_ROM_REG_PBPS2 354 #define BSP_CFG_ROM_REG_PBPS2 (~(0U)) 355 #endif 356 /* Permanent Block Protection Register 3 */ 357 #ifndef BSP_CFG_ROM_REG_PBPS3 358 #define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) 359 #endif 360 /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in 361 * the secure application, then mark them as secure) 362 */ 363 #ifndef BSP_CFG_ROM_REG_BPS_SEL0 364 #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) 365 #endif 366 /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in 367 * the secure application, then mark them as secure) 368 */ 369 #ifndef BSP_CFG_ROM_REG_BPS_SEL1 370 #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) 371 #endif 372 /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in 373 * the secure application, then mark them as secure) 374 */ 375 #ifndef BSP_CFG_ROM_REG_BPS_SEL2 376 #define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) 377 #endif 378 /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in 379 * the secure application, then mark them as secure) 380 */ 381 #ifndef BSP_CFG_ROM_REG_BPS_SEL3 382 #define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) 383 #endif 384 /* Security Attribution for Bank Select Register */ 385 #ifndef BSP_CFG_ROM_REG_BANKSEL_SEL 386 #define BSP_CFG_ROM_REG_BANKSEL_SEL (0xFFFFFFFFU) 387 #endif 388 #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT 389 #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) 390 #endif 391 392 #endif /* BSP_MCU_FAMILY_CFG_H_ */ 393
