1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef BSP_MCU_FAMILY_CFG_H_ 8 #define BSP_MCU_FAMILY_CFG_H_ 9 #include "bsp_mcu_device_pn_cfg.h" 10 #include "bsp_mcu_device_cfg.h" 11 #include "bsp_clock_cfg.h" 12 #include "bsp_mcu_info.h" 13 #define BSP_MCU_GROUP_RA6M3 (1) 14 #define BSP_LOCO_HZ (DT_PROP_OR(DT_NODELABEL(loco), clock_frequency, 0)) 15 #define BSP_MOCO_HZ (DT_PROP_OR(DT_NODELABEL(moco), clock_frequency, 0)) 16 #define BSP_SUB_CLOCK_HZ (DT_PROP_OR(DT_NODELABEL(subclk), clock_frequency, 0)) 17 #if BSP_CFG_HOCO_FREQUENCY == 0 18 #define BSP_HOCO_HZ (16000000) 19 #elif BSP_CFG_HOCO_FREQUENCY == 1 20 #define BSP_HOCO_HZ (18000000) 21 #elif BSP_CFG_HOCO_FREQUENCY == 2 22 #define BSP_HOCO_HZ (20000000) 23 #else 24 #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" 25 #endif 26 27 #define BSP_CFG_FLL_ENABLE (0) 28 29 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) 30 #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) 31 #define BSP_MCU_VBATT_SUPPORT (1) 32 33 #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) 34 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) 35 #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) 36 #define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26) 37 #define OFS_SEQ5 (1 << 28) | (1 << 30) 38 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) 39 #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) 40 #define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) 41 #define BSP_CFG_ROM_REG_MPU_PC0_START (0xFFFFFFFC) 42 #define BSP_CFG_ROM_REG_MPU_PC0_END (0xFFFFFFFF) 43 #define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) 44 #define BSP_CFG_ROM_REG_MPU_PC1_START (0xFFFFFFFC) 45 #define BSP_CFG_ROM_REG_MPU_PC1_END (0xFFFFFFFF) 46 #define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) 47 #define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) 48 #define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) 49 #define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) 50 #define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) 51 #define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) 52 #define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) 53 #define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) 54 #define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) 55 #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) 56 #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) 57 #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) 58 #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT 59 #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) 60 #endif 61 /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. 62 */ 63 #define BSP_PRV_IELS_ENUM(vector) CONCAT(ELC_, vector) 64 65 /* 66 * ID Code 67 * Note: To permanently lock and disable the debug interface define the 68 * BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. 69 * WARNING: This will disable debug access to the part and cannot be 70 * reversed by a debug probe. 71 */ 72 #if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) 73 #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) 74 #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) 75 #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) 76 #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) 77 #else 78 /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ 79 #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) 80 #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) 81 #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) 82 #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) 83 #endif 84 85 /* SDRAM controller configuration */ 86 #if DT_NODE_HAS_STATUS_OKAY(DT_INST(0, renesas_ra_sdram)) 87 #define BSP_CFG_SDRAM_TRAS \ 88 DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 0) 89 #define BSP_CFG_SDRAM_TRCD \ 90 DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 1) 91 #define BSP_CFG_SDRAM_TRP \ 92 DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 2) 93 #define BSP_CFG_SDRAM_TWR \ 94 DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 3) 95 #define BSP_CFG_SDRAM_TCL \ 96 DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 4) 97 #define BSP_CFG_SDRAM_TRFC \ 98 DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 5) 99 #define BSP_CFG_SDRAM_TREFW \ 100 DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), renesas_ra_sdram_timing, 6) 101 #define BSP_CFG_SDRAM_INIT_ARFI DT_PROP(DT_INST(0, renesas_ra_sdram), auto_refresh_interval) 102 #define BSP_CFG_SDRAM_INIT_ARFC DT_PROP(DT_INST(0, renesas_ra_sdram), auto_refresh_count) 103 #define BSP_CFG_SDRAM_INIT_PRC DT_PROP(DT_INST(0, renesas_ra_sdram), precharge_cycle_count) 104 #define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), multiplex_addr_shift) 105 #define BSP_CFG_SDRAM_ENDIAN_MODE DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), edian_mode) 106 #define BSP_CFG_SDRAM_ACCESS_MODE DT_PROP(DT_INST(0, renesas_ra_sdram), continuous_access) 107 #define BSP_CFG_SDRAM_BUS_WIDTH DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), bus_width) 108 #else 109 #define BSP_CFG_SDRAM_TRAS (0) 110 #define BSP_CFG_SDRAM_TRCD (0) 111 #define BSP_CFG_SDRAM_TRP (0) 112 #define BSP_CFG_SDRAM_TWR (0) 113 #define BSP_CFG_SDRAM_TCL (0) 114 #define BSP_CFG_SDRAM_TRFC (0) 115 #define BSP_CFG_SDRAM_TREFW (0) 116 #define BSP_CFG_SDRAM_INIT_ARFI (0) 117 #define BSP_CFG_SDRAM_INIT_ARFC (0) 118 #define BSP_CFG_SDRAM_INIT_PRC (0) 119 #define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT (0) 120 #define BSP_CFG_SDRAM_ENDIAN_MODE (0) 121 #define BSP_CFG_SDRAM_ACCESS_MODE (0) 122 #define BSP_CFG_SDRAM_BUS_WIDTH (0) 123 #endif /* DT_NODE_HAS_STATUS_OKAY(DT_INST(0, renesas_ra_sdram)) */ 124 125 #endif /* BSP_MCU_FAMILY_CFG_H_ */ 126
