1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef BSP_MCU_FAMILY_CFG_H_ 8 #define BSP_MCU_FAMILY_CFG_H_ 9 #include "bsp_mcu_device_pn_cfg.h" 10 #include "bsp_mcu_device_cfg.h" 11 #include "bsp_mcu_info.h" 12 #include "bsp_clock_cfg.h" 13 #define BSP_MCU_GROUP_RA6E2 (1) 14 #define BSP_LOCO_HZ (DT_PROP_OR(DT_NODELABEL(loco), clock_frequency, 0)) 15 #define BSP_MOCO_HZ (DT_PROP_OR(DT_NODELABEL(moco), clock_frequency, 0)) 16 #define BSP_SUB_CLOCK_HZ (DT_PROP_OR(DT_NODELABEL(subclk), clock_frequency, 0)) 17 #if BSP_CFG_HOCO_FREQUENCY == 0 18 #define BSP_HOCO_HZ (16000000) 19 #elif BSP_CFG_HOCO_FREQUENCY == 1 20 #define BSP_HOCO_HZ (18000000) 21 #elif BSP_CFG_HOCO_FREQUENCY == 2 22 #define BSP_HOCO_HZ (20000000) 23 #else 24 #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" 25 #endif 26 27 #define BSP_CFG_FLL_ENABLE (0) 28 29 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) 30 #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) 31 #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) 32 33 #if defined(_RA_TZ_SECURE) 34 #define BSP_TZ_SECURE_BUILD (1) 35 #define BSP_TZ_NONSECURE_BUILD (0) 36 #elif defined(_RA_TZ_NONSECURE) 37 #define BSP_TZ_SECURE_BUILD (0) 38 #define BSP_TZ_NONSECURE_BUILD (1) 39 #else 40 #define BSP_TZ_SECURE_BUILD (0) 41 #define BSP_TZ_NONSECURE_BUILD (0) 42 #endif 43 44 /* TrustZone Settings */ 45 #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) 46 #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) 47 #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) 48 49 /* CMSIS TrustZone Settings */ 50 #define SCB_CSR_AIRCR_INIT (1) 51 #define SCB_AIRCR_BFHFNMINS_VAL (0) 52 #define SCB_AIRCR_SYSRESETREQS_VAL (1) 53 #define SCB_AIRCR_PRIS_VAL (0) 54 #define TZ_FPU_NS_USAGE (1) 55 #ifndef SCB_NSACR_CP10_11_VAL 56 #define SCB_NSACR_CP10_11_VAL (3U) 57 #endif 58 59 #ifndef FPU_FPCCR_TS_VAL 60 #define FPU_FPCCR_TS_VAL (1U) 61 #endif 62 #define FPU_FPCCR_CLRONRETS_VAL (1) 63 64 #ifndef FPU_FPCCR_CLRONRET_VAL 65 #define FPU_FPCCR_CLRONRET_VAL (1) 66 #endif 67 68 /* The C-Cache line size that is configured during startup. */ 69 #ifndef BSP_CFG_C_CACHE_LINE_SIZE 70 #define BSP_CFG_C_CACHE_LINE_SIZE (1U) 71 #endif 72 73 /* Type 1 Peripheral Security Attribution */ 74 75 /* Peripheral Security Attribution Register (PSAR) Settings */ 76 #ifndef BSP_TZ_CFG_PSARB 77 #define BSP_TZ_CFG_PSARB \ 78 ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CEC */ | \ 79 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4) /* I3C0 */ | \ 80 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ 81 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ 82 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ 83 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ 84 (((1 > 0) ? 0U : 1U) << 31) /* SCI0 */ | 0x7FB3F7E7U) /* Unused */ 85 #endif 86 #ifndef BSP_TZ_CFG_PSARC 87 #define BSP_TZ_CFG_PSARC \ 88 ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ 89 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ 90 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ 91 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ 92 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* CANFD0 */ | \ 93 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* TRNG */ | 0xE7FFDEFC) /* Unused */ 94 #endif 95 #ifndef BSP_TZ_CFG_PSARD 96 #define BSP_TZ_CFG_PSARD \ 97 ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \ 98 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ 99 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ 100 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ 101 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ 102 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ 103 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ 104 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \ 105 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | 0xFFAE87F3) /* Unused */ 106 #endif 107 #ifndef BSP_TZ_CFG_PSARE 108 #define BSP_TZ_CFG_PSARE \ 109 ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \ 110 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ 111 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \ 112 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ 113 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ 114 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ 115 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ 116 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ 117 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | 0x3f3ff8) /* Unused */ 118 #endif 119 #ifndef BSP_TZ_CFG_MSSAR 120 #define BSP_TZ_CFG_MSSAR \ 121 ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \ 122 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | 0xfffffffc) /* Unused */ 123 #endif 124 125 /* Type 2 Peripheral Security Attribution */ 126 127 /* Security attribution for Cache registers. */ 128 #ifndef BSP_TZ_CFG_CSAR 129 #define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) 130 #endif 131 132 /* Security attribution for RSTSRn registers. */ 133 #ifndef BSP_TZ_CFG_RSTSAR 134 #define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) 135 #endif 136 137 /* Security attribution for registers of LVD channels. */ 138 #ifndef BSP_TZ_CFG_LVDSAR 139 #define BSP_TZ_CFG_LVDSAR \ 140 ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ 141 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \ 142 0xFFFFFFFCU) 143 #endif 144 145 /* Security attribution for LPM registers. */ 146 #ifndef BSP_TZ_CFG_LPMSAR 147 #define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFDCEAU : 0xFFFFFFFFU) 148 #endif 149 /* Deep Standby Interrupt Factor Security Attribution Register. */ 150 #ifndef BSP_TZ_CFG_DPFSAR 151 #define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xFAE0A00CU : 0xFFFFFFFFU) 152 #endif 153 154 /* Security attribution for CGC registers. */ 155 #ifndef BSP_TZ_CFG_CGFSAR 156 #if BSP_CFG_CLOCKS_SECURE 157 /* Protect all CGC registers from Non-secure write access. */ 158 #define BSP_TZ_CFG_CGFSAR (0xFFEAF602U) 159 #else 160 /* Allow Secure and Non-secure write access. */ 161 #define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU) 162 #endif 163 #endif 164 165 /* Security attribution for Battery Backup registers. */ 166 #ifndef BSP_TZ_CFG_BBFSAR 167 #define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) 168 #endif 169 170 /* Security attribution for registers for IRQ channels. */ 171 #ifndef BSP_TZ_CFG_ICUSARA 172 #define BSP_TZ_CFG_ICUSARA \ 173 ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ 174 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ 175 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ 176 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ 177 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ 178 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ 179 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ 180 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ 181 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ 182 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ 183 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ 184 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ 185 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ 186 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ 187 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ 188 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | 0xFFFF0000U) 189 #endif 190 191 /* Security attribution for NMI registers. */ 192 #ifndef BSP_TZ_CFG_ICUSARB 193 #define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ 194 #endif 195 196 /* Security attribution for registers for DMAC channels */ 197 #ifndef BSP_TZ_CFG_ICUSARC 198 #define BSP_TZ_CFG_ICUSARC \ 199 ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ 200 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ 201 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ 202 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ 203 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ 204 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ 205 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ 206 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | 0xFFFFFF00U) 207 #endif 208 209 /* Security attribution registers for SELSR0. */ 210 #ifndef BSP_TZ_CFG_ICUSARD 211 #define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) 212 #endif 213 214 /* Security attribution registers for WUPEN0. */ 215 #ifndef BSP_TZ_CFG_ICUSARE 216 #define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) 217 #endif 218 219 /* Security attribution registers for WUPEN1. */ 220 #ifndef BSP_TZ_CFG_ICUSARF 221 #define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) 222 #endif 223 224 /* Set DTCSTSAR if the Secure program uses the DTC. */ 225 #if RA_NOT_DEFINED == RA_NOT_DEFINED 226 #define BSP_TZ_CFG_DTC_USED (0U) 227 #else 228 #define BSP_TZ_CFG_DTC_USED (1U) 229 #endif 230 231 /* Security attribution of FLWT and FCKMHZ registers. */ 232 #ifndef BSP_TZ_CFG_FSAR 233 /* If the CGC registers are only accessible in Secure mode, than there is no 234 * reason for nonsecure applications to access FLWT and FCKMHZ. 235 */ 236 #if BSP_CFG_CLOCKS_SECURE 237 /* Protect FLWT and FCKMHZ registers from nonsecure write access. */ 238 #define BSP_TZ_CFG_FSAR (0xFEFEU) 239 #else 240 /* Allow Secure and Non-secure write access. */ 241 #define BSP_TZ_CFG_FSAR (0xFFFFU) 242 #endif 243 #endif 244 245 /* Security attribution for SRAM registers. */ 246 #ifndef BSP_TZ_CFG_SRAMSAR 247 /* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure 248 * applications to access SRAM0WTEN and therefore there is no reason to access PRCR2. 249 */ 250 #define BSP_TZ_CFG_SRAMSAR (1 | ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | 4 | 0xFFFFFFF8U) 251 #endif 252 253 /* Security attribution for Standby RAM registers. */ 254 #ifndef BSP_TZ_CFG_STBRAMSAR 255 #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) 256 #endif 257 258 /* Security attribution for the DMAC Bus Master MPU settings. */ 259 #ifndef BSP_TZ_CFG_MMPUSARA 260 /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ 261 #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) 262 #endif 263 264 /* Security Attribution Register A for BUS Control registers. */ 265 #ifndef BSP_TZ_CFG_BUSSARA 266 #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) 267 #endif 268 /* Security Attribution Register B for BUS Control registers. */ 269 #ifndef BSP_TZ_CFG_BUSSARB 270 #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) 271 #endif 272 273 /* Enable Uninitialized Non-Secure Application Fallback. */ 274 #ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK 275 #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) 276 #endif 277 278 #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) 279 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) 280 #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) 281 #define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26) 282 #define OFS_SEQ5 (1 << 28) | (1 << 30) 283 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) 284 285 /* Option Function Select Register 1 Security Attribution */ 286 #ifndef BSP_CFG_ROM_REG_OFS1_SEL 287 #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFFFFFU) 288 #endif 289 290 #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) 291 292 /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. 293 */ 294 #define BSP_PRV_IELS_ENUM(vector) CONCAT(ELC_, vector) 295 296 /* Block Protection Register 0 */ 297 #ifndef BSP_CFG_ROM_REG_BPS0 298 #define BSP_CFG_ROM_REG_BPS0 (~(0U)) 299 #endif 300 /* Block Protection Register 1 */ 301 #ifndef BSP_CFG_ROM_REG_BPS1 302 #define BSP_CFG_ROM_REG_BPS1 (0xFFFFFFFFU) 303 #endif 304 /* Block Protection Register 2 */ 305 #ifndef BSP_CFG_ROM_REG_BPS2 306 #define BSP_CFG_ROM_REG_BPS2 (0xFFFFFFFFU) 307 #endif 308 /* Block Protection Register 3 */ 309 #ifndef BSP_CFG_ROM_REG_BPS3 310 #define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) 311 #endif 312 /* Permanent Block Protection Register 0 */ 313 #ifndef BSP_CFG_ROM_REG_PBPS0 314 #define BSP_CFG_ROM_REG_PBPS0 (~(0U)) 315 #endif 316 /* Permanent Block Protection Register 1 */ 317 #ifndef BSP_CFG_ROM_REG_PBPS1 318 #define BSP_CFG_ROM_REG_PBPS1 (0xFFFFFFFFU) 319 #endif 320 /* Permanent Block Protection Register 2 */ 321 #ifndef BSP_CFG_ROM_REG_PBPS2 322 #define BSP_CFG_ROM_REG_PBPS2 (0xFFFFFFFFU) 323 #endif 324 /* Permanent Block Protection Register 3 */ 325 #ifndef BSP_CFG_ROM_REG_PBPS3 326 #define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) 327 #endif 328 /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in 329 * the secure application, then mark them as secure) 330 */ 331 #ifndef BSP_CFG_ROM_REG_BPS_SEL0 332 #define BSP_CFG_ROM_REG_BPS_SEL0 (0XFFFFFFFFU) 333 #endif 334 /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in 335 * the secure application, then mark them as secure) 336 */ 337 #ifndef BSP_CFG_ROM_REG_BPS_SEL1 338 #define BSP_CFG_ROM_REG_BPS_SEL1 (0XFFFFFFFFU) 339 #endif 340 /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in 341 * the secure application, then mark them as secure) 342 */ 343 #ifndef BSP_CFG_ROM_REG_BPS_SEL2 344 #define BSP_CFG_ROM_REG_BPS_SEL2 (0XFFFFFFFFU) 345 #endif 346 /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in 347 * the secure application, then mark them as secure) 348 */ 349 #ifndef BSP_CFG_ROM_REG_BPS_SEL3 350 #define BSP_CFG_ROM_REG_BPS_SEL3 (0XFFFFFFFFU) 351 #endif 352 #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT 353 #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) 354 #endif 355 356 /* ID Code 357 * Note: To permanently lock and disable the debug interface define the 358 * BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. 359 * WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. 360 */ 361 #if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) 362 #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) 363 #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) 364 #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) 365 #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) 366 #else 367 /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ 368 #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) 369 #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) 370 #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) 371 #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) 372 #endif 373 374 #endif /* BSP_MCU_FAMILY_CFG_H_ */ 375
