1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef BSP_MCU_FAMILY_CFG_H_ 8 #define BSP_MCU_FAMILY_CFG_H_ 9 #include "bsp_mcu_device_pn_cfg.h" 10 #include "bsp_mcu_device_cfg.h" 11 #include "bsp_mcu_info.h" 12 #include "bsp_clock_cfg.h" 13 #define BSP_MCU_GROUP_RA4M3 (1) 14 #define BSP_LOCO_HZ (DT_PROP_OR(DT_NODELABEL(loco), clock_frequency, 0)) 15 #define BSP_MOCO_HZ (DT_PROP_OR(DT_NODELABEL(moco), clock_frequency, 0)) 16 #define BSP_SUB_CLOCK_HZ (DT_PROP_OR(DT_NODELABEL(subclk), clock_frequency, 0)) 17 #if BSP_CFG_HOCO_FREQUENCY == 0 18 #define BSP_HOCO_HZ (16000000) 19 #elif BSP_CFG_HOCO_FREQUENCY == 1 20 #define BSP_HOCO_HZ (18000000) 21 #elif BSP_CFG_HOCO_FREQUENCY == 2 22 #define BSP_HOCO_HZ (20000000) 23 #else 24 #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" 25 #endif 26 27 #define BSP_CFG_FLL_ENABLE (0) 28 29 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) 30 #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) 31 #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) 32 33 #if defined(_RA_TZ_SECURE) 34 #define BSP_TZ_SECURE_BUILD (1) 35 #define BSP_TZ_NONSECURE_BUILD (0) 36 #elif defined(_RA_TZ_NONSECURE) 37 #define BSP_TZ_SECURE_BUILD (0) 38 #define BSP_TZ_NONSECURE_BUILD (1) 39 #else 40 #define BSP_TZ_SECURE_BUILD (0) 41 #define BSP_TZ_NONSECURE_BUILD (0) 42 #endif 43 44 /* TrustZone Settings */ 45 #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) 46 #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) 47 #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) 48 49 /* CMSIS TrustZone Settings */ 50 #define SCB_CSR_AIRCR_INIT (1) 51 #define SCB_AIRCR_BFHFNMINS_VAL (0) 52 #define SCB_AIRCR_SYSRESETREQS_VAL (1) 53 #define SCB_AIRCR_PRIS_VAL (0) 54 #define TZ_FPU_NS_USAGE (1) 55 #ifndef SCB_NSACR_CP10_11_VAL 56 #define SCB_NSACR_CP10_11_VAL (3U) 57 #endif 58 59 #ifndef FPU_FPCCR_TS_VAL 60 #define FPU_FPCCR_TS_VAL (1U) 61 #endif 62 #define FPU_FPCCR_CLRONRETS_VAL (1) 63 64 #ifndef FPU_FPCCR_CLRONRET_VAL 65 #define FPU_FPCCR_CLRONRET_VAL (1) 66 #endif 67 68 /* The C-Cache line size that is configured during startup. */ 69 #ifndef BSP_CFG_C_CACHE_LINE_SIZE 70 #define BSP_CFG_C_CACHE_LINE_SIZE (1U) 71 #endif 72 73 /* Type 1 Peripheral Security Attribution */ 74 75 /* Peripheral Security Attribution Register (PSAR) Settings */ 76 #ifndef BSP_TZ_CFG_PSARB 77 #define BSP_TZ_CFG_PSARB (\ 78 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \ 79 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ 80 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ 81 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ 82 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ 83 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ 84 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ 85 (((1 > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ 86 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \ 87 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ 88 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \ 89 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \ 90 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \ 91 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ 92 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \ 93 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ 94 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \ 95 0x33f4f9) /* Unused */ 96 #endif 97 #ifndef BSP_TZ_CFG_PSARC 98 #define BSP_TZ_CFG_PSARC (\ 99 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ 100 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ 101 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \ 102 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ 103 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \ 104 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ 105 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \ 106 0x7fffcef4) /* Unused */ 107 #endif 108 #ifndef BSP_TZ_CFG_PSARD 109 #define BSP_TZ_CFG_PSARD (\ 110 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \ 111 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \ 112 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \ 113 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ 114 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ 115 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ 116 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ 117 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ 118 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \ 119 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ 120 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \ 121 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ 122 0xffae07f0) /* Unused */ 123 #endif 124 #ifndef BSP_TZ_CFG_PSARE 125 #define BSP_TZ_CFG_PSARE (\ 126 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \ 127 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ 128 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \ 129 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \ 130 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \ 131 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ 132 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \ 133 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ 134 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ 135 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ 136 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ 137 (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ 138 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ 139 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ 140 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \ 141 0x3f3ff8) /* Unused */ 142 #endif 143 #ifndef BSP_TZ_CFG_MSSAR 144 #define BSP_TZ_CFG_MSSAR (\ 145 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \ 146 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ 147 0xfffffffc) /* Unused */ 148 #endif 149 150 /* Type 2 Peripheral Security Attribution */ 151 152 /* Security attribution for Cache registers. */ 153 #ifndef BSP_TZ_CFG_CSAR 154 #define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) 155 #endif 156 157 /* Security attribution for RSTSRn registers. */ 158 #ifndef BSP_TZ_CFG_RSTSAR 159 #define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) 160 #endif 161 162 /* Security attribution for registers of LVD channels. */ 163 #ifndef BSP_TZ_CFG_LVDSAR 164 #define BSP_TZ_CFG_LVDSAR (\ 165 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ 166 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \ 167 0xFFFFFFFCU) 168 #endif 169 170 /* Security attribution for LPM registers. */ 171 #ifndef BSP_TZ_CFG_LPMSAR 172 #define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) 173 #endif 174 /* Deep Standby Interrupt Factor Security Attribution Register. */ 175 #ifndef BSP_TZ_CFG_DPFSAR 176 #define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) 177 #endif 178 179 /* Security attribution for CGC registers. */ 180 #ifndef BSP_TZ_CFG_CGFSAR 181 #if BSP_CFG_CLOCKS_SECURE 182 /* Protect all CGC registers from Non-secure write access. */ 183 #define BSP_TZ_CFG_CGFSAR (0xFFFCE402U) 184 #else 185 /* Allow Secure and Non-secure write access. */ 186 #define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU) 187 #endif 188 #endif 189 190 /* Security attribution for Battery Backup registers. */ 191 #ifndef BSP_TZ_CFG_BBFSAR 192 #define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) 193 #endif 194 195 /* Security attribution for registers for IRQ channels. */ 196 #ifndef BSP_TZ_CFG_ICUSARA 197 #define BSP_TZ_CFG_ICUSARA (\ 198 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ 199 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ 200 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ 201 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ 202 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ 203 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ 204 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ 205 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ 206 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ 207 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ 208 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ 209 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ 210 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ 211 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ 212 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ 213 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \ 214 0xFFFF0000U) 215 #endif 216 217 /* Security attribution for NMI registers. */ 218 #ifndef BSP_TZ_CFG_ICUSARB 219 #define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ 220 #endif 221 222 /* Security attribution for registers for DMAC channels */ 223 #ifndef BSP_TZ_CFG_ICUSARC 224 #define BSP_TZ_CFG_ICUSARC (\ 225 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ 226 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ 227 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ 228 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ 229 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ 230 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ 231 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ 232 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \ 233 0xFFFFFF00U) 234 #endif 235 236 /* Security attribution registers for SELSR0. */ 237 #ifndef BSP_TZ_CFG_ICUSARD 238 #define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) 239 #endif 240 241 /* Security attribution registers for WUPEN0. */ 242 #ifndef BSP_TZ_CFG_ICUSARE 243 #define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) 244 #endif 245 246 /* Security attribution registers for WUPEN1. */ 247 #ifndef BSP_TZ_CFG_ICUSARF 248 #define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) 249 #endif 250 251 /* Set DTCSTSAR if the Secure program uses the DTC. */ 252 #if RA_NOT_DEFINED == RA_NOT_DEFINED 253 #define BSP_TZ_CFG_DTC_USED (0U) 254 #else 255 #define BSP_TZ_CFG_DTC_USED (1U) 256 #endif 257 258 /* Security attribution of FLWT and FCKMHZ registers. */ 259 #ifndef BSP_TZ_CFG_FSAR 260 /* If the CGC registers are only accessible in Secure mode, than there is no 261 * reason for nonsecure applications to access FLWT and FCKMHZ. 262 */ 263 #if BSP_CFG_CLOCKS_SECURE 264 /* Protect FLWT and FCKMHZ registers from nonsecure write access. */ 265 #define BSP_TZ_CFG_FSAR (0xFEFEU) 266 #else 267 /* Allow Secure and Non-secure write access. */ 268 #define BSP_TZ_CFG_FSAR (0xFFFFU) 269 #endif 270 #endif 271 272 /* Security attribution for SRAM registers. */ 273 #ifndef BSP_TZ_CFG_SRAMSAR 274 /* If the CGC registers are only accessible in Secure mode, 275 * than there is no reason for Non Secure applications to access 276 * SRAM0WTEN and therefore there is no reason to access PRCR2. 277 */ 278 #define BSP_TZ_CFG_SRAMSAR (\ 279 1 | \ 280 ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ 281 4 | \ 282 0xFFFFFFF8U) 283 #endif 284 285 /* Security attribution for Standby RAM registers.*/ 286 #ifndef BSP_TZ_CFG_STBRAMSAR 287 #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) 288 #endif 289 290 /* Security attribution for the DMAC Bus Master MPU settings. */ 291 #ifndef BSP_TZ_CFG_MMPUSARA 292 /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ 293 #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) 294 #endif 295 296 /* Security Attribution Register A for BUS Control registers. */ 297 #ifndef BSP_TZ_CFG_BUSSARA 298 #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) 299 #endif 300 /* Security Attribution Register B for BUS Control registers. */ 301 #ifndef BSP_TZ_CFG_BUSSARB 302 #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) 303 #endif 304 305 /* Enable Uninitialized Non-Secure Application Fallback. */ 306 #ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK 307 #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) 308 #endif 309 310 #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) 311 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) 312 #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) 313 #define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26) 314 #define OFS_SEQ5 (1 << 28) | (1 << 30) 315 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) 316 317 /* Option Function Select Register 1 Security Attribution */ 318 #ifndef BSP_CFG_ROM_REG_OFS1_SEL 319 #if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) 320 #define BSP_CFG_ROM_REG_OFS1_SEL \ 321 (0xFFFFF8F8U | \ 322 ((0U << 0U)) | \ 323 ((0U << 2U)) | \ 324 ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U)) 325 #else 326 #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) 327 #endif 328 #endif 329 330 #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) 331 332 /* Used to create IELS values for the interrupt initialization 333 * table g_interrupt_event_link_select. 334 */ 335 #define BSP_PRV_IELS_ENUM(vector) CONCAT(ELC_, vector) 336 337 /* Dual Mode Select Register */ 338 #ifndef BSP_CFG_ROM_REG_DUALSEL 339 #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFFFU) 340 #endif 341 342 /* Block Protection Register 0 */ 343 #ifndef BSP_CFG_ROM_REG_BPS0 344 #define BSP_CFG_ROM_REG_BPS0 (~(0U)) 345 #endif 346 /* Block Protection Register 1 */ 347 #ifndef BSP_CFG_ROM_REG_BPS1 348 #define BSP_CFG_ROM_REG_BPS1 (~(0U)) 349 #endif 350 /* Block Protection Register 2 */ 351 #ifndef BSP_CFG_ROM_REG_BPS2 352 #define BSP_CFG_ROM_REG_BPS2 (0xFFFFFFFFU) 353 #endif 354 /* Block Protection Register 3 */ 355 #ifndef BSP_CFG_ROM_REG_BPS3 356 #define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) 357 #endif 358 /* Permanent Block Protection Register 0 */ 359 #ifndef BSP_CFG_ROM_REG_PBPS0 360 #define BSP_CFG_ROM_REG_PBPS0 (~(0U)) 361 #endif 362 /* Permanent Block Protection Register 1 */ 363 #ifndef BSP_CFG_ROM_REG_PBPS1 364 #define BSP_CFG_ROM_REG_PBPS1 (~(0U)) 365 #endif 366 /* Permanent Block Protection Register 2 */ 367 #ifndef BSP_CFG_ROM_REG_PBPS2 368 #define BSP_CFG_ROM_REG_PBPS2 (0xFFFFFFFFU) 369 #endif 370 /* Permanent Block Protection Register 3 */ 371 #ifndef BSP_CFG_ROM_REG_PBPS3 372 #define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) 373 #endif 374 /* Security Attribution for Block Protection Register 0 375 * (If any blocks are marked as protected in the secure application, then mark them as secure) 376 */ 377 #ifndef BSP_CFG_ROM_REG_BPS_SEL0 378 #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) 379 #endif 380 /* Security Attribution for Block Protection Register 1 381 * (If any blocks are marked as protected in the secure application, then mark them as secure) 382 */ 383 #ifndef BSP_CFG_ROM_REG_BPS_SEL1 384 #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) 385 #endif 386 /* Security Attribution for Block Protection Register 2 387 * (If any blocks are marked as protected in the secure application, then mark them as secure) 388 */ 389 #ifndef BSP_CFG_ROM_REG_BPS_SEL2 390 #define BSP_CFG_ROM_REG_BPS_SEL2 (0xFFFFFFFFU) 391 #endif 392 /* Security Attribution for Block Protection Register 3 393 * (If any blocks are marked as protected in the secure application, then mark them as secure) 394 */ 395 #ifndef BSP_CFG_ROM_REG_BPS_SEL3 396 #define BSP_CFG_ROM_REG_BPS_SEL3 (0xFFFFFFFFU) 397 #endif 398 #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT 399 #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) 400 #endif 401 402 #endif /* BSP_MCU_FAMILY_CFG_H_ */ 403
