1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef BSP_MCU_FAMILY_CFG_H_ 8 #define BSP_MCU_FAMILY_CFG_H_ 9 #include "bsp_mcu_device_pn_cfg.h" 10 #include "bsp_mcu_device_cfg.h" 11 #include "bsp_mcu_info.h" 12 #include "bsp_clock_cfg.h" 13 14 #define BSP_MCU_GROUP_RA4M2 (1) 15 #define BSP_LOCO_HZ (DT_PROP_OR(DT_NODELABEL(loco), clock_frequency, 0)) 16 #define BSP_MOCO_HZ (DT_PROP_OR(DT_NODELABEL(moco), clock_frequency, 0)) 17 #define BSP_SUB_CLOCK_HZ (DT_PROP_OR(DT_NODELABEL(subclk), clock_frequency, 0)) 18 #if BSP_CFG_HOCO_FREQUENCY == 0 19 #define BSP_HOCO_HZ (16000000) 20 #elif BSP_CFG_HOCO_FREQUENCY == 1 21 #define BSP_HOCO_HZ (18000000) 22 #elif BSP_CFG_HOCO_FREQUENCY == 2 23 #define BSP_HOCO_HZ (20000000) 24 #else 25 #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" 26 #endif 27 28 #define BSP_CFG_FLL_ENABLE (0) 29 30 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) 31 #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) 32 #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) 33 34 #if defined(_RA_TZ_SECURE) 35 #define BSP_TZ_SECURE_BUILD (1) 36 #define BSP_TZ_NONSECURE_BUILD (0) 37 #elif defined(_RA_TZ_NONSECURE) 38 #define BSP_TZ_SECURE_BUILD (0) 39 #define BSP_TZ_NONSECURE_BUILD (1) 40 #else 41 #define BSP_TZ_SECURE_BUILD (0) 42 #define BSP_TZ_NONSECURE_BUILD (0) 43 #endif 44 45 /* TrustZone Settings */ 46 #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) 47 #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) 48 #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) 49 50 /* CMSIS TrustZone Settings */ 51 #define SCB_CSR_AIRCR_INIT (1) 52 #define SCB_AIRCR_BFHFNMINS_VAL (0) 53 #define SCB_AIRCR_SYSRESETREQS_VAL (1) 54 #define SCB_AIRCR_PRIS_VAL (0) 55 #define TZ_FPU_NS_USAGE (1) 56 #ifndef SCB_NSACR_CP10_11_VAL 57 #define SCB_NSACR_CP10_11_VAL (3U) 58 #endif 59 60 #ifndef FPU_FPCCR_TS_VAL 61 #define FPU_FPCCR_TS_VAL (1U) 62 #endif 63 #define FPU_FPCCR_CLRONRETS_VAL (1) 64 65 #ifndef FPU_FPCCR_CLRONRET_VAL 66 #define FPU_FPCCR_CLRONRET_VAL (1) 67 #endif 68 69 /* The C-Cache line size that is configured during startup. */ 70 #ifndef BSP_CFG_C_CACHE_LINE_SIZE 71 #define BSP_CFG_C_CACHE_LINE_SIZE (1U) 72 #endif 73 74 /* Type 1 Peripheral Security Attribution */ 75 76 /* Peripheral Security Attribution Register (PSAR) Settings */ 77 #ifndef BSP_TZ_CFG_PSARB 78 #define BSP_TZ_CFG_PSARB (\ 79 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ 80 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ 81 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ 82 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ 83 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ 84 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ 85 (((1 > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ 86 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \ 87 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ 88 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \ 89 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \ 90 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \ 91 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ 92 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \ 93 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ 94 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \ 95 0x33f4f9) /* Unused */ 96 #endif 97 #ifndef BSP_TZ_CFG_PSARC 98 #define BSP_TZ_CFG_PSARC (\ 99 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ 100 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ 101 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \ 102 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ 103 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \ 104 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ 105 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \ 106 0x7fffcef4) /* Unused */ 107 #endif 108 #ifndef BSP_TZ_CFG_PSARD 109 #define BSP_TZ_CFG_PSARD (\ 110 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \ 111 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \ 112 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \ 113 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ 114 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ 115 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ 116 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ 117 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ 118 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ 119 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \ 120 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ 121 0xffae07f0) /* Unused */ 122 #endif 123 #ifndef BSP_TZ_CFG_PSARE 124 #define BSP_TZ_CFG_PSARE (\ 125 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \ 126 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ 127 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \ 128 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \ 129 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \ 130 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ 131 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \ 132 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ 133 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ 134 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ 135 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ 136 (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ 137 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ 138 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ 139 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \ 140 0x3f3ff8) /* Unused */ 141 #endif 142 #ifndef BSP_TZ_CFG_MSSAR 143 #define BSP_TZ_CFG_MSSAR (\ 144 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \ 145 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ 146 0xfffffffc) /* Unused */ 147 #endif 148 149 /* Type 2 Peripheral Security Attribution */ 150 151 /* Security attribution for Cache registers. */ 152 #ifndef BSP_TZ_CFG_CSAR 153 #define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) 154 #endif 155 156 /* Security attribution for RSTSRn registers. */ 157 #ifndef BSP_TZ_CFG_RSTSAR 158 #define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) 159 #endif 160 161 /* Security attribution for registers of LVD channels. */ 162 #ifndef BSP_TZ_CFG_LVDSAR 163 #define BSP_TZ_CFG_LVDSAR (\ 164 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ 165 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \ 166 0xFFFFFFFCU) 167 #endif 168 169 /* Security attribution for LPM registers. */ 170 #ifndef BSP_TZ_CFG_LPMSAR 171 #define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) 172 #endif 173 /* Deep Standby Interrupt Factor Security Attribution Register. */ 174 #ifndef BSP_TZ_CFG_DPFSAR 175 #define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) 176 #endif 177 178 /* Security attribution for CGC registers. */ 179 #ifndef BSP_TZ_CFG_CGFSAR 180 #if BSP_CFG_CLOCKS_SECURE 181 /* Protect all CGC registers from Non-secure write access. */ 182 #define BSP_TZ_CFG_CGFSAR (0xFFFCE402U) 183 #else 184 /* Allow Secure and Non-secure write access. */ 185 #define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU) 186 #endif 187 #endif 188 189 /* Security attribution for Battery Backup registers. */ 190 #ifndef BSP_TZ_CFG_BBFSAR 191 #define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) 192 #endif 193 194 /* Security attribution for registers for IRQ channels. */ 195 #ifndef BSP_TZ_CFG_ICUSARA 196 #define BSP_TZ_CFG_ICUSARA (\ 197 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ 198 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ 199 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ 200 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ 201 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ 202 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ 203 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ 204 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ 205 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ 206 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ 207 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ 208 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ 209 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ 210 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ 211 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ 212 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \ 213 0xFFFF0000U) 214 #endif 215 216 /* Security attribution for NMI registers. */ 217 #ifndef BSP_TZ_CFG_ICUSARB 218 #define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ 219 #endif 220 221 /* Security attribution for registers for DMAC channels */ 222 #ifndef BSP_TZ_CFG_ICUSARC 223 #define BSP_TZ_CFG_ICUSARC (\ 224 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ 225 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ 226 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ 227 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ 228 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ 229 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ 230 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ 231 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \ 232 0xFFFFFF00U) 233 #endif 234 235 /* Security attribution registers for SELSR0. */ 236 #ifndef BSP_TZ_CFG_ICUSARD 237 #define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) 238 #endif 239 240 /* Security attribution registers for WUPEN0. */ 241 #ifndef BSP_TZ_CFG_ICUSARE 242 #define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) 243 #endif 244 245 /* Security attribution registers for WUPEN1. */ 246 #ifndef BSP_TZ_CFG_ICUSARF 247 #define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) 248 #endif 249 250 /* Set DTCSTSAR if the Secure program uses the DTC. */ 251 #if RA_NOT_DEFINED == RA_NOT_DEFINED 252 #define BSP_TZ_CFG_DTC_USED (0U) 253 #else 254 #define BSP_TZ_CFG_DTC_USED (1U) 255 #endif 256 257 /* Security attribution of FLWT and FCKMHZ registers. */ 258 #ifndef BSP_TZ_CFG_FSAR 259 /* If the CGC registers are only accessible in Secure mode, than there is no 260 * reason for nonsecure applications to access FLWT and FCKMHZ. 261 */ 262 #if BSP_CFG_CLOCKS_SECURE 263 /* Protect FLWT and FCKMHZ registers from nonsecure write access. */ 264 #define BSP_TZ_CFG_FSAR (0xFEFEU) 265 #else 266 /* Allow Secure and Non-secure write access. */ 267 #define BSP_TZ_CFG_FSAR (0xFFFFU) 268 #endif 269 #endif 270 271 /* Security attribution for SRAM registers. */ 272 #ifndef BSP_TZ_CFG_SRAMSAR 273 /* If the CGC registers are only accessible in Secure mode, 274 * than there is no reason for Non Secure applications to access 275 * SRAM0WTEN and therefore there is no reason to access PRCR2. 276 */ 277 #define BSP_TZ_CFG_SRAMSAR (\ 278 1 | \ 279 ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ 280 4 | \ 281 0xFFFFFFF8U) 282 #endif 283 284 /* Security attribution for Standby RAM registers. */ 285 #ifndef BSP_TZ_CFG_STBRAMSAR 286 #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) 287 #endif 288 289 /* Security attribution for the DMAC Bus Master MPU settings. */ 290 #ifndef BSP_TZ_CFG_MMPUSARA 291 /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ 292 #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) 293 #endif 294 295 /* Security Attribution Register A for BUS Control registers. */ 296 #ifndef BSP_TZ_CFG_BUSSARA 297 #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) 298 #endif 299 /* Security Attribution Register B for BUS Control registers. */ 300 #ifndef BSP_TZ_CFG_BUSSARB 301 #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) 302 #endif 303 304 /* Enable Uninitialized Non-Secure Application Fallback. */ 305 #ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK 306 #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) 307 #endif 308 309 #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) 310 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) 311 #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) 312 #define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26) 313 #define OFS_SEQ5 (1 << 28) | (1 << 30) 314 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) 315 316 /* Option Function Select Register 1 Security Attribution */ 317 #ifndef BSP_CFG_ROM_REG_OFS1_SEL 318 #if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) 319 #define BSP_CFG_ROM_REG_OFS1_SEL \ 320 (0xFFFFF8F8U | \ 321 ((0U << 0U)) | \ 322 ((0U << 2U)) | \ 323 ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U)) 324 #else 325 #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) 326 #endif 327 #endif 328 329 #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) 330 331 /* Used to create IELS values for the interrupt initialization table 332 * g_interrupt_event_link_select. 333 */ 334 #define BSP_PRV_IELS_ENUM(vector) CONCAT(ELC_, vector) 335 336 /* Dual Mode Select Register */ 337 #ifndef BSP_CFG_ROM_REG_DUALSEL 338 #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFFFU) 339 #endif 340 341 /* Block Protection Register 0 */ 342 #ifndef BSP_CFG_ROM_REG_BPS0 343 #define BSP_CFG_ROM_REG_BPS0 (~(0U)) 344 #endif 345 /* Block Protection Register 1 */ 346 #ifndef BSP_CFG_ROM_REG_BPS1 347 #define BSP_CFG_ROM_REG_BPS1 (0xFFFFFFFFU) 348 #endif 349 /* Block Protection Register 2 */ 350 #ifndef BSP_CFG_ROM_REG_BPS2 351 #define BSP_CFG_ROM_REG_BPS2 (0xFFFFFFFFU) 352 #endif 353 /* Block Protection Register 3 */ 354 #ifndef BSP_CFG_ROM_REG_BPS3 355 #define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) 356 #endif 357 /* Permanent Block Protection Register 0 */ 358 #ifndef BSP_CFG_ROM_REG_PBPS0 359 #define BSP_CFG_ROM_REG_PBPS0 (~(0U)) 360 #endif 361 /* Permanent Block Protection Register 1 */ 362 #ifndef BSP_CFG_ROM_REG_PBPS1 363 #define BSP_CFG_ROM_REG_PBPS1 (0xFFFFFFFFU) 364 #endif 365 /* Permanent Block Protection Register 2 */ 366 #ifndef BSP_CFG_ROM_REG_PBPS2 367 #define BSP_CFG_ROM_REG_PBPS2 (0xFFFFFFFFU) 368 #endif 369 /* Permanent Block Protection Register 3 */ 370 #ifndef BSP_CFG_ROM_REG_PBPS3 371 #define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) 372 #endif 373 /* Security Attribution for Block Protection Register 0 374 * (If any blocks are marked as protected in the secure application, then mark them as secure) 375 */ 376 #ifndef BSP_CFG_ROM_REG_BPS_SEL0 377 #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) 378 #endif 379 /* Security Attribution for Block Protection Register 1 380 * If any blocks are marked as protected in the secure application, then mark them as secure 381 */ 382 #ifndef BSP_CFG_ROM_REG_BPS_SEL1 383 #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) 384 #endif 385 /* Security Attribution for Block Protection Register 2 386 * If any blocks are marked as protected in the secure application, then mark them as secure 387 */ 388 #ifndef BSP_CFG_ROM_REG_BPS_SEL2 389 #define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) 390 #endif 391 /* Security Attribution for Block Protection Register 3 392 * If any blocks are marked as protected in the secure application, then mark them as secure 393 */ 394 #ifndef BSP_CFG_ROM_REG_BPS_SEL3 395 #define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) 396 #endif 397 #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT 398 #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) 399 #endif 400 401 #endif /* BSP_MCU_FAMILY_CFG_H_ */ 402
