1 /*
2  * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef BSP_MCU_FAMILY_CFG_H_
8 #define BSP_MCU_FAMILY_CFG_H_
9 #ifdef __cplusplus
10 extern "C" {
11 #endif
12 
13 #include "bsp_mcu_device_pn_cfg.h"
14 #include "bsp_mcu_device_cfg.h"
15 #include "bsp_override.h"
16 #include "bsp_mcu_info.h"
17 #include "bsp_clock_cfg.h"
18 #define BSP_MCU_GROUP_RA4L1 (1)
19 #define BSP_LOCO_HZ                 (DT_PROP_OR(DT_NODELABEL(loco), clock_frequency, 0))
20 #define BSP_MOCO_HZ                 (DT_PROP_OR(DT_NODELABEL(moco), clock_frequency, 0))
21 #define BSP_SUB_CLOCK_HZ            (DT_PROP_OR(DT_NODELABEL(subclk), clock_frequency, 0))
22 #if   BSP_CFG_HOCO_FREQUENCY == 0
23 #define BSP_HOCO_HZ                 (48000000)
24 #elif BSP_CFG_HOCO_FREQUENCY == 1
25 #define BSP_HOCO_HZ                 (64000000)
26 #elif BSP_CFG_HOCO_FREQUENCY == 2
27 #define BSP_HOCO_HZ                 (80000000)
28 #elif BSP_CFG_HOCO_FREQUENCY == 4
29 #define BSP_HOCO_HZ                 (24000000)
30 #elif BSP_CFG_HOCO_FREQUENCY == 5
31 #define BSP_HOCO_HZ                 (32000000)
32 #elif BSP_CFG_HOCO_FREQUENCY == 6
33 #define BSP_HOCO_HZ                 (40000000)
34 #else
35 #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
36 #endif
37 
38 #define BSP_CFG_FLL_ENABLE                 (0)
39 
40 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
41 #define BSP_VECTOR_TABLE_MAX_ENTRIES       (80U)
42 
43 #if defined(_RA_TZ_SECURE)
44 #define BSP_TZ_SECURE_BUILD           (1)
45 #define BSP_TZ_NONSECURE_BUILD        (0)
46 #elif defined(_RA_TZ_NONSECURE)
47 #define BSP_TZ_SECURE_BUILD           (0)
48 #define BSP_TZ_NONSECURE_BUILD        (1)
49 #else
50 #define BSP_TZ_SECURE_BUILD           (0)
51 #define BSP_TZ_NONSECURE_BUILD        (0)
52 #endif
53 
54 /* TrustZone Settings */
55 #define BSP_TZ_CFG_INIT_SECURE_ONLY       (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
56 #define BSP_TZ_CFG_SKIP_INIT              (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
57 #define BSP_TZ_CFG_EXCEPTION_RESPONSE     (0)
58 
59 /* CMSIS TrustZone Settings */
60 #define SCB_CSR_AIRCR_INIT                (1)
61 #define SCB_AIRCR_BFHFNMINS_VAL           (0)
62 #define SCB_AIRCR_SYSRESETREQS_VAL        (1)
63 #define SCB_AIRCR_PRIS_VAL                (0)
64 #define TZ_FPU_NS_USAGE                   (1)
65 #ifndef SCB_NSACR_CP10_11_VAL
66 #define SCB_NSACR_CP10_11_VAL             (3U)
67 #endif
68 
69 #ifndef FPU_FPCCR_TS_VAL
70 #define FPU_FPCCR_TS_VAL                  (1U)
71 #endif
72 #define FPU_FPCCR_CLRONRETS_VAL           (1)
73 
74 #ifndef FPU_FPCCR_CLRONRET_VAL
75 #define FPU_FPCCR_CLRONRET_VAL            (1)
76 #endif
77 
78 /* The C-Cache line size that is configured during startup. */
79 #ifndef BSP_CFG_C_CACHE_LINE_SIZE
80 #define BSP_CFG_C_CACHE_LINE_SIZE   (1U)
81 #endif
82 
83 /* Type 1 Peripheral Security Attribution */
84 
85 /* Peripheral Security Attribution Register (PSAR) Settings */
86 #ifndef BSP_TZ_CFG_PSARB
87 #define BSP_TZ_CFG_PSARB (\
88             ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* UARTA0 */ & \
89             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* UARTA1 */ ) | \
90             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4) /* I3C */ | \
91             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5) /* IrDA */ | \
92             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
93             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \
94             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
95             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
96             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
97             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \
98             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
99             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
100             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \
101             0x23b7f5ce) /* Unused */
102 #endif
103 #ifndef BSP_TZ_CFG_PSARC
104 #define BSP_TZ_CFG_PSARC (\
105             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \
106             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
107             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU2 */ | \
108             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4) /* SLCDC */ | \
109             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \
110             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
111             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* CANFD0 */ | \
112             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* RSIP-E11A */ | \
113             0x77ffdee4) /* Unused */
114 #endif
115 #ifndef BSP_TZ_CFG_PSARD
116 #define BSP_TZ_CFG_PSARD (\
117             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \
118             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \
119             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \
120             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
121             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \
122             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
123             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \
124             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \
125             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* ACMPLP */ | \
126             0xdfee87f3) /* Unused */
127 #endif
128 #ifndef BSP_TZ_CFG_PSARE
129 #define BSP_TZ_CFG_PSARE (\
130             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \
131             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \
132             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \
133             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \
134             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \
135             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
136             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \
137             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
138             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \
139             0x3fffff8) /* Unused */
140 #endif
141 #ifndef BSP_TZ_CFG_MSSAR
142 #define BSP_TZ_CFG_MSSAR (\
143             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \
144             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
145             0xfffffffc) /* Unused */
146 #endif
147 
148 /* Type 2 Peripheral Security Attribution */
149 
150 /* Security attribution for Cache registers. */
151 #ifndef BSP_TZ_CFG_CSAR
152 #define BSP_TZ_CFG_CSAR (0xFFFFFFFFU)
153 #endif
154 
155 /* Security attribution for RSTSRn registers. */
156 #ifndef BSP_TZ_CFG_RSTSAR
157 #define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU)
158 #endif
159 
160 /* Security attribution for registers of LVD channels. */
161 #ifndef BSP_TZ_CFG_LVDSAR
162 /* The LVD driver needs to access both channels. This means that the security attribution for both channels must be the same. */
163 #if (RA_NOT_DEFINED > 0) || (RA_NOT_DEFINED > 0)
164 #define BSP_TZ_CFG_LVDSAR (0U)
165 #else
166 #define BSP_TZ_CFG_LVDSAR (3U)
167 #endif
168 #endif
169 
170 /* Security attribution for LPM registers. */
171 #ifndef BSP_TZ_CFG_LPMSAR
172 #define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU)
173 #endif
174 
175 /* Security attribution for CGC registers. */
176 #ifndef BSP_TZ_CFG_CGFSAR
177 #if BSP_CFG_CLOCKS_SECURE
178 /* Protect all CGC registers from Non-secure write access. */
179 #define BSP_TZ_CFG_CGFSAR (0xFBEAF602U)
180 #else
181 /* Allow Secure and Non-secure write access. */
182 #define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU)
183 #endif
184 #endif
185 
186 /* Security attribution for registers for IRQ channels. */
187 #ifndef BSP_TZ_CFG_ICUSARA
188 #define BSP_TZ_CFG_ICUSARA (\
189             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
190             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
191             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
192             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \
193             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \
194             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \
195             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \
196             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \
197             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \
198             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \
199             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
200             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \
201             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
202             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \
203             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \
204             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \
205             0xFFFF0000U)
206 #endif
207 
208 /* Security attribution for NMI registers. */
209 #ifndef BSP_TZ_CFG_ICUSARB
210 #define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
211 #endif
212 
213 /* Security attribution for registers for DMAC channels */
214 #ifndef BSP_TZ_CFG_ICUSARC
215 #define BSP_TZ_CFG_ICUSARC (\
216             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
217             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
218             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
219             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
220             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
221             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
222             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
223             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \
224             0xFFFFFF00U)
225 #endif
226 
227 /* Security attribution registers for SELSR0. */
228 #ifndef BSP_TZ_CFG_ICUSARD
229 #define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
230 #endif
231 
232 /* Security attribution registers for WUPEN0. */
233 #ifndef BSP_TZ_CFG_ICUSARE
234 #define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU)
235 #endif
236 
237 /* Security attribution registers for WUPEN1. */
238 #ifndef BSP_TZ_CFG_ICUSARF
239 #define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU)
240 #endif
241 
242 /* Set DTCSTSAR if the Secure program uses the DTC. */
243 #if RA_NOT_DEFINED == RA_NOT_DEFINED
244 #define BSP_TZ_CFG_DTC_USED (0U)
245 #else
246  #define BSP_TZ_CFG_DTC_USED (1U)
247 #endif
248 
249 /* Security attribution of FLWT and FCKMHZ registers. */
250 #ifndef BSP_TZ_CFG_FSAR
251 /* If the CGC registers are only accessible in Secure mode, than there is no
252  * reason for nonsecure applications to access FLWT and FCKMHZ. */
253 #if BSP_CFG_CLOCKS_SECURE
254 /* Protect FLWT and FCKMHZ registers from nonsecure write access. */
255 #define BSP_TZ_CFG_FSAR (0xFEFEU)
256 #else
257 /* Allow Secure and Non-secure write access. */
258 #define BSP_TZ_CFG_FSAR (0xFFFFU)
259 #endif
260 #endif
261 
262 /* Security attribution for SRAM registers. */
263 #ifndef BSP_TZ_CFG_SRAMSAR
264 #define BSP_TZ_CFG_SRAMSAR (\
265         1 | \
266         4 | \
267         0xFFFFFFFAU)
268 #endif
269 
270 /* Security attribution for the DMAC Bus Master MPU settings. */
271 #ifndef BSP_TZ_CFG_MMPUSARA
272 /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
273 #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
274 #endif
275 
276 /* Security Attribution Register A for BUS Control registers. */
277 #ifndef BSP_TZ_CFG_BUSSARA
278 #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
279 #endif
280 /* Security Attribution Register B for BUS Control registers. */
281 #ifndef BSP_TZ_CFG_BUSSARB
282 #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
283 #endif
284 
285 /* Enable Uninitialized Non-Secure Application Fallback. */
286 #ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
287 #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
288 #endif
289 
290 #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
291 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
292 #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
293 #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
294 #define OFS_SEQ5 (1 << 28) | (1 << 30)
295 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
296 
297 /* Option Function Select Register 1 Security Attribution */
298 #ifndef BSP_CFG_ROM_REG_OFS1_SEL
299 #if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
300 #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF0FFU | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0xF00U : 0U))
301 #else
302 #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF0F8U)
303 #endif
304 #endif
305 
306 #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (2) |  (1 << 8))
307 
308 /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
309 #define BSP_PRV_IELS_ENUM(vector)    CONCAT(ELC_, vector)
310 
311 /* Dual Mode Select Register */
312 #ifndef BSP_CFG_ROM_REG_DUALSEL
313 #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U))
314 #endif
315 
316 /* Block Protection Register 0 */
317 #ifndef BSP_CFG_ROM_REG_BPS0
318 #define BSP_CFG_ROM_REG_BPS0 (~( 0U))
319 #endif
320 /* Block Protection Register 1 */
321 #ifndef BSP_CFG_ROM_REG_BPS1
322 #define BSP_CFG_ROM_REG_BPS1 (0xFFFFFFFFU)
323 #endif
324 /* Block Protection Register 2 */
325 #ifndef BSP_CFG_ROM_REG_BPS2
326 #define BSP_CFG_ROM_REG_BPS2 (~( 0U))
327 #endif
328 /* Block Protection Register 3 */
329 #ifndef BSP_CFG_ROM_REG_BPS3
330 #define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU)
331 #endif
332 /* Permanent Block Protection Register 0 */
333 #ifndef BSP_CFG_ROM_REG_PBPS0
334 #define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
335 #endif
336 /* Permanent Block Protection Register 1 */
337 #ifndef BSP_CFG_ROM_REG_PBPS1
338 #define BSP_CFG_ROM_REG_PBPS1 (0xFFFFFFFFU)
339 #endif
340 /* Permanent Block Protection Register 2 */
341 #ifndef BSP_CFG_ROM_REG_PBPS2
342 #define BSP_CFG_ROM_REG_PBPS2 (~( 0U))
343 #endif
344 /* Permanent Block Protection Register 3 */
345 #ifndef BSP_CFG_ROM_REG_PBPS3
346 #define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU)
347 #endif
348 /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
349 #ifndef BSP_CFG_ROM_REG_BPS_SEL0
350 #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
351 #endif
352 /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
353 #ifndef BSP_CFG_ROM_REG_BPS_SEL1
354 #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
355 #endif
356 /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
357 #ifndef BSP_CFG_ROM_REG_BPS_SEL2
358 #define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2)
359 #endif
360 /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
361 #ifndef BSP_CFG_ROM_REG_BPS_SEL3
362 #define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_BPS3)
363 #endif
364 /* Security Attribution for Bank Select Register */
365 #ifndef BSP_CFG_ROM_REG_BANKSEL_SEL
366 #define BSP_CFG_ROM_REG_BANKSEL_SEL (0xFFFFFFFFU)
367 #endif
368 #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
369 #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
370 #endif
371 
372 #ifdef __cplusplus
373 }
374 #endif
375 #endif /* BSP_MCU_FAMILY_CFG_H_ */
376