1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef BSP_MCU_FAMILY_CFG_H_ 8 #define BSP_MCU_FAMILY_CFG_H_ 9 #include "bsp_mcu_device_pn_cfg.h" 10 #include "bsp_mcu_device_cfg.h" 11 #include "bsp_mcu_info.h" 12 #include "bsp_clock_cfg.h" 13 #define BSP_MCU_GROUP_RA4E2 (1) 14 #define BSP_LOCO_HZ (DT_PROP_OR(DT_NODELABEL(loco), clock_frequency, 0)) 15 #define BSP_MOCO_HZ (DT_PROP_OR(DT_NODELABEL(moco), clock_frequency, 0)) 16 #define BSP_SUB_CLOCK_HZ (DT_PROP_OR(DT_NODELABEL(subclk), clock_frequency, 0)) 17 #if BSP_CFG_HOCO_FREQUENCY == 0 18 #define BSP_HOCO_HZ (16000000) 19 #elif BSP_CFG_HOCO_FREQUENCY == 1 20 #define BSP_HOCO_HZ (18000000) 21 #elif BSP_CFG_HOCO_FREQUENCY == 2 22 #define BSP_HOCO_HZ (20000000) 23 #else 24 #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" 25 #endif 26 27 #define BSP_CFG_FLL_ENABLE (0) 28 29 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) 30 #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) 31 #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) 32 33 #if defined(_RA_TZ_SECURE) 34 #define BSP_TZ_SECURE_BUILD (1) 35 #define BSP_TZ_NONSECURE_BUILD (0) 36 #elif defined(_RA_TZ_NONSECURE) 37 #define BSP_TZ_SECURE_BUILD (0) 38 #define BSP_TZ_NONSECURE_BUILD (1) 39 #else 40 #define BSP_TZ_SECURE_BUILD (0) 41 #define BSP_TZ_NONSECURE_BUILD (0) 42 #endif 43 44 /* TrustZone Settings */ 45 #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) 46 #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) 47 #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) 48 49 /* CMSIS TrustZone Settings */ 50 #define SCB_CSR_AIRCR_INIT (1) 51 #define SCB_AIRCR_BFHFNMINS_VAL (0) 52 #define SCB_AIRCR_SYSRESETREQS_VAL (1) 53 #define SCB_AIRCR_PRIS_VAL (0) 54 #define TZ_FPU_NS_USAGE (1) 55 #ifndef SCB_NSACR_CP10_11_VAL 56 #define SCB_NSACR_CP10_11_VAL (3U) 57 #endif 58 59 #ifndef FPU_FPCCR_TS_VAL 60 #define FPU_FPCCR_TS_VAL (1U) 61 #endif 62 #define FPU_FPCCR_CLRONRETS_VAL (1) 63 64 #ifndef FPU_FPCCR_CLRONRET_VAL 65 #define FPU_FPCCR_CLRONRET_VAL (1) 66 #endif 67 68 /* The C-Cache line size that is configured during startup. */ 69 #ifndef BSP_CFG_C_CACHE_LINE_SIZE 70 #define BSP_CFG_C_CACHE_LINE_SIZE (1U) 71 #endif 72 73 /* Type 1 Peripheral Security Attribution */ 74 75 /* Peripheral Security Attribution Register (PSAR) Settings */ 76 #ifndef BSP_TZ_CFG_PSARB 77 #define BSP_TZ_CFG_PSARB (\ 78 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CEC */ | \ 79 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4) /* I3C0 */ | \ 80 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ 81 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ 82 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ 83 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ 84 (((1 > 0) ? 0U : 1U) << 31) /* SCI0 */ | \ 85 0x7FB3F7E7) /* Unused */ 86 #endif 87 #ifndef BSP_TZ_CFG_PSARC 88 #define BSP_TZ_CFG_PSARC (\ 89 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ 90 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ 91 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ 92 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ 93 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* TFU */ | \ 94 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* CANFD0 */ | \ 95 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* TRNG */ | \ 96 0xE7FFDEFC) /* Unused */ 97 #endif 98 #ifndef BSP_TZ_CFG_PSARD 99 #define BSP_TZ_CFG_PSARD (\ 100 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \ 101 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ 102 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ 103 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ 104 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ 105 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ 106 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ 107 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \ 108 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ 109 0xFFAE87F3) /* Unused */ 110 #endif 111 #ifndef BSP_TZ_CFG_PSARE 112 #define BSP_TZ_CFG_PSARE (\ 113 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \ 114 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ 115 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \ 116 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ 117 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ 118 (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ 119 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \ 120 0x33FFFFF8) /* Unused */ 121 #endif 122 #ifndef BSP_TZ_CFG_MSSAR 123 #define BSP_TZ_CFG_MSSAR (\ 124 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \ 125 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ 126 0xfffffffc) /* Unused */ 127 #endif 128 129 /* Type 2 Peripheral Security Attribution */ 130 131 /* Security attribution for Cache registers. */ 132 #ifndef BSP_TZ_CFG_CSAR 133 #define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) 134 #endif 135 136 /* Security attribution for RSTSRn registers. */ 137 #ifndef BSP_TZ_CFG_RSTSAR 138 #define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) 139 #endif 140 141 /* Security attribution for registers of LVD channels. */ 142 #ifndef BSP_TZ_CFG_LVDSAR 143 #define BSP_TZ_CFG_LVDSAR (\ 144 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ 145 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \ 146 0xFFFFFFFCU) 147 #endif 148 149 /* Security attribution for LPM registers. */ 150 #ifndef BSP_TZ_CFG_LPMSAR 151 #define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFDCEAU : 0xFFFFFFFFU) 152 #endif 153 /* Deep Standby Interrupt Factor Security Attribution Register. */ 154 #ifndef BSP_TZ_CFG_DPFSAR 155 #define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xFAE0A00CU : 0xFFFFFFFFU) 156 #endif 157 158 /* Security attribution for CGC registers. */ 159 #ifndef BSP_TZ_CFG_CGFSAR 160 #if BSP_CFG_CLOCKS_SECURE 161 /* Protect all CGC registers from Non-secure write access. */ 162 #define BSP_TZ_CFG_CGFSAR (0xFFEAF602U) 163 #else 164 /* Allow Secure and Non-secure write access. */ 165 #define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU) 166 #endif 167 #endif 168 169 /* Security attribution for Battery Backup registers. */ 170 #ifndef BSP_TZ_CFG_BBFSAR 171 #define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) 172 #endif 173 174 /* Security attribution for registers for IRQ channels. */ 175 #ifndef BSP_TZ_CFG_ICUSARA 176 #define BSP_TZ_CFG_ICUSARA (\ 177 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ 178 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ 179 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ 180 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ 181 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ 182 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ 183 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ 184 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ 185 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ 186 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ 187 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ 188 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ 189 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ 190 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ 191 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ 192 0xFFFF8000U) 193 #endif 194 195 /* Security attribution for NMI registers. */ 196 #ifndef BSP_TZ_CFG_ICUSARB 197 #define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ 198 #endif 199 200 /* Security attribution for registers for DMAC channels */ 201 #ifndef BSP_TZ_CFG_ICUSARC 202 #define BSP_TZ_CFG_ICUSARC (\ 203 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ 204 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ 205 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ 206 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ 207 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ 208 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ 209 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ 210 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \ 211 0xFFFFFF00U) 212 #endif 213 214 /* Security attribution registers for SELSR0. */ 215 #ifndef BSP_TZ_CFG_ICUSARD 216 #define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) 217 #endif 218 219 /* Security attribution registers for WUPEN0. */ 220 #ifndef BSP_TZ_CFG_ICUSARE 221 #define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x84F2FFFFU : 0xFFFFFFFFU) 222 #endif 223 224 /* Security attribution registers for WUPEN1. */ 225 #ifndef BSP_TZ_CFG_ICUSARF 226 #define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFF7FFU : 0xFFFFFFFFU) 227 #endif 228 229 /* Set DTCSTSAR if the Secure program uses the DTC. */ 230 #if RA_NOT_DEFINED == RA_NOT_DEFINED 231 #define BSP_TZ_CFG_DTC_USED (0U) 232 #else 233 #define BSP_TZ_CFG_DTC_USED (1U) 234 #endif 235 236 /* Security attribution of FLWT and FCKMHZ registers. */ 237 #ifndef BSP_TZ_CFG_FSAR 238 /* If the CGC registers are only accessible in Secure mode, than there is no 239 * reason for nonsecure applications to access FLWT and FCKMHZ. 240 */ 241 #if BSP_CFG_CLOCKS_SECURE 242 /* Protect FLWT and FCKMHZ registers from nonsecure write access. */ 243 #define BSP_TZ_CFG_FSAR (0xFEFEU) 244 #else 245 /* Allow Secure and Non-secure write access. */ 246 #define BSP_TZ_CFG_FSAR (0xFFFFU) 247 #endif 248 #endif 249 250 /* Security attribution for SRAM registers. */ 251 #ifndef BSP_TZ_CFG_SRAMSAR 252 /* If the CGC registers are only accessible in Secure mode, 253 * than there is no reason for Non Secure applications to access 254 * SRAM0WTEN and therefore there is no reason to access PRCR2. 255 */ 256 #define BSP_TZ_CFG_SRAMSAR (\ 257 1 | \ 258 ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ 259 4 | \ 260 0xFFFFFFF8U) 261 #endif 262 263 /* Security attribution for Standby RAM registers. */ 264 #ifndef BSP_TZ_CFG_STBRAMSAR 265 #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) 266 #endif 267 268 /* Security attribution for the DMAC Bus Master MPU settings. */ 269 #ifndef BSP_TZ_CFG_MMPUSARA 270 /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ 271 #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) 272 #endif 273 274 /* Security Attribution Register A for BUS Control registers. */ 275 #ifndef BSP_TZ_CFG_BUSSARA 276 #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) 277 #endif 278 /* Security Attribution Register B for BUS Control registers. */ 279 #ifndef BSP_TZ_CFG_BUSSARB 280 #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) 281 #endif 282 283 /* Enable Uninitialized Non-Secure Application Fallback. */ 284 #ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK 285 #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) 286 #endif 287 288 #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) 289 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) 290 #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) 291 #define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26) 292 #define OFS_SEQ5 (1 << 28) | (1 << 30) 293 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) 294 295 /* Option Function Select Register 1 Security Attribution */ 296 #ifndef BSP_CFG_ROM_REG_OFS1_SEL 297 #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFFFFFU) 298 #endif 299 300 #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) 301 302 /* Used to create IELS values for the interrupt initialization table 303 * g_interrupt_event_link_select. 304 */ 305 #define BSP_PRV_IELS_ENUM(vector) CONCAT(ELC_, vector) 306 307 /* Block Protection Register 0 */ 308 #ifndef BSP_CFG_ROM_REG_BPS0 309 #define BSP_CFG_ROM_REG_BPS0 (~(0U)) 310 #endif 311 /* Block Protection Register 1 */ 312 #ifndef BSP_CFG_ROM_REG_BPS1 313 #define BSP_CFG_ROM_REG_BPS1 (0xFFFFFFFFU) 314 #endif 315 /* Block Protection Register 2 */ 316 #ifndef BSP_CFG_ROM_REG_BPS2 317 #define BSP_CFG_ROM_REG_BPS2 (0xFFFFFFFFU) 318 #endif 319 /* Block Protection Register 3 */ 320 #ifndef BSP_CFG_ROM_REG_BPS3 321 #define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) 322 #endif 323 /* Permanent Block Protection Register 0 */ 324 #ifndef BSP_CFG_ROM_REG_PBPS0 325 #define BSP_CFG_ROM_REG_PBPS0 (~(0U)) 326 #endif 327 /* Permanent Block Protection Register 1 */ 328 #ifndef BSP_CFG_ROM_REG_PBPS1 329 #define BSP_CFG_ROM_REG_PBPS1 (0xFFFFFFFFU) 330 #endif 331 /* Permanent Block Protection Register 2 */ 332 #ifndef BSP_CFG_ROM_REG_PBPS2 333 #define BSP_CFG_ROM_REG_PBPS2 (0xFFFFFFFFU) 334 #endif 335 /* Permanent Block Protection Register 3 */ 336 #ifndef BSP_CFG_ROM_REG_PBPS3 337 #define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) 338 #endif 339 /* Security Attribution for Block Protection Register 0 - Not supported by this MCU */ 340 #ifndef BSP_CFG_ROM_REG_BPS_SEL0 341 #define BSP_CFG_ROM_REG_BPS_SEL0 (0XFFFFFFFFU) 342 #endif 343 /* Security Attribution for Block Protection Register 1 - Not supported by this MCU */ 344 #ifndef BSP_CFG_ROM_REG_BPS_SEL1 345 #define BSP_CFG_ROM_REG_BPS_SEL1 (0XFFFFFFFFU) 346 #endif 347 /* Security Attribution for Block Protection Register 2 - Not supported by this MCU */ 348 #ifndef BSP_CFG_ROM_REG_BPS_SEL2 349 #define BSP_CFG_ROM_REG_BPS_SEL2 (0XFFFFFFFFU) 350 #endif 351 /* Security Attribution for Block Protection Register 3 - Not supported by this MCU */ 352 #ifndef BSP_CFG_ROM_REG_BPS_SEL3 353 #define BSP_CFG_ROM_REG_BPS_SEL3 (0XFFFFFFFFU) 354 #endif 355 #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT 356 #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) 357 #endif 358 359 /* 360 * ID Code 361 * Note: To permanently lock and disable the debug interface define the 362 * BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. 363 * WARNING: This will disable debug access to the part and cannot be 364 * reversed by a debug probe. 365 */ 366 #if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) 367 #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) 368 #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) 369 #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) 370 #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) 371 #else 372 /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ 373 #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) 374 #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) 375 #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) 376 #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) 377 #endif 378 379 #endif /* BSP_MCU_FAMILY_CFG_H_ */ 380
