1 /*
2  * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef BSP_MCU_FAMILY_CFG_H_
8 #define BSP_MCU_FAMILY_CFG_H_
9 #include "bsp_mcu_device_pn_cfg.h"
10 #include "bsp_mcu_device_cfg.h"
11 #include "bsp_mcu_info.h"
12 #include "bsp_clock_cfg.h"
13 #define BSP_MCU_GROUP_RA4E1 (1)
14 #define BSP_LOCO_HZ                 (DT_PROP_OR(DT_NODELABEL(loco), clock_frequency, 0))
15 #define BSP_MOCO_HZ                 (DT_PROP_OR(DT_NODELABEL(moco), clock_frequency, 0))
16 #define BSP_SUB_CLOCK_HZ            (DT_PROP_OR(DT_NODELABEL(subclk), clock_frequency, 0))
17 #if   BSP_CFG_HOCO_FREQUENCY == 0
18 #define BSP_HOCO_HZ                 (16000000)
19 #elif BSP_CFG_HOCO_FREQUENCY == 1
20 #define BSP_HOCO_HZ                 (18000000)
21 #elif BSP_CFG_HOCO_FREQUENCY == 2
22 #define BSP_HOCO_HZ                 (20000000)
23 #else
24 #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
25 #endif
26 
27 #define BSP_CFG_FLL_ENABLE                 (0)
28 
29 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
30 #define BSP_VECTOR_TABLE_MAX_ENTRIES       (112U)
31 #define BSP_CFG_INLINE_IRQ_FUNCTIONS       (1)
32 
33 #if defined(_RA_TZ_SECURE)
34 #define BSP_TZ_SECURE_BUILD           (1)
35 #define BSP_TZ_NONSECURE_BUILD        (0)
36 #elif defined(_RA_TZ_NONSECURE)
37 #define BSP_TZ_SECURE_BUILD           (0)
38 #define BSP_TZ_NONSECURE_BUILD        (1)
39 #else
40 #define BSP_TZ_SECURE_BUILD           (0)
41 #define BSP_TZ_NONSECURE_BUILD        (0)
42 #endif
43 
44 /* TrustZone Settings */
45 #define BSP_TZ_CFG_INIT_SECURE_ONLY       (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
46 #define BSP_TZ_CFG_SKIP_INIT              (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
47 #define BSP_TZ_CFG_EXCEPTION_RESPONSE     (0)
48 
49 /* CMSIS TrustZone Settings */
50 #define SCB_CSR_AIRCR_INIT                (1)
51 #define SCB_AIRCR_BFHFNMINS_VAL           (0)
52 #define SCB_AIRCR_SYSRESETREQS_VAL        (1)
53 #define SCB_AIRCR_PRIS_VAL                (0)
54 #define TZ_FPU_NS_USAGE                   (1)
55 #ifndef SCB_NSACR_CP10_11_VAL
56 #define SCB_NSACR_CP10_11_VAL             (3U)
57 #endif
58 
59 #ifndef FPU_FPCCR_TS_VAL
60 #define FPU_FPCCR_TS_VAL                  (1U)
61 #endif
62 #define FPU_FPCCR_CLRONRETS_VAL           (1)
63 
64 #ifndef FPU_FPCCR_CLRONRET_VAL
65 #define FPU_FPCCR_CLRONRET_VAL            (1)
66 #endif
67 
68 /* Type 1 Peripheral Security Attribution */
69 
70 /* Peripheral Security Attribution Register (PSAR) Settings */
71 #ifndef BSP_TZ_CFG_PSARB
72 #define BSP_TZ_CFG_PSARB (\
73             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \
74             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \
75             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \
76             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
77             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \
78             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
79             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
80             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
81             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \
82             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
83             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \
84             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
85             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \
86             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
87             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \
88             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
89             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \
90             0x33f4f9) /* Unused */
91 #endif
92 #ifndef BSP_TZ_CFG_PSARC
93 #define BSP_TZ_CFG_PSARC (\
94             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \
95             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
96             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \
97             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \
98             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \
99             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
100             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \
101             0x7fffcef4) /* Unused */
102 #endif
103 #ifndef BSP_TZ_CFG_PSARD
104 #define BSP_TZ_CFG_PSARD (\
105             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \
106             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \
107             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \
108             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \
109             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \
110             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
111             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \
112             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
113             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \
114             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \
115             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \
116             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \
117             0xffae07f0) /* Unused */
118 #endif
119 #ifndef BSP_TZ_CFG_PSARE
120 #define BSP_TZ_CFG_PSARE (\
121             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \
122             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \
123             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \
124             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \
125             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \
126             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
127             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \
128             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
129             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \
130             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \
131             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \
132             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
133             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \
134             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
135             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \
136             0x3f3ff8) /* Unused */
137 #endif
138 #ifndef BSP_TZ_CFG_MSSAR
139 #define BSP_TZ_CFG_MSSAR (\
140             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \
141             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
142             0xfffffffc) /* Unused */
143 #endif
144 
145 /* Type 2 Peripheral Security Attribution */
146 
147 /* Security attribution for RSTSRn registers. */
148 #ifndef BSP_TZ_CFG_RSTSAR
149 #define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU)
150 #endif
151 
152 /* Security attribution for registers of LVD channels. */
153 #ifndef BSP_TZ_CFG_LVDSAR
154 #define BSP_TZ_CFG_LVDSAR (\
155             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
156             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \
157             0xFFFFFFFCU)
158 #endif
159 
160 /* Security attribution for LPM registers. */
161 #ifndef BSP_TZ_CFG_LPMSAR
162 #define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFDCEAU : 0xFFFFFFFFU)
163 #endif
164 /* Deep Standby Interrupt Factor Security Attribution Register. */
165 #ifndef BSP_TZ_CFG_DPFSAR
166 #define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E0FC0CU : 0xFFFFFFFFU)
167 #endif
168 
169 /* Security attribution for CGC registers. */
170 #ifndef BSP_TZ_CFG_CGFSAR
171 #if BSP_CFG_CLOCKS_SECURE
172 /* Protect all CGC registers from Non-secure write access. */
173 #define BSP_TZ_CFG_CGFSAR (0xFFFEE402U)
174 #else
175 /* Allow Secure and Non-secure write access. */
176 #define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU)
177 #endif
178 #endif
179 
180 /* Security attribution for Battery Backup registers. */
181 #ifndef BSP_TZ_CFG_BBFSAR
182 #define BSP_TZ_CFG_BBFSAR (0x00FFFFFF)
183 #endif
184 
185 /* Security attribution for registers for IRQ channels. */
186 #ifndef BSP_TZ_CFG_ICUSARA
187 #define BSP_TZ_CFG_ICUSARA (\
188             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
189             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
190             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
191             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \
192             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \
193             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \
194             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \
195             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \
196             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \
197             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \
198             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
199             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \
200             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
201             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \
202             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \
203             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \
204             0xFFFF0000U)
205 #endif
206 
207 /* Security attribution for NMI registers. */
208 #ifndef BSP_TZ_CFG_ICUSARB
209 #define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
210 #endif
211 
212 /* Security attribution for registers for DMAC channels */
213 #ifndef BSP_TZ_CFG_ICUSARC
214 #define BSP_TZ_CFG_ICUSARC (\
215             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
216             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
217             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
218             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
219             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
220             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
221             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
222             (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \
223             0xFFFFFF00U)
224 #endif
225 
226 /* Security attribution registers for SELSR0. */
227 #ifndef BSP_TZ_CFG_ICUSARD
228 #define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
229 #endif
230 
231 /* Security attribution registers for WUPEN0. */
232 #ifndef BSP_TZ_CFG_ICUSARE
233 #define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU)
234 #endif
235 
236 /* Security attribution registers for WUPEN1. */
237 #ifndef BSP_TZ_CFG_ICUSARF
238 #define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU)
239 #endif
240 
241 /* Set DTCSTSAR if the Secure program uses the DTC. */
242 #if RA_NOT_DEFINED == RA_NOT_DEFINED
243 #define BSP_TZ_CFG_DTC_USED (0U)
244 #else
245  #define BSP_TZ_CFG_DTC_USED (1U)
246 #endif
247 
248 /* Security attribution of FLWT and FCKMHZ registers. */
249 #ifndef BSP_TZ_CFG_FSAR
250 /* If the CGC registers are only accessible in Secure mode, than there is no
251  * reason for nonsecure applications to access FLWT and FCKMHZ. */
252 #if BSP_CFG_CLOCKS_SECURE
253 /* Protect FLWT and FCKMHZ registers from nonsecure write access. */
254 #define BSP_TZ_CFG_FSAR (0xFEFEU)
255 #else
256 /* Allow Secure and Non-secure write access. */
257 #define BSP_TZ_CFG_FSAR (0xFFFFU)
258 #endif
259 #endif
260 
261 /* Security attribution for SRAM registers. */
262 #ifndef BSP_TZ_CFG_SRAMSAR
263 /* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access
264  * SRAM0WTEN and therefore there is no reason to access PRCR2. */
265 #define BSP_TZ_CFG_SRAMSAR (\
266         1 | \
267         ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
268         4 | \
269         0xFFFFFFF8U)
270 #endif
271 
272 /* Security attribution for Standby RAM registers. */
273 #ifndef BSP_TZ_CFG_STBRAMSAR
274 #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
275 #endif
276 
277 /* Security attribution for the DMAC Bus Master MPU settings. */
278 #ifndef BSP_TZ_CFG_MMPUSARA
279 /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
280 #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
281 #endif
282 
283 /* Security Attribution Register A for BUS Control registers. */
284 #ifndef BSP_TZ_CFG_BUSSARA
285 #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
286 #endif
287 /* Security Attribution Register B for BUS Control registers. */
288 #ifndef BSP_TZ_CFG_BUSSARB
289 #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
290 #endif
291 
292 /* Enable Uninitialized Non-Secure Application Fallback. */
293 #ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
294 #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
295 #endif
296 
297 #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
298 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
299 #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
300 #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
301 #define OFS_SEQ5 (1 << 28) | (1 << 30)
302 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
303 
304 /* Option Function Select Register 1 Security Attribution */
305 #ifndef BSP_CFG_ROM_REG_OFS1_SEL
306 #if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
307             #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U))
308 #else
309 #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
310 #endif
311 #endif
312 
313 #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) |  (0 << 8))
314 
315 /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
316 #define BSP_PRV_IELS_ENUM(vector)    CONCAT(ELC_, vector)
317 
318 /* Dual Mode Select Register */
319 #ifndef BSP_CFG_ROM_REG_DUALSEL
320 #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFFFU)
321 #endif
322 /* Block Protection Register 0 */
323 #ifndef BSP_CFG_ROM_REG_BPS0
324 #define BSP_CFG_ROM_REG_BPS0 (~( 0U))
325 #endif
326 /* Block Protection Register 1 */
327 #ifndef BSP_CFG_ROM_REG_BPS1
328 #define BSP_CFG_ROM_REG_BPS1 (0xFFFFFFFFU)
329 #endif
330 /* Block Protection Register 2 */
331 #ifndef BSP_CFG_ROM_REG_BPS2
332 #define BSP_CFG_ROM_REG_BPS2 (0xFFFFFFFFU)
333 #endif
334 /* Block Protection Register 3 */
335 #ifndef BSP_CFG_ROM_REG_BPS3
336 #define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU)
337 #endif
338 /* Permanent Block Protection Register 0 */
339 #ifndef BSP_CFG_ROM_REG_PBPS0
340 #define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
341 #endif
342 /* Permanent Block Protection Register 1 */
343 #ifndef BSP_CFG_ROM_REG_PBPS1
344 #define BSP_CFG_ROM_REG_PBPS1 (0xFFFFFFFFU)
345 #endif
346 /* Permanent Block Protection Register 2 */
347 #ifndef BSP_CFG_ROM_REG_PBPS2
348 #define BSP_CFG_ROM_REG_PBPS2 (0xFFFFFFFFU)
349 #endif
350 /* Permanent Block Protection Register 3 */
351 #ifndef BSP_CFG_ROM_REG_PBPS3
352 #define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU)
353 #endif
354 /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
355 #ifndef BSP_CFG_ROM_REG_BPS_SEL0
356 #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
357 #endif
358 /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
359 #ifndef BSP_CFG_ROM_REG_BPS_SEL1
360 #define BSP_CFG_ROM_REG_BPS_SEL1 (0xFFFFFFFFU)
361 #endif
362 /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
363 #ifndef BSP_CFG_ROM_REG_BPS_SEL2
364 #define BSP_CFG_ROM_REG_BPS_SEL2 (0xFFFFFFFFU)
365 #endif
366 /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
367 #ifndef BSP_CFG_ROM_REG_BPS_SEL3
368 #define BSP_CFG_ROM_REG_BPS_SEL3 (0xFFFFFFFFU)
369 #endif
370 #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
371 #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
372 #endif
373 
374 #endif /* BSP_MCU_FAMILY_CFG_H_ */
375