1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * Copyright (c) 2024 TOKITA Hiroshi 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 #ifndef BSP_MCU_FAMILY_CFG_H_ 8 #define BSP_MCU_FAMILY_CFG_H_ 9 #include "bsp_mcu_device_pn_cfg.h" 10 #include "bsp_mcu_device_cfg.h" 11 #include "bsp_mcu_info.h" 12 #include "bsp_clock_cfg.h" 13 #define BSP_MCU_GROUP_RA2A1 (1) 14 #define BSP_LOCO_HZ (DT_PROP_OR(DT_NODELABEL(loco), clock_frequency, 0)) 15 #define BSP_MOCO_HZ (DT_PROP_OR(DT_NODELABEL(moco), clock_frequency, 0)) 16 #define BSP_SUB_CLOCK_HZ (DT_PROP_OR(DT_NODELABEL(subclk), clock_frequency, 0)) 17 #if BSP_CFG_HOCO_FREQUENCY == 0 18 #define BSP_HOCO_HZ (24000000) 19 #elif BSP_CFG_HOCO_FREQUENCY == 2 20 #define BSP_HOCO_HZ (32000000) 21 #elif BSP_CFG_HOCO_FREQUENCY == 4 22 #define BSP_HOCO_HZ (48000000) 23 #elif BSP_CFG_HOCO_FREQUENCY == 5 24 #define BSP_HOCO_HZ (64000000) 25 #else 26 #error \ 27 "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" 28 #endif 29 30 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) 31 #define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) 32 #define BSP_CFG_INLINE_IRQ_FUNCTIONS (0) 33 34 #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) 35 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) 36 #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) 37 #define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26) 38 #define OFS_SEQ5 (1 << 28) | (1 << 30) 39 #define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) 40 #define BSP_CFG_ROM_REG_OFS0 \ 41 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) 42 #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) 43 #define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) 44 #define BSP_CFG_ROM_REG_MPU_PC0_START (0x000FFFFC) 45 #define BSP_CFG_ROM_REG_MPU_PC0_END (0x000FFFFF) 46 #define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) 47 #define BSP_CFG_ROM_REG_MPU_PC1_START (0x000FFFFC) 48 #define BSP_CFG_ROM_REG_MPU_PC1_END (0x000FFFFF) 49 #define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) 50 #define BSP_CFG_ROM_REG_MPU_REGION0_START (0x000FFFFC) 51 #define BSP_CFG_ROM_REG_MPU_REGION0_END (0x000FFFFF) 52 #define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) 53 #define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) 54 #define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) 55 #define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) 56 #define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) 57 #define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) 58 #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) 59 #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) 60 #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) 61 #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT 62 #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) 63 #endif 64 /* Used to create IELS values for the interrupt initialization table 65 * g_interrupt_event_link_select. */ 66 #define BSP_PRV_IELS_ENUM(vector) CONCAT(ELC_, vector) 67 68 /* 69 ID Code 70 Note: To lock and disable the debug interface define BSP_ID_CODE_LOCKED in 71 compiler settings. WARNING: This will disable debug access to the part. 72 However, ALeRASE command will be accepted, which will clear (reset) the ID 73 code. After clearing ID code, debug access will be enabled. 74 */ 75 #if defined(BSP_ID_CODE_LOCKED) 76 #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) 77 #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) 78 #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) 79 #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) 80 #else 81 /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ 82 #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) 83 #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) 84 #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) 85 #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) 86 #endif 87 88 #endif /* BSP_MCU_FAMILY_CFG_H_ */ 89
