1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef BSP_FEATURE_H 8 #define BSP_FEATURE_H 9 10 /*********************************************************************************************************************** 11 * Includes <System Includes> , "Project Includes" 12 **********************************************************************************************************************/ 13 14 /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 15 FSP_HEADER 16 17 /*********************************************************************************************************************** 18 * Macro definitions 19 **********************************************************************************************************************/ 20 #define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U) 21 #define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U) 22 #define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKADC) 23 #define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1U) 24 #define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U) 25 #define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U) 26 #define BSP_FEATURE_ADC_HAS_PGA (1U) 27 #define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (1U) 28 #define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_UNIT_NUM (1U) 29 #define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U) 30 #define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12U) 31 #define BSP_FEATURE_ADC_REGISTER_MASK_TYPE (1U) 32 #define BSP_FEATURE_ADC_SAMPLE_STATE_COUNT_TYPE (1U) 33 #define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150U) 34 #define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0U) 35 #define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (0U) 36 #define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1U) 37 #define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0x00000FFFU) 38 #define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1U) 39 #define BSP_FEATURE_ADC_TSN_SLOPE (4000U) 40 #define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x000FU) // 0 to 3 in unit0 41 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x00FFU) // 0 to 7 in unit1 42 #define BSP_FEATURE_ADC_UNIT_2_CHANNELS (0x0000U) // unit2 is unsupported 43 #define BSP_FEATURE_ADC_UNIT (2U) 44 #define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U) 45 46 #define BSP_FEATURE_ADDRESS_EXPANDER_SUPPORTED (0U) 47 48 #define BSP_FEATURE_BSC_32BIT_DATA_BUS_WIDTH_SUPPORTED (0U) 49 #define BSP_FEATURE_BSC_HAS_CS_MIRROR_AREA (1U) 50 #define BSP_FEATURE_BSC_NOR_CS0_BASE_ADDRESS (0x00000000U) 51 #define BSP_FEATURE_BSC_NOR_CS2_BASE_ADDRESS (0x00000000U) 52 #define BSP_FEATURE_BSC_NOR_CS3_BASE_ADDRESS (0x00000000U) 53 #define BSP_FEATURE_BSC_NOR_CS5_BASE_ADDRESS (0x00000000U) 54 #define BSP_FEATURE_BSC_NOR_CS0_BASE_MIRROR_ADDRESS (0x50000000U) 55 #define BSP_FEATURE_BSC_NOR_CS2_BASE_MIRROR_ADDRESS (0x54000000U) 56 #define BSP_FEATURE_BSC_NOR_CS3_BASE_MIRROR_ADDRESS (0x58000000U) 57 #define BSP_FEATURE_BSC_NOR_CS5_BASE_MIRROR_ADDRESS (0x5C000000U) 58 59 #define BSP_FEATURE_BSP_AFMT_UNIT (0U) 60 #define BSP_FEATURE_BSP_BISS_UNIT (0U) 61 #define BSP_FEATURE_BSP_BOOT_PARAMETER (1U) 62 #define BSP_FEATURE_BSP_CA55_CORE_NUM (0U) 63 #define BSP_FEATURE_BSP_CR52_CORE_NUM (1U) 64 #define BSP_FEATURE_BSP_DDRSS_SUPPORTED (0U) 65 #define BSP_FEATURE_BSP_ENCOUT_SUPPORTED (0U) 66 #define BSP_FEATURE_BSP_ENDAT_UNIT (0U) 67 #define BSP_FEATURE_BSP_EVENT_NUM_MAX (500) 68 #define BSP_FEATURE_BSP_HAS_CR52_CPU1_TCM (0U) 69 #define BSP_FEATURE_BSP_HAS_CR52_CPU1_LLPP (0U) 70 #define BSP_FEATURE_BSP_HAS_SYSTEMRAM_MIRROR_AREA (1U) 71 #define BSP_FEATURE_BSP_HDSL_UNIT (0U) 72 #define BSP_FEATURE_BSP_IO_REGION_ADDRESS_DIFF_DEDICATED (0U) 73 #define BSP_FEATURE_BSP_IO_REGION_ADDRESS_DIFF_SELECTABLE (R_PORT_SR_BASE - R_PORT_NSR_BASE) 74 #define BSP_FEATURE_BSP_IO_SELECTABLE_NON_SAFETY_BASE (R_PORT_NSR_BASE) 75 #define BSP_FEATURE_BSP_IO_SELECTABLE_NON_SAFETY_PORT (25U) 76 #define BSP_FEATURE_BSP_IRQ_CR52_SEL_SUPPORTED (0U) 77 #define BSP_FEATURE_BSP_IRQ_ENCIF_SEL_SUPPORTED (0U) 78 #define BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED (0U) 79 #define BSP_FEATURE_BSP_IRQ_PRIORITY_MASK (0xF8U) 80 #define BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT (3U) 81 #define BSP_FEATURE_BSP_LCDC_SUPPORTED (0U) 82 #define BSP_FEATURE_BSP_MASTER_MPU_REGION_TYPE (1U) 83 #define BSP_FEATURE_BSP_MASTER_MPU0_SUPPORTED (1U) 84 #define BSP_FEATURE_BSP_MASTER_MPU1_SUPPORTED (1U) 85 #define BSP_FEATURE_BSP_MASTER_MPU2_SUPPORTED (1U) 86 #define BSP_FEATURE_BSP_MASTER_MPU3_SUPPORTED (1U) 87 #define BSP_FEATURE_BSP_MASTER_MPU4_SUPPORTED (1U) 88 #define BSP_FEATURE_BSP_MASTER_MPU5_SUPPORTED (0U) 89 #define BSP_FEATURE_BSP_MASTER_MPU6_SUPPORTED (1U) 90 #define BSP_FEATURE_BSP_MASTER_MPU7_SUPPORTED (1U) 91 #define BSP_FEATURE_BSP_MASTER_MPU8_SUPPORTED (1U) 92 #define BSP_FEATURE_BSP_MASTER_MPU9_SUPPORTED (0U) 93 #define BSP_FEATURE_BSP_MASTER_MPU10_SUPPORTED (0U) 94 #define BSP_FEATURE_BSP_MASTER_MPU11_SUPPORTED (0U) 95 #define BSP_FEATURE_BSP_MASTER_MPU12_SUPPORTED (0U) 96 #define BSP_FEATURE_BSP_MASTER_MPU13_SUPPORTED (0U) 97 #define BSP_FEATURE_BSP_MASTER_MPU14_SUPPORTED (0U) 98 #define BSP_FEATURE_BSP_MASTER_MPU15_SUPPORTED (0U) 99 #define BSP_FEATURE_BSP_MODULE_RESET_DUMMY_READ_COUNT (3U) 100 #define BSP_FEATURE_BSP_MSTP_CA55_HAS_MSTPCRN (0U) 101 #define BSP_FEATURE_BSP_MSTP_CR52_CPU1_HAS_MSTPCRH (0U) 102 #define BSP_FEATURE_BSP_MSTP_CR52_HAS_MSTPCRN (0U) 103 #define BSP_FEATURE_BSP_NON_SELECTABLE_INTERRUPT_EVENT_NUM (448) 104 #define BSP_FEATURE_BSP_PCIE_SUPPORTED (0U) 105 #define BSP_FEATURE_BSP_SDHI_SUPPORTED (0U) 106 #define BSP_FEATURE_BSP_SELECTABLE_INTERRUPT_EVENT_NUM (0) 107 #define BSP_FEATURE_BSP_SELECTABLE_INTERRUPT_START (0) 108 #define BSP_FEATURE_BSP_SEMAPHORE_SUPPORTED (0U) 109 #define BSP_FEATURE_BSP_SHOSTIF_SUPPORTED (1U) 110 #define BSP_FEATURE_BSP_PHOSTIF_SUPPORTED (1U) 111 #define BSP_FEATURE_BSP_SLAVE_STOP_SUPPORTED (0U) 112 #define BSP_FEATURE_BSP_TRACE_CLOCK_SUPPORTED (1U) 113 114 #define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) 115 #define BSP_FEATURE_CAN_CLOCK (0U) 116 #define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) 117 #define BSP_FEATURE_CAN_NUM_CHANNELS (2U) 118 119 #define BSP_FEATURE_CANFD_NUM_CHANNELS (2U) 120 #define BSP_FEATURE_CANFD_NUM_INSTANCES (1U) 121 122 #define BSP_FEATURE_CGC_CKIO_CLOCK_FREQ_TYPE (1U) 123 #define BSP_FEATURE_CGC_CLMA_UNIT (4U) 124 #define BSP_FEATURE_CGC_CLOCK_SOURCE_NUM (3) 125 #define BSP_FEATURE_CGC_CR52_ATCM_0WAIT_MAX_FREQ_HZ (400000000U) 126 #define BSP_FEATURE_CGC_CR52_CLOCK_TYPE (1U) 127 #define BSP_FEATURE_CGC_HAS_BCLK (1U) 128 #define BSP_FEATURE_CGC_HAS_FCLK (1U) 129 #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) 130 #define BSP_FEATURE_CGC_HAS_FLWT (1U) 131 #define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) 132 #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) 133 #define BSP_FEATURE_CGC_HAS_PCLKA (1U) 134 #define BSP_FEATURE_CGC_HAS_PCLKB (1U) 135 #define BSP_FEATURE_CGC_HAS_PCLKC (1U) 136 #define BSP_FEATURE_CGC_HAS_PCLKD (1U) 137 #define BSP_FEATURE_CGC_HAS_PLL (1U) 138 #define BSP_FEATURE_CGC_HAS_PLL2 (0U) 139 #define BSP_FEATURE_CGC_HAS_PLL3 (0U) 140 #define BSP_FEATURE_CGC_HAS_PLL4 (0U) 141 #define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0U) 142 #define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U) 143 #define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) 144 #define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) 145 #define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) 146 #define BSP_FEATURE_CGC_LOCO_CONTROL_ADDRESS (0x81280070U) 147 #define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) 148 #define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz 149 #define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0U) // This MCU does not have Low Voltage Mode 150 #define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0U) // This MCU does not have Middle Speed Mode 151 #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) 152 #define BSP_FEATURE_CGC_MODRV_MASK (0x30U) 153 #define BSP_FEATURE_CGC_MODRV_SHIFT (0x4U) 154 #define BSP_FEATURE_CGC_PCLKSCI_CLOCK_FREQ_TYPE (1U) 155 #define BSP_FEATURE_CGC_PCLKSPI_CLOCK_FREQ_TYPE (1U) 156 #define BSP_FEATURE_CGC_PLL_OR_MAIN_CLOCK_SELECTABLE (0U) 157 #define BSP_FEATURE_CGC_PLL_START_PROCESS_TYPE (1U) 158 #define BSP_FEATURE_CGC_PLL0_CONTROL_ADDRESS (NULL) 159 #define BSP_FEATURE_CGC_PLL0_PROTECT (NULL) 160 #define BSP_FEATURE_CGC_PLL0_SSC_SUPPORTED (0U) 161 #define BSP_FEATURE_CGC_PLL0_STANDBY_STATE_SUPPORTED (0U) 162 #define BSP_FEATURE_CGC_PLL1_CONTROL_ADDRESS (0x81280050U) 163 #define BSP_FEATURE_CGC_PLL1_PROTECT (BSP_REG_PROTECT_LPC_RESET) 164 #define BSP_FEATURE_CGC_PLL1_STANDBY_STATE_SUPPORTED (1U) 165 #define BSP_FEATURE_CGC_PLL2_CONTROL_ADDRESS (NULL) 166 #define BSP_FEATURE_CGC_PLL2_PROTECT (NULL) 167 #define BSP_FEATURE_CGC_PLL2_SSC_SUPPORTED (0U) 168 #define BSP_FEATURE_CGC_PLL2_STANDBY_STATE_SUPPORTED (0U) 169 #define BSP_FEATURE_CGC_PLL3_CONTROL_ADDRESS (NULL) 170 #define BSP_FEATURE_CGC_PLL3_PROTECT (NULL) 171 #define BSP_FEATURE_CGC_PLL3_STANDBY_STATE_SUPPORTED (0U) 172 #define BSP_FEATURE_CGC_PLL3_VCO_SETTING_SUPPORTED (0U) 173 #define BSP_FEATURE_CGC_PLLCCR_MAX_HZ (240000000U) 174 #define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) 175 #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) 176 #define BSP_FEATURE_CGC_SCKCR_TYPE (1U) 177 #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) 178 #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) 179 #define BSP_FEATURE_CGC_SODRV_SHIFT (0x1U) 180 #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0U) 181 182 #define BSP_FEATURE_CMT_VALID_CHANNEL_MASK (0x3FU) 183 184 #define BSP_FEATURE_CMTW_VALID_CHANNEL_MASK (0x3U) 185 186 #define BSP_FEATURE_CRC_VALID_CHANNEL_MASK (0x3U) 187 188 #define BSP_FEATURE_DDR_SUPPORTED (0U) 189 #define BSP_FEATURE_DMAC_HAS_CPU1_TCM_AREA (0U) 190 #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) 191 #define BSP_FEATURE_DMAC_MAX_UNIT (2U) 192 #define BSP_FEATURE_DMAC_UNIT0_ERROR_NUM (5U) 193 194 #define BSP_FEATURE_DSMIF_ADDRESS_OFFSET (0x0400) 195 #define BSP_FEATURE_DSMIF_CHANNEL_STATUS (1U) 196 #define BSP_FEATURE_DSMIF_CORE_CLOCK_SELECTABLE (0U) 197 #define BSP_FEATURE_DSMIF_DATA_FORMAT_SEL (0U) 198 #define BSP_FEATURE_DSMIF_ERROR_STATUS_CLR (5U) 199 #define BSP_FEATURE_DSMIF_HAS_LLPP_UNIT (2U) 200 #define BSP_FEATURE_DSMIF_LLPP_BASE_ADDRESS (R_DSMIF0_BASE) 201 #define BSP_FEATURE_DSMIF_LLPP1_BASE_ADDRESS (0) 202 #define BSP_FEATURE_DSMIF_MCLK_FREQ_TYPE (1U) 203 #define BSP_FEATURE_DSMIF_OVERCURRENT_DETECT_CONTROL (1U) 204 #define BSP_FEATURE_DSMIF_OVERCURRENT_DETECT_ISR (1U) 205 #define BSP_FEATURE_DSMIF_OVERCURRENT_DETECT_NOTIFY (0U) 206 #define BSP_FEATURE_DSMIF_OVERCURRENT_ERROR_STATUS (1U) 207 #define BSP_FEATURE_DSMIF_OVERCURRENT_NOTIFY_STATUS (0U) 208 #define BSP_FEATURE_DSMIF_UNIT (2U) 209 #define BSP_FEATURE_DSMIF_VALID_UNIT_MASK (0x3U) 210 #define BSP_FEATURE_DSMIF_VERSION (1U) 211 212 #define BSP_FEATURE_ELC_ELC_SSEL_NUM (19) 213 #define BSP_FEATURE_ELC_EVENT_MASK_NUM (4U) 214 #define BSP_FEATURE_ELC_GPT_EVENT_MASK_NUM (0U) 215 #define BSP_FEATURE_ELC_GROUP1_PORT_NUM (BSP_IO_PORT_16) 216 #define BSP_FEATURE_ELC_GROUP2_PORT_NUM (BSP_IO_PORT_18) 217 #define BSP_FEATURE_ELC_PERIPHERAL_0_MASK (0xFFFFFFFFU) // ELC event source no.0 to 31 available on this MCU 218 #define BSP_FEATURE_ELC_PERIPHERAL_1_MASK (0x007FF9FFU) // ELC event source no.32 to 63 available on this MCU. 219 #define BSP_FEATURE_ELC_PERIPHERAL_2_MASK (0x00000000U) // ELC event source no.64 to 95 available on this MCU. 220 #define BSP_FEATURE_ELC_PERIPHERAL_3_MASK (0x00000000U) // ELC event source no.96 to 127 available on this MCU. 221 #define BSP_FEATURE_ELC_PERIPHERAL_4_MASK (0x00000000U) // ELC event source no.128 to 159 available on this MCU. 222 #define BSP_FEATURE_ELC_PERIPHERAL_5_MASK (0x00000000U) // ELC event source no.160 to 191 available on this MCU. 223 #define BSP_FEATURE_ELC_PERIPHERAL_6_MASK (0x00000000U) // ELC event source no.192 to 223 available on this MCU. 224 #define BSP_FEATURE_ELC_PERIPHERAL_7_MASK (0x00000000U) // ELC event source no.224 to 255 available on this MCU. 225 #define BSP_FEATURE_ELC_PERIPHERAL_TYPE (1U) 226 227 #define BSP_FEATURE_ESC_MAX_PORTS (3U) 228 #define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU) 229 #define BSP_FEATURE_ETHER_PHY_MAX_CHANNELS (3U) 230 #define BSP_FEATURE_ETHSS_MAX_PORTS (3U) 231 #define BSP_FEATURE_ETHSS_SWITCH_MODE_BIT_MASK (3U) 232 #define BSP_FEATURE_ETHSW_MAX_CHANNELS (1U) 233 #define BSP_FEATURE_ETHSW_SUPPORTED (1U) 234 #define BSP_FEATURE_GMAC_B_SUPPORTED (0U) 235 #define BSP_FEATURE_GMAC_MAX_CHANNELS (1U) 236 #define BSP_FEATURE_GMAC_MAX_PORTS (3U) 237 #define BSP_FEATURE_GMAC_UNIT (1U) 238 239 #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x3FFFF) 240 #define BSP_FEATURE_GPT_CHANNEL (18U) 241 #define BSP_FEATURE_GPT_INPUT_CAPTURE_SIGNAL_SELECTABLE (0U) 242 #define BSP_FEATURE_GPT_LLPP_BASE_ADDRESS (R_GPT0_BASE) 243 #define BSP_FEATURE_GPT_LLPP_BASE_CHANNEL (0U) // LLPP channel: ch0-6 244 #define BSP_FEATURE_GPT_LLPP_CHANNEL_ADDRESS_OFFSET (R_GPT1_BASE - R_GPT0_BASE) 245 #define BSP_FEATURE_GPT_LLPP_CHANNEL_MASK (0x007F) 246 #define BSP_FEATURE_GPT_LLPP_CHANNEL_PER_UNIT (7U) 247 #define BSP_FEATURE_GPT_LLPP_UNIT_ADDRESS_OFFSET (0U) 248 #define BSP_FEATURE_GPT_LLPP1_BASE_ADDRESS (0) 249 #define BSP_FEATURE_GPT_LLPP1_BASE_CHANNEL (0U) // LLPP1 is unsupported 250 #define BSP_FEATURE_GPT_LLPP1_CHANNEL_ADDRESS_OFFSET (0) 251 #define BSP_FEATURE_GPT_LLPP1_CHANNEL_MASK (0x0000) 252 #define BSP_FEATURE_GPT_LLPP1_UNIT_ADDRESS_OFFSET (0U) 253 #define BSP_FEATURE_GPT_NONSAFETY_BASE_ADDRESS (R_GPT7_BASE) 254 #define BSP_FEATURE_GPT_NONSAFETY_BASE_CHANNEL (7U) // Non-safety channel: ch7-13 255 #define BSP_FEATURE_GPT_NONSAFETY_CHANNEL_ADDRESS_OFFSET (R_GPT8_BASE - R_GPT7_BASE) 256 #define BSP_FEATURE_GPT_NONSAFETY_CHANNEL_MASK (0x007F) 257 #define BSP_FEATURE_GPT_REGISTER_MASK_TYPE (1U) 258 #define BSP_FEATURE_GPT_SAFETY_BASE_ADDRESS (R_GPT14_BASE) 259 #define BSP_FEATURE_GPT_SAFETY_BASE_CHANNEL (14U) // safety channel: ch14-17 260 #define BSP_FEATURE_GPT_SAFETY_CHANNEL_ADDRESS_OFFSET (R_GPT15_BASE - R_GPT14_BASE) 261 #define BSP_FEATURE_GPT_SAFETY_CHANNEL_MASK (0x000F) 262 #define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FFFF) 263 #define BSP_FEATURE_GPTE_CHANNEL_MASK (0xF0) 264 #define BSP_FEATURE_GPTEH_CHANNEL_MASK (0xF) 265 266 #define BSP_FEATURE_ICU_ERROR_CA55_SUPPORTED (0U) 267 #define BSP_FEATURE_ICU_ERROR_CR52_CPU1_SUPPORTED (0U) 268 #define BSP_FEATURE_ICU_ERROR_DSMIF_ERR_INTERRUPT_SUPPORTED (0U) 269 #define BSP_FEATURE_ICU_ERROR_DSMIF_ERR_REG_NUM (0U) 270 #define BSP_FEATURE_ICU_ERROR_DSMIF_ERR0_REG_MASK (0x00000000U) 271 #define BSP_FEATURE_ICU_ERROR_DSMIF_ERR1_REG_MASK (0x00000000U) 272 #define BSP_FEATURE_ICU_ERROR_DSMIF_ERR2_REG_MASK (0x00000000U) 273 #define BSP_FEATURE_ICU_ERROR_DSMIF_ERR3_REG_MASK (0x00000000U) 274 #define BSP_FEATURE_ICU_ERROR_DSMIF_ERR4_REG_MASK (0x00000000U) 275 #define BSP_FEATURE_ICU_ERROR_DSMIF_ERR5_REG_MASK (0x00000000U) 276 #define BSP_FEATURE_ICU_ERROR_DSMIF_ERR7_REG_MASK (0x00000000U) 277 #define BSP_FEATURE_ICU_ERROR_DSMIF_ERR8_REG_MASK (0x00000000U) 278 #define BSP_FEATURE_ICU_ERROR_DSMIF_ERR10_REG_MASK (0x00000000U) 279 #define BSP_FEATURE_ICU_ERROR_DSMIF_ERR11_REG_MASK (0x00000000U) 280 #define BSP_FEATURE_ICU_ERROR_ENCIF_ERR_INTERRUPT_SUPPORTED (0U) 281 #define BSP_FEATURE_ICU_ERROR_ENCIF_ERR_REG_NUM (0U) 282 #define BSP_FEATURE_ICU_ERROR_ENCIF_ERR0_REG_MASK (0x00000000U) 283 #define BSP_FEATURE_ICU_ERROR_ENCIF_ERR1_REG_MASK (0x00000000U) 284 #define BSP_FEATURE_ICU_ERROR_ENCIF_ERR2_REG_MASK (0x00000000U) 285 #define BSP_FEATURE_ICU_ERROR_ENCIF_ERR3_REG_MASK (0x00000000U) 286 #define BSP_FEATURE_ICU_ERROR_ENCIF_ERR4_REG_MASK (0x00000000U) 287 #define BSP_FEATURE_ICU_ERROR_ERR_SOURCE_NUM (4U) 288 #define BSP_FEATURE_ICU_ERROR_PERI_ERR_REG_NUM (2U) 289 #define BSP_FEATURE_ICU_ERROR_PERI_ERR0_REG_MASK (0xFFFFFEFFU) 290 #define BSP_FEATURE_ICU_ERROR_PERI_ERR1_REG_MASK (0x19FFA3FFU) 291 #define BSP_FEATURE_ICU_ERROR_PERI_ERR2_REG_MASK (0x00000000U) 292 #define BSP_FEATURE_ICU_ERROR_PERI_ERR3_REG_MASK (0x00000000U) 293 #define BSP_FEATURE_ICU_ERROR_PERIPHERAL_TYPE (1U) 294 #define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) 295 #define BSP_FEATURE_ICU_INTER_CPU_IRQ_CHANNEL (0U) 296 #define BSP_FEATURE_ICU_INTER_CPU_IRQ_CHANNELS_MASK (0x00U) 297 #define BSP_FEATURE_ICU_INTER_CPU_IRQ_NS_SWINT_MASK (0x00U) // Non-safety channel: ch0-5 (bit0-5) 298 #define BSP_FEATURE_ICU_INTER_CPU_IRQ_S_SWINT_MASK (0x00U) // Safety channel: ch6-7 (bit6-7) 299 #define BSP_FEATURE_ICU_INTER_CPU_IRQ_S_SWINT_SHIFT (0U) 300 #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) 301 #define BSP_FEATURE_ICU_SAFETY_REGISTER_TYPE (1) 302 #define BSP_FEATURE_ICU_WUPEN_MASK (0xFF4FFFFFU) 303 304 #define BSP_FEATURE_IIC_FAST_MODE_PLUS (0U) 305 #define BSP_FEATURE_IIC_SAFETY_CHANNEL (2U) 306 #define BSP_FEATURE_IIC_SAFETY_CHANNEL_BASE_ADDRESS (R_IIC2_BASE) 307 #define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07) 308 309 #define BSP_FEATURE_IOPORT_ELC_PORTS (4U) 310 #define BSP_FEATURE_IOPORT_HAS_ETHERNET (1U) 311 #define BSP_FEATURE_IOPORT_HAS_NONSAFETY_DEDICATED_PORT (0U) 312 #define BSP_FEATURE_IOPORT_PIN_PFC_TYPE (1U) 313 #define BSP_FEATURE_IOPORT_PORT_NUM (25U) 314 #define BSP_FEATURE_IOPORT_SELECTABLE_PORT_MAX (24U) 315 316 #define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY {{0, 15}, {0, 13}, {1, 31}, {1, 6}, {1, 5}, {1, 4}, \ 317 {2, 5} \ 318 } 319 #define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (1U) 320 #define BSP_FEATURE_LPM_DPSIEGR_MASK (0x00137FFFU) 321 #define BSP_FEATURE_LPM_DPSIER_MASK (0x071F7FFFU) 322 #define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) 323 #define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U) 324 #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) 325 #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) 326 #define BSP_FEATURE_LPM_HAS_STCONR (1U) 327 #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0U) 328 #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000000FFU) 329 #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7342FFFFU) 330 331 #define BSP_FEATURE_MAILBOX_SEM_SUPPORTED (0U) 332 333 #define BSP_FEATURE_MTU3_MAX_CHANNELS (9U) 334 #define BSP_FEATURE_MTU3_UVW_MAX_CHANNELS (3U) 335 #define BSP_FEATURE_MTU3_VALID_CHANNEL_MASK (0x01FF) 336 337 #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) 338 #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) 339 340 #define BSP_FEATURE_PCIE_CHANNEL0_ERROR_AXI_NUM (0) 341 #define BSP_FEATURE_PCIE_CHANNEL0_ERROR_CORRECTABLE_RC_NUM (0) 342 #define BSP_FEATURE_PCIE_CHANNEL0_ERROR_FATAL_RC_NUM (0) 343 #define BSP_FEATURE_PCIE_CHANNEL0_ERROR_NON_FATAL_RC_NUM (0) 344 #define BSP_FEATURE_PCIE_CHANNEL0_ERROR_RC_NUM (0) 345 #define BSP_FEATURE_PCIE_CHANNEL1_ERROR_AXI_NUM (0) 346 #define BSP_FEATURE_PCIE_CHANNEL1_ERROR_CORRECTABLE_RC_NUM (0) 347 #define BSP_FEATURE_PCIE_CHANNEL1_ERROR_FATAL_RC_NUM (0) 348 #define BSP_FEATURE_PCIE_CHANNEL1_ERROR_NON_FATAL_RC_NUM (0) 349 #define BSP_FEATURE_PCIE_CHANNEL1_ERROR_RC_NUM (0) 350 351 #define BSP_FEATURE_POE3_ERROR_SIGNAL_TYPE (1U) 352 #define BSP_FEATURE_POE3_PIN_SELECT_TYPE (1U) 353 354 #define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) 355 #define BSP_FEATURE_POEG_ERROR_SIGNAL_TYPE (1U) 356 #define BSP_FEATURE_POEG_GROUP_OFSSET_ADDRESS (0x400) 357 #define BSP_FEATURE_POEG_LLPP_UNIT (0U) 358 #define BSP_FEATURE_POEG_MAX_UNIT (2U) 359 #define BSP_FEATURE_POEG_NONSAFETY_UNIT (1U) 360 #define BSP_FEATURE_POEG_SAFETY_UNIT (2U) 361 362 #define BSP_FEATURE_RSIP_JTAG_DEBUG_AUTH_LEVEL1 (1U) 363 #define BSP_FEATURE_RSIP_JTAG_DEBUG_AUTH_LEVEL2 (1U) 364 #define BSP_FEATURE_RSIP_SCI_USB_BOOT_AUTH (0U) 365 #define BSP_FEATURE_RSIP_OTP_ADDRESS_SPACE (1U) 366 #define BSP_FEATURE_RSIP_OTF_CHANNEL (0U) 367 368 #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) 369 #define BSP_FEATURE_SCI_CHANNELS (0x3FU) 370 #define BSP_FEATURE_SCI_SAFETY_CHANNEL (5U) 371 #define BSP_FEATURE_SCI_SAFETY_CHANNEL_BASE_ADDRESS (R_SCI5_BASE) 372 #define BSP_FEATURE_SCI_SPI_MAX_CPUCLK_MHZ (800U) 373 #define BSP_FEATURE_SCI_SPI_MIN_PCLKM_MHZ (100U) // Minimum PCLKM greater than minimum SCInASYNCCLK 374 #define BSP_FEATURE_SCI_SPI_MIN_SCINASYNCCLK_MHZ (75U) 375 #define BSP_FEATURE_SCI_UART_CTSPEN_CHANNELS (0x03FU) 376 #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3FFU) 377 #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) 378 #define BSP_FEATURE_SCIE_SUPPORTED (0U) 379 380 #define BSP_FEATURE_SEM_SUPPORTED (0U) 381 #define BSP_FEATURE_SHARED_MEMORY_SETTING_TYPE (1U) 382 383 #define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) 384 #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) 385 #define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) 386 #define BSP_FEATURE_SPI_MAX_CHANNEL (4U) 387 #define BSP_FEATURE_SPI_SAFETY_CHANNEL (3U) 388 #define BSP_FEATURE_SPI_SAFETY_CHANNEL_BASE_ADDRESS (R_SPI3_BASE) 389 390 #define BSP_FEATURE_TFU_FIXED_POINT_SUPPORTED (0) 391 #define BSP_FEATURE_TFU_SUPPORTED (1U) 392 #define BSP_FEATURE_TFU_UNIT (1U) 393 #define BSP_FEATURE_TFU_UNIT_NUMBER (0) 394 #define BSP_FEATURE_TFU_VERSION (1) 395 396 #define BSP_FEATURE_TSU_B_CALIBRAION_DATA_CHECK_ENABLE (0) // Feature not available on this MCU 397 #define BSP_FEATURE_TSU_B_CALIBRAION_DATA_INVALID (0) // Feature not available on this MCU 398 #define BSP_FEATURE_TSU_B_CALIBRAION_DATA_MASK (0) // Feature not available on this MCU 399 #define BSP_FEATURE_TSU_B_CONTINUOUS_MODE_SUPPORTED (0) // Feature not available on this MCU 400 #define BSP_FEATURE_TSU_B_ELC_TRIGGER_SUPPORTED (0) // Feature not available on this MCU 401 #define BSP_FEATURE_TSU_B_HIGH_TEMPERATURE (0) // Feature not available on this MCU 402 #define BSP_FEATURE_TSU_B_LOW_TEMPERATURE (0) // Feature not available on this MCU 403 #define BSP_FEATURE_TSU_B_UNIT_0_HIGH_TEMPERATURE_REGISTER (0) // Feature not available on this MCU 404 #define BSP_FEATURE_TSU_B_UNIT_0_LOW_TEMPERATURE_REGISTER (0) // Feature not available on this MCU 405 #define BSP_FEATURE_TSU_VERSION (1U) 406 407 #define BSP_FEATURE_TZC400_SUPPORTED (0U) 408 409 #define BSP_FEATURE_USB_HOST_HS_SET_TYPE (1U) 410 411 #define BSP_FEATURE_XSPI_CHANNELS (0x03U) 412 #define BSP_FEATURE_XSPI_CS_ADDRESS_SPACE_SETTING_TYPE (1U) 413 #define BSP_FEATURE_XSPI_DEVICE_0_MIRROR_START_ADDRESS (0x40000000U) 414 #define BSP_FEATURE_XSPI_DEVICE_0_START_ADDRESS (0x60000000U) 415 #define BSP_FEATURE_XSPI_DEVICE_1_MIRROR_START_ADDRESS (0x48000000U) 416 #define BSP_FEATURE_XSPI_DEVICE_1_START_ADDRESS (0x68000000U) 417 #define BSP_FEATURE_XSPI_DEVICE_ADDRESS_SPACE_SIZE (0x8000000U) 418 #define BSP_FEATURE_XSPI_HAS_AXI_BRIDGE (0U) 419 #define BSP_FEATURE_XSPI_NUM_CHIP_SELECT (2U) 420 #define BSP_FEATURE_XSPI_VOLTAGE_SETTING_SUPPORTED (0U) 421 422 /*********************************************************************************************************************** 423 * Typedef definitions 424 **********************************************************************************************************************/ 425 426 /*********************************************************************************************************************** 427 * Exported global variables 428 **********************************************************************************************************************/ 429 430 /*********************************************************************************************************************** 431 * Exported global functions (to be accessed by other files) 432 **********************************************************************************************************************/ 433 434 /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 435 FSP_FOOTER 436 437 #endif 438
