1 /*
2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 
7 /***********************************************************************************************************************
8  * Includes   <System Includes> , "Project Includes"
9  **********************************************************************************************************************/
10 #include <string.h>
11 #include "bsp_api.h"
12 
13 #include "../../../../../mcu/all/bsp_clocks.h"
14 
15 /***********************************************************************************************************************
16  * Macro definitions
17  **********************************************************************************************************************/
18 #define BSP_CPCAR_CP_ENABLE             (0x00F00000)
19 #define BSP_FPEXC_EN_ENABLE             (0x40000000)
20 #define BSP_TCM_ALL_ACCESS_ENABLE       (0x00000003)
21 
22 #define BSP_PRIORITY_MASK               BSP_FEATURE_BSP_IRQ_PRIORITY_MASK /* Priority mask value for GIC */
23 #define BSP_ENABLE_GROUP_INT            (0x00000001)                      /* Enable Group1 interrupt value */
24 #define BSP_ICC_CTLR                    (0x00000001)                      /* ICC_BPR0 is used for Group1 interrupt */
25 
26 #define BSP_BG_REGION_ENABLE            (0x00020000)                      /* Enable EL1 background region */
27 #define BSP_BG_REGION_DISABLE           (0x00000000)                      /* Disable EL1 background region */
28 #define BSP_SCTLR_BR_BIT                (BSP_CFG_SCTLR_BR_BIT)            /* Enable EL1 background region */
29 
30 #define BSP_ICACHE_ENABLE               (0x00001000)
31 #define BSP_ICACHE_DISABLE              (0x00000000)
32 
33 #define BSP_DATACACHE_ENABLE            (0x00000004)
34 #define BSP_DATACACHE_DISABLE           (0x00000000)
35 
36 #define BSP_WRITE_THROUGH_TRANSIENT     (0x0003) /* Normal-Memory: Write-Through transient */
37 #define BSP_NON_CACHEABLE               (0x0004) /* Normal-Memory: Non-Cacheable */
38 #define BSP_WRITE_BACK_TRANSIENT        (0x0007) /* Normal-Memory: Write-Back transient */
39 #define BSP_WRITE_NON_THROUGH           (0x000B) /* Normal-Memory: Write-Through non-transient. */
40 #define BSP_WRITE_BACK_NON_TRANSIENT    (0x000F) /* Normal-Memory: Write-Back non-transient. */
41 
42 #define BSP_TYPE_NORMAL_MEMORY          (0)
43 #define BSP_TYPE_DEVICE_MEMORY          (1)
44 
45 #define BSP_READ_ALLOCATE               (0xFFFF) /* Read allocate (bit1=1, "1" mask except bit1) */
46 #define BSP_READ_NOT_ALLOCATE           (0xFFFD) /* Read not allocate (bit1=0, "1" mask except bit1) */
47 #define BSP_WRITE_ALLOCATE              (0xFFFF) /* Write allocate (bit0=1, "1" mask except bit0) */
48 #define BSP_WRITE_NOT_ALLOCATE          (0xFFFE) /* Write not allocate (bit0=0, "1" mask except bit0) */
49 
50 #define BSP_DEVICE_NGNRNE               (0x0000) /* Device-nGnRnE memory */
51 #define BSP_DEVICE_NGNRE                (0x0004) /* Device-nGnRE memory */
52 #define BSP_DEVICE_NGRE                 (0x0008) /* Device-nGRE memory */
53 #define BSP_DEVICE_GRE                  (0x000C) /* Device-GRE memory */
54 
55 #define BSP_OFFSET_ATTR0_INNER          (0)
56 #define BSP_OFFSET_ATTR0_OUTER          (4)
57 #define BSP_OFFSET_ATTR0_DEVICE         (0)
58 #define BSP_OFFSET_ATTR1_INNER          (8)
59 #define BSP_OFFSET_ATTR1_OUTER          (12)
60 #define BSP_OFFSET_ATTR1_DEVICE         (8)
61 
62 #define BSP_OFFSET_ATTR2_INNER          (16)
63 #define BSP_OFFSET_ATTR2_OUTER          (20)
64 #define BSP_OFFSET_ATTR2_DEVICE         (16)
65 #define BSP_OFFSET_ATTR3_INNER          (24)
66 #define BSP_OFFSET_ATTR3_OUTER          (28)
67 #define BSP_OFFSET_ATTR3_DEVICE         (24)
68 
69 #define BSP_OFFSET_ATTR4_INNER          (0)
70 #define BSP_OFFSET_ATTR4_OUTER          (4)
71 #define BSP_OFFSET_ATTR4_DEVICE         (0)
72 #define BSP_OFFSET_ATTR5_INNER          (8)
73 #define BSP_OFFSET_ATTR5_OUTER          (12)
74 #define BSP_OFFSET_ATTR5_DEVICE         (8)
75 
76 #define BSP_OFFSET_ATTR6_INNER          (16)
77 #define BSP_OFFSET_ATTR6_OUTER          (20)
78 #define BSP_OFFSET_ATTR6_DEVICE         (16)
79 #define BSP_OFFSET_ATTR7_INNER          (24)
80 #define BSP_OFFSET_ATTR7_OUTER          (28)
81 #define BSP_OFFSET_ATTR7_DEVICE         (24)
82 
83 #define BSP_NON_SHAREABLE               (0 << 3)
84 #define BSP_OUTER_SHAREABLE             (2 << 3)
85 #define BSP_INNER_SHAREABLE             (3 << 3)
86 #define BSP_EL1RW_EL0NO                 (0 << 1)
87 #define BSP_EL1RW_EL0RW                 (1 << 1)
88 #define BSP_EL1RO_EL0NO                 (2 << 1)
89 #define BSP_EL1RO_EL0RO                 (3 << 1)
90 #define BSP_EXECUTE_ENABLE              (0)
91 #define BSP_EXECUTE_NEVER               (1)
92 #define BSP_REGION_DISABLE              (0)
93 #define BSP_REGION_ENABLE               (1)
94 #define BSP_ATTRINDEX0                  (0 << 1)
95 #define BSP_ATTRINDEX1                  (1 << 1)
96 #define BSP_ATTRINDEX2                  (2 << 1)
97 #define BSP_ATTRINDEX3                  (3 << 1)
98 #define BSP_ATTRINDEX4                  (4 << 1)
99 #define BSP_ATTRINDEX5                  (5 << 1)
100 #define BSP_ATTRINDEX6                  (6 << 1)
101 #define BSP_ATTRINDEX7                  (7 << 1)
102 
103 /* Attr0 */
104 #if BSP_CFG_CPU_MPU_ATTR0_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */
105  #define BSP_CFG_CPU_MPU_ATTR0          (BSP_CFG_CPU_MPU_ATTR0_DEVICE_TYPE << BSP_OFFSET_ATTR0_DEVICE)
106 #else                                                    /* MEMORY TYPE == NORMAL MEMORY */
107  #define BSP_CFG_CPU_MPU_ATTR0          (((BSP_CFG_CPU_MPU_ATTR0_INNER &                                     \
108                                            (BSP_CFG_CPU_MPU_ATTR0_INNER_READ) &                              \
109                                            (BSP_CFG_CPU_MPU_ATTR0_INNER_WRITE)) << BSP_OFFSET_ATTR0_INNER) | \
110                                          ((BSP_CFG_CPU_MPU_ATTR0_OUTER &                                     \
111                                            (BSP_CFG_CPU_MPU_ATTR0_OUTER_READ) &                              \
112                                            (BSP_CFG_CPU_MPU_ATTR0_OUTER_WRITE)) << BSP_OFFSET_ATTR0_OUTER))
113 #endif                                                   /* BSP_CFG_CPU_MPU_ATTR0_TYPE */
114 
115 /* Attr1 */
116 #if BSP_CFG_CPU_MPU_ATTR1_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */
117  #define BSP_CFG_CPU_MPU_ATTR1          (BSP_CFG_CPU_MPU_ATTR1_DEVICE_TYPE << BSP_OFFSET_ATTR1_DEVICE)
118 #else                                                    /* MEMORY TYPE == NORMAL MEMORY */
119  #define BSP_CFG_CPU_MPU_ATTR1          (((BSP_CFG_CPU_MPU_ATTR1_INNER &                                     \
120                                            (BSP_CFG_CPU_MPU_ATTR1_INNER_READ) &                              \
121                                            (BSP_CFG_CPU_MPU_ATTR1_INNER_WRITE)) << BSP_OFFSET_ATTR1_INNER) | \
122                                          ((BSP_CFG_CPU_MPU_ATTR1_OUTER &                                     \
123                                            (BSP_CFG_CPU_MPU_ATTR1_OUTER_READ) &                              \
124                                            (BSP_CFG_CPU_MPU_ATTR1_OUTER_WRITE)) << BSP_OFFSET_ATTR1_OUTER))
125 #endif                                                   /* BSP_CFG_CPU_MPU_ATTR1_TYPE */
126 
127 /* Attr2 */
128 #if BSP_CFG_CPU_MPU_ATTR2_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */
129  #define BSP_CFG_CPU_MPU_ATTR2          (BSP_CFG_CPU_MPU_ATTR2_DEVICE_TYPE << BSP_OFFSET_ATTR2_DEVICE)
130 #else                                                    /* MEMORY TYPE == NORMAL MEMORY */
131  #define BSP_CFG_CPU_MPU_ATTR2          (((BSP_CFG_CPU_MPU_ATTR2_INNER &                                     \
132                                            (BSP_CFG_CPU_MPU_ATTR2_INNER_READ) &                              \
133                                            (BSP_CFG_CPU_MPU_ATTR2_INNER_WRITE)) << BSP_OFFSET_ATTR2_INNER) | \
134                                          ((BSP_CFG_CPU_MPU_ATTR2_OUTER &                                     \
135                                            (BSP_CFG_CPU_MPU_ATTR2_OUTER_READ) &                              \
136                                            (BSP_CFG_CPU_MPU_ATTR2_OUTER_WRITE)) << BSP_OFFSET_ATTR2_OUTER))
137 #endif                                                   /* BSP_CFG_CPU_MPU_ATTR2_TYPE */
138 
139 /* Attr3 */
140 #if BSP_CFG_CPU_MPU_ATTR3_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */
141  #define BSP_CFG_CPU_MPU_ATTR3          (BSP_CFG_CPU_MPU_ATTR3_DEVICE_TYPE << BSP_OFFSET_ATTR3_DEVICE)
142 #else                                                    /* MEMORY TYPE == NORMAL MEMORY */
143  #define BSP_CFG_CPU_MPU_ATTR3          (((BSP_CFG_CPU_MPU_ATTR3_INNER &                                     \
144                                            (BSP_CFG_CPU_MPU_ATTR3_INNER_READ) &                              \
145                                            (BSP_CFG_CPU_MPU_ATTR3_INNER_WRITE)) << BSP_OFFSET_ATTR3_INNER) | \
146                                          ((BSP_CFG_CPU_MPU_ATTR3_OUTER &                                     \
147                                            (BSP_CFG_CPU_MPU_ATTR3_OUTER_READ) &                              \
148                                            (BSP_CFG_CPU_MPU_ATTR3_OUTER_WRITE)) << BSP_OFFSET_ATTR3_OUTER))
149 #endif                                                   /* BSP_CFG_CPU_MPU_ATTR3_TYPE */
150 
151 /* Attr4 */
152 #if BSP_CFG_CPU_MPU_ATTR4_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */
153  #define BSP_CFG_CPU_MPU_ATTR4          (BSP_CFG_CPU_MPU_ATTR4_DEVICE_TYPE << BSP_OFFSET_ATTR4_DEVICE)
154 #else                                                    /* MEMORY TYPE == NORMAL MEMORY */
155  #define BSP_CFG_CPU_MPU_ATTR4          (((BSP_CFG_CPU_MPU_ATTR4_INNER &                                     \
156                                            (BSP_CFG_CPU_MPU_ATTR4_INNER_READ) &                              \
157                                            (BSP_CFG_CPU_MPU_ATTR4_INNER_WRITE)) << BSP_OFFSET_ATTR4_INNER) | \
158                                          ((BSP_CFG_CPU_MPU_ATTR4_OUTER &                                     \
159                                            (BSP_CFG_CPU_MPU_ATTR4_OUTER_READ) &                              \
160                                            (BSP_CFG_CPU_MPU_ATTR4_OUTER_WRITE)) << BSP_OFFSET_ATTR4_OUTER))
161 #endif                                                   /* BSP_CFG_CPU_MPU_ATTR4_TYPE */
162 
163 /* Attr5 */
164 #if BSP_CFG_CPU_MPU_ATTR5_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */
165  #define BSP_CFG_CPU_MPU_ATTR5          (BSP_CFG_CPU_MPU_ATTR5_DEVICE_TYPE << BSP_OFFSET_ATTR5_DEVICE)
166 #else                                                    /* MEMORY TYPE == NORMAL MEMORY */
167  #define BSP_CFG_CPU_MPU_ATTR5          (((BSP_CFG_CPU_MPU_ATTR5_INNER &                                     \
168                                            (BSP_CFG_CPU_MPU_ATTR5_INNER_READ) &                              \
169                                            (BSP_CFG_CPU_MPU_ATTR5_INNER_WRITE)) << BSP_OFFSET_ATTR5_INNER) | \
170                                          ((BSP_CFG_CPU_MPU_ATTR5_OUTER &                                     \
171                                            (BSP_CFG_CPU_MPU_ATTR5_OUTER_READ) &                              \
172                                            (BSP_CFG_CPU_MPU_ATTR5_OUTER_WRITE)) << BSP_OFFSET_ATTR5_OUTER))
173 #endif                                                   /* BSP_CFG_CPU_MPU_ATTR5_TYPE */
174 
175 /* Attr6 */
176 #if BSP_CFG_CPU_MPU_ATTR6_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */
177  #define BSP_CFG_CPU_MPU_ATTR6          (BSP_CFG_CPU_MPU_ATTR6_DEVICE_TYPE << BSP_OFFSET_ATTR6_DEVICE)
178 #else                                                    /* MEMORY TYPE == NORMAL MEMORY */
179  #define BSP_CFG_CPU_MPU_ATTR6          (((BSP_CFG_CPU_MPU_ATTR6_INNER &                                     \
180                                            (BSP_CFG_CPU_MPU_ATTR6_INNER_READ) &                              \
181                                            (BSP_CFG_CPU_MPU_ATTR6_INNER_WRITE)) << BSP_OFFSET_ATTR6_INNER) | \
182                                          ((BSP_CFG_CPU_MPU_ATTR6_OUTER &                                     \
183                                            (BSP_CFG_CPU_MPU_ATTR6_OUTER_READ) &                              \
184                                            (BSP_CFG_CPU_MPU_ATTR6_OUTER_WRITE)) << BSP_OFFSET_ATTR6_OUTER))
185 #endif                                                   /* BSP_CFG_CPU_MPU_ATTR6_TYPE */
186 
187 /* Attr7 */
188 #if BSP_CFG_CPU_MPU_ATTR7_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */
189  #define BSP_CFG_CPU_MPU_ATTR7          (BSP_CFG_CPU_MPU_ATTR7_DEVICE_TYPE << BSP_OFFSET_ATTR7_DEVICE)
190 #else                                                    /* MEMORY TYPE == NORMAL MEMORY */
191  #define BSP_CFG_CPU_MPU_ATTR7          (((BSP_CFG_CPU_MPU_ATTR7_INNER &                                     \
192                                            (BSP_CFG_CPU_MPU_ATTR7_INNER_READ) &                              \
193                                            (BSP_CFG_CPU_MPU_ATTR7_INNER_WRITE)) << BSP_OFFSET_ATTR7_INNER) | \
194                                          ((BSP_CFG_CPU_MPU_ATTR7_OUTER &                                     \
195                                            (BSP_CFG_CPU_MPU_ATTR7_OUTER_READ) &                              \
196                                            (BSP_CFG_CPU_MPU_ATTR7_OUTER_WRITE)) << BSP_OFFSET_ATTR7_OUTER))
197 #endif                                 /* BSP_CFG_CPU_MPU_ATTR7_TYPE */
198 
199 #define ATTR_3_2_1_0                    (BSP_CFG_CPU_MPU_ATTR3 | BSP_CFG_CPU_MPU_ATTR2 | BSP_CFG_CPU_MPU_ATTR1 | \
200                                          BSP_CFG_CPU_MPU_ATTR0)
201 #define ATTR_7_6_5_4                    (BSP_CFG_CPU_MPU_ATTR7 | BSP_CFG_CPU_MPU_ATTR6 | BSP_CFG_CPU_MPU_ATTR5 | \
202                                          BSP_CFG_CPU_MPU_ATTR4)
203 
204 #if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR0_TYPE)
205  #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR0_INNER) && \
206     (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR0_INNER_READ) &&    \
207     (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR0_INNER_WRITE))
208   #error "If you select Write-Through transient, set either Read or Write to allocate."
209  #endif
210  #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR0_OUTER) && \
211     (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR0_OUTER_READ) &&    \
212     (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR0_OUTER_WRITE))
213   #error "If you select Write-Through transient, set either Read or Write to allocate."
214  #endif
215 #endif
216 
217 #if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR1_TYPE)
218  #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR1_INNER) && \
219     (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR1_INNER_READ) &&    \
220     (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR1_INNER_WRITE))
221   #error "If you select Write-Through transient, set either Read or Write to allocate."
222  #endif
223  #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR1_OUTER) && \
224     (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR1_OUTER_READ) &&    \
225     (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR1_OUTER_WRITE))
226   #error "If you select Write-Through transient, set either Read or Write to allocate."
227  #endif
228 #endif
229 
230 #if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR2_TYPE)
231  #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR2_INNER) && \
232     (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR2_INNER_READ) &&    \
233     (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR2_INNER_WRITE))
234   #error "If you select Write-Through transient, set either Read or Write to allocate."
235  #endif
236  #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR2_OUTER) && \
237     (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR2_OUTER_READ) &&    \
238     (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR2_OUTER_WRITE))
239   #error "If you select Write-Through transient, set either Read or Write to allocate."
240  #endif
241 #endif
242 
243 #if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR3_TYPE)
244  #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR3_INNER) && \
245     (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR3_INNER_READ) &&    \
246     (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR3_INNER_WRITE))
247   #error "If you select Write-Through transient, set either Read or Write to allocate."
248  #endif
249  #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR3_OUTER) && \
250     (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR3_OUTER_READ) &&    \
251     (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR3_OUTER_WRITE))
252   #error "If you select Write-Through transient, set either Read or Write to allocate."
253  #endif
254 #endif
255 
256 #if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR4_TYPE)
257  #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR4_INNER) && \
258     (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR4_INNER_READ) &&    \
259     (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR4_INNER_WRITE))
260   #error "If you select Write-Through transient, set either Read or Write to allocate."
261  #endif
262  #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR4_OUTER) && \
263     (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR4_OUTER_READ) &&    \
264     (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR4_OUTER_WRITE))
265   #error "If you select Write-Through transient, set either Read or Write to allocate."
266  #endif
267 #endif
268 
269 #if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR5_TYPE)
270  #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR5_INNER) && \
271     (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR5_INNER_READ) &&    \
272     (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR5_INNER_WRITE))
273   #error "If you select Write-Through transient, set either Read or Write to allocate."
274  #endif
275  #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR5_OUTER) && \
276     (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR5_OUTER_READ) &&    \
277     (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR5_OUTER_WRITE))
278   #error "If you select Write-Through transient, set either Read or Write to allocate."
279  #endif
280 #endif
281 
282 #if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR6_TYPE)
283  #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR6_INNER) && \
284     (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR6_INNER_READ) &&    \
285     (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR6_INNER_WRITE))
286   #error "If you select Write-Through transient, set either Read or Write to allocate."
287  #endif
288  #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR6_OUTER) && \
289     (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR6_OUTER_READ) &&    \
290     (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR6_OUTER_WRITE))
291   #error "If you select Write-Through transient, set either Read or Write to allocate."
292  #endif
293 #endif
294 
295 #if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR7_TYPE)
296  #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR7_INNER) && \
297     (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR7_INNER_READ) &&    \
298     (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR7_INNER_WRITE))
299   #error "If you select Write-Through transient, set either Read or Write to allocate."
300  #endif
301  #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR7_OUTER) && \
302     (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR7_OUTER_READ) &&    \
303     (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR7_OUTER_WRITE))
304   #error "If you select Write-Through transient, set either Read or Write to allocate."
305  #endif
306 #endif
307 
308 /* Region template */
309 #define EL1_MPU_REGION_ADDRESS_MASK                         (0xFFFFFFC0)
310 
311 #if (1 != _RZN_ORDINAL) && (0 == BSP_FEATURE_BSP_HAS_SYSTEMRAM_MIRROR_AREA)
312  #define EL1_MPU_REGION_ATTRIBUTE_MASK                      (0x3F)
313  #define EL1_MPU_REGION_SYSTEMRAM_CACHE_ADDRESS_START       (0x10000000)
314  #define EL1_MPU_REGION_SYSTEMRAM_CACHE_ADDRESS_END         (0x100FFFC0)
315  #define EL1_MPU_REGION_SYSTEMRAM_NONCACHE_ADDRESS_START    (0x10100000)
316  #define EL1_MPU_REGION_SYSTEMRAM_NONCACHE_ADDRESS_END      (0x101FFFC0)
317 
318 #endif
319 
320 #define EL1_MPU_REGION_COUNT                                (24)
321 
322 #define EL1_MPU_REGIONXX_BASE(n)     ((BSP_CFG_EL1_MPU_REGION ## n ## _BASE & EL1_MPU_REGION_ADDRESS_MASK) | \
323                                       BSP_CFG_EL1_MPU_REGION ## n ## _SH |                                   \
324                                       BSP_CFG_EL1_MPU_REGION ## n ## _AP |                                   \
325                                       BSP_CFG_EL1_MPU_REGION ## n ## _XN)
326 
327 #define EL1_MPU_REGIONXX_LIMIT(n)    ((BSP_CFG_EL1_MPU_REGION ## n ## _LIMIT & EL1_MPU_REGION_ADDRESS_MASK) | \
328                                       BSP_CFG_EL1_MPU_REGION ## n ## _ATTRINDEX |                             \
329                                       BSP_CFG_EL1_MPU_REGION ## n ## _ENABLE)
330 
331 /* region 0 */
332 #define EL1_MPU_REGION00_BASE     EL1_MPU_REGIONXX_BASE(00)
333 #define EL1_MPU_REGION00_LIMIT    EL1_MPU_REGIONXX_LIMIT(00)
334 
335 /* region 1 */
336 #define EL1_MPU_REGION01_BASE     EL1_MPU_REGIONXX_BASE(01)
337 #define EL1_MPU_REGION01_LIMIT    EL1_MPU_REGIONXX_LIMIT(01)
338 
339 /* region 2 */
340 #define EL1_MPU_REGION02_BASE     EL1_MPU_REGIONXX_BASE(02)
341 #define EL1_MPU_REGION02_LIMIT    EL1_MPU_REGIONXX_LIMIT(02)
342 
343 /* region 3 */
344 #define EL1_MPU_REGION03_BASE     EL1_MPU_REGIONXX_BASE(03)
345 #define EL1_MPU_REGION03_LIMIT    EL1_MPU_REGIONXX_LIMIT(03)
346 
347 /* region 4 */
348 #define EL1_MPU_REGION04_BASE     EL1_MPU_REGIONXX_BASE(04)
349 #define EL1_MPU_REGION04_LIMIT    EL1_MPU_REGIONXX_LIMIT(04)
350 
351 /* region 5 */
352 #define EL1_MPU_REGION05_BASE     EL1_MPU_REGIONXX_BASE(05)
353 #define EL1_MPU_REGION05_LIMIT    EL1_MPU_REGIONXX_LIMIT(05)
354 
355 /* region 6 */
356 #define EL1_MPU_REGION06_BASE     EL1_MPU_REGIONXX_BASE(06)
357 #define EL1_MPU_REGION06_LIMIT    EL1_MPU_REGIONXX_LIMIT(06)
358 
359 /* region 7 */
360 #define EL1_MPU_REGION07_BASE     EL1_MPU_REGIONXX_BASE(07)
361 #define EL1_MPU_REGION07_LIMIT    EL1_MPU_REGIONXX_LIMIT(07)
362 
363 /* region 8 */
364 #define EL1_MPU_REGION08_BASE     EL1_MPU_REGIONXX_BASE(08)
365 #define EL1_MPU_REGION08_LIMIT    EL1_MPU_REGIONXX_LIMIT(08)
366 
367 /* region 9 */
368 #define EL1_MPU_REGION09_BASE     EL1_MPU_REGIONXX_BASE(09)
369 #define EL1_MPU_REGION09_LIMIT    EL1_MPU_REGIONXX_LIMIT(09)
370 
371 /* region 10 */
372 #define EL1_MPU_REGION10_BASE     EL1_MPU_REGIONXX_BASE(10)
373 #define EL1_MPU_REGION10_LIMIT    EL1_MPU_REGIONXX_LIMIT(10)
374 
375 /* region 11 */
376 #define EL1_MPU_REGION11_BASE     EL1_MPU_REGIONXX_BASE(11)
377 #define EL1_MPU_REGION11_LIMIT    EL1_MPU_REGIONXX_LIMIT(11)
378 
379 /* region 12 */
380 #define EL1_MPU_REGION12_BASE     EL1_MPU_REGIONXX_BASE(12)
381 #define EL1_MPU_REGION12_LIMIT    EL1_MPU_REGIONXX_LIMIT(12)
382 
383 /* region 13 */
384 #define EL1_MPU_REGION13_BASE     EL1_MPU_REGIONXX_BASE(13)
385 #define EL1_MPU_REGION13_LIMIT    EL1_MPU_REGIONXX_LIMIT(13)
386 
387 /* region 14 */
388 #define EL1_MPU_REGION14_BASE     EL1_MPU_REGIONXX_BASE(14)
389 #define EL1_MPU_REGION14_LIMIT    EL1_MPU_REGIONXX_LIMIT(14)
390 
391 /* region 15 */
392 #define EL1_MPU_REGION15_BASE     EL1_MPU_REGIONXX_BASE(15)
393 #define EL1_MPU_REGION15_LIMIT    EL1_MPU_REGIONXX_LIMIT(15)
394 
395 /* region 16 */
396 #define EL1_MPU_REGION16_BASE     EL1_MPU_REGIONXX_BASE(16)
397 #define EL1_MPU_REGION16_LIMIT    EL1_MPU_REGIONXX_LIMIT(16)
398 
399 /* region 17 */
400 #define EL1_MPU_REGION17_BASE     EL1_MPU_REGIONXX_BASE(17)
401 #define EL1_MPU_REGION17_LIMIT    EL1_MPU_REGIONXX_LIMIT(17)
402 
403 /* region 18 */
404 #define EL1_MPU_REGION18_BASE     EL1_MPU_REGIONXX_BASE(18)
405 #define EL1_MPU_REGION18_LIMIT    EL1_MPU_REGIONXX_LIMIT(18)
406 
407 /* region 19 */
408 #define EL1_MPU_REGION19_BASE     EL1_MPU_REGIONXX_BASE(19)
409 #define EL1_MPU_REGION19_LIMIT    EL1_MPU_REGIONXX_LIMIT(19)
410 
411 /* region 20 */
412 #define EL1_MPU_REGION20_BASE     EL1_MPU_REGIONXX_BASE(20)
413 #define EL1_MPU_REGION20_LIMIT    EL1_MPU_REGIONXX_LIMIT(20)
414 
415 /* region 21 */
416 #define EL1_MPU_REGION21_BASE     EL1_MPU_REGIONXX_BASE(21)
417 #define EL1_MPU_REGION21_LIMIT    EL1_MPU_REGIONXX_LIMIT(21)
418 
419 /* region 22 */
420 #define EL1_MPU_REGION22_BASE     EL1_MPU_REGIONXX_BASE(22)
421 #define EL1_MPU_REGION22_LIMIT    EL1_MPU_REGIONXX_LIMIT(22)
422 
423 /* region 23 */
424 #define EL1_MPU_REGION23_BASE     EL1_MPU_REGIONXX_BASE(23)
425 #define EL1_MPU_REGION23_LIMIT    EL1_MPU_REGIONXX_LIMIT(23)
426 
427 /***********************************************************************************************************************
428  * Typedef definitions
429  **********************************************************************************************************************/
430 typedef struct st_bsp_mpu_config
431 {
432     uint32_t base;
433     uint32_t limit;
434 } bsp_mpu_config_t;
435 
436 /***********************************************************************************************************************
437  * Global Variables
438  **********************************************************************************************************************/
439 
440 /* This vector table is for SGI and PPI interrupts. */
441 BSP_DONT_REMOVE fsp_vector_t g_sgi_ppi_vector_table[BSP_CORTEX_VECTOR_TABLE_ENTRIES] =
442 {
443     NULL,                              /* INTID0    : SOFTWARE_GENERATE_INT0                   */
444     NULL,                              /* INTID1    : SOFTWARE_GENERATE_INT1                   */
445     NULL,                              /* INTID2    : SOFTWARE_GENERATE_INT2                   */
446     NULL,                              /* INTID3    : SOFTWARE_GENERATE_INT3                   */
447     NULL,                              /* INTID4    : SOFTWARE_GENERATE_INT4                   */
448     NULL,                              /* INTID5    : SOFTWARE_GENERATE_INT5                   */
449     NULL,                              /* INTID6    : SOFTWARE_GENERATE_INT6                   */
450     NULL,                              /* INTID7    : SOFTWARE_GENERATE_INT7                   */
451     NULL,                              /* INTID8    : SOFTWARE_GENERATE_INT8                   */
452     NULL,                              /* INTID9    : SOFTWARE_GENERATE_INT9                   */
453     NULL,                              /* INTID10   : SOFTWARE_GENERATE_INT10                  */
454     NULL,                              /* INTID11   : SOFTWARE_GENERATE_INT11                  */
455     NULL,                              /* INTID12   : SOFTWARE_GENERATE_INT12                  */
456     NULL,                              /* INTID13   : SOFTWARE_GENERATE_INT13                  */
457     NULL,                              /* INTID14   : SOFTWARE_GENERATE_INT14                  */
458     NULL,                              /* INTID15   : SOFTWARE_GENERATE_INT15                  */
459     NULL,                              /* INTID16   : RESERVED                                 */
460     NULL,                              /* INTID17   : RESERVED                                 */
461     NULL,                              /* INTID18   : RESERVED                                 */
462     NULL,                              /* INTID19   : RESERVED                                 */
463     NULL,                              /* INTID20   : RESERVED                                 */
464     NULL,                              /* INTID21   : RESERVED                                 */
465     NULL,                              /* INTID22   : DEBUG_COMMUNICATIONS_CHANNEL_INT         */
466     NULL,                              /* INTID23   : PERFORMANCE_MONITOR_COUNTER_OVERFLOW_INT */
467     NULL,                              /* INTID24   : CROSS_TRIGGER_INTERFACE_INT              */
468     NULL,                              /* INTID25   : VIRTUAL_CPU_INTERFACE_MAINTENANCE_INT    */
469     NULL,                              /* INTID26   : HYPERVISOR_TIMER_INT                     */
470     NULL,                              /* INTID27   : VIRTUAL_TIMER_INT                        */
471     NULL,                              /* INTID28   : RESERVED                                 */
472     NULL,                              /* INTID29   : RESERVED                                 */
473     NULL,                              /* INTID30   : NON-SECURE_PHYSICAL_TIMER_INT            */
474     NULL,                              /* INTID31   : RESERVED                                 */
475 };
476 
477 /***********************************************************************************************************************
478  * Exported global variables (to be accessed by other files)
479  **********************************************************************************************************************/
480 
481 /***********************************************************************************************************************
482  * Exported global functions (to be accessed by other files)
483  **********************************************************************************************************************/
484 
485 /***********************************************************************************************************************
486  * Private global variables and functions
487  **********************************************************************************************************************/
488 static const bsp_mpu_config_t g_bsp_el1_mpu[EL1_MPU_REGION_COUNT] =
489 {
490     {EL1_MPU_REGION00_BASE, EL1_MPU_REGION00_LIMIT},
491     {EL1_MPU_REGION01_BASE, EL1_MPU_REGION01_LIMIT},
492     {EL1_MPU_REGION02_BASE, EL1_MPU_REGION02_LIMIT},
493     {EL1_MPU_REGION03_BASE, EL1_MPU_REGION03_LIMIT},
494     {EL1_MPU_REGION04_BASE, EL1_MPU_REGION04_LIMIT},
495     {EL1_MPU_REGION05_BASE, EL1_MPU_REGION05_LIMIT},
496     {EL1_MPU_REGION06_BASE, EL1_MPU_REGION06_LIMIT},
497     {EL1_MPU_REGION07_BASE, EL1_MPU_REGION07_LIMIT},
498     {EL1_MPU_REGION08_BASE, EL1_MPU_REGION08_LIMIT},
499     {EL1_MPU_REGION09_BASE, EL1_MPU_REGION09_LIMIT},
500     {EL1_MPU_REGION10_BASE, EL1_MPU_REGION10_LIMIT},
501     {EL1_MPU_REGION11_BASE, EL1_MPU_REGION11_LIMIT},
502     {EL1_MPU_REGION12_BASE, EL1_MPU_REGION12_LIMIT},
503     {EL1_MPU_REGION13_BASE, EL1_MPU_REGION13_LIMIT},
504     {EL1_MPU_REGION14_BASE, EL1_MPU_REGION14_LIMIT},
505     {EL1_MPU_REGION15_BASE, EL1_MPU_REGION15_LIMIT},
506     {EL1_MPU_REGION16_BASE, EL1_MPU_REGION16_LIMIT},
507     {EL1_MPU_REGION17_BASE, EL1_MPU_REGION17_LIMIT},
508     {EL1_MPU_REGION18_BASE, EL1_MPU_REGION18_LIMIT},
509     {EL1_MPU_REGION19_BASE, EL1_MPU_REGION19_LIMIT},
510     {EL1_MPU_REGION20_BASE, EL1_MPU_REGION20_LIMIT},
511     {EL1_MPU_REGION21_BASE, EL1_MPU_REGION21_LIMIT},
512     {EL1_MPU_REGION22_BASE, EL1_MPU_REGION22_LIMIT},
513     {EL1_MPU_REGION23_BASE, EL1_MPU_REGION23_LIMIT},
514 };
515 
516 #if __FPU_USED
517 void bsp_fpu_advancedsimd_init(void);
518 
519 #endif
520 
521 #if (0 == BSP_CFG_CORE_CR52)
522 void bsp_slavetcm_enable(void);
523 
524 #endif
525 
526 void bsp_memory_protect_setting(void);
527 void bsp_mpu_init(uint32_t region, uint32_t base, uint32_t limit);
528 void bsp_irq_cfg_common(void);
529 
530 #if __FPU_USED
531 
532 /*******************************************************************************************************************//**
533  * Initialize FPU and Advanced SIMD setting.
534  **********************************************************************************************************************/
bsp_fpu_advancedsimd_init(void)535 void bsp_fpu_advancedsimd_init (void)
536 {
537     uint32_t apacr;
538     uint32_t fpexc;
539 
540     /* Enables cp10 and cp11 accessing */
541     apacr  = __get_CPACR();
542     apacr |= BSP_CPCAR_CP_ENABLE;
543     __set_CPACR(apacr);
544     __ISB();
545 
546     /* Enables the FPU */
547     fpexc  = __get_FPEXC();
548     fpexc |= BSP_FPEXC_EN_ENABLE;
549     __set_FPEXC(fpexc);
550     __ISB();
551 }
552 
553 #endif
554 
555 #if (0 == BSP_CFG_CORE_CR52)
556 
557 /*******************************************************************************************************************//**
558  * Settings the privilege level required for the AXIS to access the TCM.
559  **********************************************************************************************************************/
bsp_slavetcm_enable(void)560 void bsp_slavetcm_enable (void)
561 {
562     uint32_t imp_slavepctlr;
563 
564     /* Enable TCM access privilege and non privilege */
565     imp_slavepctlr  = __get_IMP_SLAVEPCTLR();
566     imp_slavepctlr |= BSP_TCM_ALL_ACCESS_ENABLE;
567     __DSB();
568 
569     __set_IMP_SLAVEPCTLR(imp_slavepctlr);
570     __ISB();
571 }
572 
573 #endif
574 
575 /*******************************************************************************************************************//**
576  * Initialize memory protection settings.
577  **********************************************************************************************************************/
bsp_memory_protect_setting(void)578 void bsp_memory_protect_setting (void)
579 {
580     uint32_t sctlr;
581     uint32_t mair0;
582     uint32_t mair1;
583     uint32_t region;
584     uint32_t base_address;
585     uint32_t limit_address;
586 
587 #if (1 != _RZN_ORDINAL) && (0 == BSP_FEATURE_BSP_HAS_SYSTEMRAM_MIRROR_AREA)
588  #if defined(__ICCARM__)
589   #pragma section="USER_DATA_NONCACHE_WBLOCK"
590     uint32_t cache_end      = (uint32_t) __section_begin("USER_DATA_NONCACHE_WBLOCK") - 1;
591     uint32_t noncache_start = (uint32_t) __section_begin("USER_DATA_NONCACHE_WBLOCK");
592  #elif defined(__GNUC__)
593     extern void * _data_noncache_start;
594     uint32_t      cache_end      = (uint32_t) &_data_noncache_start - 1;
595     uint32_t      noncache_start = (uint32_t) &_data_noncache_start;
596  #endif
597 #endif
598 
599     /* Adopt EL1 default memory map as background map */
600     sctlr  = __get_SCTLR();
601     sctlr |= BSP_SCTLR_BR_BIT;
602     __DSB();
603     __set_SCTLR(sctlr);
604     __ISB();
605 
606     /* Configure Memory Attribute Indirection Registers */
607     mair0 = ATTR_3_2_1_0;
608     mair1 = ATTR_7_6_5_4;
609     __set_MAIR0(mair0);
610     __set_MAIR1(mair1);
611     __DSB();
612 
613     /* Setup region. */
614     for (region = 0; region < EL1_MPU_REGION_COUNT; region++)
615     {
616         base_address  = g_bsp_el1_mpu[region].base;
617         limit_address = g_bsp_el1_mpu[region].limit;
618 
619 #if (1 != _RZN_ORDINAL) && (0 == BSP_FEATURE_BSP_HAS_SYSTEMRAM_MIRROR_AREA)
620         if ((EL1_MPU_REGION_SYSTEMRAM_CACHE_ADDRESS_START == (base_address & EL1_MPU_REGION_ADDRESS_MASK)) &&
621             (EL1_MPU_REGION_SYSTEMRAM_CACHE_ADDRESS_END == (limit_address & EL1_MPU_REGION_ADDRESS_MASK)))
622         {
623             limit_address = (cache_end & EL1_MPU_REGION_ADDRESS_MASK) |
624                             (g_bsp_el1_mpu[region].limit & EL1_MPU_REGION_ATTRIBUTE_MASK);
625         }
626         else if ((EL1_MPU_REGION_SYSTEMRAM_NONCACHE_ADDRESS_START == (base_address & EL1_MPU_REGION_ADDRESS_MASK)) &&
627                  (EL1_MPU_REGION_SYSTEMRAM_NONCACHE_ADDRESS_END == (limit_address & EL1_MPU_REGION_ADDRESS_MASK)))
628         {
629             base_address = (noncache_start & EL1_MPU_REGION_ADDRESS_MASK) |
630                            (g_bsp_el1_mpu[region].base & EL1_MPU_REGION_ATTRIBUTE_MASK);
631         }
632         else
633         {
634             // Do Nothing
635         }
636 #endif
637 
638         bsp_mpu_init(region, base_address, limit_address);
639     }
640 
641     R_BSP_CacheInvalidateAll();
642 
643     R_BSP_CacheEnableMemoryProtect();
644 
645 #if (BSP_ICACHE_ENABLE == BSP_CFG_SCTLR_I_BIT)
646     R_BSP_CacheEnableInst();
647 #else
648     R_BSP_CacheDisableInst();
649 #endif
650 
651 #if (BSP_DATACACHE_ENABLE == BSP_CFG_SCTLR_C_BIT)
652     R_BSP_CacheEnableData();
653 #else
654     R_BSP_CacheDisableData();
655 #endif
656 }
657 
658 /*******************************************************************************************************************//**
659  * Core MPU initialization block.
660  **********************************************************************************************************************/
bsp_mpu_init(uint32_t region,uint32_t base,uint32_t limit)661 void bsp_mpu_init (uint32_t region, uint32_t base, uint32_t limit)
662 {
663     /* Selects the current EL1-controlled MPU region registers, PRBAR, and PRLAR */
664     __set_PRSELR(region);
665     __DSB();
666 
667     /* Set the base address and attributes of the MPU region controlled by EL1 */
668     __set_PRBAR(base);
669     __DSB();
670 
671     /* Set the limit address and attributes of the MPU region controlled by EL1 */
672     __set_PRLAR(limit);
673     __DSB();
674 }
675 
676 /*******************************************************************************************************************//**
677  * Initialize common configuration settings for interrupts
678  **********************************************************************************************************************/
bsp_irq_cfg_common(void)679 void bsp_irq_cfg_common (void)
680 {
681     uint32_t icc_pmr;
682     uint32_t icc_igrpen1;
683     uint32_t icc_ctlr;
684 
685     /* Set priority mask level for CPU interface */
686     icc_pmr = BSP_PRIORITY_MASK;
687     __set_ICC_PMR(icc_pmr);
688 
689     /* Enable group 1 interrupts */
690     icc_igrpen1 = BSP_ENABLE_GROUP_INT;
691     __set_ICC_IGRPEN1(icc_igrpen1);
692 
693     /* Use ICC_BPR0 for interrupt preemption for both group 0 and group 1 interrupts */
694     icc_ctlr  = __get_ICC_CTLR();
695     icc_ctlr |= BSP_ICC_CTLR;
696     __set_ICC_CTLR(icc_ctlr);
697 
698     __ISB();
699 }
700