1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef BSP_CLOCKS_H 8 #define BSP_CLOCKS_H 9 10 /*********************************************************************************************************************** 11 * Includes 12 **********************************************************************************************************************/ 13 #include "bsp_clock_cfg.h" 14 #include "bsp_api.h" 15 16 /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 17 FSP_HEADER 18 19 /*********************************************************************************************************************** 20 * Macro definitions 21 **********************************************************************************************************************/ 22 23 /* Startup clock frequency of each system clock. These macros are only helpful if the system clock and dividers have 24 * not changed since startup. These macros are not used in FSP modules except for the clock startup code. */ 25 26 /* xSPI unit0 clock options. */ 27 #define BSP_CLOCKS_XSPI0_CLOCK_DIV0_150_0_MHZ (0x01) // xSPI0 base clock 800MHz and xSPI0 clock 150.0MHz. 28 #define BSP_CLOCKS_XSPI0_CLOCK_DIV0_133_3_MHZ (0x02) // xSPI0 base clock 800MHz and xSPI0 clock 133.3MHz. 29 #define BSP_CLOCKS_XSPI0_CLOCK_DIV0_100_0_MHZ (0x03) // xSPI0 base clock 800MHz and xSPI0 clock 100.0 MHz. 30 #define BSP_CLOCKS_XSPI0_CLOCK_DIV0_50_0_MHZ (0x04) // xSPI0 base clock 800MHz and xSPI0 clock 50.0 MHz. 31 #define BSP_CLOCKS_XSPI0_CLOCK_DIV0_25_0_MHZ (0x05) // xSPI0 base clock 800MHz and xSPI0 clock 25.0 MHz. 32 #define BSP_CLOCKS_XSPI0_CLOCK_DIV0_12_5_MHZ (0x06) // xSPI0 base clock 800MHz and xSPI0 clock 12.5 MHz. 33 #define BSP_CLOCKS_XSPI0_CLOCK_DIV1_75_0_MHZ (0x43) // xSPI0 base clock 600MHz and xSPI0 clock 75.0 MHz. 34 #define BSP_CLOCKS_XSPI0_CLOCK_DIV1_37_5_MHZ (0x44) // xSPI0 base clock 600MHz and xSPI0 clock 37.5 MHz. 35 36 /* xSPI unit1 clock options. */ 37 #define BSP_CLOCKS_XSPI1_CLOCK_DIV0_150_0_MHZ (0x01) // xSPI1 base clock 800MHz and xSPI1 clock 150.0MHz. 38 #define BSP_CLOCKS_XSPI1_CLOCK_DIV0_133_3_MHZ (0x02) // xSPI1 base clock 800MHz and xSPI1 clock 133.3MHz. 39 #define BSP_CLOCKS_XSPI1_CLOCK_DIV0_100_0_MHZ (0x03) // xSPI1 base clock 800MHz and xSPI1 clock 100.0 MHz. 40 #define BSP_CLOCKS_XSPI1_CLOCK_DIV0_50_0_MHZ (0x04) // xSPI1 base clock 800MHz and xSPI1 clock 50.0 MHz. 41 #define BSP_CLOCKS_XSPI1_CLOCK_DIV0_25_0_MHZ (0x05) // xSPI1 base clock 800MHz and xSPI1 clock 25.0 MHz. 42 #define BSP_CLOCKS_XSPI1_CLOCK_DIV0_12_5_MHZ (0x06) // xSPI1 base clock 800MHz and xSPI1 clock 12.5 MHz. 43 #define BSP_CLOCKS_XSPI1_CLOCK_DIV1_75_0_MHZ (0x43) // xSPI1 base clock 600MHz and xSPI1 clock 75.0 MHz. 44 #define BSP_CLOCKS_XSPI1_CLOCK_DIV1_37_5_MHZ (0x44) // xSPI1 base clock 600MHz and xSPI1 clock 37.5 MHz. 45 46 /* CKIO clock options. */ 47 #if (1U == BSP_FEATURE_CGC_CKIO_CLOCK_FREQ_TYPE) 48 #define BSP_CLOCKS_CKIO_ICLK_DIV2 (0) // CKIO clock 100.0 MHz (when SCKCR2.DIVSELSUB = 0), 49 // or 75.0 MHz (when SCKCR2.DIVSELSUB = 1). 50 #define BSP_CLOCKS_CKIO_ICLK_DIV3 (1) // CKIO clock 66.7 MHz (when SCKCR2.DIVSELSUB = 0), 51 // or 50.0 MHz (when SCKCR2.DIVSELSUB = 1). 52 #define BSP_CLOCKS_CKIO_ICLK_DIV4 (2) // CKIO clock 50.0 MHz (when SCKCR2.DIVSELSUB = 0), 53 // or 37.5 MHz (when SCKCR2.DIVSELSUB = 1). 54 #define BSP_CLOCKS_CKIO_ICLK_DIV5 (3) // CKIO clock 40.0 MHz (when SCKCR2.DIVSELSUB = 0), 55 // or 30.0 MHz (when SCKCR2.DIVSELSUB = 1). 56 #define BSP_CLOCKS_CKIO_ICLK_DIV6 (4) // CKIO clock 33.3 MHz (when SCKCR2.DIVSELSUB = 0), 57 // or 25.0 MHz (when SCKCR2.DIVSELSUB = 1). 58 #define BSP_CLOCKS_CKIO_ICLK_DIV7 (5) // CKIO clock 28.6 MHz (when SCKCR2.DIVSELSUB = 0), 59 // or 21.4 MHz (when SCKCR2.DIVSELSUB = 1). 60 #define BSP_CLOCKS_CKIO_ICLK_DIV8 (6) // CKIO clock 25.0 MHz (when SCKCR2.DIVSELSUB = 0), 61 // or 18.75 MHz (when SCKCR2.DIVSELSUB = 1). 62 #elif (2U == BSP_FEATURE_CGC_CKIO_CLOCK_FREQ_TYPE) 63 #define BSP_CLOCKS_CKIO_125_0_MHZ (0) // CKIO clock 125.0 MHz. 64 #define BSP_CLOCKS_CKIO_83_3_MHZ (1) // CKIO clock 83.3 MHz. 65 #define BSP_CLOCKS_CKIO_62_5_MHZ (2) // CKIO clock 62.5 MHz. 66 #define BSP_CLOCKS_CKIO_50_0_MHZ (3) // CKIO clock 50.0 MHz. 67 #define BSP_CLOCKS_CKIO_41_7_MHZ (4) // CKIO clock 41.7 MHz. 68 #define BSP_CLOCKS_CKIO_35_7_MHZ (5) // CKIO clock 35.7 MHz. 69 #define BSP_CLOCKS_CKIO_31_25_MHZ (6) // CKIO clock 31.25 MHz. 70 #endif 71 72 /* CANFD clock options. */ 73 #define BSP_CLOCKS_CANFD_CLOCK_80_MHZ (0) // CANFD clock 80 MHz. 74 #define BSP_CLOCKS_CANFD_CLOCK_40_MHZ (1) // CANFD clock 40 MHz. 75 #define BSP_CLOCKS_CANFD_CLOCK_PCLKM (1) // CANFD clock source PCLKM. 76 77 /* ENCOUT clock options. */ 78 #define BSP_CLOCKS_ENCO_CLOCK_80_MHZ (1) // ENCOUT clock 80 MHz. 79 #define BSP_CLOCKS_ENCO_CLOCK_20_MHZ (0) // ENCOUT clock 20 MHz. 80 81 /* Ethernet PHY reference clock (ETHn_REFCLK : n = 0 to 2) options. */ 82 #define BSP_CLOCKS_PHYSEL_PLL1_DIV (0) // PLL1 devider clock. 83 #define BSP_CLOCKS_PHYSEL_MAINOSC_DIV (1) // Main clock oscillator. 84 85 /* Alternative clock options when main clock abnormal oscillation is detected. */ 86 #define BSP_CLOCKS_CLMASEL_LOCO (0) // LOCO clock. 87 #define BSP_CLOCKS_CLMASEL_PLL (1) // PLL clock. 88 89 /* LCDC clock options. */ 90 #define BSP_CLOCKS_LCDCDIVSEL_DIV_2 (0x00) // Divide LCDC source clock by 2. 91 #define BSP_CLOCKS_LCDCDIVSEL_DIV_4 (0x01) // Divide LCDC source clock by 4. 92 #define BSP_CLOCKS_LCDCDIVSEL_DIV_6 (0x02) // Divide LCDC source clock by 6. 93 #define BSP_CLOCKS_LCDCDIVSEL_DIV_8 (0x03) // Divide LCDC source clock by 8. 94 #define BSP_CLOCKS_LCDCDIVSEL_DIV_10 (0x04) // Divide LCDC source clock by 10. 95 #define BSP_CLOCKS_LCDCDIVSEL_DIV_12 (0x05) // Divide LCDC source clock by 12. 96 #define BSP_CLOCKS_LCDCDIVSEL_DIV_14 (0x06) // Divide LCDC source clock by 14. 97 #define BSP_CLOCKS_LCDCDIVSEL_DIV_16 (0x07) // Divide LCDC source clock by 16. 98 #define BSP_CLOCKS_LCDCDIVSEL_DIV_18 (0x08) // Divide LCDC source clock by 18. 99 #define BSP_CLOCKS_LCDCDIVSEL_DIV_20 (0x09) // Divide LCDC source clock by 20. 100 #define BSP_CLOCKS_LCDCDIVSEL_DIV_22 (0x0A) // Divide LCDC source clock by 22. 101 #define BSP_CLOCKS_LCDCDIVSEL_DIV_24 (0x0B) // Divide LCDC source clock by 24. 102 #define BSP_CLOCKS_LCDCDIVSEL_DIV_26 (0x0C) // Divide LCDC source clock by 26. 103 #define BSP_CLOCKS_LCDCDIVSEL_DIV_28 (0x0D) // Divide LCDC source clock by 28. 104 #define BSP_CLOCKS_LCDCDIVSEL_DIV_30 (0x0E) // Divide LCDC source clock by 30. 105 #define BSP_CLOCKS_LCDCDIVSEL_DIV_32 (0x0F) // Divide LCDC source clock by 32. 106 107 /* SPI clock options. */ 108 #if (1U == BSP_FEATURE_CGC_PCLKSPI_CLOCK_FREQ_TYPE) 109 #define BSP_CLOCKS_SPI0_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SPI0 asynchronous serial clock 75.0 MHz. 110 #define BSP_CLOCKS_SPI0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SPI0 asynchronous serial clock 96.0 MHz. 111 #define BSP_CLOCKS_SPI1_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SPI1 asynchronous serial clock 75.0 MHz. 112 #define BSP_CLOCKS_SPI1_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SPI1 asynchronous serial clock 96.0 MHz. 113 #define BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SPI2 asynchronous serial clock 75.0 MHz. 114 #define BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SPI2 asynchronous serial clock 96.0 MHz. 115 #define BSP_CLOCKS_SPI3_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SPI3 asynchronous serial clock 75.0 MHz. 116 #define BSP_CLOCKS_SPI3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SPI3 asynchronous serial clock 96.0 MHz. 117 118 #elif (2U == BSP_FEATURE_CGC_PCLKSPI_CLOCK_FREQ_TYPE) 119 #define BSP_CLOCKS_SPI0_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0x00) // SPI0 asynchronous serial clock 75.0 MHz. 120 #define BSP_CLOCKS_SPI0_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ (0x01) // SPI0 asynchronous serial clock 80.0 MHz. 121 #define BSP_CLOCKS_SPI0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (0x02) // SPI0 asynchronous serial clock 96.0 MHz. 122 #define BSP_CLOCKS_SPI0_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ (0x03) // SPI0 asynchronous serial clock 100.0 MHz. 123 #define BSP_CLOCKS_SPI1_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0x00) // SPI1 asynchronous serial clock 75.0 MHz. 124 #define BSP_CLOCKS_SPI1_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ (0x01) // SPI1 asynchronous serial clock 80.0 MHz. 125 #define BSP_CLOCKS_SPI1_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (0x02) // SPI1 asynchronous serial clock 96.0 MHz. 126 #define BSP_CLOCKS_SPI1_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ (0x03) // SPI1 asynchronous serial clock 100.0 MHz. 127 #define BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0x00) // SPI2 asynchronous serial clock 75.0 MHz. 128 #define BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ (0x01) // SPI2 asynchronous serial clock 80.0 MHz. 129 #define BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (0x02) // SPI2 asynchronous serial clock 96.0 MHz. 130 #define BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ (0x03) // SPI2 asynchronous serial clock 100.0 MHz. 131 #define BSP_CLOCKS_SPI3_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0x00) // SPI3 asynchronous serial clock 75.0 MHz. 132 #define BSP_CLOCKS_SPI3_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ (0x01) // SPI3 asynchronous serial clock 80.0 MHz. 133 #define BSP_CLOCKS_SPI3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (0x02) // SPI3 asynchronous serial clock 96.0 MHz. 134 #define BSP_CLOCKS_SPI3_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ (0x03) // SPI3 asynchronous serial clock 100.0 MHz. 135 #endif 136 137 /* SCI clock options. */ 138 #if (1U == BSP_FEATURE_CGC_PCLKSCI_CLOCK_FREQ_TYPE) 139 #define BSP_CLOCKS_SCI0_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SCI0 asynchronous serial clock 75.0 MHz. 140 #define BSP_CLOCKS_SCI0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SCI0 asynchronous serial clock 96.0 MHz. 141 #define BSP_CLOCKS_SCI1_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SCI1 asynchronous serial clock 75.0 MHz. 142 #define BSP_CLOCKS_SCI1_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SCI1 asynchronous serial clock 96.0 MHz. 143 #define BSP_CLOCKS_SCI2_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SCI2 asynchronous serial clock 75.0 MHz. 144 #define BSP_CLOCKS_SCI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SCI2 asynchronous serial clock 96.0 MHz. 145 #define BSP_CLOCKS_SCI3_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SCI3 asynchronous serial clock 75.0 MHz. 146 #define BSP_CLOCKS_SCI3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SCI3 asynchronous serial clock 96.0 MHz. 147 #define BSP_CLOCKS_SCI4_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SCI4 asynchronous serial clock 75.0 MHz. 148 #define BSP_CLOCKS_SCI4_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SCI4 asynchronous serial clock 96.0 MHz. 149 #define BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SCI5 asynchronous serial clock 75.0 MHz. 150 #define BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SCI5 asynchronous serial clock 96.0 MHz. 151 #elif (2U == BSP_FEATURE_CGC_PCLKSCI_CLOCK_FREQ_TYPE) 152 #define BSP_CLOCKS_SCI0_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0x00) // SCI0 asynchronous serial clock 75.0 MHz. 153 #define BSP_CLOCKS_SCI0_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ (0x01) // SCI0 asynchronous serial clock 80.0 MHz. 154 #define BSP_CLOCKS_SCI0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (0x02) // SCI0 asynchronous serial clock 96.0 MHz. 155 #define BSP_CLOCKS_SCI0_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ (0x03) // SCI0 asynchronous serial clock 100.0 MHz. 156 #define BSP_CLOCKS_SCI1_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0x00) // SCI1 asynchronous serial clock 75.0 MHz. 157 #define BSP_CLOCKS_SCI1_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ (0x01) // SCI1 asynchronous serial clock 80.0 MHz. 158 #define BSP_CLOCKS_SCI1_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (0x02) // SCI1 asynchronous serial clock 96.0 MHz. 159 #define BSP_CLOCKS_SCI1_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ (0x03) // SCI1 asynchronous serial clock 100.0 MHz. 160 #define BSP_CLOCKS_SCI2_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0x00) // SCI2 asynchronous serial clock 75.0 MHz. 161 #define BSP_CLOCKS_SCI2_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ (0x01) // SCI2 asynchronous serial clock 80.0 MHz. 162 #define BSP_CLOCKS_SCI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (0x02) // SCI2 asynchronous serial clock 96.0 MHz. 163 #define BSP_CLOCKS_SCI2_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ (0x03) // SCI2 asynchronous serial clock 100.0 MHz. 164 #define BSP_CLOCKS_SCI3_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0x00) // SCI3 asynchronous serial clock 75.0 MHz. 165 #define BSP_CLOCKS_SCI3_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ (0x01) // SCI3 asynchronous serial clock 80.0 MHz. 166 #define BSP_CLOCKS_SCI3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (0x02) // SCI3 asynchronous serial clock 96.0 MHz. 167 #define BSP_CLOCKS_SCI3_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ (0x03) // SCI3 asynchronous serial clock 100.0 MHz. 168 #define BSP_CLOCKS_SCI4_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0x00) // SCI4 asynchronous serial clock 75.0 MHz. 169 #define BSP_CLOCKS_SCI4_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ (0x01) // SCI4 asynchronous serial clock 80.0 MHz. 170 #define BSP_CLOCKS_SCI4_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (0x02) // SCI4 asynchronous serial clock 96.0 MHz. 171 #define BSP_CLOCKS_SCI4_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ (0x03) // SCI4 asynchronous serial clock 100.0 MHz. 172 #define BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0x00) // SCI5 asynchronous serial clock 75.0 MHz. 173 #define BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ (0x01) // SCI5 asynchronous serial clock 80.0 MHz. 174 #define BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (0x02) // SCI5 asynchronous serial clock 96.0 MHz. 175 #define BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ (0x03) // SCI5 asynchronous serial clock 100.0 MHz. 176 #endif 177 178 /* SCIE clock options. */ 179 #if (1U == BSP_FEATURE_SCIE_SUPPORTED) 180 #define BSP_CLOCKS_SCIE0_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0x00) // SCIE0 asynchronous serial clock 75.0 MHz. 181 #define BSP_CLOCKS_SCIE0_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ (0x01) // SCIE0 asynchronous serial clock 80.0 MHz. 182 #define BSP_CLOCKS_SCIE0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (0x02) // SCIE0 asynchronous serial clock 96.0 MHz. 183 #define BSP_CLOCKS_SCIE0_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ (0x03) // SCIE0 asynchronous serial clock 100.0 MHz. 184 #define BSP_CLOCKS_SCIE1_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0x00) // SCIE1 asynchronous serial clock 75.0 MHz. 185 #define BSP_CLOCKS_SCIE1_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ (0x01) // SCIE1 asynchronous serial clock 80.0 MHz. 186 #define BSP_CLOCKS_SCIE1_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (0x02) // SCIE1 asynchronous serial clock 96.0 MHz. 187 #define BSP_CLOCKS_SCIE1_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ (0x03) // SCIE1 asynchronous serial clock 100.0 MHz. 188 #define BSP_CLOCKS_SCIE2_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0x00) // SCIE2 asynchronous serial clock 75.0 MHz. 189 #define BSP_CLOCKS_SCIE2_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ (0x01) // SCIE2 asynchronous serial clock 80.0 MHz. 190 #define BSP_CLOCKS_SCIE2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (0x02) // SCIE2 asynchronous serial clock 96.0 MHz. 191 #define BSP_CLOCKS_SCIE2_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ (0x03) // SCIE2 asynchronous serial clock 100.0 MHz. 192 #define BSP_CLOCKS_SCIE3_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0x00) // SCIE3 asynchronous serial clock 75.0 MHz. 193 #define BSP_CLOCKS_SCIE3_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ (0x01) // SCIE3 asynchronous serial clock 80.0 MHz. 194 #define BSP_CLOCKS_SCIE3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (0x02) // SCIE3 asynchronous serial clock 96.0 MHz. 195 #define BSP_CLOCKS_SCIE3_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ (0x03) // SCIE3 asynchronous serial clock 100.0 MHz. 196 #define BSP_CLOCKS_SCIE4_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0x00) // SCIE4 asynchronous serial clock 75.0 MHz. 197 #define BSP_CLOCKS_SCIE4_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ (0x01) // SCIE4 asynchronous serial clock 80.0 MHz. 198 #define BSP_CLOCKS_SCIE4_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (0x02) // SCIE4 asynchronous serial clock 96.0 MHz. 199 #define BSP_CLOCKS_SCIE4_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ (0x03) // SCIE4 asynchronous serial clock 100.0 MHz. 200 #define BSP_CLOCKS_SCIE5_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0x00) // SCIE5 asynchronous serial clock 75.0 MHz. 201 #define BSP_CLOCKS_SCIE5_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ (0x01) // SCIE5 asynchronous serial clock 80.0 MHz. 202 #define BSP_CLOCKS_SCIE5_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (0x02) // SCIE5 asynchronous serial clock 96.0 MHz. 203 #define BSP_CLOCKS_SCIE5_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ (0x03) // SCIE5 asynchronous serial clock 100.0 MHz. 204 #define BSP_CLOCKS_SCIE6_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0x00) // SCIE6 asynchronous serial clock 75.0 MHz. 205 #define BSP_CLOCKS_SCIE6_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ (0x01) // SCIE6 asynchronous serial clock 80.0 MHz. 206 #define BSP_CLOCKS_SCIE6_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (0x02) // SCIE6 asynchronous serial clock 96.0 MHz. 207 #define BSP_CLOCKS_SCIE6_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ (0x03) // SCIE6 asynchronous serial clock 100.0 MHz. 208 #define BSP_CLOCKS_SCIE7_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0x00) // SCIE7 asynchronous serial clock 75.0 MHz. 209 #define BSP_CLOCKS_SCIE7_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ (0x01) // SCIE7 asynchronous serial clock 80.0 MHz. 210 #define BSP_CLOCKS_SCIE7_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (0x02) // SCIE7 asynchronous serial clock 96.0 MHz. 211 #define BSP_CLOCKS_SCIE7_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ (0x03) // SCIE7 asynchronous serial clock 100.0 MHz. 212 #define BSP_CLOCKS_SCIE8_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0x00) // SCIE8 asynchronous serial clock 75.0 MHz. 213 #define BSP_CLOCKS_SCIE8_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ (0x01) // SCIE8 asynchronous serial clock 80.0 MHz. 214 #define BSP_CLOCKS_SCIE8_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (0x02) // SCIE8 asynchronous serial clock 96.0 MHz. 215 #define BSP_CLOCKS_SCIE8_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ (0x03) // SCIE8 asynchronous serial clock 100.0 MHz. 216 #define BSP_CLOCKS_SCIE9_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0x00) // SCIE9 asynchronous serial clock 75.0 MHz. 217 #define BSP_CLOCKS_SCIE9_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ (0x01) // SCIE9 asynchronous serial clock 80.0 MHz. 218 #define BSP_CLOCKS_SCIE9_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (0x02) // SCIE9 asynchronous serial clock 96.0 MHz. 219 #define BSP_CLOCKS_SCIE9_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ (0x03) // SCIE9 asynchronous serial clock 100.0 MHz. 220 #define BSP_CLOCKS_SCIE10_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0x00) // SCIE10 asynchronous serial clock 75.0 MHz. 221 #define BSP_CLOCKS_SCIE10_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ (0x01) // SCIE10 asynchronous serial clock 80.0 MHz. 222 #define BSP_CLOCKS_SCIE10_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (0x02) // SCIE10 asynchronous serial clock 96.0 MHz. 223 #define BSP_CLOCKS_SCIE10_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ (0x03) // SCIE10 asynchronous serial clock 100.0 MHz. 224 #define BSP_CLOCKS_SCIE11_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0x00) // SCIE11 asynchronous serial clock 75.0 MHz. 225 #define BSP_CLOCKS_SCIE11_ASYNCHRONOUS_SERIAL_CLOCK_80_MHZ (0x01) // SCIE11 asynchronous serial clock 80.0 MHz. 226 #define BSP_CLOCKS_SCIE11_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (0x02) // SCIE11 asynchronous serial clock 96.0 MHz. 227 #define BSP_CLOCKS_SCIE11_ASYNCHRONOUS_SERIAL_CLOCK_100_MHZ (0x03) // SCIE11 asynchronous serial clock 100.0 MHz. 228 #endif 229 230 #if (1U == BSP_FEATURE_CGC_SCKCR_TYPE) 231 232 /* CR52 CPU0 clock options. */ 233 #define BSP_CLOCKS_FSELCPU0_ICLK_MUL2 (1) // CPU0 clock 400 MHz (when SCKCR2.DIVSELSUB = 0), 234 // or 300 MHz (when SCKCR2.DIVSELSUB = 1). 235 #define BSP_CLOCKS_FSELCPU0_ICLK_MUL1 (0) // CPU0 clock 200 MHz (when SCKCR2.DIVSELSUB = 0), 236 // or 150 MHz (when SCKCR2.DIVSELSUB = 1). 237 238 /* Peripheral module base clock options. */ 239 #define BSP_CLOCKS_DIVSELSUB_0 (0) // ICLK:200MHz, PCLKH:200MHz, PCLKM:100MHz, 240 // PCLKL:50MHz, PCLKADC:25MHz, PCLKGPTL:400MHz. 241 #define BSP_CLOCKS_DIVSELSUB_1 (1) // ICLK:150MHz, PCLKH:150MHz, PCLKM:75 MHz, 242 // PCLKL:37.5MHz, PCLKADC:18.75MHz, PCLKGPTL:300MHz. 243 244 #elif (2U == BSP_FEATURE_CGC_SCKCR_TYPE) 245 246 /* CR52 CPU0 clock options. */ 247 #define BSP_CLOCKS_CR52CPU0_500_MHZ (0) // CPU0 clock 500 MHz. 248 #define BSP_CLOCKS_CR52CPU0_1000_MHZ (1) // CPU0 clock 1000 MHz. 249 250 /* CR52 CPU1 clock options. */ 251 #define BSP_CLOCKS_CR52CPU1_500_MHZ (0) // CPU1 clock 500 MHz. 252 #define BSP_CLOCKS_CR52CPU1_1000_MHZ (1) // CPU1 clock 1000 MHz. 253 254 /* CA55 core0 clock options. */ 255 #define BSP_CLOCKS_CA55CORE0_600_MHZ (0) // CA55 core0 clock 600 MHz. 256 #define BSP_CLOCKS_CA55CORE0_1200_MHZ (1) // CA55 core0 clock 1200 MHz. 257 258 /* CA55 core1 clock options. */ 259 #define BSP_CLOCKS_CA55CORE1_600_MHZ (0) // CA55 core1 clock 600 MHz. 260 #define BSP_CLOCKS_CA55CORE1_1200_MHZ (1) // CA55 core1 clock 1200 MHz. 261 262 /* CA55 core2 clock options. */ 263 #define BSP_CLOCKS_CA55CORE2_600_MHZ (0) // CA55 core2 clock 600 MHz. 264 #define BSP_CLOCKS_CA55CORE2_1200_MHZ (1) // CA55 core2 clock 1200 MHz. 265 266 /* CA55 core3 clock options. */ 267 #define BSP_CLOCKS_CA55CORE3_600_MHZ (0) // CA55 core3 clock 600 MHz. 268 #define BSP_CLOCKS_CA55CORE3_1200_MHZ (1) // CA55 core3 clock 1200 MHz. 269 270 /* CA55 SCU CLOCK options. */ 271 #define BSP_CLOCKS_CA55SCLK_500_MHZ (0) // CA55 SCU clock 500 MHz. 272 #define BSP_CLOCKS_CA55SCLK_1000_MHZ (1) // CA55 SCU clock 1000 MHz. 273 #endif 274 275 /* LOCO enable options. */ 276 #define BSP_CLOCKS_LOCO_DISABLE (0) // LOCO Stop 277 #define BSP_CLOCKS_LOCO_ENABLE (1) // LOCO Run 278 279 /* PLL0 enable options. */ 280 #define BSP_CLOCKS_PLL0_STANDBY (0) // PLL0 is standby state. 281 #define BSP_CLOCKS_PLL0_NORMAL (1) // PLL0 is normal state. 282 283 /* PLL1 enable options. */ 284 #define BSP_CLOCKS_PLL1_INITIAL (0xFF) // Initial (This value should not be reflected in the register) 285 #define BSP_CLOCKS_PLL1_STANDBY (0) // PLL1 is standby state. 286 #define BSP_CLOCKS_PLL1_NORMAL (1) // PLL1 is normal state. 287 288 /* PLL2 enable options. */ 289 #define BSP_CLOCKS_PLL2_STANDBY (0) // PLL2 is standby state. 290 #define BSP_CLOCKS_PLL2_NORMAL (1) // PLL2 is normal state. 291 292 /* PLL3 enable options. */ 293 #define BSP_CLOCKS_PLL3_STANDBY (0) // PLL3 is standby state. 294 #define BSP_CLOCKS_PLL3_NORMAL (1) // PLL3 is normal state. 295 296 /* PLL0 SSC options. */ 297 #define BSP_CLOCKS_PLL0SSCEN_DISABLE (0) // PLL0 SSC function is enabled 298 #define BSP_CLOCKS_PLL0SSCEN_ENABLE (1) // PLL0 SSC function is disabled 299 300 /* PLL2 SSC options. */ 301 #define BSP_CLOCKS_PLL2SSCEN_DISABLE (0) // PLL2 SSC function is enabled 302 #define BSP_CLOCKS_PLL2SSCEN_ENABLE (1) // PLL2 SSC function is disabled 303 304 /* CLMA error mask options. */ 305 #define BSP_CLOCKS_CLMA0_ERROR_MASK (0) // CLMA0 error is not transferred to POE3 and POEG. 306 #define BSP_CLOCKS_CLMA0_ERROR_NOT_MASK (1) // CLMA0 error is transferred to POE3 and POEG. 307 #define BSP_CLOCKS_CLMA1_ERROR_MASK (0) // CLMA1 error is not transferred to POE3 and POEG. 308 #define BSP_CLOCKS_CLMA1_ERROR_NOT_MASK (1) // CLMA1 error is transferred to POE3 and POEG. 309 #define BSP_CLOCKS_CLMA2_ERROR_MASK (0) // CLMA0 error is not transferred to POE3 and POEG. 310 #define BSP_CLOCKS_CLMA2_ERROR_NOT_MASK (1) // CLMA0 error is transferred to POE3 and POEG. 311 #define BSP_CLOCKS_CLMA3_ERROR_MASK (0) // CLMA3 error is not transferred to POE3 and POEG. 312 #define BSP_CLOCKS_CLMA3_ERROR_NOT_MASK (1) // CLMA3 error is transferred to POE3 and POEG. 313 #define BSP_CLOCKS_CLMA4_ERROR_MASK (0) // CLMA4 error is not transferred to POE3 and POEG. 314 #define BSP_CLOCKS_CLMA4_ERROR_NOT_MASK (1) // CLMA4 error is transferred to POE3 and POEG. 315 #define BSP_CLOCKS_CLMA5_ERROR_MASK (0) // CLMA5 error is not transferred to POE3 and POEG. 316 #define BSP_CLOCKS_CLMA5_ERROR_NOT_MASK (1) // CLMA5 error is transferred to POE3 and POEG. 317 #define BSP_CLOCKS_CLMA6_ERROR_MASK (0) // CLMA6 error is not transferred to POE3 and POEG. 318 #define BSP_CLOCKS_CLMA6_ERROR_NOT_MASK (1) // CLMA6 error is transferred to POE3 and POEG. 319 320 /* CLMA enable options. */ 321 #define BSP_CLOCKS_CLMA0_DISABLE (0) // Disable CLMA0 operation. 322 #define BSP_CLOCKS_CLMA0_ENABLE (1) // Enable CLMA0 operation. 323 #define BSP_CLOCKS_CLMA1_DISABLE (0) // Disable CLMA1 operation. 324 #define BSP_CLOCKS_CLMA1_ENABLE (1) // Enable CLMA1 operation. 325 #define BSP_CLOCKS_CLMA2_DISABLE (0) // Disable CLMA2 operation. 326 #define BSP_CLOCKS_CLMA2_ENABLE (1) // Enable CLMA2 operation. 327 #define BSP_CLOCKS_CLMA3_DISABLE (0) // Disable CLMA3 operation. 328 #define BSP_CLOCKS_CLMA3_ENABLE (1) // Enable CLMA3 operation. 329 #define BSP_CLOCKS_CLMA4_DISABLE (0) // Disable CLMA4 operation. 330 #define BSP_CLOCKS_CLMA4_ENABLE (1) // Enable CLMA4 operation. 331 #define BSP_CLOCKS_CLMA5_DISABLE (0) // Disable CLMA5 operation. 332 #define BSP_CLOCKS_CLMA5_ENABLE (1) // Enable CLMA5 operation. 333 #define BSP_CLOCKS_CLMA6_DISABLE (0) // Disable CLMA6 operation. 334 #define BSP_CLOCKS_CLMA6_ENABLE (1) // Enable CLMA6 operation. 335 336 #if (1U == BSP_FEATURE_CGC_SCKCR_TYPE) 337 338 /* Create a mask of valid bits in SCKCR. */ 339 #define BSP_PRV_SCKCR_FSELXSPI0_MASK (7U << 0) 340 #define BSP_PRV_SCKCR_DIVSELXSPI0_MASK (1U << 6) 341 #define BSP_PRV_SCKCR_FSELXSPI1_MASK (7U << 8) 342 #define BSP_PRV_SCKCR_DIVSELXSPI1_MASK (1U << 14) 343 #define BSP_PRV_SCKCR_CKIO_MASK (7U << 16) 344 #define BSP_PRV_SCKCR_FSELCANFD_MASK (1U << 20) 345 #define BSP_PRV_SCKCR_PHYSEL_MASK (1U << 21) 346 #define BSP_PRV_SCKCR_CLMASEL_MASK (1U << 22) 347 #define BSP_PRV_SCKCR_SPI0ASYNCSEL_MASK (1U << 24) 348 #define BSP_PRV_SCKCR_SPI1ASYNCSEL_MASK (1U << 25) 349 #define BSP_PRV_SCKCR_SPI2ASYNCSEL_MASK (1U << 26) 350 #define BSP_PRV_SCKCR_SCI0ASYNCSEL_MASK (1U << 27) 351 #define BSP_PRV_SCKCR_SCI1ASYNCSEL_MASK (1U << 28) 352 #define BSP_PRV_SCKCR_SCI2ASYNCSEL_MASK (1U << 29) 353 #define BSP_PRV_SCKCR_SCI3ASYNCSEL_MASK (1U << 30) 354 #define BSP_PRV_SCKCR_SCI4ASYNCSEL_MASK (1U << 31) 355 #define BSP_PRV_SCKCR_MASK (((((((((((((((BSP_PRV_SCKCR_FSELXSPI0_MASK | \ 356 BSP_PRV_SCKCR_DIVSELXSPI0_MASK) | \ 357 BSP_PRV_SCKCR_FSELXSPI1_MASK) | \ 358 BSP_PRV_SCKCR_DIVSELXSPI1_MASK) | \ 359 BSP_PRV_SCKCR_CKIO_MASK) | \ 360 BSP_PRV_SCKCR_FSELCANFD_MASK) | \ 361 BSP_PRV_SCKCR_PHYSEL_MASK) | \ 362 BSP_PRV_SCKCR_CLMASEL_MASK) | \ 363 BSP_PRV_SCKCR_SPI0ASYNCSEL_MASK) | \ 364 BSP_PRV_SCKCR_SPI1ASYNCSEL_MASK) | \ 365 BSP_PRV_SCKCR_SPI2ASYNCSEL_MASK) | \ 366 BSP_PRV_SCKCR_SCI0ASYNCSEL_MASK) | \ 367 BSP_PRV_SCKCR_SCI1ASYNCSEL_MASK) | \ 368 BSP_PRV_SCKCR_SCI2ASYNCSEL_MASK) | \ 369 BSP_PRV_SCKCR_SCI3ASYNCSEL_MASK) | \ 370 BSP_PRV_SCKCR_SCI4ASYNCSEL_MASK) 371 372 #define BSP_PRV_SCKCR_DIVSELXSPI_MASK (BSP_PRV_SCKCR_DIVSELXSPI0_MASK | \ 373 BSP_PRV_SCKCR_DIVSELXSPI1_MASK) 374 375 /* Create a mask of valid bits in SCKCR2. */ 376 #define BSP_PRV_SCKCR2_FSELCPU0_MASK (3U << 0) 377 #define BSP_PRV_SCKCR2_RESERVED_BIT4_MASK (1U << 4) 378 #define BSP_PRV_SCKCR2_DIVSELSUB_MASK (1U << 5) 379 #define BSP_PRV_SCKCR2_SPI3ASYNCSEL_MASK (1U << 24) 380 #define BSP_PRV_SCKCR2_SCI5ASYNCSEL_MASK (1U << 25) 381 #define BSP_PRV_SCKCR2_MASK ((((BSP_PRV_SCKCR2_FSELCPU0_MASK | \ 382 BSP_PRV_SCKCR2_RESERVED_BIT4_MASK) | \ 383 BSP_PRV_SCKCR2_DIVSELSUB_MASK) | \ 384 BSP_PRV_SCKCR2_SPI3ASYNCSEL_MASK) | \ 385 BSP_PRV_SCKCR2_SCI5ASYNCSEL_MASK) 386 387 #elif (2U == BSP_FEATURE_CGC_SCKCR_TYPE) 388 389 /* Create a mask of valid bits in SCKCR. */ 390 #define BSP_PRV_SCKCR_FSELXSPI0_MASK (7U << 0) 391 #define BSP_PRV_SCKCR_DIVSELXSPI0_MASK (1U << 6) 392 #define BSP_PRV_SCKCR_FSELXSPI1_MASK (7U << 8) 393 #define BSP_PRV_SCKCR_DIVSELXSPI1_MASK (1U << 14) 394 #define BSP_PRV_SCKCR_CKIO_MASK (7U << 16) 395 #define BSP_PRV_SCKCR_FSELCANFD_MASK (1U << 20) 396 #define BSP_PRV_SCKCR_PHYSEL_MASK (1U << 21) 397 #define BSP_PRV_SCKCR_CLMASEL_MASK (1U << 22) 398 399 #define BSP_PRV_SCKCR_MASK (((((((BSP_PRV_SCKCR_FSELXSPI0_MASK | \ 400 BSP_PRV_SCKCR_DIVSELXSPI0_MASK) | \ 401 BSP_PRV_SCKCR_FSELXSPI1_MASK) | \ 402 BSP_PRV_SCKCR_DIVSELXSPI1_MASK) | \ 403 BSP_PRV_SCKCR_CKIO_MASK) | \ 404 BSP_PRV_SCKCR_FSELCANFD_MASK) | \ 405 BSP_PRV_SCKCR_PHYSEL_MASK) | \ 406 BSP_PRV_SCKCR_CLMASEL_MASK) 407 408 #define BSP_PRV_SCKCR_DIVSELXSPI_MASK (BSP_PRV_SCKCR_DIVSELXSPI0_MASK | \ 409 BSP_PRV_SCKCR_DIVSELXSPI1_MASK) 410 411 /* Create a mask of valid bits in SCKCR2. */ 412 #define BSP_PRV_SCKCR2_CR52CPU0_MASK (3U << 0) 413 #define BSP_PRV_SCKCR2_CR52CPU1_MASK (3U << 2) 414 #define BSP_PRV_SCKCR2_CA55CORE0_MASK (1U << 8) 415 #define BSP_PRV_SCKCR2_CA55CORE1_MASK (1U << 9) 416 #define BSP_PRV_SCKCR2_CA55CORE2_MASK (1U << 10) 417 #define BSP_PRV_SCKCR2_CA55CORE3_MASK (1U << 11) 418 #define BSP_PRV_SCKCR2_CA55SCLK_MASK (1U << 12) 419 #define BSP_PRV_SCKCR2_SPI3ASYNCSEL_MASK (3U << 16) 420 #define BSP_PRV_SCKCR2_SCI5ASYNCSEL_MASK (3U << 18) 421 #define BSP_PRV_SCKCR2_MASK ((((((((BSP_PRV_SCKCR2_CR52CPU0_MASK | \ 422 BSP_PRV_SCKCR2_CR52CPU1_MASK) | \ 423 BSP_PRV_SCKCR2_CA55CORE0_MASK) | \ 424 BSP_PRV_SCKCR2_CA55CORE1_MASK) | \ 425 BSP_PRV_SCKCR2_CA55CORE2_MASK) | \ 426 BSP_PRV_SCKCR2_CA55CORE3_MASK) | \ 427 BSP_PRV_SCKCR2_CA55SCLK_MASK) | \ 428 BSP_PRV_SCKCR2_SPI3ASYNCSEL_MASK) | \ 429 BSP_PRV_SCKCR2_SCI5ASYNCSEL_MASK) 430 431 /* Create a mask of valid bits in SCKCR3. */ 432 #define BSP_PRV_SCKCR3_SPI0ASYNCSEL_MASK (3U << 0) 433 #define BSP_PRV_SCKCR3_SPI1ASYNCSEL_MASK (3U << 2) 434 #define BSP_PRV_SCKCR3_SPI2ASYNCSEL_MASK (3U << 4) 435 #define BSP_PRV_SCKCR3_SCI0ASYNCSEL_MASK (3U << 6) 436 #define BSP_PRV_SCKCR3_SCI1ASYNCSEL_MASK (3U << 8) 437 #define BSP_PRV_SCKCR3_SCI2ASYNCSEL_MASK (3U << 10) 438 #define BSP_PRV_SCKCR3_SCI3ASYNCSEL_MASK (3U << 12) 439 #define BSP_PRV_SCKCR3_SCI4ASYNCSEL_MASK (3U << 14) 440 #define BSP_PRV_SCKCR3_LCDCDIVSEL_MASK (15U << 20) 441 #define BSP_PRV_SCKCR3_MASK (((((((((BSP_PRV_SCKCR3_SPI0ASYNCSEL_MASK) | \ 442 BSP_PRV_SCKCR3_SPI1ASYNCSEL_MASK) | \ 443 BSP_PRV_SCKCR3_SPI2ASYNCSEL_MASK) | \ 444 BSP_PRV_SCKCR3_SCI0ASYNCSEL_MASK) | \ 445 BSP_PRV_SCKCR3_SCI1ASYNCSEL_MASK) | \ 446 BSP_PRV_SCKCR3_SCI2ASYNCSEL_MASK) | \ 447 BSP_PRV_SCKCR3_SCI3ASYNCSEL_MASK) | \ 448 BSP_PRV_SCKCR3_SCI4ASYNCSEL_MASK) | \ 449 BSP_PRV_SCKCR3_LCDCDIVSEL_MASK) 450 451 /* Create a mask of valid bits in SCKCR4. */ 452 #define BSP_PRV_SCKCR4_SCIE0ASYNCSEL_MASK (3U << 0) 453 #define BSP_PRV_SCKCR4_SCIE1ASYNCSEL_MASK (3U << 2) 454 #define BSP_PRV_SCKCR4_SCIE2ASYNCSEL_MASK (3U << 4) 455 #define BSP_PRV_SCKCR4_SCIE3ASYNCSEL_MASK (3U << 6) 456 #define BSP_PRV_SCKCR4_SCIE4ASYNCSEL_MASK (3U << 8) 457 #define BSP_PRV_SCKCR4_SCIE5ASYNCSEL_MASK (3U << 10) 458 #define BSP_PRV_SCKCR4_SCIE6ASYNCSEL_MASK (3U << 12) 459 #define BSP_PRV_SCKCR4_SCIE7ASYNCSEL_MASK (3U << 14) 460 #define BSP_PRV_SCKCR4_SCIE8ASYNCSEL_MASK (3U << 16) 461 #define BSP_PRV_SCKCR4_SCIE9ASYNCSEL_MASK (3U << 18) 462 #define BSP_PRV_SCKCR4_SCIE10ASYNCSEL_MASK (3U << 20) 463 #define BSP_PRV_SCKCR4_SCIE11ASYNCSEL_MASK (3U << 22) 464 #define BSP_PRV_SCKCR4_ENCOUTCLK_MASK (1U << 24) 465 #define BSP_PRV_SCKCR4_MASK (((((((((((((BSP_PRV_SCKCR4_SCIE0ASYNCSEL_MASK) | \ 466 BSP_PRV_SCKCR4_SCIE1ASYNCSEL_MASK) | \ 467 BSP_PRV_SCKCR4_SCIE2ASYNCSEL_MASK) | \ 468 BSP_PRV_SCKCR4_SCIE3ASYNCSEL_MASK) | \ 469 BSP_PRV_SCKCR4_SCIE4ASYNCSEL_MASK) | \ 470 BSP_PRV_SCKCR4_SCIE5ASYNCSEL_MASK) | \ 471 BSP_PRV_SCKCR4_SCIE6ASYNCSEL_MASK) | \ 472 BSP_PRV_SCKCR4_SCIE7ASYNCSEL_MASK) | \ 473 BSP_PRV_SCKCR4_SCIE8ASYNCSEL_MASK) | \ 474 BSP_PRV_SCKCR4_SCIE9ASYNCSEL_MASK) | \ 475 BSP_PRV_SCKCR4_SCIE10ASYNCSEL_MASK) | \ 476 BSP_PRV_SCKCR4_SCIE11ASYNCSEL_MASK) | \ 477 BSP_PRV_SCKCR4_ENCOUTCLK_MASK) 478 479 #endif 480 481 /*********************************************************************************************************************** 482 * Typedef definitions 483 **********************************************************************************************************************/ 484 485 /*********************************************************************************************************************** 486 * Exported global variables 487 **********************************************************************************************************************/ 488 489 /*********************************************************************************************************************** 490 * Exported global functions (to be accessed by other files) 491 **********************************************************************************************************************/ 492 493 /* Public functions defined in bsp.h */ 494 void bsp_clock_init(void); // Used internally by BSP 495 496 /* Used internally by CGC */ 497 498 void bsp_prv_clock_set(uint32_t sckcr, uint32_t sckcr2, uint32_t sckcr3, uint32_t sckcr4); 499 500 /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 501 FSP_FOOTER 502 503 #endif 504
