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Searched defs:BSP_CFG_PLL_SOURCE (Results 1 – 17 of 17) sorted by relevance

/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4w1/
Dbsp_clock_cfg.h30 #define BSP_CFG_PLL_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll))) macro
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m1/
Dbsp_clock_cfg.h30 #define BSP_CFG_PLL_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll))) macro
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m1/
Dbsp_clock_cfg.h28 #define BSP_CFG_PLL_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll))) macro
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m2/
Dbsp_clock_cfg.h28 #define BSP_CFG_PLL_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll))) macro
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m3/
Dbsp_clock_cfg.h28 #define BSP_CFG_PLL_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll))) macro
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m2/
Dbsp_clock_cfg.h28 #define BSP_CFG_PLL_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll))) macro
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m3/
Dbsp_clock_cfg.h28 #define BSP_CFG_PLL_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll))) macro
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6e1/
Dbsp_clock_cfg.h28 #define BSP_CFG_PLL_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll))) macro
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4e1/
Dbsp_clock_cfg.h28 #define BSP_CFG_PLL_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll))) macro
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6e2/
Dbsp_clock_cfg.h28 #define BSP_CFG_PLL_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll))) macro
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4e2/
Dbsp_clock_cfg.h28 #define BSP_CFG_PLL_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll))) macro
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m4/
Dbsp_clock_cfg.h28 #define BSP_CFG_PLL_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll))) macro
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4l1/
Dbsp_clock_cfg.h33 #define BSP_CFG_PLL_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll))) macro
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m5/
Dbsp_clock_cfg.h28 #define BSP_CFG_PLL_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll))) macro
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8t1/
Dbsp_clock_cfg.h31 #define BSP_CFG_PLL_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll))) macro
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8d1/
Dbsp_clock_cfg.h32 #define BSP_CFG_PLL_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll))) macro
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8m1/
Dbsp_clock_cfg.h32 #define BSP_CFG_PLL_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll))) macro