| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4w1/ |
| D | bsp_clock_cfg.h | 31 #define BSP_CFG_PLL_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll), div, 2) macro
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m1/ |
| D | bsp_clock_cfg.h | 31 #define BSP_CFG_PLL_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll), div, 2) macro
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m1/ |
| D | bsp_clock_cfg.h | 29 #define BSP_CFG_PLL_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll), div, 1) macro
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m2/ |
| D | bsp_clock_cfg.h | 29 #define BSP_CFG_PLL_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll), div, 1) macro
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m3/ |
| D | bsp_clock_cfg.h | 29 #define BSP_CFG_PLL_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll), div, 2) macro
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m2/ |
| D | bsp_clock_cfg.h | 29 #define BSP_CFG_PLL_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll), div, 3) macro
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m3/ |
| D | bsp_clock_cfg.h | 29 #define BSP_CFG_PLL_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll), div, 3) macro
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6e1/ |
| D | bsp_clock_cfg.h | 29 #define BSP_CFG_PLL_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll), div, 1) macro
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4e1/ |
| D | bsp_clock_cfg.h | 29 #define BSP_CFG_PLL_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll), div, 1) macro
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6e2/ |
| D | bsp_clock_cfg.h | 29 #define BSP_CFG_PLL_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll), div, 1) macro
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4e2/ |
| D | bsp_clock_cfg.h | 29 #define BSP_CFG_PLL_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll), div, 1) macro
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m4/ |
| D | bsp_clock_cfg.h | 29 #define BSP_CFG_PLL_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll), div, 1) macro
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4l1/ |
| D | bsp_clock_cfg.h | 34 #define BSP_CFG_PLL_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll), div, 1) macro
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m5/ |
| D | bsp_clock_cfg.h | 29 #define BSP_CFG_PLL_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll), div, 1) macro
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8t1/ |
| D | bsp_clock_cfg.h | 32 #define BSP_CFG_PLL_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll), div, 1) macro
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8d1/ |
| D | bsp_clock_cfg.h | 33 #define BSP_CFG_PLL_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll), div, 1) macro
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8m1/ |
| D | bsp_clock_cfg.h | 33 #define BSP_CFG_PLL_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll), div, 1) macro
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