1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef BSP_MCU_FAMILY_CFG_H_ 8 #define BSP_MCU_FAMILY_CFG_H_ 9 #include "bsp_mcu_device_pn_cfg.h" 10 #include "bsp_mcu_device_cfg.h" 11 #include "bsp_mcu_info.h" 12 #include "bsp_clock_cfg.h" 13 #define BSP_MCU_GROUP_RA2L1 (1) 14 #define BSP_LOCO_HZ (DT_PROP_OR(DT_NODELABEL(loco), clock_frequency, 0)) 15 #define BSP_MOCO_HZ (DT_PROP_OR(DT_NODELABEL(moco), clock_frequency, 0)) 16 #define BSP_SUB_CLOCK_HZ (DT_PROP_OR(DT_NODELABEL(subclk), clock_frequency, 0)) 17 #if BSP_CFG_HOCO_FREQUENCY == 0 18 #define BSP_HOCO_HZ (24000000) 19 #elif BSP_CFG_HOCO_FREQUENCY == 2 20 #define BSP_HOCO_HZ (32000000) 21 #elif BSP_CFG_HOCO_FREQUENCY == 4 22 #define BSP_HOCO_HZ (48000000) 23 #elif BSP_CFG_HOCO_FREQUENCY == 5 24 #define BSP_HOCO_HZ (64000000) 25 #else 26 #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" 27 #endif 28 29 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) 30 #define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) 31 #define BSP_CFG_INLINE_IRQ_FUNCTIONS (0) 32 33 #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) 34 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) 35 #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) 36 #define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26) 37 #define OFS_SEQ5 (1 << 28) | (1 << 30) 38 #define BSP_CFG_USE_LOW_VOLTAGE_MODE (0) 39 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) 40 #define BSP_CFG_ROM_REG_OFS1_ICSATS (1 << 31) 41 #define BSP_CFG_ROM_REG_OFS1 (0x7FFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8) | \ 42 (BSP_CFG_ROM_REG_OFS1_ICSATS)) 43 #define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) 44 #define BSP_CFG_ROM_REG_MPU_PC0_START (0x000FFFFC) 45 #define BSP_CFG_ROM_REG_MPU_PC0_END (0x000FFFFF) 46 #define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) 47 #define BSP_CFG_ROM_REG_MPU_PC1_START (0x000FFFFC) 48 #define BSP_CFG_ROM_REG_MPU_PC1_END (0x000FFFFF) 49 #define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) 50 #define BSP_CFG_ROM_REG_MPU_REGION0_START (0x000FFFFC) 51 #define BSP_CFG_ROM_REG_MPU_REGION0_END (0x000FFFFF) 52 #define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) 53 #define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) 54 #define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) 55 #define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) 56 #define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) 57 #define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) 58 #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) 59 #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) 60 #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) 61 #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT 62 #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) 63 #endif 64 /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. 65 */ 66 #define BSP_PRV_IELS_ENUM(vector) CONCAT(ICU_, vector) 67 68 #define BSP_CFG_DCDC_ENABLE (0) 69 #define BSP_CFG_DCDC_VOLTAGE_RANGE (BSP_POWER_MODE_DCDC_2V7_TO_3V6) 70 71 /* 72 * ID Code 73 * Note: To permanently lock and disable the debug interface define the 74 * BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. WARNING: This 75 * will disable debug access to the part and cannot be reversed by a 76 * debug probe. 77 */ 78 #if defined(BSP_ID_CODE_LOCKED) 79 #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) 80 #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) 81 #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) 82 #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) 83 #else 84 /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ 85 #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) 86 #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) 87 #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) 88 #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) 89 #endif 90 #endif /* BSP_MCU_FAMILY_CFG_H_ */ 91
