1 /* 2 * Copyright 2023 Cirrus Logic, Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_CHARGER_BQ24190_H_ 8 #define ZEPHYR_DRIVERS_CHARGER_BQ24190_H_ 9 10 /* Input Source Control */ 11 #define BQ24190_REG_ISC 0x00 12 #define BQ24190_REG_ISC_EN_HIZ_MASK BIT(7) 13 #define BQ24190_REG_ISC_EN_HIZ_SHIFT 7 14 #define BQ24190_REG_ISC_VINDPM_MASK GENMASK(6, 3) 15 #define BQ24190_REG_ISC_VINDPM_SHIFT 3 16 #define BQ24190_REG_ISC_IINLIM_MASK GENMASK(2, 0) 17 18 /* Power-On Configuration */ 19 #define BQ24190_REG_POC 0x01 20 #define BQ24190_REG_POC_RESET_MASK BIT(7) 21 #define BQ24190_REG_POC_RESET_SHIFT 7 22 #define BQ24190_RESET_MAX_TRIES 100 23 #define BQ24190_REG_POC_WDT_RESET_MASK BIT(6) 24 #define BQ24190_REG_POC_WDT_RESET_SHIFT 6 25 #define BQ24190_REG_POC_CHG_CONFIG_MASK GENMASK(5, 4) 26 #define BQ24190_REG_POC_CHG_CONFIG_SHIFT 4 27 #define BQ24190_REG_POC_CHG_CONFIG_DISABLE 0x0 28 #define BQ24190_REG_POC_CHG_CONFIG_CHARGE 0x1 29 #define BQ24190_REG_POC_CHG_CONFIG_OTG 0x2 30 #define BQ24190_REG_POC_CHG_CONFIG_OTG_ALT 0x3 31 #define BQ24190_REG_POC_SYS_MIN_MASK GENMASK(3, 1) 32 #define BQ24190_REG_POC_SYS_MIN_SHIFT 1 33 #define BQ24190_REG_POC_SYS_MIN_MIN_UV 3000000 34 #define BQ24190_REG_POC_SYS_MIN_MAX_UV 3700000 35 #define BQ24190_REG_POC_BOOST_LIM_MASK BIT(0) 36 #define BQ24190_REG_POC_BOOST_LIM_SHIFT 0 37 38 /* Charge Current Control */ 39 #define BQ24190_REG_CCC 0x02 40 #define BQ24190_REG_CCC_ICHG_MASK GENMASK(7, 2) 41 #define BQ24190_REG_CCC_ICHG_SHIFT 2 42 #define BQ24190_REG_CCC_ICHG_STEP_UA 64000 43 #define BQ24190_REG_CCC_ICHG_OFFSET_UA 512000 44 #define BQ24190_REG_CCC_ICHG_MIN_UA BQ24190_REG_CCC_ICHG_OFFSET_UA 45 #define BQ24190_REG_CCC_ICHG_MAX_UA 4544000 46 #define BQ24190_REG_CCC_FORCE_20PCT_MASK BIT(0) 47 #define BQ24190_REG_CCC_FORCE_20PCT_SHIFT 0 48 49 /* Pre-charge/Termination Current Cntl */ 50 #define BQ24190_REG_PCTCC 0x03 51 #define BQ24190_REG_PCTCC_IPRECHG_MASK GENMASK(7, 4) 52 #define BQ24190_REG_PCTCC_IPRECHG_SHIFT 4 53 #define BQ24190_REG_PCTCC_IPRECHG_STEP_UA 128000 54 #define BQ24190_REG_PCTCC_IPRECHG_OFFSET_UA 128000 55 #define BQ24190_REG_PCTCC_IPRECHG_MIN_UA BQ24190_REG_PCTCC_IPRECHG_OFFSET_UA 56 #define BQ24190_REG_PCTCC_IPRECHG_MAX_UA 2048000 57 #define BQ24190_REG_PCTCC_ITERM_MASK GENMASK(3, 0) 58 #define BQ24190_REG_PCTCC_ITERM_SHIFT 0 59 #define BQ24190_REG_PCTCC_ITERM_STEP_UA 128000 60 #define BQ24190_REG_PCTCC_ITERM_OFFSET_UA 128000 61 #define BQ24190_REG_PCTCC_ITERM_MIN_UA BQ24190_REG_PCTCC_ITERM_OFFSET_UA 62 #define BQ24190_REG_PCTCC_ITERM_MAX_UA 2048000 63 64 /* Charge Voltage Control */ 65 #define BQ24190_REG_CVC 0x04 66 #define BQ24190_REG_CVC_VREG_MASK GENMASK(7, 2) 67 #define BQ24190_REG_CVC_VREG_SHIFT 2 68 #define BQ24190_REG_CVC_VREG_STEP_UV 16000 69 #define BQ24190_REG_CVC_VREG_OFFSET_UV 3504000 70 #define BQ24190_REG_CVC_VREG_MIN_UV BQ24190_REG_CVC_VREG_OFFSET_UV 71 #define BQ24190_REG_CVC_VREG_MAX_UV 4400000 72 #define BQ24190_REG_CVC_BATLOWV_MASK BIT(1) 73 #define BQ24190_REG_CVC_BATLOWV_SHIFT 1 74 #define BQ24190_REG_CVC_VRECHG_MASK BIT(0) 75 #define BQ24190_REG_CVC_VRECHG_SHIFT 0 76 77 /* Charge Term/Timer Control */ 78 #define BQ24190_REG_CTTC 0x05 79 #define BQ24190_REG_CTTC_EN_TERM_MASK BIT(7) 80 #define BQ24190_REG_CTTC_EN_TERM_SHIFT 7 81 #define BQ24190_REG_CTTC_TERM_STAT_MASK BIT(6) 82 #define BQ24190_REG_CTTC_TERM_STAT_SHIFT 6 83 #define BQ24190_REG_CTTC_WATCHDOG_MASK GENMASK(5, 4) 84 #define BQ24190_REG_CTTC_WATCHDOG_SHIFT 4 85 #define BQ24190_REG_CTTC_EN_TIMER_MASK BIT(3) 86 #define BQ24190_REG_CTTC_EN_TIMER_SHIFT 3 87 #define BQ24190_REG_CTTC_CHG_TIMER_MASK GENMASK(2, 1) 88 #define BQ24190_REG_CTTC_CHG_TIMER_SHIFT 1 89 #define BQ24190_REG_CTTC_JEITA_ISET_MASK BIT(0) 90 #define BQ24190_REG_CTTC_JEITA_ISET_SHIFT 0 91 92 /* IR Comp/Thermal Regulation Control */ 93 #define BQ24190_REG_ICTRC 0x06 94 #define BQ24190_REG_ICTRC_BAT_COMP_MASK GENMASK(7, 5) 95 #define BQ24190_REG_ICTRC_BAT_COMP_SHIFT 5 96 #define BQ24190_REG_ICTRC_VCLAMP_MASK GENMASK(4, 2) 97 #define BQ24190_REG_ICTRC_VCLAMP_SHIFT 2 98 #define BQ24190_REG_ICTRC_TREG_MASK GENMASK(1, 0) 99 #define BQ24190_REG_ICTRC_TREG_SHIFT 0 100 101 /* Misc. Operation Control */ 102 #define BQ24190_REG_MOC 0x07 103 #define BQ24190_REG_MOC_DPDM_EN_MASK BIT(7) 104 #define BQ24190_REG_MOC_DPDM_EN_SHIFT 7 105 #define BQ24190_REG_MOC_TMR2X_EN_MASK BIT(6) 106 #define BQ24190_REG_MOC_TMR2X_EN_SHIFT 6 107 #define BQ24190_REG_MOC_BATFET_DISABLE_MASK BIT(5) 108 #define BQ24190_REG_MOC_BATFET_DISABLE_SHIFT 5 109 #define BQ24190_REG_MOC_JEITA_VSET_MASK BIT(4) 110 #define BQ24190_REG_MOC_JEITA_VSET_SHIFT 4 111 #define BQ24190_REG_MOC_INT_MASK_MASK GENMASK(1, 0) 112 #define BQ24190_REG_MOC_INT_MASK_SHIFT 0 113 114 /* System Status */ 115 #define BQ24190_REG_SS 0x08 116 #define BQ24190_REG_SS_VBUS_STAT_MASK GENMASK(7, 6) 117 #define BQ24190_REG_SS_VBUS_STAT_SHIFT 6 118 #define BQ24190_REG_SS_CHRG_STAT_MASK GENMASK(5, 4) 119 #define BQ24190_REG_SS_CHRG_STAT_SHIFT 4 120 #define BQ24190_CHRG_STAT_NOT_CHRGING 0x0 121 #define BQ24190_CHRG_STAT_PRECHRG 0x1 122 #define BQ24190_CHRG_STAT_FAST_CHRG 0x2 123 #define BQ24190_CHRG_STAT_CHRG_TERM 0x3 124 #define BQ24190_REG_SS_DPM_STAT_MASK BIT(3) 125 #define BQ24190_REG_SS_DPM_STAT_SHIFT 3 126 #define BQ24190_REG_SS_PG_STAT_MASK BIT(2) 127 #define BQ24190_REG_SS_PG_STAT_SHIFT 2 128 #define BQ24190_REG_SS_THERM_STAT_MASK BIT(1) 129 #define BQ24190_REG_SS_THERM_STAT_SHIFT 1 130 #define BQ24190_REG_SS_VSYS_STAT_MASK BIT(0) 131 #define BQ24190_REG_SS_VSYS_STAT_SHIFT 0 132 133 /* Fault */ 134 #define BQ24190_REG_F 0x09 135 #define BQ24190_REG_F_WATCHDOG_FAULT_MASK BIT(7) 136 #define BQ24190_REG_F_WATCHDOG_FAULT_SHIFT 7 137 #define BQ24190_REG_F_BOOST_FAULT_MASK BIT(6) 138 #define BQ24190_REG_F_BOOST_FAULT_SHIFT 6 139 #define BQ24190_REG_F_CHRG_FAULT_MASK GENMASK(5, 4) 140 #define BQ24190_REG_F_CHRG_FAULT_SHIFT 4 141 #define BQ24190_CHRG_FAULT_INPUT_FAULT 0x1 142 #define BQ24190_CHRG_FAULT_TSHUT 0x2 143 #define BQ24190_CHRG_SAFETY_TIMER 0x3 144 #define BQ24190_REG_F_BAT_FAULT_MASK BIT(3) 145 #define BQ24190_REG_F_BAT_FAULT_SHIFT 3 146 #define BQ24190_REG_F_NTC_FAULT_MASK GENMASK(2, 0) 147 #define BQ24190_REG_F_NTC_FAULT_SHIFT 0 148 #define BQ24190_NTC_FAULT_TS1_COLD 0x1 149 #define BQ24190_NTC_FAULT_TS1_HOT 0x2 150 #define BQ24190_NTC_FAULT_TS2_COLD 0x3 151 #define BQ24190_NTC_FAULT_TS2_HOT 0x4 152 #define BQ24190_NTC_FAULT_TS1_TS2_COLD 0x5 153 #define BQ24190_NTC_FAULT_TS1_TS2_HOT 0x6 154 155 /* Vendor/Part/Revision Status */ 156 #define BQ24190_REG_VPRS 0x0A 157 #define BQ24190_REG_VPRS_PN_MASK GENMASK(5, 3) 158 #define BQ24190_REG_VPRS_PN_SHIFT 3 159 #define BQ24190_REG_VPRS_PN_24190 0x4 160 #define BQ24190_REG_VPRS_PN_24192 0x5 /* Also 24193, 24196 */ 161 #define BQ24190_REG_VPRS_PN_24192I 0x3 162 #define BQ24190_REG_VPRS_TS_PROFILE_MASK BIT(2) 163 #define BQ24190_REG_VPRS_TS_PROFILE_SHIFT 2 164 #define BQ24190_REG_VPRS_DEV_REG_MASK GENMASK(1, 0) 165 #define BQ24190_REG_VPRS_DEV_REG_SHIFT 0 166 167 #endif 168
