1 /*
2 * Copyright 2023-2024 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stdint.h>
8 #include "fsl_common.h"
9 #include "fsl_debug_console.h"
10 #if defined(MIMXRT798S_cm33_core0_SERIES)
11 #include "fsl_cache.h"
12 #endif
13 #include "fsl_clock.h"
14 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
15 #include "fsl_lpi2c.h"
16 #endif /* SDK_I2C_BASED_COMPONENT_USED */
17 #include "clock_config.h"
18 #include "board.h"
19
20 /*******************************************************************************
21 * Definitions
22 ******************************************************************************/
23 #if defined(MIMXRT798S_cm33_core0_SERIES)
24 #define HYPERRAM_CMD_LUT_SEQ_IDX_SYNC_READ 0
25 #define HYPERRAM_CMD_LUT_SEQ_IDX_SYNC_WRITE 1
26 #define HYPERRAM_CMD_LUT_SEQ_IDX_BURST_READ 2
27 #define HYPERRAM_CMD_LUT_SEQ_IDX_BURST_WRITE 3
28 #define HYPERRAM_CMD_LUT_SEQ_IDX_REG_READ 4
29 #define HYPERRAM_CMD_LUT_SEQ_IDX_REG_WRITE 5
30 #define HYPERRAM_CMD_LUT_SEQ_IDX_RESET 6
31
32 #define CUSTOM_LUT_LENGTH 40
33 #endif
34
35 /*******************************************************************************
36 * Variables
37 ******************************************************************************/
38
39 /*******************************************************************************
40 * Prototypes
41 ******************************************************************************/
42
43 /*******************************************************************************
44 * Code
45 ******************************************************************************/
46 /* Initialize debug console. */
BOARD_InitDebugConsole(void)47 void BOARD_InitDebugConsole(void)
48 {
49 uint32_t uartClkSrcFreq;
50
51 #if (defined(MIMXRT798S_cm33_core0_SERIES) || defined(MIMXRT798S_hifi4_SERIES))
52 CLOCK_AttachClk(BOARD_DEBUG_UART_FCCLK_ATTACH);
53 CLOCK_SetClkDiv(BOARD_DEBUG_UART_FCCLK_DIV, 1U);
54
55 /* attach FC0 clock to LP_FLEXCOMM (debug console) */
56 CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
57 #else
58 CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
59 CLOCK_SetClkDiv(BOARD_DEBUG_UART_CLK_DIV, 4U);
60 #endif
61
62 uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
63
64 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
65 }
66
67 #if defined(MIMXRT798S_cm33_core0_SERIES)
AT_QUICKACCESS_SECTION_CODE(void BOARD_EnableXspiCache (CACHE64_CTRL_Type * cache))68 AT_QUICKACCESS_SECTION_CODE(void BOARD_EnableXspiCache(CACHE64_CTRL_Type *cache))
69 {
70 /* First, invalidate the entire cache. */
71 cache->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK;
72 while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U)
73 {
74 }
75 /* As a precaution clear the bits to avoid inadvertently re-running this command. */
76 cache->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK);
77 /* Now enable the cache. */
78 cache->CCR |= CACHE64_CTRL_CCR_ENCACHE_MASK;
79 }
80
AT_QUICKACCESS_SECTION_CODE(void BOARD_DisableXspiCache (CACHE64_CTRL_Type * cache))81 AT_QUICKACCESS_SECTION_CODE(void BOARD_DisableXspiCache(CACHE64_CTRL_Type *cache))
82 {
83 /* First, clean XSPI cache. */
84 cache->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_GO_MASK;
85 while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U)
86 {
87 }
88 /* As a precaution clear the bits to avoid inadvertently re-running this command. */
89 cache->CCR &= ~(CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK);
90
91 /* Now disable XSPI cache. */
92 cache->CCR &= ~CACHE64_CTRL_CCR_ENCACHE_MASK;
93 }
94
BOARD_ConfigMPU(void)95 void BOARD_ConfigMPU(void)
96 {
97 uint8_t attr;
98 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
99 extern uint32_t Image$$RW_m_ncache$$Base[];
100 /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
101 extern uint32_t Image$$RW_m_ncache_unused$$Base[];
102 extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
103 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
104 uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
105 0 :
106 ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
107 #elif defined(__MCUXPRESSO)
108 extern uint32_t __base_NCACHE_REGION;
109 extern uint32_t __top_NCACHE_REGION;
110 uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
111 uint32_t nonCacheSize = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
112 #elif defined(__ICCARM__) || defined(__GNUC__)
113 extern uint32_t __NCACHE_REGION_START[];
114 extern uint32_t __NCACHE_REGION_SIZE[];
115 uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
116 uint32_t nonCacheSize = (uint32_t)__NCACHE_REGION_SIZE;
117 #else
118 #error "Unsupported compiler"
119 #endif
120
121 XCACHE_DisableCache(XCACHE0);
122 XCACHE_DisableCache(XCACHE1);
123
124 /* Disable MPU */
125 ARM_MPU_Disable();
126
127 /* Attr0: device memory. */
128 ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE));
129 /* Attr1: non cacheable. */
130 ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE));
131 /* Attr2: non transient, write through, read allocate. */
132 attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U);
133 ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr));
134 /* Attr3: non transient, write back, read/write allocate. */
135 attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U);
136 ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr));
137
138 /* Region 0: [0x0, 0x1FFFFFFF], non-shareable, read/write, any privileged, executable. Attr 2 (write through). */
139 ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0U, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x1FFFFFFFU, 2U));
140 /* Region 2 (Peripherals): [0x40000000, 0x5FFFFFFF], non-shareable, read/write, non-privileged, executable. Attr 0
141 * (device). */
142 ARM_MPU_SetRegion(2U, ARM_MPU_RBAR(0x40000000U, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x5FFFFFFF, 0U));
143
144 if (nonCacheSize != 0)
145 {
146 /* The MPU region size should a granularity of 32 bytes. */
147 assert((nonCacheSize & 0x1FU) == 0x0U);
148
149 /* Region 1 setting : outter-shareable, read-write, non-privileged, executable. Attr 1. (non-cacheable) */
150 ARM_MPU_SetRegion(1U, ARM_MPU_RBAR(nonCacheStart, ARM_MPU_SH_OUTER, 0U, 1U, 0U),
151 ARM_MPU_RLAR(nonCacheStart + nonCacheSize - 1, 1U));
152 }
153
154 /*
155 * Enable MPU and HFNMIENA feature
156 * HFNMIENA ensures the core uses MPU configuration when in hard fault, NMI, and FAULTMASK handlers,
157 * otherwise all memory regions are accessed without MPU protection.
158 */
159 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
160
161 /* Enable code & system cache */
162 XCACHE_EnableCache(XCACHE0);
163 XCACHE_EnableCache(XCACHE1);
164
165 /* flush pipeline */
166 __DSB();
167 __ISB();
168 }
169
BOARD_DeinitXspi(XSPI_Type * base,CACHE64_CTRL_Type * cache)170 void BOARD_DeinitXspi(XSPI_Type *base, CACHE64_CTRL_Type *cache)
171 {
172 if (base == XSPI0)
173 {
174 /* Enable clock again. */
175 CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_CLR_XSPI0_MASK;
176 }
177 else if (base == XSPI1)
178 {
179 /* Enable clock again. */
180 CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_CLR_XSPI1_MASK;
181 }
182 else
183 {
184 }
185
186 base->MCR &= ~XSPI_MCR_MDIS_MASK;
187 if ((cache->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) != 0x00U)
188 {
189 BOARD_DisableXspiCache(cache);
190 }
191 /* Wait until XSPI is not busy */
192 while ((base->SR & XSPI_SR_BUSY_MASK) != 0U)
193 {
194 }
195 /* Disable module. */
196 base->MCR |= XSPI_MCR_MDIS_MASK;
197 }
198
BOARD_InitXspi(XSPI_Type * base,CACHE64_CTRL_Type * cache)199 void BOARD_InitXspi(XSPI_Type *base, CACHE64_CTRL_Type *cache)
200 {
201 /* Enable XSPI module */
202 base->MCR |= XSPI_MCR_MDIS_MASK;
203
204 base->MCR |= XSPI_MCR_SWRSTSD_MASK | XSPI_MCR_SWRSTHD_MASK;
205 for (uint32_t i = 0U; i < 6U; i++)
206 {
207 __NOP();
208 }
209 base->MCR &= ~(XSPI_MCR_SWRSTSD_MASK | XSPI_MCR_SWRSTHD_MASK);
210 base->MCR |= XSPI_MCR_IPS_TG_RST_MASK | XSPI_MCR_MDIS_MASK;
211 base->MCR &= ~XSPI_MCR_ISD3FA_MASK;
212 base->MCR &= ~XSPI_MCR_MDIS_MASK;
213 base->MCR |= XSPI_MCR_MDIS_MASK;
214 base->MCR |= XSPI_MCR_ISD3FA_MASK;
215 base->MCR &= ~XSPI_MCR_MDIS_MASK;
216
217 base->MCR |= XSPI_MCR_MDIS_MASK;
218 base->SMPR = (((base->SMPR) & (~XSPI_SMPR_DLLFSMPFA_MASK)) |
219 XSPI_SMPR_DLLFSMPFA(FSL_FEATURE_XSPI_DLL_REF_VALUE_DDR_DELAY_TAP_NUM));
220 base->MCR &= ~XSPI_MCR_MDIS_MASK;
221
222 base->DLLCR[0] &= ~(XSPI_DLLCR_SLV_DLL_BYPASS_MASK | XSPI_DLLCR_DLL_CDL8_MASK | XSPI_DLLCR_SLV_DLY_OFFSET_MASK |
223 XSPI_DLLCR_SLV_FINE_OFFSET_MASK | XSPI_DLLCR_DLLRES_MASK | XSPI_DLLCR_DLL_REFCNTR_MASK |
224 XSPI_DLLCR_FREQEN_MASK);
225 base->DLLCR[0] &= ~(XSPI_DLLCR_SLV_EN_MASK | XSPI_DLLCR_SLAVE_AUTO_UPDT_MASK | XSPI_DLLCR_DLLEN_MASK);
226 /* Enable subordinate as auto update mode. */
227 base->DLLCR[0] |= XSPI_DLLCR_SLV_EN_MASK | XSPI_DLLCR_SLAVE_AUTO_UPDT_MASK;
228 /* program DLL to desired delay. */
229 base->DLLCR[0] |= XSPI_DLLCR_DLLRES(FSL_FEATURE_XSPI_DLL_REF_VALUE_AUTOUPDATE_X16_DISABLE_RES) |
230 XSPI_DLLCR_DLL_REFCNTR(FSL_FEATURE_XSPI_DLL_REF_VALUE_AUTOUPDATE_X16_DISABLED_REF_COUNTER) |
231 XSPI_DLLCR_SLV_FINE_OFFSET(0) | XSPI_DLLCR_SLV_DLY_OFFSET(0) | XSPI_DLLCR_FREQEN(1U);
232 /* Load above settings into delay chain. */
233 base->DLLCR[0] |= XSPI_DLLCR_SLV_UPD_MASK;
234 base->DLLCR[0] |= XSPI_DLLCR_DLLEN_MASK;
235 base->DLLCR[0] &= ~XSPI_DLLCR_SLV_UPD_MASK;
236
237 while ((base->DLLSR & XSPI_DLLSR_SLVA_LOCK_MASK) == 0UL)
238 {
239 }
240
241 if ((cache->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) == 0x00U)
242 {
243 BOARD_EnableXspiCache(cache);
244 /* flush pipeline */
245 __DSB();
246 __ISB();
247 }
248 }
249
250 /* BOARD_SetXspiClock run in RAM used to configure XSPI clock source and divider when XIP. */
BOARD_SetXspiClock(XSPI_Type * base,uint32_t src,uint32_t divider)251 void BOARD_SetXspiClock(XSPI_Type *base, uint32_t src, uint32_t divider)
252 {
253 if (base == XSPI0)
254 {
255 if ((CLKCTL0->XSPI0FCLKSEL != CLKCTL0_XSPI0FCLKSEL_SEL(src)) ||
256 ((CLKCTL0->XSPI0FCLKDIV & CLKCTL0_XSPI0FCLKDIV_DIV_MASK) != (divider - 1)))
257 {
258 /* Always deinit XSPI and init XSPI for the flash to make sure the flash works correctly after the
259 XSPI root clock changed as the default XSPI configuration may does not work for the new root clock
260 frequency. */
261 BOARD_DeinitXspi(base, CACHE64_CTRL0);
262
263 /* Disable clock before changing clock source */
264 CLKCTL0->PSCCTL1_CLR = CLKCTL0_PSCCTL1_CLR_XSPI0_MASK;
265 /* Update XSPI clock. */
266 CLKCTL0->XSPI0FCLKSEL = CLKCTL0_XSPI0FCLKSEL_SEL(src) | CLKCTL0_XSPI0FCLKSEL_SEL_EN_MASK;
267 CLKCTL0->XSPI0FCLKDIV = CLKCTL0_XSPI0FCLKDIV_DIV(divider - 1);
268 while ((CLKCTL0->XSPI0FCLKDIV) & CLKCTL0_XSPI0FCLKDIV_REQFLAG_MASK)
269 {
270 }
271 /* Enable XSPI clock again */
272 CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_SET_XSPI0_MASK;
273
274 BOARD_InitXspi(base, CACHE64_CTRL0);
275 }
276 }
277 else if (base == XSPI1)
278 {
279 if ((CLKCTL0->XSPI1FCLKSEL != CLKCTL0_XSPI1FCLKSEL_SEL(src)) ||
280 ((CLKCTL0->XSPI1FCLKDIV & CLKCTL0_XSPI1FCLKDIV_DIV_MASK) != (divider - 1)))
281 {
282 /* Always deinit XSPI and init XSPI for the flash to make sure the flash works correctly after the
283 XSPI root clock changed as the default XSPI configuration may does not work for the new root clock
284 frequency. */
285 BOARD_DeinitXspi(base, CACHE64_CTRL1);
286
287 /* Disable clock before changing clock source */
288 CLKCTL0->PSCCTL1_CLR = CLKCTL0_PSCCTL1_CLR_XSPI1_MASK;
289 /* Update XSPI clock. */
290 CLKCTL0->XSPI1FCLKSEL = CLKCTL0_XSPI1FCLKSEL_SEL(src) | CLKCTL0_XSPI1FCLKSEL_SEL_EN_MASK;
291 CLKCTL0->XSPI1FCLKDIV = CLKCTL0_XSPI1FCLKDIV_DIV(divider - 1);
292 while ((CLKCTL0->XSPI1FCLKDIV) & CLKCTL0_XSPI1FCLKDIV_REQFLAG_MASK)
293 {
294 }
295 /* Enable XSPI clock again */
296 CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_SET_XSPI1_MASK;
297
298 BOARD_InitXspi(base, CACHE64_CTRL1);
299 }
300 }
301 else
302 {
303 return;
304 }
305 }
306
BOARD_XspiClockSafeConfig(void)307 void BOARD_XspiClockSafeConfig(void)
308 {
309 BOARD_SetXspiClock(XSPI0, 0U, 1U);
310 BOARD_SetXspiClock(XSPI1, 0U, 1U);
311 }
312
xspi_hyper_ram_get_mcr(XSPI_Type * base,uint32_t regAddr,uint8_t * mrVal)313 static void xspi_hyper_ram_get_mcr(XSPI_Type *base, uint32_t regAddr, uint8_t *mrVal)
314 {
315 xspi_transfer_t flashXfer = {0U};
316
317 /* Read data */
318 if (base == XSPI1)
319 {
320 flashXfer.deviceAddress = XSPI1_AMBA_BASE + regAddr;
321 }
322 else if (base == XSPI2)
323 {
324 flashXfer.deviceAddress = XSPI2_AMBA_BASE + regAddr;
325 }
326 flashXfer.cmdType = kXSPI_Read;
327 flashXfer.seqIndex = HYPERRAM_CMD_LUT_SEQ_IDX_REG_READ;
328 flashXfer.targetGroup = kXSPI_TargetGroup0;
329 flashXfer.data = (uint32_t *)mrVal;
330 flashXfer.dataSize = 4;
331 flashXfer.lockArbitration = false;
332
333 (void)XSPI_TransferBlocking(base, &flashXfer);
334 }
335
xspi_hyper_ram_write_mcr(XSPI_Type * base,uint32_t regAddr,uint8_t * mrVal)336 static void xspi_hyper_ram_write_mcr(XSPI_Type *base, uint32_t regAddr, uint8_t *mrVal)
337 {
338 xspi_transfer_t flashXfer = {0U};
339
340 /* Write data */
341 if (base == XSPI1)
342 {
343 flashXfer.deviceAddress = XSPI1_AMBA_BASE + regAddr;
344 }
345 else if (base == XSPI2)
346 {
347 flashXfer.deviceAddress = XSPI2_AMBA_BASE + regAddr;
348 }
349 flashXfer.cmdType = kXSPI_Write;
350 flashXfer.seqIndex = HYPERRAM_CMD_LUT_SEQ_IDX_REG_WRITE;
351 flashXfer.targetGroup = kXSPI_TargetGroup0;
352 flashXfer.data = (uint32_t *)mrVal;
353 flashXfer.dataSize = 4;
354 flashXfer.lockArbitration = false;
355
356 (void)XSPI_TransferBlocking(base, &flashXfer);
357 }
358
BOARD_Init16bitsPsRam(XSPI_Type * base)359 void BOARD_Init16bitsPsRam(XSPI_Type *base)
360 {
361 xspi_config_t config;
362 xspi_ahb_access_config_t psRamAhbAccessConfig;
363 xspi_ip_access_config_t psRamIpAccessConfig;
364
365 config.ptrAhbAccessConfig = &psRamAhbAccessConfig;
366 config.ptrIpAccessConfig = &psRamIpAccessConfig;
367
368 /* clang-format off */
369 const uint32_t customLUT[CUSTOM_LUT_LENGTH] = {
370 #if (defined(BOARD_PSRAM_ENABLE_VARIABLE_LATENCY) && BOARD_PSRAM_ENABLE_VARIABLE_LATENCY)
371 [5 * HYPERRAM_CMD_LUT_SEQ_IDX_BURST_READ] = XSPI_LUT_SEQ(kXSPI_Command_DDR, kXSPI_8PAD, 0xA0,
372 kXSPI_Command_RADDR_DDR, kXSPI_8PAD, 0x18),
373 [5 * HYPERRAM_CMD_LUT_SEQ_IDX_BURST_READ + 1] = XSPI_LUT_SEQ(kXSPI_Command_CADDR_DDR, kXSPI_8PAD, 0x10,
374 kXSPI_Command_DUMMY_SDR, kXSPI_8PAD, 6), /* Dummy cycle: 2 * 6 + 2 */
375 [5 * HYPERRAM_CMD_LUT_SEQ_IDX_BURST_READ + 2] = XSPI_LUT_SEQ(kXSPI_Command_READ_DDR, kXSPI_8PAD, 0x04,
376 kXSPI_Command_STOP, kXSPI_1PAD, 0x0),
377
378 /* Memory Write */
379 [5 * HYPERRAM_CMD_LUT_SEQ_IDX_BURST_WRITE + 0] = XSPI_LUT_SEQ(kXSPI_Command_DDR, kXSPI_8PAD, 0x20,
380 kXSPI_Command_RADDR_DDR, kXSPI_8PAD, 0x18),
381 [5 * HYPERRAM_CMD_LUT_SEQ_IDX_BURST_WRITE + 1] = XSPI_LUT_SEQ(kXSPI_Command_CADDR_DDR, kXSPI_8PAD, 0x10,
382 kXSPI_Command_DUMMY_SDR, kXSPI_8PAD, 6), /* Dummy cycle: 2 * 6 + 2 */
383 [5 * HYPERRAM_CMD_LUT_SEQ_IDX_BURST_WRITE + 2] = XSPI_LUT_SEQ(kXSPI_Command_WRITE_DDR, kXSPI_8PAD, 0x04,
384 kXSPI_Command_STOP, kXSPI_1PAD, 0X0),
385
386 [5 * HYPERRAM_CMD_LUT_SEQ_IDX_REG_READ] = XSPI_LUT_SEQ(kXSPI_Command_DDR, kXSPI_8PAD, 0xE0,
387 kXSPI_Command_RADDR_DDR, kXSPI_8PAD, 0x18),
388 [5 * HYPERRAM_CMD_LUT_SEQ_IDX_REG_READ + 1] = XSPI_LUT_SEQ(kXSPI_Command_CADDR_DDR, kXSPI_8PAD, 0x10,
389 kXSPI_Command_DUMMY_SDR, kXSPI_8PAD, 0x6), /* Dummy cycle: 2 * 6 + 2 */
390 [5 * HYPERRAM_CMD_LUT_SEQ_IDX_REG_READ + 2] = XSPI_LUT_SEQ(kXSPI_Command_READ_DDR, kXSPI_8PAD, 0x04,
391 kXSPI_Command_STOP, kXSPI_1PAD, 0x0),
392
393 /* Register write */
394 [5 * HYPERRAM_CMD_LUT_SEQ_IDX_REG_WRITE] = XSPI_LUT_SEQ(kXSPI_Command_DDR, kXSPI_8PAD, 0x60,
395 kXSPI_Command_RADDR_DDR, kXSPI_8PAD, 0x18),
396 [5 * HYPERRAM_CMD_LUT_SEQ_IDX_REG_WRITE + 1] = XSPI_LUT_SEQ(kXSPI_Command_CADDR_DDR, kXSPI_8PAD, 0x10,
397 kXSPI_Command_WRITE_DDR, kXSPI_8PAD, 0x02),
398 [5 * HYPERRAM_CMD_LUT_SEQ_IDX_REG_WRITE + 2] = XSPI_LUT_SEQ(kXSPI_Command_STOP, kXSPI_1PAD, 0x0,
399 kXSPI_Command_STOP, kXSPI_1PAD, 0x0),
400 #else
401 /* Memory Read */
402 [5 * HYPERRAM_CMD_LUT_SEQ_IDX_BURST_READ] = XSPI_LUT_SEQ(kXSPI_Command_DDR, kXSPI_8PAD, 0xA0,
403 kXSPI_Command_RADDR_DDR, kXSPI_8PAD, 0x18),
404 [5 * HYPERRAM_CMD_LUT_SEQ_IDX_BURST_READ + 1] = XSPI_LUT_SEQ(kXSPI_Command_CADDR_DDR, kXSPI_8PAD, 0x10,
405 kXSPI_Command_DUMMY_SDR, kXSPI_8PAD, 13),
406 [5 * HYPERRAM_CMD_LUT_SEQ_IDX_BURST_READ + 2] = XSPI_LUT_SEQ(kXSPI_Command_READ_DDR, kXSPI_8PAD, 0x04,
407 kXSPI_Command_STOP, kXSPI_1PAD, 0x0),
408
409 /* Memory Write */
410 [5 * HYPERRAM_CMD_LUT_SEQ_IDX_BURST_WRITE] = XSPI_LUT_SEQ(kXSPI_Command_DDR, kXSPI_8PAD, 0x20,
411 kXSPI_Command_RADDR_DDR, kXSPI_8PAD, 0x18),
412 [5 * HYPERRAM_CMD_LUT_SEQ_IDX_BURST_WRITE + 1] = XSPI_LUT_SEQ(kXSPI_Command_CADDR_DDR, kXSPI_8PAD, 0x10,
413 kXSPI_Command_DUMMY_SDR, kXSPI_8PAD, 13), /* Dummy cycle: 13 + 1 */
414 [5 * HYPERRAM_CMD_LUT_SEQ_IDX_BURST_WRITE + 2] = XSPI_LUT_SEQ(kXSPI_Command_WRITE_DDR, kXSPI_8PAD, 0x04,
415 kXSPI_Command_STOP, kXSPI_1PAD, 0X0),
416
417 /* Register Read */
418 [5 * HYPERRAM_CMD_LUT_SEQ_IDX_REG_READ] = XSPI_LUT_SEQ(kXSPI_Command_DDR, kXSPI_8PAD, 0xE0,
419 kXSPI_Command_RADDR_DDR, kXSPI_8PAD, 0x18),
420 [5 * HYPERRAM_CMD_LUT_SEQ_IDX_REG_READ + 1] = XSPI_LUT_SEQ(kXSPI_Command_CADDR_DDR, kXSPI_8PAD, 0x10,
421 kXSPI_Command_DUMMY_SDR, kXSPI_8PAD, 13), /* Dummy cycle: 13 + 1 */
422 [5 * HYPERRAM_CMD_LUT_SEQ_IDX_REG_READ + 2] = XSPI_LUT_SEQ(kXSPI_Command_READ_DDR, kXSPI_8PAD, 0x04,
423 kXSPI_Command_STOP, kXSPI_1PAD, 0x0),
424
425 /* Register write */
426 [5 * HYPERRAM_CMD_LUT_SEQ_IDX_REG_WRITE] = XSPI_LUT_SEQ(kXSPI_Command_DDR, kXSPI_8PAD, 0x60,
427 kXSPI_Command_RADDR_DDR, kXSPI_8PAD, 0x18),
428 [5 * HYPERRAM_CMD_LUT_SEQ_IDX_REG_WRITE + 1] = XSPI_LUT_SEQ(kXSPI_Command_CADDR_DDR, kXSPI_8PAD, 0x10,
429 kXSPI_Command_WRITE_DDR, kXSPI_8PAD, 0x02),
430 [5 * HYPERRAM_CMD_LUT_SEQ_IDX_REG_WRITE + 2] = XSPI_LUT_SEQ(kXSPI_Command_STOP, kXSPI_1PAD, 0x0,
431 kXSPI_Command_STOP, kXSPI_1PAD, 0x0),
432 #endif
433 /* reset */
434 [5 * HYPERRAM_CMD_LUT_SEQ_IDX_RESET + 0] = XSPI_LUT_SEQ(kXSPI_Command_DDR, kXSPI_8PAD, 0xFF, kXSPI_Command_DDR, kXSPI_8PAD, 0xFF),
435 [5 * HYPERRAM_CMD_LUT_SEQ_IDX_RESET + 1] = XSPI_LUT_SEQ(kXSPI_Command_STOP, kXSPI_8PAD, 0x0, kXSPI_Command_STOP, kXSPI_8PAD, 0x0),
436 };
437 /* clang-format on */
438
439 xspi_device_ddr_config_t psRamDdrConfig = {
440 .ddrDataAlignedClk = kXSPI_DDRDataAlignedWith2xInternalRefClk,
441 .enableByteSwapInOctalMode = false,
442 .enableDdr = true,
443 };
444
445 xspi_device_config_t psRamDeviceConfig = {
446 .xspiRootClk = 500000000, /*!< 500MHz */
447 .enableCknPad = true, /*!< CKN signal is connected in board. */
448 .deviceInterface = kXSPI_HyperBus, /*!< HyperBus protocol. */
449 .interfaceSettings.hyperBusSettings.x16Mode = kXSPI_x16ModeEnabledOnlyData, /*!< Only Data use x16 mode. */
450 #if (defined(BOARD_PSRAM_ENABLE_VARIABLE_LATENCY) && BOARD_PSRAM_ENABLE_VARIABLE_LATENCY)
451 .interfaceSettings.hyperBusSettings.enableVariableLatency =
452 true, /*!< Enable additional latency to increase performance. */
453 #else
454 .interfaceSettings.hyperBusSettings.enableVariableLatency = false,
455 #endif
456 .interfaceSettings.hyperBusSettings.forceBit10To1 = false,
457 .CSHoldTime = 3,
458 .CSSetupTime = 3,
459 .sampleClkConfig.sampleClkSource = kXSPI_SampleClkFromExternalDQS,
460 .sampleClkConfig.enableDQSLatency = false,
461 .sampleClkConfig.dllConfig.dllMode = kXSPI_AutoUpdateMode,
462 .sampleClkConfig.dllConfig.useRefValue = true,
463 .sampleClkConfig.dllConfig.enableCdl8 = false,
464 .addrMode = kXSPI_Device2ByteAddressable,
465 .columnAddrWidth = 3U,
466 .enableCASInterleaving = false,
467 .deviceSize[0] = 0x8000U,
468 .deviceSize[1] = 0x8000U, /*!< Single die device, so deviceSize1 should equal to deviceSize0. */
469 .ptrDeviceRegInfo = NULL,
470 .ptrDeviceDdrConfig = &psRamDdrConfig,
471 };
472 /* Get XSPI default settings and configure the xspi. */
473 XSPI_GetDefaultConfig(&config);
474 if (base == XSPI2)
475 {
476 POWER_DisablePD(kPDRUNCFG_APD_XSPI2);
477 POWER_DisablePD(kPDRUNCFG_PPD_XSPI2);
478 POWER_ApplyPD();
479
480 CLOCK_AttachClk(kMAIN_PLL_PFD3_to_XSPI2);
481 CLOCK_SetClkDiv(kCLOCK_DivXspi2Clk, 1U);
482 #if (defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
483 CLOCK_EnableClock(kCLOCK_Xspi2);
484 #endif
485 }
486 else
487 {
488 psRamDeviceConfig.xspiRootClk = 400000000;
489 POWER_DisablePD(kPDRUNCFG_APD_XSPI1);
490 POWER_DisablePD(kPDRUNCFG_PPD_XSPI1);
491 POWER_ApplyPD();
492
493 CLOCK_AttachClk(kAUDIO_PLL_PFD1_to_XSPI1);
494 CLOCK_SetClkDiv(kCLOCK_DivXspi1Clk, 1U);
495 #if (defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
496 CLOCK_EnableClock(kCLOCK_Xspi1);
497 #endif
498 }
499
500 xspi_ahb_write_config_t psRamAhbWriteConfig = {
501 .AWRSeqIndex = HYPERRAM_CMD_LUT_SEQ_IDX_BURST_WRITE,
502 .blockRead = false,
503 .blockSequenceWrite = false,
504 .pageWaitTimeoutValue = 0UL,
505 .policy = kXSPI_SoftwareClearPPWFlag,
506 };
507 config.ptrAhbAccessConfig->ARDSeqIndex = HYPERRAM_CMD_LUT_SEQ_IDX_BURST_READ;
508 config.ptrAhbAccessConfig->ahbErrorPayload.highPayload = 0x5A5A5A5A;
509 config.ptrAhbAccessConfig->ahbErrorPayload.lowPayload = 0x5A5A5A5A;
510 config.ptrAhbAccessConfig->enableAHBBufferWriteFlush = true;
511 config.ptrAhbAccessConfig->enableAHBPrefetch = true;
512 config.ptrAhbAccessConfig->ptrAhbWriteConfig = &psRamAhbWriteConfig;
513
514 config.ptrIpAccessConfig->ptrSfpFradConfig = NULL;
515 config.ptrIpAccessConfig->ptrSfpMdadConfig = NULL;
516
517 XSPI_Init(base, &config);
518 XSPI_SetDeviceConfig(base, &psRamDeviceConfig);
519
520 /* Update LUT table. */
521 XSPI_UpdateLUT(base, 0, customLUT, CUSTOM_LUT_LENGTH);
522
523 uint16_t cr1Register[2] = {0x0, 0x0};
524
525 /* Enable CLKn. */
526 (void)xspi_hyper_ram_get_mcr(base, ((1U << 11) | (1U << 0)), (uint8_t *)cr1Register);
527 cr1Register[1] &= ~(0x01 << 6); /* enable ckn */
528 (void)xspi_hyper_ram_write_mcr(base, ((1U << 12) | (1U << 0)), (uint8_t *)cr1Register);
529
530
531 #if (defined(BOARD_PSRAM_ENABLE_VARIABLE_LATENCY) && BOARD_PSRAM_ENABLE_VARIABLE_LATENCY)
532 /* Following code to enable variable latency for hyperRAM */
533 uint16_t cr0Register[2] = {0x0U, 0x0U};
534
535 (void)xspi_hyper_ram_get_mcr(base, (1U << 11), (uint8_t *)cr0Register);
536
537 cr0Register[1] &= ~(1U << 3U);
538 cr0Register[0] &= ~(0x07 << 4); /* Clear drive strength */
539 cr0Register[0] |= (0x03 << 4); /* 46Ohms */
540
541 (void)xspi_hyper_ram_write_mcr(base, (1U << 11), (uint8_t *)cr0Register);
542 #endif
543 /* Updated address mode for AHB access. */
544 psRamDeviceConfig.addrMode = kXSPI_Device4ByteAddressable;
545 XSPI_SetDeviceConfig(base, &psRamDeviceConfig);
546 }
547
548 #endif /* MIMXRT798S_cm33_core0_SERIES */
549
550 #if defined(MIMXRT798S_cm33_core0_SERIES) || defined(MIMXRT798S_cm33_core1_SERIES)
GlikeyWriteEnable(GLIKEY_Type * base,uint8_t idx)551 void GlikeyWriteEnable(GLIKEY_Type *base, uint8_t idx)
552 {
553 (void)GLIKEY_SyncReset(base);
554
555 (void)GLIKEY_StartEnable(base, idx);
556 (void)GLIKEY_ContinueEnable(base, GLIKEY_CODEWORD_STEP1);
557 (void)GLIKEY_ContinueEnable(base, GLIKEY_CODEWORD_STEP2);
558 (void)GLIKEY_ContinueEnable(base, GLIKEY_CODEWORD_STEP3);
559 (void)GLIKEY_ContinueEnable(base, GLIKEY_CODEWORD_STEP_EN);
560 }
561
GlikeyClearConfig(GLIKEY_Type * base)562 void GlikeyClearConfig(GLIKEY_Type *base)
563 {
564 (void)GLIKEY_SyncReset(base);
565 }
566
567 /* Disable the secure check for AHBSC and enable periperhals/sram access for masters */
BOARD_InitAHBSC(void)568 void BOARD_InitAHBSC(void)
569 {
570 #if defined(MIMXRT798S_cm33_core0_SERIES)
571 GlikeyWriteEnable(GLIKEY0, 1U);
572 AHBSC0->MISC_CTRL_DP_REG = 0x000086aa;
573 AHBSC0->MISC_CTRL_REG = 0x000086aa; /* AHBSC0 MISC_CTRL_REG, disable Privilege & Secure checking. */
574
575 GlikeyWriteEnable(GLIKEY0, 7U);
576 /* Enable arbiter0 accessing SRAM */
577 AHBSC0->COMPUTE_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF;
578 AHBSC0->SENSE_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF;
579 AHBSC0->MEDIA_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF;
580 AHBSC0->NPU_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF;
581 AHBSC0->HIFI4_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF;
582 #endif
583
584 GlikeyWriteEnable(GLIKEY1, 1U);
585 AHBSC3->MISC_CTRL_DP_REG = 0x000086aa;
586 AHBSC3->MISC_CTRL_REG = 0x000086aa; /* AHBSC3 MISC_CTRL_REG, disable Privilege & Secure checking.*/
587
588 GlikeyWriteEnable(GLIKEY1, 9U);
589 /* Enable arbiter1 accessing SRAM */
590 AHBSC3->COMPUTE_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
591 AHBSC3->SENSE_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
592 AHBSC3->MEDIA_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
593 AHBSC3->NPU_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
594 AHBSC3->HIFI4_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
595 AHBSC3->HIFI1_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
596
597 GlikeyWriteEnable(GLIKEY1, 8U);
598 /* Access enable for COMPUTE domain masters to common APB peripherals.*/
599 AHBSC3->COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE = 0xffffffff;
600 AHBSC3->SENSE_APB_PERIPHERAL_ACCESS_ENABLE = 0xffffffff;
601 GlikeyWriteEnable(GLIKEY1, 7U);
602 AHBSC3->COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE = 0xffffffff;
603 AHBSC3->SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE = 0xffffffff;
604
605 GlikeyWriteEnable(GLIKEY2, 1U);
606 /*Disable secure and secure privilege checking. */
607 AHBSC4->MISC_CTRL_DP_REG = 0x000086aa;
608 AHBSC4->MISC_CTRL_REG = 0x000086aa;
609
610 #if defined(MIMXRT798S_cm33_core0_SERIES)
611 GlikeyClearConfig(GLIKEY0);
612 #endif
613 GlikeyClearConfig(GLIKEY1);
614 GlikeyClearConfig(GLIKEY2);
615 }
616 #endif /* MIMXRT798S_cm33_core0_SERIES || MIMXRT798S_cm33_core1_SERIES */
617
618 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
BOARD_I2C_Init(LPI2C_Type * base,uint32_t clkSrc_Hz)619 void BOARD_I2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
620 {
621 lpi2c_master_config_t i2cConfig = {0};
622
623 LPI2C_MasterGetDefaultConfig(&i2cConfig);
624 LPI2C_MasterInit(base, &i2cConfig, clkSrc_Hz);
625 }
626
BOARD_I2C_Send(LPI2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint8_t * txBuff,uint8_t txBuffSize)627 status_t BOARD_I2C_Send(LPI2C_Type *base,
628 uint8_t deviceAddress,
629 uint32_t subAddress,
630 uint8_t subaddressSize,
631 uint8_t *txBuff,
632 uint8_t txBuffSize)
633 {
634 lpi2c_master_transfer_t masterXfer;
635
636 /* Prepare transfer structure. */
637 masterXfer.slaveAddress = deviceAddress;
638 masterXfer.direction = kLPI2C_Write;
639 masterXfer.subaddress = subAddress;
640 masterXfer.subaddressSize = subaddressSize;
641 masterXfer.data = txBuff;
642 masterXfer.dataSize = txBuffSize;
643 masterXfer.flags = kLPI2C_TransferDefaultFlag;
644
645 return LPI2C_MasterTransferBlocking(base, &masterXfer);
646 }
647
BOARD_I2C_Receive(LPI2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)648 status_t BOARD_I2C_Receive(LPI2C_Type *base,
649 uint8_t deviceAddress,
650 uint32_t subAddress,
651 uint8_t subaddressSize,
652 uint8_t *rxBuff,
653 uint8_t rxBuffSize)
654 {
655 lpi2c_master_transfer_t masterXfer;
656
657 /* Prepare transfer structure. */
658 masterXfer.slaveAddress = deviceAddress;
659 masterXfer.subaddress = subAddress;
660 masterXfer.subaddressSize = subaddressSize;
661 masterXfer.data = rxBuff;
662 masterXfer.dataSize = rxBuffSize;
663 masterXfer.direction = kLPI2C_Read;
664 masterXfer.flags = kLPI2C_TransferDefaultFlag;
665
666 return LPI2C_MasterTransferBlocking(base, &masterXfer);
667 }
668
BOARD_PMIC_I2C_Init(void)669 void BOARD_PMIC_I2C_Init(void)
670 {
671 BOARD_I2C_Init(BOARD_PMIC_I2C_BASEADDR, BOARD_PMIC_I2C_CLOCK_FREQ);
672 }
673
BOARD_PMIC_I2C_Deinit(void)674 void BOARD_PMIC_I2C_Deinit(void)
675 {
676 LPI2C_MasterDeinit(BOARD_PMIC_I2C_BASEADDR);
677 }
678
BOARD_PMIC_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)679 status_t BOARD_PMIC_I2C_Send(
680 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
681 {
682 return BOARD_I2C_Send(BOARD_PMIC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
683 txBuffSize);
684 }
685
BOARD_PMIC_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)686 status_t BOARD_PMIC_I2C_Receive(
687 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
688 {
689 return BOARD_I2C_Receive(BOARD_PMIC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
690 }
691
692 #if defined(MIMXRT798S_cm33_core0_SERIES)
BOARD_MIPIPanelTouch_I2C_Init(void)693 void BOARD_MIPIPanelTouch_I2C_Init(void)
694 {
695 CLOCK_AttachClk(kOSC_CLK_to_FCCLK0);
696 CLOCK_AttachClk(kFCCLK0_to_FLEXCOMM8);
697 CLOCK_EnableClock(kCLOCK_LPFlexComm8);
698 BOARD_I2C_Init(BOARD_MIPI_PANEL_TOUCH_I2C_BASEADDR, BOARD_MIPI_PANEL_TOUCH_I2C_CLOCK_FREQ);
699 }
700
BOARD_MIPIPanelTouch_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)701 status_t BOARD_MIPIPanelTouch_I2C_Send(
702 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
703 {
704 return BOARD_I2C_Send(BOARD_MIPI_PANEL_TOUCH_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize,
705 (uint8_t *)txBuff, txBuffSize);
706 }
707
BOARD_MIPIPanelTouch_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)708 status_t BOARD_MIPIPanelTouch_I2C_Receive(
709 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
710 {
711 return BOARD_I2C_Receive(BOARD_MIPI_PANEL_TOUCH_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
712 rxBuffSize);
713 }
714 #endif
715 #endif
716
