1 /*
2 * Copyright 2018 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13 /* clang-format off */
14 /*
15 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
16 !!GlobalInfo
17 product: Pins v4.1
18 processor: MKV11Z128xxx7
19 package_id: MKV11Z128VLH7
20 mcu_data: ksdk2_0
21 processor_version: 4.0.0
22 board: FRDM-KV11Z
23 pin_labels:
24 - {pin_num: '1', pin_signal: ADC1_SE12/PTE0/UART1_TX, label: TP18}
25 - {pin_num: '2', pin_signal: ADC1_SE13/PTE1/LLWU_P0/UART1_RX, label: TP19}
26 - {pin_num: '11', pin_signal: ADC0_SE12/PTE22, label: TP22}
27 - {pin_num: '12', pin_signal: ADC0_SE13/PTE23, label: TP23}
28 - {pin_num: '19', pin_signal: ADC0_SE14/CMP0_IN4/PTE31, label: TP24}
29 - {pin_num: '27', pin_signal: PTA5/FTM0_CH2/FTM5_FLT0, label: TP25}
30 - {pin_num: '28', pin_signal: PTA12/CAN0_TX/FTM1_CH0/FTM1_QD_PHA, label: TP26}
31 - {pin_num: '42', pin_signal: PTB19/CAN0_RX/FTM3_CH3, label: TP20}
32 - {pin_num: '41', pin_signal: PTB18/CAN0_TX/FTM3_CH2, label: TP21}
33 - {pin_num: '55', pin_signal: ADC1_SE16/PTC10/FTM5_CH0/FTM5_QD_PHA, label: TP17}
34 - {pin_num: '56', pin_signal: ADC1_SE17/PTC11/LLWU_P11/FTM5_CH1/FTM5_QD_PHB, label: TP16}
35 - {pin_num: '13', pin_signal: VDDA, label: VDDA}
36 - {pin_num: '14', pin_signal: VREFH, label: 'J2[16]/AREF/VREFH'}
37 - {pin_num: '15', pin_signal: VREFL, label: VREFL}
38 - {pin_num: '16', pin_signal: VSSA, label: VSSA}
39 - {pin_num: '32', pin_signal: EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0/FTM3_CH2, label: 'Y2[1]', identifier: EXTAL}
40 - {pin_num: '33', pin_signal: XTAL0/PTA19/FTM0_FLT0/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1, label: 'Y2[2]', identifier: XTAL}
41 - {pin_num: '3', pin_signal: VDD3, label: 'J3[4]/J3[8]/J13[1]/P3V3/P3V3_KV11/VDD'}
42 - {pin_num: '30', pin_signal: VDD30, label: 'J3[4]/J3[8]/J13[1]/P3V3/P3V3_KV11/VDD'}
43 - {pin_num: '48', pin_signal: VDD48, label: 'J3[4]/J3[8]/J13[1]/P3V3/P3V3_KV11/VDD'}
44 - {pin_num: '4', pin_signal: VSS4, label: 'J2[14]/J3[12]/J3[14]/J13[3]/J13[5]/GND/VSS'}
45 - {pin_num: '31', pin_signal: VSS31, label: 'J2[14]/J3[12]/J3[14]/J13[3]/J13[5]/GND/VSS'}
46 - {pin_num: '47', pin_signal: VSS47, label: 'J2[14]/J3[12]/J3[14]/J13[3]/J13[5]/GND/VSS'}
47 - {pin_num: '5', pin_signal: ADC0_SE1/ADC0_DP1/ADC1_SE0/PTE16/SPI0_PCS0/UART1_TX/FTM_CLKIN0/FTM0_FLT3, label: 'J4[4]/PTE16'}
48 - {pin_num: '6', pin_signal: ADC0_DM1/ADC0_SE5/ADC1_SE5/PTE17/LLWU_P19/SPI0_SCK/UART1_RX/FTM_CLKIN1/LPTMR0_ALT3, label: 'J2[7]/PTE17-ADC0_SE5'}
49 - {pin_num: '7', pin_signal: ADC0_SE6/ADC1_SE1/ADC1_DP1/PTE18/LLWU_P20/SPI0_SOUT/UART1_CTS_b/I2C0_SDA/SPI0_SIN, label: 'J2[1]/PTE18-ADC0_SE6'}
50 - {pin_num: '8', pin_signal: ADC0_SE7/ADC1_SE7/ADC1_DM1/PTE19/SPI0_SIN/UART1_RTS_b/I2C0_SCL/SPI0_SOUT, label: 'J2[5]/PTE19-ADC0_SE7'}
51 - {pin_num: '9', pin_signal: ADC0_SE0/ADC0_DP0/PTE20/FTM1_CH0/UART0_TX, label: 'J4[6]/ADC0_DP0/THER_A', identifier: ADC0_DP_THER}
52 - {pin_num: '10', pin_signal: ADC0_SE4/ADC0_DM0/PTE21/FTM1_CH1/UART0_RX, label: 'J4[8]/ADC0_DM0/THER_B', identifier: ADC0_DM_THER}
53 - {pin_num: '17', pin_signal: CMP1_IN5/CMP0_IN5/PTE29/FTM0_CH2/FTM_CLKIN0, label: 'J1[13]/J1[14]/LD1[4]/PTE29', identifier: LED_GREEN}
54 - {pin_num: '18', pin_signal: ADC1_SE4/CMP1_IN4/DAC0_OUT/PTE30/FTM0_CH3/FTM_CLKIN1, label: 'J2[9]/PTE30- ADC1_ SE4'}
55 - {pin_num: '20', pin_signal: PTE24/CAN0_TX/FTM0_CH0/I2C0_SCL/EWM_OUT_b, label: 'J1[1]/J1[8]/U9[1]/PTE24', identifier: CAN_TX}
56 - {pin_num: '21', pin_signal: PTE25/LLWU_P21/CAN0_RX/FTM0_CH1/I2C0_SDA/EWM_IN, label: 'J1[5]/J1[12]/LD1[3]/U9[4]/PTE25', identifier: LED_BLUE;CAN_RX}
57 - {pin_num: '22', pin_signal: PTA0/UART0_CTS_b/FTM0_CH5/EWM_IN/SWD_CLK, label: 'J13[4]/U8[4]/SWD_ CLK_ KV11'}
58 - {pin_num: '23', pin_signal: PTA1/UART0_RX/FTM2_CH0/CMP0_OUT/FTM2_QD_PHA/FTM1_CH1/FTM4_CH0, label: 'J3[3]/PTA1- FRDM- MC- ENC_ A'}
59 - {pin_num: '24', pin_signal: PTA2/UART0_TX/FTM2_CH1/CMP1_OUT/FTM2_QD_PHB/FTM1_CH0/FTM4_CH1, label: 'J3[1]/PTA2- FRDM- MC- ENC_ B'}
60 - {pin_num: '25', pin_signal: PTA3/UART0_RTS_b/FTM0_CH0/FTM2_FLT0/EWM_OUT_b/SWD_DIO, label: 'J13[2]/U7[4]/SWD_ DIO_ TGTMCU'}
61 - {pin_num: '26', pin_signal: PTA4/LLWU_P3/FTM0_CH1/FTM4_FLT0/FTM0_FLT3/NMI_b, label: 'J2[4]/PTA4', identifier: SW3}
62 - {pin_num: '29', pin_signal: PTA13/LLWU_P4/CAN0_RX/FTM1_CH1/FTM1_QD_PHB, label: 'U9[8]/PTA13', identifier: CAN_S}
63 - {pin_num: '34', pin_signal: PTA20/RESET_b, label: 'J3[6]/J10[3]/J13[10]/RST_TGTMCU_B'}
64 - {pin_num: '35', pin_signal: ADC0_SE8/ADC1_SE8/PTB0/LLWU_P5/I2C0_SCL/FTM1_CH0/FTM1_QD_PHA/UART0_RX, label: 'J1[10]/J1[11]/PTB0', identifier: SW2}
65 - {pin_num: '36', pin_signal: ADC0_SE9/ADC1_SE9/PTB1/I2C0_SDA/FTM1_CH1/FTM0_FLT2/EWM_IN/FTM1_QD_PHB/UART0_TX, label: 'J2[3]/PTB1-ADC0_SE9'}
66 - {pin_num: '37', pin_signal: ADC0_SE10/ADC1_SE10/ADC1_DM2/PTB2/I2C0_SCL/UART0_RTS_b/FTM0_FLT1/FTM0_FLT3, label: 'J2[15]/J2[20]/J4[12]/U10[9]/PTB2', identifier: ACCEL_INT2}
67 - {pin_num: '38', pin_signal: ADC1_SE2/ADC1_DP2/PTB3/I2C0_SDA/UART0_CTS_b/FTM0_FLT0, label: 'J2[11]/J2[18]/J4[10]/U10[11]/PTB3', identifier: ACCEL_INT1}
68 - {pin_num: '39', pin_signal: PTB16/UART0_RX/FTM_CLKIN2/CAN0_TX/EWM_IN, label: 'J1[6]/U3[4]/UART0_RX_TGTMCU', identifier: DEBUG_UART_RX}
69 - {pin_num: '40', pin_signal: PTB17/UART0_TX/FTM_CLKIN1/CAN0_RX/EWM_OUT_b, label: 'U5[1]/UART0_TX_TGTMCU', identifier: DEBUG_UART_TX}
70 - {pin_num: '43', pin_signal: ADC1_SE11/PTC0/SPI0_PCS4/PDB_EXTRG0/CMP0_OUT/FTM0_FLT0/SPI0_PCS0, label: 'J4[2]/PTC0'}
71 - {pin_num: '44', pin_signal: ADC1_SE3/PTC1/LLWU_P6/SPI0_PCS3/UART1_RTS_b/FTM0_CH0/FTM2_CH0, label: 'J3[15]/PTC1-FRDM-MC-PWM_AT'}
72 - {pin_num: '45', pin_signal: ADC0_SE11/CMP1_IN0/PTC2/SPI0_PCS2/UART1_CTS_b/FTM0_CH1/FTM2_CH1, label: 'J3[13]/PTC2-FRDM-MC-PWM_AB'}
73 - {pin_num: '46', pin_signal: CMP1_IN1/PTC3/LLWU_P7/SPI0_PCS1/UART1_RX/FTM0_CH2/CLKOUT/FTM3_FLT0, label: 'J3[11]/PTC3-FRDM-MC-PWM_BT'}
74 - {pin_num: '49', pin_signal: PTC4/LLWU_P8/SPI0_PCS0/UART1_TX/FTM0_CH3/CMP1_OUT, label: 'J3[9]/PTC4- FRDM- MC- PWM_ BB'}
75 - {pin_num: '50', pin_signal: PTC5/LLWU_P9/SPI0_SCK/LPTMR0_ALT2/CMP0_OUT/FTM0_CH2, label: 'J2[12]/J2[17]/PTC5'}
76 - {pin_num: '51', pin_signal: CMP0_IN0/PTC6/LLWU_P10/SPI0_SOUT/PDB_EXTRG1/UART0_RX/I2C0_SCL, label: 'J2[8]/J2[13]/U10[4]/I2C0_SCL/SPI0_SOUT/PTC6', identifier: ACCEL_SCL}
77 - {pin_num: '52', pin_signal: CMP0_IN1/PTC7/SPI0_SIN/UART0_TX/I2C0_SDA, label: 'J1[15]/J1[16]/U10[6]/I2C0_SDA/PTC7', identifier: ACCEL_SDA}
78 - {pin_num: '53', pin_signal: ADC1_SE14/CMP0_IN2/PTC8/FTM3_CH4, label: 'J4[9]/PTC8'}
79 - {pin_num: '54', pin_signal: ADC1_SE15/CMP0_IN3/PTC9/FTM3_CH5, label: 'J4[11]/PTC9'}
80 - {pin_num: '57', pin_signal: PTD0/LLWU_P12/SPI0_PCS0/UART0_CTS_b/FTM0_CH0/UART1_RX/FTM3_CH0, label: 'J1[2]/J1[7]/J4[1]/PTD0'}
81 - {pin_num: '58', pin_signal: ADC0_SE2/PTD1/SPI0_SCK/UART0_RTS_b/FTM0_CH1/UART1_TX/FTM3_CH1, label: 'J1[4]/J1[9]/J4[3]/U10[16]/PTD1', identifier: ACCEL_RST}
82 - {pin_num: '59', pin_signal: PTD2/LLWU_P13/SPI0_SOUT/UART0_RX/FTM0_CH2/FTM3_CH2/I2C0_SCL, label: 'J2[2]/J4[5]/PTD2'}
83 - {pin_num: '60', pin_signal: PTD3/SPI0_SIN/UART0_TX/FTM0_CH3/FTM3_CH3/I2C0_SDA, label: 'J2[10]/J2[19]/J4[7]/SPI0_SIN/PTD3'}
84 - {pin_num: '61', pin_signal: PTD4/LLWU_P14/SPI0_PCS1/UART0_RTS_b/FTM0_CH4/FTM2_CH0/EWM_IN/SPI0_PCS0, label: 'J3[7]/PTD4- FRDM- MC- PWM_ CT'}
85 - {pin_num: '62', pin_signal: ADC0_SE3/PTD5/SPI0_PCS2/UART0_CTS_b/FTM0_CH5/FTM2_CH1/EWM_OUT_b/SPI0_SCK, label: 'J3[5]/PTD5- FRDM- MC- PWM_ CB'}
86 - {pin_num: '63', pin_signal: ADC1_SE6/PTD6/LLWU_P15/FTM4_CH0/UART0_RX/FTM0_CH0/FTM1_CH0/FTM0_FLT0/SPI0_SOUT, label: 'J2[6]/LD1[1]/PTD6', identifier: LED_RED}
87 - {pin_num: '64', pin_signal: PTD7/FTM4_CH1/UART0_TX/FTM0_CH1/FTM1_CH1/FTM0_FLT1/SPI0_SIN, label: 'J1[3]/PTD7- FRDM- MC- ENC_ I'}
88 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
89 */
90 /* clang-format on */
91
92 #include "fsl_common.h"
93 #include "fsl_port.h"
94 #include "fsl_gpio.h"
95 #include "pin_mux.h"
96
97 /* FUNCTION ************************************************************************************************************
98 *
99 * Function Name : BOARD_InitBootPins
100 * Description : Calls initialization functions.
101 *
102 * END ****************************************************************************************************************/
BOARD_InitBootPins(void)103 void BOARD_InitBootPins(void)
104 {
105 BOARD_InitPins();
106 BOARD_InitDEBUG_UARTPins();
107 }
108
109 /* clang-format off */
110 /*
111 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
112 BOARD_InitPins:
113 - options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
114 - pin_list: []
115 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
116 */
117 /* clang-format on */
118
119 /* FUNCTION ************************************************************************************************************
120 *
121 * Function Name : BOARD_InitPins
122 * Description : Configures pin routing and optionally pin electrical features.
123 *
124 * END ****************************************************************************************************************/
BOARD_InitPins(void)125 void BOARD_InitPins(void)
126 {
127 }
128
129 /* clang-format off */
130 /*
131 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
132 BOARD_InitButtonsPins:
133 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
134 - pin_list:
135 - {pin_num: '35', peripheral: GPIOB, signal: 'GPIO, 0', pin_signal: ADC0_SE8/ADC1_SE8/PTB0/LLWU_P5/I2C0_SCL/FTM1_CH0/FTM1_QD_PHA/UART0_RX, direction: INPUT, slew_rate: slow,
136 drive_strength: low, pull_select: up, pull_enable: enable}
137 - {pin_num: '26', peripheral: GPIOA, signal: 'GPIO, 4', pin_signal: PTA4/LLWU_P3/FTM0_CH1/FTM4_FLT0/FTM0_FLT3/NMI_b, direction: INPUT, slew_rate: slow, pull_select: up,
138 pull_enable: enable, passive_filter: enable}
139 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
140 */
141 /* clang-format on */
142
143 /* FUNCTION ************************************************************************************************************
144 *
145 * Function Name : BOARD_InitButtonsPins
146 * Description : Configures pin routing and optionally pin electrical features.
147 *
148 * END ****************************************************************************************************************/
BOARD_InitButtonsPins(void)149 void BOARD_InitButtonsPins(void)
150 {
151 /* Port A Clock Gate Control: Clock enabled */
152 CLOCK_EnableClock(kCLOCK_PortA);
153 /* Port B Clock Gate Control: Clock enabled */
154 CLOCK_EnableClock(kCLOCK_PortB);
155
156 gpio_pin_config_t SW3_config = {
157 .pinDirection = kGPIO_DigitalInput,
158 .outputLogic = 0U
159 };
160 /* Initialize GPIO functionality on pin PTA4 (pin 26) */
161 GPIO_PinInit(BOARD_SW3_GPIO, BOARD_SW3_PIN, &SW3_config);
162
163 gpio_pin_config_t SW2_config = {
164 .pinDirection = kGPIO_DigitalInput,
165 .outputLogic = 0U
166 };
167 /* Initialize GPIO functionality on pin PTB0 (pin 35) */
168 GPIO_PinInit(BOARD_SW2_GPIO, BOARD_SW2_PIN, &SW2_config);
169
170 const port_pin_config_t SW3 = {/* Internal pull-up resistor is enabled */
171 kPORT_PullUp,
172 /* Slow slew rate is configured */
173 kPORT_SlowSlewRate,
174 /* Passive filter is enabled */
175 kPORT_PassiveFilterEnable,
176 /* Low drive strength is configured */
177 kPORT_LowDriveStrength,
178 /* Pin is configured as PTA4 */
179 kPORT_MuxAsGpio};
180 /* PORTA4 (pin 26) is configured as PTA4 */
181 PORT_SetPinConfig(BOARD_SW3_PORT, BOARD_SW3_PIN, &SW3);
182
183 const port_pin_config_t SW2 = {/* Internal pull-up resistor is enabled */
184 kPORT_PullUp,
185 /* Slow slew rate is configured */
186 kPORT_SlowSlewRate,
187 /* Passive filter is disabled */
188 kPORT_PassiveFilterDisable,
189 /* Low drive strength is configured */
190 kPORT_LowDriveStrength,
191 /* Pin is configured as PTB0 */
192 kPORT_MuxAsGpio};
193 /* PORTB0 (pin 35) is configured as PTB0 */
194 PORT_SetPinConfig(BOARD_SW2_PORT, BOARD_SW2_PIN, &SW2);
195 }
196
197 /* clang-format off */
198 /*
199 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
200 BOARD_InitLEDsPins:
201 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
202 - pin_list:
203 - {pin_num: '63', peripheral: GPIOD, signal: 'GPIO, 6', pin_signal: ADC1_SE6/PTD6/LLWU_P15/FTM4_CH0/UART0_RX/FTM0_CH0/FTM1_CH0/FTM0_FLT0/SPI0_SOUT, direction: OUTPUT,
204 gpio_init_state: 'true', slew_rate: slow, drive_strength: low, pull_select: down, pull_enable: disable}
205 - {pin_num: '17', peripheral: GPIOE, signal: 'GPIO, 29', pin_signal: CMP1_IN5/CMP0_IN5/PTE29/FTM0_CH2/FTM_CLKIN0, direction: OUTPUT, gpio_init_state: 'true', slew_rate: slow,
206 pull_select: down, pull_enable: disable}
207 - {pin_num: '21', peripheral: GPIOE, signal: 'GPIO, 25', pin_signal: PTE25/LLWU_P21/CAN0_RX/FTM0_CH1/I2C0_SDA/EWM_IN, identifier: LED_BLUE, direction: OUTPUT, gpio_init_state: 'true',
208 slew_rate: slow, pull_select: down, pull_enable: disable}
209 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
210 */
211 /* clang-format on */
212
213 /* FUNCTION ************************************************************************************************************
214 *
215 * Function Name : BOARD_InitLEDsPins
216 * Description : Configures pin routing and optionally pin electrical features.
217 *
218 * END ****************************************************************************************************************/
BOARD_InitLEDsPins(void)219 void BOARD_InitLEDsPins(void)
220 {
221 /* Port D Clock Gate Control: Clock enabled */
222 CLOCK_EnableClock(kCLOCK_PortD);
223 /* Port E Clock Gate Control: Clock enabled */
224 CLOCK_EnableClock(kCLOCK_PortE);
225
226 gpio_pin_config_t LED_RED_config = {
227 .pinDirection = kGPIO_DigitalOutput,
228 .outputLogic = 1U
229 };
230 /* Initialize GPIO functionality on pin PTD6 (pin 63) */
231 GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_PIN, &LED_RED_config);
232
233 gpio_pin_config_t LED_BLUE_config = {
234 .pinDirection = kGPIO_DigitalOutput,
235 .outputLogic = 1U
236 };
237 /* Initialize GPIO functionality on pin PTE25 (pin 21) */
238 GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_PIN, &LED_BLUE_config);
239
240 gpio_pin_config_t LED_GREEN_config = {
241 .pinDirection = kGPIO_DigitalOutput,
242 .outputLogic = 1U
243 };
244 /* Initialize GPIO functionality on pin PTE29 (pin 17) */
245 GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_PIN, &LED_GREEN_config);
246
247 const port_pin_config_t LED_RED = {/* Internal pull-up/down resistor is disabled */
248 kPORT_PullDisable,
249 /* Slow slew rate is configured */
250 kPORT_SlowSlewRate,
251 /* Passive filter is disabled */
252 kPORT_PassiveFilterDisable,
253 /* Low drive strength is configured */
254 kPORT_LowDriveStrength,
255 /* Pin is configured as PTD6 */
256 kPORT_MuxAsGpio};
257 /* PORTD6 (pin 63) is configured as PTD6 */
258 PORT_SetPinConfig(BOARD_LED_RED_PORT, BOARD_LED_RED_PIN, &LED_RED);
259
260 const port_pin_config_t LED_BLUE = {/* Internal pull-up/down resistor is disabled */
261 kPORT_PullDisable,
262 /* Slow slew rate is configured */
263 kPORT_SlowSlewRate,
264 /* Passive filter is disabled */
265 kPORT_PassiveFilterDisable,
266 /* Low drive strength is configured */
267 kPORT_LowDriveStrength,
268 /* Pin is configured as PTE25 */
269 kPORT_MuxAsGpio};
270 /* PORTE25 (pin 21) is configured as PTE25 */
271 PORT_SetPinConfig(BOARD_LED_BLUE_PORT, BOARD_LED_BLUE_PIN, &LED_BLUE);
272
273 const port_pin_config_t LED_GREEN = {/* Internal pull-up/down resistor is disabled */
274 kPORT_PullDisable,
275 /* Slow slew rate is configured */
276 kPORT_SlowSlewRate,
277 /* Passive filter is disabled */
278 kPORT_PassiveFilterDisable,
279 /* Low drive strength is configured */
280 kPORT_LowDriveStrength,
281 /* Pin is configured as PTE29 */
282 kPORT_MuxAsGpio};
283 /* PORTE29 (pin 17) is configured as PTE29 */
284 PORT_SetPinConfig(BOARD_LED_GREEN_PORT, BOARD_LED_GREEN_PIN, &LED_GREEN);
285 }
286
287 /* clang-format off */
288 /*
289 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
290 BOARD_InitDEBUG_UARTPins:
291 - options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
292 - pin_list:
293 - {pin_num: '40', peripheral: UART0, signal: TX, pin_signal: PTB17/UART0_TX/FTM_CLKIN1/CAN0_RX/EWM_OUT_b, direction: OUTPUT, slew_rate: fast, open_drain: disable,
294 pull_select: down, pull_enable: disable}
295 - {pin_num: '39', peripheral: UART0, signal: RX, pin_signal: PTB16/UART0_RX/FTM_CLKIN2/CAN0_TX/EWM_IN, slew_rate: fast, pull_select: down, pull_enable: disable}
296 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
297 */
298 /* clang-format on */
299
300 /* FUNCTION ************************************************************************************************************
301 *
302 * Function Name : BOARD_InitDEBUG_UARTPins
303 * Description : Configures pin routing and optionally pin electrical features.
304 *
305 * END ****************************************************************************************************************/
BOARD_InitDEBUG_UARTPins(void)306 void BOARD_InitDEBUG_UARTPins(void)
307 {
308 /* Port B Clock Gate Control: Clock enabled */
309 CLOCK_EnableClock(kCLOCK_PortB);
310
311 const port_pin_config_t DEBUG_UART_RX = {/* Internal pull-up/down resistor is disabled */
312 kPORT_PullDisable,
313 /* Fast slew rate is configured */
314 kPORT_FastSlewRate,
315 /* Passive filter is disabled */
316 kPORT_PassiveFilterDisable,
317 /* Low drive strength is configured */
318 kPORT_LowDriveStrength,
319 /* Pin is configured as UART0_RX */
320 kPORT_MuxAlt3};
321 /* PORTB16 (pin 39) is configured as UART0_RX */
322 PORT_SetPinConfig(BOARD_DEBUG_UART_RX_PORT, BOARD_DEBUG_UART_RX_PIN, &DEBUG_UART_RX);
323
324 const port_pin_config_t DEBUG_UART_TX = {/* Internal pull-up/down resistor is disabled */
325 kPORT_PullDisable,
326 /* Fast slew rate is configured */
327 kPORT_FastSlewRate,
328 /* Passive filter is disabled */
329 kPORT_PassiveFilterDisable,
330 /* Low drive strength is configured */
331 kPORT_LowDriveStrength,
332 /* Pin is configured as UART0_TX */
333 kPORT_MuxAlt3};
334 /* PORTB17 (pin 40) is configured as UART0_TX */
335 PORT_SetPinConfig(BOARD_DEBUG_UART_TX_PORT, BOARD_DEBUG_UART_TX_PIN, &DEBUG_UART_TX);
336
337 SIM->SOPT5 = ((SIM->SOPT5 &
338 /* Mask bits to zero which are setting */
339 (~(SIM_SOPT5_UART0TXSRC_MASK | SIM_SOPT5_UART0RXSRC_MASK | SIM_SOPT5_UART0ODE_MASK)))
340
341 /* UART 0 Transmit Data Source Select: UART0_TX pin. */
342 | SIM_SOPT5_UART0TXSRC(SOPT5_UART0TXSRC_UART_TX)
343
344 /* UART 0 Receive Data Source Select: UART0_RX pin. */
345 | SIM_SOPT5_UART0RXSRC(SOPT5_UART0RXSRC_UART_RX)
346
347 /* UART0 Open Drain Enable: Open drain is disabled on UART0. */
348 | SIM_SOPT5_UART0ODE(SOPT5_UART0ODE_DISABLED));
349 }
350
351 /* clang-format off */
352 /*
353 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
354 BOARD_InitOSCPins:
355 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
356 - pin_list:
357 - {pin_num: '32', peripheral: OSC0, signal: EXTAL0, pin_signal: EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0/FTM3_CH2, slew_rate: no_init, pull_select: no_init, pull_enable: no_init}
358 - {pin_num: '33', peripheral: OSC0, signal: XTAL0, pin_signal: XTAL0/PTA19/FTM0_FLT0/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1, slew_rate: no_init, pull_select: no_init,
359 pull_enable: no_init}
360 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
361 */
362 /* clang-format on */
363
364 /* FUNCTION ************************************************************************************************************
365 *
366 * Function Name : BOARD_InitOSCPins
367 * Description : Configures pin routing and optionally pin electrical features.
368 *
369 * END ****************************************************************************************************************/
BOARD_InitOSCPins(void)370 void BOARD_InitOSCPins(void)
371 {
372 /* Port A Clock Gate Control: Clock enabled */
373 CLOCK_EnableClock(kCLOCK_PortA);
374
375 /* PORTA18 (pin 32) is configured as EXTAL0 */
376 PORT_SetPinMux(BOARD_EXTAL_PORT, BOARD_EXTAL_PIN, kPORT_PinDisabledOrAnalog);
377
378 /* PORTA19 (pin 33) is configured as XTAL0 */
379 PORT_SetPinMux(BOARD_XTAL_PORT, BOARD_XTAL_PIN, kPORT_PinDisabledOrAnalog);
380 }
381
382 /* clang-format off */
383 /*
384 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
385 BOARD_InitACCELPins:
386 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
387 - pin_list:
388 - {pin_num: '51', peripheral: I2C0, signal: SCL, pin_signal: CMP0_IN0/PTC6/LLWU_P10/SPI0_SOUT/PDB_EXTRG1/UART0_RX/I2C0_SCL, pull_select: down, pull_enable: disable}
389 - {pin_num: '52', peripheral: I2C0, signal: SDA, pin_signal: CMP0_IN1/PTC7/SPI0_SIN/UART0_TX/I2C0_SDA, pull_select: down, pull_enable: disable}
390 - {pin_num: '58', peripheral: GPIOD, signal: 'GPIO, 1', pin_signal: ADC0_SE2/PTD1/SPI0_SCK/UART0_RTS_b/FTM0_CH1/UART1_TX/FTM3_CH1, direction: OUTPUT, gpio_init_state: 'false',
391 slew_rate: slow, pull_select: down, pull_enable: disable}
392 - {pin_num: '38', peripheral: GPIOB, signal: 'GPIO, 3', pin_signal: ADC1_SE2/ADC1_DP2/PTB3/I2C0_SDA/UART0_CTS_b/FTM0_FLT0, direction: INPUT, slew_rate: fast, pull_select: up,
393 pull_enable: enable}
394 - {pin_num: '37', peripheral: GPIOB, signal: 'GPIO, 2', pin_signal: ADC0_SE10/ADC1_SE10/ADC1_DM2/PTB2/I2C0_SCL/UART0_RTS_b/FTM0_FLT1/FTM0_FLT3, direction: INPUT,
395 slew_rate: fast, pull_select: up, pull_enable: enable}
396 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
397 */
398 /* clang-format on */
399
400 /* FUNCTION ************************************************************************************************************
401 *
402 * Function Name : BOARD_InitACCELPins
403 * Description : Configures pin routing and optionally pin electrical features.
404 *
405 * END ****************************************************************************************************************/
BOARD_InitACCELPins(void)406 void BOARD_InitACCELPins(void)
407 {
408 /* Port B Clock Gate Control: Clock enabled */
409 CLOCK_EnableClock(kCLOCK_PortB);
410 /* Port C Clock Gate Control: Clock enabled */
411 CLOCK_EnableClock(kCLOCK_PortC);
412 /* Port D Clock Gate Control: Clock enabled */
413 CLOCK_EnableClock(kCLOCK_PortD);
414
415 gpio_pin_config_t ACCEL_INT2_config = {
416 .pinDirection = kGPIO_DigitalInput,
417 .outputLogic = 0U
418 };
419 /* Initialize GPIO functionality on pin PTB2 (pin 37) */
420 GPIO_PinInit(BOARD_ACCEL_INT2_GPIO, BOARD_ACCEL_INT2_PIN, &ACCEL_INT2_config);
421
422 gpio_pin_config_t ACCEL_INT1_config = {
423 .pinDirection = kGPIO_DigitalInput,
424 .outputLogic = 0U
425 };
426 /* Initialize GPIO functionality on pin PTB3 (pin 38) */
427 GPIO_PinInit(BOARD_ACCEL_INT1_GPIO, BOARD_ACCEL_INT1_PIN, &ACCEL_INT1_config);
428
429 gpio_pin_config_t ACCEL_RST_config = {
430 .pinDirection = kGPIO_DigitalOutput,
431 .outputLogic = 0U
432 };
433 /* Initialize GPIO functionality on pin PTD1 (pin 58) */
434 GPIO_PinInit(BOARD_ACCEL_RST_GPIO, BOARD_ACCEL_RST_PIN, &ACCEL_RST_config);
435
436 const port_pin_config_t ACCEL_INT2 = {/* Internal pull-up resistor is enabled */
437 kPORT_PullUp,
438 /* Fast slew rate is configured */
439 kPORT_FastSlewRate,
440 /* Passive filter is disabled */
441 kPORT_PassiveFilterDisable,
442 /* Low drive strength is configured */
443 kPORT_LowDriveStrength,
444 /* Pin is configured as PTB2 */
445 kPORT_MuxAsGpio};
446 /* PORTB2 (pin 37) is configured as PTB2 */
447 PORT_SetPinConfig(BOARD_ACCEL_INT2_PORT, BOARD_ACCEL_INT2_PIN, &ACCEL_INT2);
448
449 const port_pin_config_t ACCEL_INT1 = {/* Internal pull-up resistor is enabled */
450 kPORT_PullUp,
451 /* Fast slew rate is configured */
452 kPORT_FastSlewRate,
453 /* Passive filter is disabled */
454 kPORT_PassiveFilterDisable,
455 /* Low drive strength is configured */
456 kPORT_LowDriveStrength,
457 /* Pin is configured as PTB3 */
458 kPORT_MuxAsGpio};
459 /* PORTB3 (pin 38) is configured as PTB3 */
460 PORT_SetPinConfig(BOARD_ACCEL_INT1_PORT, BOARD_ACCEL_INT1_PIN, &ACCEL_INT1);
461
462 const port_pin_config_t ACCEL_SCL = {/* Internal pull-up/down resistor is disabled */
463 kPORT_PullDisable,
464 /* Fast slew rate is configured */
465 kPORT_FastSlewRate,
466 /* Passive filter is disabled */
467 kPORT_PassiveFilterDisable,
468 /* Low drive strength is configured */
469 kPORT_LowDriveStrength,
470 /* Pin is configured as I2C0_SCL */
471 kPORT_MuxAlt7};
472 /* PORTC6 (pin 51) is configured as I2C0_SCL */
473 PORT_SetPinConfig(BOARD_ACCEL_SCL_PORT, BOARD_ACCEL_SCL_PIN, &ACCEL_SCL);
474
475 const port_pin_config_t ACCEL_SDA = {/* Internal pull-up/down resistor is disabled */
476 kPORT_PullDisable,
477 /* Fast slew rate is configured */
478 kPORT_FastSlewRate,
479 /* Passive filter is disabled */
480 kPORT_PassiveFilterDisable,
481 /* Low drive strength is configured */
482 kPORT_LowDriveStrength,
483 /* Pin is configured as I2C0_SDA */
484 kPORT_MuxAlt7};
485 /* PORTC7 (pin 52) is configured as I2C0_SDA */
486 PORT_SetPinConfig(BOARD_ACCEL_SDA_PORT, BOARD_ACCEL_SDA_PIN, &ACCEL_SDA);
487
488 const port_pin_config_t ACCEL_RST = {/* Internal pull-up/down resistor is disabled */
489 kPORT_PullDisable,
490 /* Slow slew rate is configured */
491 kPORT_SlowSlewRate,
492 /* Passive filter is disabled */
493 kPORT_PassiveFilterDisable,
494 /* Low drive strength is configured */
495 kPORT_LowDriveStrength,
496 /* Pin is configured as PTD1 */
497 kPORT_MuxAsGpio};
498 /* PORTD1 (pin 58) is configured as PTD1 */
499 PORT_SetPinConfig(BOARD_ACCEL_RST_PORT, BOARD_ACCEL_RST_PIN, &ACCEL_RST);
500 }
501
502 /* clang-format off */
503 /*
504 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
505 BOARD_InitThermistorPins:
506 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
507 - pin_list:
508 - {pin_num: '9', peripheral: ADC0, signal: 'DP, 0', pin_signal: ADC0_SE0/ADC0_DP0/PTE20/FTM1_CH0/UART0_TX, slew_rate: slow, pull_select: down, pull_enable: disable}
509 - {pin_num: '10', peripheral: ADC0, signal: 'DM, 0', pin_signal: ADC0_SE4/ADC0_DM0/PTE21/FTM1_CH1/UART0_RX, slew_rate: slow, pull_select: down, pull_enable: disable}
510 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
511 */
512 /* clang-format on */
513
514 /* FUNCTION ************************************************************************************************************
515 *
516 * Function Name : BOARD_InitThermistorPins
517 * Description : Configures pin routing and optionally pin electrical features.
518 *
519 * END ****************************************************************************************************************/
BOARD_InitThermistorPins(void)520 void BOARD_InitThermistorPins(void)
521 {
522 /* Port E Clock Gate Control: Clock enabled */
523 CLOCK_EnableClock(kCLOCK_PortE);
524
525 const port_pin_config_t ADC0_DP_THER = {/* Internal pull-up/down resistor is disabled */
526 kPORT_PullDisable,
527 /* Slow slew rate is configured */
528 kPORT_SlowSlewRate,
529 /* Passive filter is disabled */
530 kPORT_PassiveFilterDisable,
531 /* Low drive strength is configured */
532 kPORT_LowDriveStrength,
533 /* Pin is configured as ADC0_DP0 */
534 kPORT_PinDisabledOrAnalog};
535 /* PORTE20 (pin 9) is configured as ADC0_DP0 */
536 PORT_SetPinConfig(BOARD_ADC0_DP_THER_PORT, BOARD_ADC0_DP_THER_PIN, &ADC0_DP_THER);
537
538 const port_pin_config_t ADC0_DM_THER = {/* Internal pull-up/down resistor is disabled */
539 kPORT_PullDisable,
540 /* Slow slew rate is configured */
541 kPORT_SlowSlewRate,
542 /* Passive filter is disabled */
543 kPORT_PassiveFilterDisable,
544 /* Low drive strength is configured */
545 kPORT_LowDriveStrength,
546 /* Pin is configured as ADC0_DM0 */
547 kPORT_PinDisabledOrAnalog};
548 /* PORTE21 (pin 10) is configured as ADC0_DM0 */
549 PORT_SetPinConfig(BOARD_ADC0_DM_THER_PORT, BOARD_ADC0_DM_THER_PIN, &ADC0_DM_THER);
550 }
551
552 /* clang-format off */
553 /*
554 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
555 BOARD_InitCANPins:
556 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
557 - pin_list:
558 - {pin_num: '20', peripheral: CAN0, signal: TX, pin_signal: PTE24/CAN0_TX/FTM0_CH0/I2C0_SCL/EWM_OUT_b, slew_rate: fast, pull_select: down, pull_enable: disable}
559 - {pin_num: '21', peripheral: CAN0, signal: RX, pin_signal: PTE25/LLWU_P21/CAN0_RX/FTM0_CH1/I2C0_SDA/EWM_IN, identifier: CAN_RX, slew_rate: fast, pull_select: down,
560 pull_enable: disable}
561 - {pin_num: '29', peripheral: GPIOA, signal: 'GPIO, 13', pin_signal: PTA13/LLWU_P4/CAN0_RX/FTM1_CH1/FTM1_QD_PHB, direction: OUTPUT, gpio_init_state: 'false', slew_rate: slow,
562 pull_select: down, pull_enable: disable}
563 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
564 */
565 /* clang-format on */
566
567 /* FUNCTION ************************************************************************************************************
568 *
569 * Function Name : BOARD_InitCANPins
570 * Description : Configures pin routing and optionally pin electrical features.
571 *
572 * END ****************************************************************************************************************/
BOARD_InitCANPins(void)573 void BOARD_InitCANPins(void)
574 {
575 /* Port A Clock Gate Control: Clock enabled */
576 CLOCK_EnableClock(kCLOCK_PortA);
577 /* Port E Clock Gate Control: Clock enabled */
578 CLOCK_EnableClock(kCLOCK_PortE);
579
580 gpio_pin_config_t CAN_S_config = {
581 .pinDirection = kGPIO_DigitalOutput,
582 .outputLogic = 0U
583 };
584 /* Initialize GPIO functionality on pin PTA13 (pin 29) */
585 GPIO_PinInit(BOARD_CAN_S_GPIO, BOARD_CAN_S_PIN, &CAN_S_config);
586
587 const port_pin_config_t CAN_S = {/* Internal pull-up/down resistor is disabled */
588 kPORT_PullDisable,
589 /* Slow slew rate is configured */
590 kPORT_SlowSlewRate,
591 /* Passive filter is disabled */
592 kPORT_PassiveFilterDisable,
593 /* Low drive strength is configured */
594 kPORT_LowDriveStrength,
595 /* Pin is configured as PTA13 */
596 kPORT_MuxAsGpio};
597 /* PORTA13 (pin 29) is configured as PTA13 */
598 PORT_SetPinConfig(BOARD_CAN_S_PORT, BOARD_CAN_S_PIN, &CAN_S);
599
600 const port_pin_config_t CAN_TX = {/* Internal pull-up/down resistor is disabled */
601 kPORT_PullDisable,
602 /* Fast slew rate is configured */
603 kPORT_FastSlewRate,
604 /* Passive filter is disabled */
605 kPORT_PassiveFilterDisable,
606 /* Low drive strength is configured */
607 kPORT_LowDriveStrength,
608 /* Pin is configured as CAN0_TX */
609 kPORT_MuxAlt2};
610 /* PORTE24 (pin 20) is configured as CAN0_TX */
611 PORT_SetPinConfig(BOARD_CAN_TX_PORT, BOARD_CAN_TX_PIN, &CAN_TX);
612
613 const port_pin_config_t CAN_RX = {/* Internal pull-up/down resistor is disabled */
614 kPORT_PullDisable,
615 /* Fast slew rate is configured */
616 kPORT_FastSlewRate,
617 /* Passive filter is disabled */
618 kPORT_PassiveFilterDisable,
619 /* Low drive strength is configured */
620 kPORT_LowDriveStrength,
621 /* Pin is configured as CAN0_RX */
622 kPORT_MuxAlt2};
623 /* PORTE25 (pin 21) is configured as CAN0_RX */
624 PORT_SetPinConfig(BOARD_CAN_RX_PORT, BOARD_CAN_RX_PIN, &CAN_RX);
625 }
626 /***********************************************************************************************************************
627 * EOF
628 **********************************************************************************************************************/
629
