1 /* 2 * Copyright 2018-2019 NXP. 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _PIN_MUX_H_ 9 #define _PIN_MUX_H_ 10 11 /*! 12 * @addtogroup pin_mux 13 * @{ 14 */ 15 16 /*********************************************************************************************************************** 17 * API 18 **********************************************************************************************************************/ 19 20 #if defined(__cplusplus) 21 extern "C" { 22 #endif 23 24 /*! 25 * @brief Calls initialization functions. 26 * 27 */ 28 void BOARD_InitBootPins(void); 29 30 /*! @name PORTA2 (coord K6), J9[6]/JTAG_TDO/TRACE_SWO/EZP_DO 31 @{ */ 32 #define BOARD_TRACE_SWO_PORT PORTA /*!<@brief PORT device name: PORTA */ 33 #define BOARD_TRACE_SWO_PIN 2U /*!<@brief PORTA pin index: 2 */ 34 /* @} */ 35 36 /*! 37 * @brief Configures pin routing and optionally pin electrical features. 38 * 39 */ 40 void BOARD_InitPins(void); 41 42 /*! @name PORTD11 (coord B2), SW2 43 @{ */ 44 #define BOARD_SW2_GPIO GPIOD /*!<@brief GPIO device name: GPIOD */ 45 #define BOARD_SW2_PORT PORTD /*!<@brief PORT device name: PORTD */ 46 #define BOARD_SW2_PIN 11U /*!<@brief PORTD pin index: 11 */ 47 /* @} */ 48 49 /*! @name PORTA10 (coord M9), SW3 50 @{ */ 51 #define BOARD_SW3_GPIO GPIOA /*!<@brief GPIO device name: GPIOA */ 52 #define BOARD_SW3_PORT PORTA /*!<@brief PORT device name: PORTA */ 53 #define BOARD_SW3_PIN 10U /*!<@brief PORTA pin index: 10 */ 54 /* @} */ 55 56 /*! 57 * @brief Configures pin routing and optionally pin electrical features. 58 * 59 */ 60 void BOARD_InitBUTTONsPins(void); 61 62 /*! @name PORTA11 (coord L9), LEDRGB_BLUE 63 @{ */ 64 #define BOARD_LED_BLUE_GPIO GPIOA /*!<@brief GPIO device name: GPIOA */ 65 #define BOARD_LED_BLUE_PORT PORTA /*!<@brief PORT device name: PORTA */ 66 #define BOARD_LED_BLUE_PIN 11U /*!<@brief PORTA pin index: 11 */ 67 /* @} */ 68 69 /*! @name PORTE6 (coord E1), LEDRGB_GREEN 70 @{ */ 71 #define BOARD_LED_GREEN_GPIO GPIOE /*!<@brief GPIO device name: GPIOE */ 72 #define BOARD_LED_GREEN_PORT PORTE /*!<@brief PORT device name: PORTE */ 73 #define BOARD_LED_GREEN_PIN 6U /*!<@brief PORTE pin index: 6 */ 74 /* @} */ 75 76 /*! @name PORTC9 (coord D7), LEDRGB_RED 77 @{ */ 78 #define BOARD_LED_RED_GPIO GPIOC /*!<@brief GPIO device name: GPIOC */ 79 #define BOARD_LED_RED_PORT PORTC /*!<@brief PORT device name: PORTC */ 80 #define BOARD_LED_RED_PIN 9U /*!<@brief PORTC pin index: 9 */ 81 /* @} */ 82 83 /*! 84 * @brief Configures pin routing and optionally pin electrical features. 85 * 86 */ 87 void BOARD_InitLEDsPins(void); 88 89 #define PORT_DFER_DFE_8_MASK 0x0100u /*!<@brief Digital Filter Enable Mask for item 8. */ 90 #define PORT_DFER_DFE_9_MASK 0x0200u /*!<@brief Digital Filter Enable Mask for item 9. */ 91 92 /*! @name PORTD8 (coord C9), U8[4]/U19[11]/I2C0_SCL 93 @{ */ 94 #define BOARD_ACCEL_SCL_PORT PORTD /*!<@brief PORT device name: PORTD */ 95 #define BOARD_ACCEL_SCL_PIN 8U /*!<@brief PORTD pin index: 8 */ 96 /* @} */ 97 98 /*! @name PORTD9 (coord B9), U8[6]/U19[12]/I2C0_SDA 99 @{ */ 100 #define BOARD_ACCEL_SDA_PORT PORTD /*!<@brief PORT device name: PORTD */ 101 #define BOARD_ACCEL_SDA_PIN 9U /*!<@brief PORTD pin index: 9 */ 102 /* @} */ 103 104 /*! @name PORTC17 (coord D5), U8[11]/FXOS8700CQ_INT1 105 @{ */ 106 #define BOARD_ACCEL_INT1_GPIO GPIOC /*!<@brief GPIO device name: GPIOC */ 107 #define BOARD_ACCEL_INT1_PORT PORTC /*!<@brief PORT device name: PORTC */ 108 #define BOARD_ACCEL_INT1_PIN 17U /*!<@brief PORTC pin index: 17 */ 109 /* @} */ 110 111 /*! @name PORTC13 (coord D6), U8[9]/FXOS8700CQ_INT2 112 @{ */ 113 #define BOARD_ACCEL_INT2_GPIO GPIOC /*!<@brief GPIO device name: GPIOC */ 114 #define BOARD_ACCEL_INT2_PORT PORTC /*!<@brief PORT device name: PORTC */ 115 #define BOARD_ACCEL_INT2_PIN 13U /*!<@brief PORTC pin index: 13 */ 116 /* @} */ 117 118 /*! 119 * @brief Configures pin routing and optionally pin electrical features. 120 * 121 */ 122 void BOARD_InitACCEL_I2CPins(void); 123 124 #define PORT_DFER_DFE_8_MASK 0x0100u /*!<@brief Digital Filter Enable Mask for item 8. */ 125 #define PORT_DFER_DFE_9_MASK 0x0200u /*!<@brief Digital Filter Enable Mask for item 9. */ 126 127 /*! @name PORTD9 (coord B9), U8[6]/U19[12]/I2C0_SDA 128 @{ */ 129 #define BOARD_GYRO_SDA_PORT PORTD /*!<@brief PORT device name: PORTD */ 130 #define BOARD_GYRO_SDA_PIN 9U /*!<@brief PORTD pin index: 9 */ 131 /* @} */ 132 133 /*! @name PORTD8 (coord C9), U8[4]/U19[11]/I2C0_SCL 134 @{ */ 135 #define BOARD_GYRO_SCL_PORT PORTD /*!<@brief PORT device name: PORTD */ 136 #define BOARD_GYRO_SCL_PIN 8U /*!<@brief PORTD pin index: 8 */ 137 /* @} */ 138 139 /*! @name PORTA29 (coord H11), U19[3]/FXAS21002_INT1 140 @{ */ 141 #define BOARD_GYRO_INT1_GPIO GPIOA /*!<@brief GPIO device name: GPIOA */ 142 #define BOARD_GYRO_INT1_PORT PORTA /*!<@brief PORT device name: PORTA */ 143 #define BOARD_GYRO_INT1_PIN 29U /*!<@brief PORTA pin index: 29 */ 144 /* @} */ 145 146 /*! @name PORTA28 (coord H12), U19[2]/FXAS21002_INT2 147 @{ */ 148 #define BOARD_GYRO_INT2_GPIO GPIOA /*!<@brief GPIO device name: GPIOA */ 149 #define BOARD_GYRO_INT2_PORT PORTA /*!<@brief PORT device name: PORTA */ 150 #define BOARD_GYRO_INT2_PIN 28U /*!<@brief PORTA pin index: 28 */ 151 /* @} */ 152 153 /*! 154 * @brief Configures pin routing and optionally pin electrical features. 155 * 156 */ 157 void BOARD_InitGYRO_I2CPins(void); 158 159 #define SOPT5_UART0TXSRC_UART_TX 0x00u /*!<@brief UART 0 transmit data source select: UART0_TX pin */ 160 161 /*! @name PORTB16 (coord E10), U7[4]/UART0_RX 162 @{ */ 163 #define BOARD_DEBUG_UART_RX_PORT PORTB /*!<@brief PORT device name: PORTB */ 164 #define BOARD_DEBUG_UART_RX_PIN 16U /*!<@brief PORTB pin index: 16 */ 165 /* @} */ 166 167 /*! @name PORTB17 (coord E9), U10[1]/UART0_TX 168 @{ */ 169 #define BOARD_DEBUG_UART_TX_PORT PORTB /*!<@brief PORT device name: PORTB */ 170 #define BOARD_DEBUG_UART_TX_PIN 17U /*!<@brief PORTB pin index: 17 */ 171 /* @} */ 172 173 /*! 174 * @brief Configures pin routing and optionally pin electrical features. 175 * 176 */ 177 void BOARD_InitDEBUG_UARTPins(void); 178 179 #define PORT_DFER_DFE_10_MASK 0x0400u /*!<@brief Digital Filter Enable Mask for item 10. */ 180 181 /*! @name PORTE3 (coord E4), SDHC0_CMD 182 @{ */ 183 #define BOARD_SDHC0_CMD_PORT PORTE /*!<@brief PORT device name: PORTE */ 184 #define BOARD_SDHC0_CMD_PIN 3U /*!<@brief PORTE pin index: 3 */ 185 /* @} */ 186 187 /*! @name PORTE1 (coord D2), SDHC0_D0 188 @{ */ 189 #define BOARD_SDHC0_D0_PORT PORTE /*!<@brief PORT device name: PORTE */ 190 #define BOARD_SDHC0_D0_PIN 1U /*!<@brief PORTE pin index: 1 */ 191 /* @} */ 192 193 /*! @name PORTE0 (coord D3), SDHC0_D1 194 @{ */ 195 #define BOARD_SDHC0_D1_PORT PORTE /*!<@brief PORT device name: PORTE */ 196 #define BOARD_SDHC0_D1_PIN 0U /*!<@brief PORTE pin index: 0 */ 197 /* @} */ 198 199 /*! @name PORTE5 (coord E2), SDHC0_D2 200 @{ */ 201 #define BOARD_SDHC0_D2_PORT PORTE /*!<@brief PORT device name: PORTE */ 202 #define BOARD_SDHC0_D2_PIN 5U /*!<@brief PORTE pin index: 5 */ 203 /* @} */ 204 205 /*! @name PORTE4 (coord E3), SDHC0_D3 206 @{ */ 207 #define BOARD_SDHC0_D3_PORT PORTE /*!<@brief PORT device name: PORTE */ 208 #define BOARD_SDHC0_D3_PIN 4U /*!<@brief PORTE pin index: 4 */ 209 /* @} */ 210 211 /*! @name PORTE2 (coord D1), SDHC0_DCLK 212 @{ */ 213 #define BOARD_SDHC0_DCLK_PORT PORTE /*!<@brief PORT device name: PORTE */ 214 #define BOARD_SDHC0_DCLK_PIN 2U /*!<@brief PORTE pin index: 2 */ 215 /* @} */ 216 217 /*! @name PORTD10 (coord B3), SD_CARD_DETECT 218 @{ */ 219 #define BOARD_SDCARD_CARD_DETECTION_GPIO GPIOD /*!<@brief GPIO device name: GPIOD */ 220 #define BOARD_SDCARD_CARD_DETECTION_PORT PORTD /*!<@brief PORT device name: PORTD */ 221 #define BOARD_SDCARD_CARD_DETECTION_PIN 10U /*!<@brief PORTD pin index: 10 */ 222 /* @} */ 223 224 /*! 225 * @brief Configures pin routing and optionally pin electrical features. 226 * 227 */ 228 void BOARD_InitSDHC0Pins(void); 229 230 #define SOPT2_RMIISRC_ENET 0x01u /*!<@brief RMII clock source select: External bypass clock (ENET_1588_CLKIN). */ 231 232 /*! @name PORTE26 (coord K4), U13[16]/ETHERNET_CLOCK 233 @{ */ 234 #define BOARD_ETHERNET_CLOCK_PORT PORTE /*!<@brief PORT device name: PORTE */ 235 #define BOARD_ETHERNET_CLOCK_PIN 26U /*!<@brief PORTE pin index: 26 */ 236 /* @} */ 237 238 /*! @name PORTA14 (coord L10), U13[15]/RMII0_CRS_DV 239 @{ */ 240 #define BOARD_RMII0_CRS_DV_PORT PORTA /*!<@brief PORT device name: PORTA */ 241 #define BOARD_RMII0_CRS_DV_PIN 14U /*!<@brief PORTA pin index: 14 */ 242 /* @} */ 243 244 /*! @name PORTB1 (coord H9), U13[11]/RMII0_MDC 245 @{ */ 246 #define BOARD_RMII0_MDC_PORT PORTB /*!<@brief PORT device name: PORTB */ 247 #define BOARD_RMII0_MDC_PIN 1U /*!<@brief PORTB pin index: 1 */ 248 /* @} */ 249 250 /*! @name PORTB0 (coord H10), U13[10]/RMII0_MDIO 251 @{ */ 252 #define BOARD_RMII0_MDIO_PORT PORTB /*!<@brief PORT device name: PORTB */ 253 #define BOARD_RMII0_MDIO_PIN 0U /*!<@brief PORTB pin index: 0 */ 254 /* @} */ 255 256 /*! @name PORTA13 (coord J9), U13[13]/RMII0_RXD0 257 @{ */ 258 #define BOARD_RMII0_RXD0_PORT PORTA /*!<@brief PORT device name: PORTA */ 259 #define BOARD_RMII0_RXD0_PIN 13U /*!<@brief PORTA pin index: 13 */ 260 /* @} */ 261 262 /*! @name PORTA12 (coord K9), U13[12]/RMII0_RXD1 263 @{ */ 264 #define BOARD_RMII0_RXD1_PORT PORTA /*!<@brief PORT device name: PORTA */ 265 #define BOARD_RMII0_RXD1_PIN 12U /*!<@brief PORTA pin index: 12 */ 266 /* @} */ 267 268 /*! @name PORTA5 (coord M8), U13[17]/RMII0_RXER 269 @{ */ 270 #define BOARD_RMII0_RXER_PORT PORTA /*!<@brief PORT device name: PORTA */ 271 #define BOARD_RMII0_RXER_PIN 5U /*!<@brief PORTA pin index: 5 */ 272 /* @} */ 273 274 /*! @name PORTA16 (coord K10), U13[20]/RMII0_TXD_0 275 @{ */ 276 #define BOARD_RMII0_TXD_0_PORT PORTA /*!<@brief PORT device name: PORTA */ 277 #define BOARD_RMII0_TXD_0_PIN 16U /*!<@brief PORTA pin index: 16 */ 278 /* @} */ 279 280 /*! @name PORTA17 (coord K11), U13[21]/RMII0_TXD_1 281 @{ */ 282 #define BOARD_RMII0_TXD_1_PORT PORTA /*!<@brief PORT device name: PORTA */ 283 #define BOARD_RMII0_TXD_1_PIN 17U /*!<@brief PORTA pin index: 17 */ 284 /* @} */ 285 286 /*! @name PORTA15 (coord L11), U13[19]/RMII0_TXEN 287 @{ */ 288 #define BOARD_RMII0_TXEN_PORT PORTA /*!<@brief PORT device name: PORTA */ 289 #define BOARD_RMII0_TXEN_PIN 15U /*!<@brief PORTA pin index: 15 */ 290 /* @} */ 291 292 /*! @name PORTE26 (coord K4), U13[16]/ETHERNET_CLOCK 293 @{ */ 294 #define BOARD_ENET_1588_CLKIN_PORT PORTE /*!<@brief PORT device name: PORTE */ 295 #define BOARD_ENET_1588_CLKIN_PIN 26U /*!<@brief PORTE pin index: 26 */ 296 /* @} */ 297 298 /*! 299 * @brief Configures pin routing and optionally pin electrical features. 300 * 301 */ 302 void BOARD_InitENETPins(void); 303 304 /*! @name USB1_DM (coord K1), K66_MICRO_USB_DN 305 @{ */ 306 /* @} */ 307 308 /*! @name USB1_DP (coord J1), K66_MICRO_USB_DP 309 @{ */ 310 /* @} */ 311 312 /*! @name PORTE10 (coord F1), USB_ID 313 @{ */ 314 #define BOARD_USB_ID_PORT PORTE /*!<@brief PORT device name: PORTE */ 315 #define BOARD_USB_ID_PIN 10U /*!<@brief PORTE pin index: 10 */ 316 /* @} */ 317 318 /*! @name USB1_VBUS (coord L1), P5V_K66_USB 319 @{ */ 320 /* @} */ 321 322 /*! 323 * @brief Configures pin routing and optionally pin electrical features. 324 * 325 */ 326 void BOARD_InitUSBPins(void); 327 328 /*! @name PORTA18 (coord M12), EXTAL0 329 @{ */ 330 #define BOARD_EXTAL0_PORT PORTA /*!<@brief PORT device name: PORTA */ 331 #define BOARD_EXTAL0_PIN 18U /*!<@brief PORTA pin index: 18 */ 332 /* @} */ 333 334 /*! @name PORTA19 (coord M11), X501[3] 335 @{ */ 336 #define BOARD_XTAL0_PORT PORTA /*!<@brief PORT device name: PORTA */ 337 #define BOARD_XTAL0_PIN 19U /*!<@brief PORTA pin index: 19 */ 338 /* @} */ 339 340 /*! @name EXTAL32 (coord M6), Y3[2] 341 @{ */ 342 /* @} */ 343 344 /*! @name XTAL32 (coord M7), Y3[1] 345 @{ */ 346 /* @} */ 347 348 /*! 349 * @brief Configures pin routing and optionally pin electrical features. 350 * 351 */ 352 void BOARD_InitOSCsPins(void); 353 354 #if defined(__cplusplus) 355 } 356 #endif 357 358 /*! 359 * @} 360 */ 361 #endif /* _PIN_MUX_H_ */ 362 363 /*********************************************************************************************************************** 364 * EOF 365 **********************************************************************************************************************/ 366