1 /*
2 * Copyright 2022-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /*
8 * How to setup clock using clock driver functions:
9 *
10 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
11 *
12 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
13 *
14 * 3. Call CLOCK_SetRootClock() to configure corresponding module clock source and divider.
15 *
16 */
17
18 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
19 !!GlobalInfo
20 product: Clocks v11.0
21 processor: MIMXRT1166xxxxx
22 package_id: MIMXRT1166DVM6A
23 mcu_data: ksdk2_0
24 processor_version: 0.0.0
25 board: MIMXRT1160-EVK
26 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
27
28 #include "clock_config.h"
29 #include "fsl_iomuxc.h"
30 #include "fsl_dcdc.h"
31 #include "fsl_pmu.h"
32 #include "fsl_clock.h"
33
34 /*******************************************************************************
35 * Definitions
36 ******************************************************************************/
37
38 /*******************************************************************************
39 * Variables
40 ******************************************************************************/
41
42 /*******************************************************************************
43 ************************ BOARD_InitBootClocks function ************************
44 ******************************************************************************/
BOARD_InitBootClocks(void)45 void BOARD_InitBootClocks(void)
46 {
47 BOARD_BootClockRUN();
48 }
49
50 #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
51 #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
52 /* This function should not run from SDRAM since it will change SEMC configuration. */
53 AT_QUICKACCESS_SECTION_CODE(void UpdateSemcClock(void));
UpdateSemcClock(void)54 void UpdateSemcClock(void)
55 {
56 /* Enable self-refresh mode and update semc clock root to 200MHz. */
57 SEMC->IPCMD = 0xA55A000D;
58 while ((SEMC->INTR & 0x3) == 0)
59 ;
60 SEMC->INTR = 0x3;
61 SEMC->DCCR = 0x0B;
62 /*
63 * Currently we are using SEMC parameter which fit both 166MHz and 200MHz, only
64 * need to change the SEMC clock root here. If customer is using their own DCD and
65 * want to switch from 166MHz to 200MHz, extra SEMC configuration might need to be
66 * adjusted here to fine tune the SDRAM performance
67 */
68 CCM->CLOCK_ROOT[kCLOCK_Root_Semc].CONTROL = 0x602;
69 }
70 #endif
71 #endif
72
73 /*******************************************************************************
74 ********************** Configuration BOARD_BootClockRUN ***********************
75 ******************************************************************************/
76 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
77 !!Configuration
78 name: BOARD_BootClockRUN
79 called_from_default_init: true
80 outputs:
81 - {id: ACMP_CLK_ROOT.outFreq, value: 24 MHz}
82 - {id: ADC1_CLK_ROOT.outFreq, value: 24 MHz}
83 - {id: ADC2_CLK_ROOT.outFreq, value: 24 MHz}
84 - {id: ARM_PLL_CLK.outFreq, value: 600 MHz}
85 - {id: ASRC_CLK_ROOT.outFreq, value: 24 MHz}
86 - {id: AXI_CLK_ROOT.outFreq, value: 600 MHz}
87 - {id: BUS_CLK_ROOT.outFreq, value: 198 MHz}
88 - {id: BUS_LPSR_CLK_ROOT.outFreq, value: 120 MHz}
89 - {id: CAN1_CLK_ROOT.outFreq, value: 24 MHz}
90 - {id: CAN2_CLK_ROOT.outFreq, value: 24 MHz}
91 - {id: CAN3_CLK_ROOT.outFreq, value: 24 MHz}
92 - {id: CCM_CLKO1_CLK_ROOT.outFreq, value: 24 MHz}
93 - {id: CCM_CLKO2_CLK_ROOT.outFreq, value: 24 MHz}
94 - {id: CLK_1M.outFreq, value: 1 MHz}
95 - {id: CSI2_CLK_ROOT.outFreq, value: 24 MHz}
96 - {id: CSI2_ESC_CLK_ROOT.outFreq, value: 24 MHz}
97 - {id: CSI2_UI_CLK_ROOT.outFreq, value: 24 MHz}
98 - {id: CSI_CLK_ROOT.outFreq, value: 24 MHz}
99 - {id: CSSYS_CLK_ROOT.outFreq, value: 24 MHz}
100 - {id: CSTRACE_CLK_ROOT.outFreq, value: 132 MHz}
101 - {id: ELCDIF_CLK_ROOT.outFreq, value: 24 MHz}
102 - {id: EMV1_CLK_ROOT.outFreq, value: 24 MHz}
103 - {id: EMV2_CLK_ROOT.outFreq, value: 24 MHz}
104 - {id: ENET1_CLK_ROOT.outFreq, value: 24 MHz}
105 - {id: ENET2_CLK_ROOT.outFreq, value: 24 MHz}
106 - {id: ENET_1G_TX_CLK.outFreq, value: 24 MHz}
107 - {id: ENET_25M_CLK_ROOT.outFreq, value: 24 MHz}
108 - {id: ENET_TIMER1_CLK_ROOT.outFreq, value: 24 MHz}
109 - {id: ENET_TIMER2_CLK_ROOT.outFreq, value: 24 MHz}
110 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 24 MHz}
111 - {id: FLEXIO2_CLK_ROOT.outFreq, value: 24 MHz}
112 - {id: FLEXSPI1_CLK_ROOT.outFreq, value: 24 MHz}
113 - {id: FLEXSPI2_CLK_ROOT.outFreq, value: 24 MHz}
114 - {id: GC355_CLK_ROOT.outFreq, value: 492.0000125 MHz}
115 - {id: GPT1_CLK_ROOT.outFreq, value: 24 MHz}
116 - {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz}
117 - {id: GPT2_CLK_ROOT.outFreq, value: 24 MHz}
118 - {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz}
119 - {id: GPT3_CLK_ROOT.outFreq, value: 24 MHz}
120 - {id: GPT3_ipg_clk_highfreq.outFreq, value: 24 MHz}
121 - {id: GPT4_CLK_ROOT.outFreq, value: 24 MHz}
122 - {id: GPT4_ipg_clk_highfreq.outFreq, value: 24 MHz}
123 - {id: GPT5_CLK_ROOT.outFreq, value: 24 MHz}
124 - {id: GPT5_ipg_clk_highfreq.outFreq, value: 24 MHz}
125 - {id: GPT6_CLK_ROOT.outFreq, value: 24 MHz}
126 - {id: GPT6_ipg_clk_highfreq.outFreq, value: 24 MHz}
127 - {id: LCDIFV2_CLK_ROOT.outFreq, value: 24 MHz}
128 - {id: LPI2C1_CLK_ROOT.outFreq, value: 24 MHz}
129 - {id: LPI2C2_CLK_ROOT.outFreq, value: 24 MHz}
130 - {id: LPI2C3_CLK_ROOT.outFreq, value: 24 MHz}
131 - {id: LPI2C4_CLK_ROOT.outFreq, value: 24 MHz}
132 - {id: LPI2C5_CLK_ROOT.outFreq, value: 24 MHz}
133 - {id: LPI2C6_CLK_ROOT.outFreq, value: 24 MHz}
134 - {id: LPSPI1_CLK_ROOT.outFreq, value: 24 MHz}
135 - {id: LPSPI2_CLK_ROOT.outFreq, value: 24 MHz}
136 - {id: LPSPI3_CLK_ROOT.outFreq, value: 24 MHz}
137 - {id: LPSPI4_CLK_ROOT.outFreq, value: 24 MHz}
138 - {id: LPSPI5_CLK_ROOT.outFreq, value: 24 MHz}
139 - {id: LPSPI6_CLK_ROOT.outFreq, value: 24 MHz}
140 - {id: LPUART10_CLK_ROOT.outFreq, value: 24 MHz}
141 - {id: LPUART11_CLK_ROOT.outFreq, value: 24 MHz}
142 - {id: LPUART12_CLK_ROOT.outFreq, value: 24 MHz}
143 - {id: LPUART1_CLK_ROOT.outFreq, value: 24 MHz}
144 - {id: LPUART2_CLK_ROOT.outFreq, value: 24 MHz}
145 - {id: LPUART3_CLK_ROOT.outFreq, value: 24 MHz}
146 - {id: LPUART4_CLK_ROOT.outFreq, value: 24 MHz}
147 - {id: LPUART5_CLK_ROOT.outFreq, value: 24 MHz}
148 - {id: LPUART6_CLK_ROOT.outFreq, value: 24 MHz}
149 - {id: LPUART7_CLK_ROOT.outFreq, value: 24 MHz}
150 - {id: LPUART8_CLK_ROOT.outFreq, value: 24 MHz}
151 - {id: LPUART9_CLK_ROOT.outFreq, value: 24 MHz}
152 - {id: M4_CLK_ROOT.outFreq, value: 240 MHz}
153 - {id: M4_SYSTICK_CLK_ROOT.outFreq, value: 24 MHz}
154 - {id: M7_CLK_ROOT.outFreq, value: 600 MHz}
155 - {id: M7_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz}
156 - {id: MIC_CLK_ROOT.outFreq, value: 24 MHz}
157 - {id: MIPI_DSI_TX_CLK_ESC_ROOT.outFreq, value: 24 MHz}
158 - {id: MIPI_ESC_CLK_ROOT.outFreq, value: 24 MHz}
159 - {id: MIPI_REF_CLK_ROOT.outFreq, value: 24 MHz}
160 - {id: MQS_CLK_ROOT.outFreq, value: 24 MHz}
161 - {id: MQS_MCLK.outFreq, value: 24 MHz}
162 - {id: OSC_24M.outFreq, value: 24 MHz}
163 - {id: OSC_32K.outFreq, value: 32.768 kHz}
164 - {id: OSC_RC_16M.outFreq, value: 16 MHz}
165 - {id: OSC_RC_400M.outFreq, value: 400 MHz}
166 - {id: OSC_RC_48M.outFreq, value: 48 MHz}
167 - {id: OSC_RC_48M_DIV2.outFreq, value: 24 MHz}
168 - {id: PLL_VIDEO_CLK.outFreq, value: 984.000025 MHz}
169 - {id: SAI1_CLK_ROOT.outFreq, value: 24 MHz}
170 - {id: SAI1_MCLK1.outFreq, value: 24 MHz}
171 - {id: SAI1_MCLK3.outFreq, value: 24 MHz}
172 - {id: SAI2_CLK_ROOT.outFreq, value: 24 MHz}
173 - {id: SAI2_MCLK1.outFreq, value: 24 MHz}
174 - {id: SAI2_MCLK3.outFreq, value: 24 MHz}
175 - {id: SAI3_CLK_ROOT.outFreq, value: 24 MHz}
176 - {id: SAI3_MCLK1.outFreq, value: 24 MHz}
177 - {id: SAI3_MCLK3.outFreq, value: 24 MHz}
178 - {id: SAI4_CLK_ROOT.outFreq, value: 24 MHz}
179 - {id: SAI4_MCLK1.outFreq, value: 24 MHz}
180 - {id: SEMC_CLK_ROOT.outFreq, value: 198 MHz}
181 - {id: SPDIF_CLK_ROOT.outFreq, value: 24 MHz}
182 - {id: SYS_PLL2_CLK.outFreq, value: 528 MHz}
183 - {id: SYS_PLL2_PFD0_CLK.outFreq, value: 352 MHz}
184 - {id: SYS_PLL2_PFD1_CLK.outFreq, value: 594 MHz}
185 - {id: SYS_PLL2_PFD2_CLK.outFreq, value: 396 MHz}
186 - {id: SYS_PLL2_PFD3_CLK.outFreq, value: 396 MHz}
187 - {id: SYS_PLL3_CLK.outFreq, value: 480 MHz}
188 - {id: SYS_PLL3_DIV2_CLK.outFreq, value: 240 MHz}
189 - {id: SYS_PLL3_PFD0_CLK.outFreq, value: 8640/13 MHz}
190 - {id: SYS_PLL3_PFD1_CLK.outFreq, value: 8640/17 MHz}
191 - {id: SYS_PLL3_PFD2_CLK.outFreq, value: 270 MHz}
192 - {id: SYS_PLL3_PFD3_CLK.outFreq, value: 4320/11 MHz}
193 - {id: USDHC1_CLK_ROOT.outFreq, value: 24 MHz}
194 - {id: USDHC2_CLK_ROOT.outFreq, value: 24 MHz}
195 settings:
196 - {id: CoreBusClockRootsInitializationConfig, value: selectedCore}
197 - {id: ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG, value: Low}
198 - {id: ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG, value: Enabled}
199 - {id: ANADIG_PLL.ARM_PLL_POST_DIV.scale, value: '4'}
200 - {id: ANADIG_PLL.ARM_PLL_PREDIV.scale, value: '1', locked: true}
201 - {id: ANADIG_PLL.ARM_PLL_VDIV.scale, value: '200', locked: true}
202 - {id: ANADIG_PLL.PLL_AUDIO_BYPASS.sel, value: ANADIG_OSC.OSC_24M}
203 - {id: ANADIG_PLL.PLL_VIDEO.denom, value: '960000'}
204 - {id: ANADIG_PLL.PLL_VIDEO.div, value: '41'}
205 - {id: ANADIG_PLL.PLL_VIDEO.num, value: '1'}
206 - {id: ANADIG_PLL.SYS_PLL1_BYPASS.sel, value: ANADIG_OSC.OSC_24M}
207 - {id: ANADIG_PLL.SYS_PLL2.denom, value: '268435455'}
208 - {id: ANADIG_PLL.SYS_PLL2.div, value: '22'}
209 - {id: ANADIG_PLL.SYS_PLL2.num, value: '0'}
210 - {id: ANADIG_PLL.SYS_PLL2_PFD3_DIV.scale, value: '24'}
211 - {id: ANADIG_PLL.SYS_PLL2_SS_DIV.scale, value: '268435455'}
212 - {id: ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale, value: '22', locked: true}
213 - {id: ANADIG_PLL.SYS_PLL3_PFD3_MUL.scale, value: '18', locked: true}
214 - {id: ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG, value: Enabled}
215 - {id: ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG, value: Disabled}
216 - {id: ANADIG_PLL_PLL_VIDEO_CTRL0_POWERUP_CFG, value: Enabled}
217 - {id: ANADIG_PLL_SYS_PLL1_CTRL0_POWERUP_CFG, value: Disabled}
218 - {id: ANADIG_PLL_SYS_PLL1_CTRL_GATE_CFG, value: Disabled}
219 - {id: ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG, value: Enabled}
220 - {id: ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG, value: Enabled}
221 - {id: ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG, value: Enabled}
222 - {id: CCM.CLOCK_ROOT0.MUX.sel, value: ANADIG_PLL.ARM_PLL_CLK}
223 - {id: CCM.CLOCK_ROOT1.DIV.scale, value: '2'}
224 - {id: CCM.CLOCK_ROOT1.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
225 - {id: CCM.CLOCK_ROOT2.DIV.scale, value: '2'}
226 - {id: CCM.CLOCK_ROOT2.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD3_CLK}
227 - {id: CCM.CLOCK_ROOT25.DIV.scale, value: '22'}
228 - {id: CCM.CLOCK_ROOT25.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
229 - {id: CCM.CLOCK_ROOT26.DIV.scale, value: '22'}
230 - {id: CCM.CLOCK_ROOT26.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
231 - {id: CCM.CLOCK_ROOT3.DIV.scale, value: '4'}
232 - {id: CCM.CLOCK_ROOT3.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
233 - {id: CCM.CLOCK_ROOT4.DIV.scale, value: '3'}
234 - {id: CCM.CLOCK_ROOT4.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD1_CLK}
235 - {id: CCM.CLOCK_ROOT6.DIV.scale, value: '4'}
236 - {id: CCM.CLOCK_ROOT6.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
237 - {id: CCM.CLOCK_ROOT68.DIV.scale, value: '2'}
238 - {id: CCM.CLOCK_ROOT68.MUX.sel, value: ANADIG_PLL.PLL_VIDEO_CLK}
239 - {id: CCM.CLOCK_ROOT8.DIV.scale, value: '240'}
240 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
241
242 /*******************************************************************************
243 * Variables for BOARD_BootClockRUN configuration
244 ******************************************************************************/
245
246 #if __CORTEX_M == 7
247 #define BYPASS_LDO_LPSR 1
248 #endif
249
250 const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
251 {
252 .postDivider = kCLOCK_PllPostDiv4, /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */
253 .loopDivider = 200, /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */
254 };
255
256 const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN =
257 {
258 .mfd = 268435455, /* Denominator of spread spectrum */
259 .ss = NULL, /* Spread spectrum parameter */
260 .ssEnable = false, /* Enable spread spectrum or not */
261 };
262
263 const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
264 {
265 .loopDivider = 41, /* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */
266 .postDivider = 0, /* Divider after PLL, should only be 1, 2, 4, 8, 16, 32 */
267 .numerator = 1, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
268 .denominator = 960000, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
269 .ss = NULL, /* Spread spectrum parameter */
270 .ssEnable = false, /* Enable spread spectrum or not */
271 };
272
273 /*******************************************************************************
274 * Code for BOARD_BootClockRUN configuration
275 ******************************************************************************/
BOARD_BootClockRUN(void)276 void BOARD_BootClockRUN(void)
277 {
278 clock_root_config_t rootCfg = {0};
279
280 /* Set DCDC to DCM mode to improve the efficiency for light loading in run mode and transient performance with a big loading step. */
281 DCDC_BootIntoDCM(DCDC);
282
283 #if defined(BYPASS_LDO_LPSR) && BYPASS_LDO_LPSR
284 PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, true);
285 PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS, true);
286 #endif
287
288 /* Config CLK_1M */
289 CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz);
290
291 /* Init OSC RC 16M */
292 ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK;
293
294 /* Init OSC RC 400M */
295 CLOCK_OSC_EnableOscRc400M();
296 CLOCK_OSC_GateOscRc400M(false);
297
298 /* Init OSC RC 48M */
299 CLOCK_OSC_EnableOsc48M(true);
300 CLOCK_OSC_EnableOsc48MDiv2(true);
301
302 /* Config OSC 24M */
303 ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0);
304 /* Wait for 24M OSC to be stable. */
305 while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK !=
306 (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK))
307 {
308 }
309
310 /* Switch both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */
311 #if __CORTEX_M == 7
312 rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2;
313 rootCfg.div = 1;
314 CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
315
316 rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
317 rootCfg.div = 1;
318 CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
319 #endif
320
321 #if __CORTEX_M == 4
322 rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2;
323 rootCfg.div = 1;
324 CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
325
326 rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2;
327 rootCfg.div = 1;
328 CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
329 #endif
330
331 /*
332 * if DCD is used, please make sure the clock source of SEMC is not changed in the following PLL/PFD configuration code.
333 */
334 /* Init Arm Pll. */
335 CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
336
337 /* Bypass Sys Pll1. */
338 CLOCK_SetPllBypass(kCLOCK_PllSys1, true);
339
340 /* DeInit Sys Pll1. */
341 CLOCK_DeinitSysPll1();
342
343 /* Init Sys Pll2. */
344 CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN);
345
346 /* Init System Pll2 pfd0. */
347 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27);
348
349 /* Init System Pll2 pfd1. */
350 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16);
351
352 /* Init System Pll2 pfd2. */
353 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
354
355 /* Init System Pll2 pfd3. */
356 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 24);
357
358 /* Init Sys Pll3. */
359 CLOCK_InitSysPll3();
360
361 /* Init System Pll3 pfd0. */
362 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 13);
363
364 /* Init System Pll3 pfd1. */
365 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 17);
366
367 /* Init System Pll3 pfd2. */
368 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 32);
369
370 /* Init System Pll3 pfd3. */
371 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22);
372
373 /* Bypass Audio Pll. */
374 CLOCK_SetPllBypass(kCLOCK_PllAudio, true);
375
376 /* DeInit Audio Pll. */
377 CLOCK_DeinitAudioPll();
378
379 /* Init Video Pll. */
380 CLOCK_InitVideoPll(&videoPllConfig_BOARD_BootClockRUN);
381
382 /* Module clock root configurations. */
383 /* Configure M7 using ARM_PLL_CLK */
384 #if __CORTEX_M == 7
385 rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut;
386 rootCfg.div = 1;
387 CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
388 #endif
389
390 /* Configure M4 using SYS_PLL3_CLK */
391 #if __CORTEX_M == 4
392 rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Out;
393 rootCfg.div = 2;
394 CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
395 #endif
396
397 /* Configure BUS using SYS_PLL2_PFD3_CLK */
398 rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll2Pfd3;
399 rootCfg.div = 2;
400 CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg);
401
402 /* Configure BUS_LPSR using SYS_PLL3_CLK */
403 rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out;
404 rootCfg.div = 4;
405 CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
406
407 /* Configure SEMC using SYS_PLL2_PFD1_CLK */
408 #ifndef SKIP_SEMC_INIT
409 rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1;
410 rootCfg.div = 3;
411 CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg);
412 #endif
413
414 #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
415 #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
416 UpdateSemcClock();
417 #endif
418 #endif
419
420 /* Configure CSSYS using OSC_RC_48M_DIV2 */
421 rootCfg.mux = kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2;
422 rootCfg.div = 1;
423 CLOCK_SetRootClock(kCLOCK_Root_Cssys, &rootCfg);
424
425 /* Configure CSTRACE using SYS_PLL2_CLK */
426 rootCfg.mux = kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out;
427 rootCfg.div = 4;
428 CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg);
429
430 /* Configure M4_SYSTICK using OSC_RC_48M_DIV2 */
431 #if __CORTEX_M == 4
432 rootCfg.mux = kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
433 rootCfg.div = 1;
434 CLOCK_SetRootClock(kCLOCK_Root_M4_Systick, &rootCfg);
435 #endif
436
437 /* Configure M7_SYSTICK using OSC_RC_48M_DIV2 */
438 #if __CORTEX_M == 7
439 rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
440 rootCfg.div = 240;
441 CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
442 #endif
443
444 /* Configure ADC1 using OSC_RC_48M_DIV2 */
445 rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2;
446 rootCfg.div = 1;
447 CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg);
448
449 /* Configure ADC2 using OSC_RC_48M_DIV2 */
450 rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2;
451 rootCfg.div = 1;
452 CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg);
453
454 /* Configure ACMP using OSC_RC_48M_DIV2 */
455 rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2;
456 rootCfg.div = 1;
457 CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg);
458
459 /* Configure FLEXIO1 using OSC_RC_48M_DIV2 */
460 rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2;
461 rootCfg.div = 1;
462 CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg);
463
464 /* Configure FLEXIO2 using OSC_RC_48M_DIV2 */
465 rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2;
466 rootCfg.div = 1;
467 CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg);
468
469 /* Configure GPT1 using OSC_RC_48M_DIV2 */
470 rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2;
471 rootCfg.div = 1;
472 CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg);
473
474 /* Configure GPT2 using OSC_RC_48M_DIV2 */
475 rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2;
476 rootCfg.div = 1;
477 CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg);
478
479 /* Configure GPT3 using OSC_RC_48M_DIV2 */
480 rootCfg.mux = kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2;
481 rootCfg.div = 1;
482 CLOCK_SetRootClock(kCLOCK_Root_Gpt3, &rootCfg);
483
484 /* Configure GPT4 using OSC_RC_48M_DIV2 */
485 rootCfg.mux = kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2;
486 rootCfg.div = 1;
487 CLOCK_SetRootClock(kCLOCK_Root_Gpt4, &rootCfg);
488
489 /* Configure GPT5 using OSC_RC_48M_DIV2 */
490 rootCfg.mux = kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2;
491 rootCfg.div = 1;
492 CLOCK_SetRootClock(kCLOCK_Root_Gpt5, &rootCfg);
493
494 /* Configure GPT6 using OSC_RC_48M_DIV2 */
495 rootCfg.mux = kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2;
496 rootCfg.div = 1;
497 CLOCK_SetRootClock(kCLOCK_Root_Gpt6, &rootCfg);
498
499 /* Configure FLEXSPI1 using OSC_RC_48M_DIV2 */
500 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) || defined(FLEXSPI_IN_USE))
501 rootCfg.mux = kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2;
502 rootCfg.div = 1;
503 CLOCK_SetRootClock(kCLOCK_Root_Flexspi1, &rootCfg);
504 #endif
505
506 /* Configure FLEXSPI2 using OSC_RC_48M_DIV2 */
507 rootCfg.mux = kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2;
508 rootCfg.div = 1;
509 CLOCK_SetRootClock(kCLOCK_Root_Flexspi2, &rootCfg);
510
511 /* Configure CAN1 using OSC_RC_48M_DIV2 */
512 rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2;
513 rootCfg.div = 1;
514 CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg);
515
516 /* Configure CAN2 using OSC_RC_48M_DIV2 */
517 rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2;
518 rootCfg.div = 1;
519 CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg);
520
521 /* Configure CAN3 using OSC_RC_48M_DIV2 */
522 rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2;
523 rootCfg.div = 1;
524 CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg);
525
526 /* Configure LPUART1 using SYS_PLL2_CLK */
527 rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out;
528 rootCfg.div = 22;
529 CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg);
530
531 /* Configure LPUART2 using SYS_PLL2_CLK */
532 rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out;
533 rootCfg.div = 22;
534 CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg);
535
536 /* Configure LPUART3 using OSC_RC_48M_DIV2 */
537 rootCfg.mux = kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2;
538 rootCfg.div = 1;
539 CLOCK_SetRootClock(kCLOCK_Root_Lpuart3, &rootCfg);
540
541 /* Configure LPUART4 using OSC_RC_48M_DIV2 */
542 rootCfg.mux = kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2;
543 rootCfg.div = 1;
544 CLOCK_SetRootClock(kCLOCK_Root_Lpuart4, &rootCfg);
545
546 /* Configure LPUART5 using OSC_RC_48M_DIV2 */
547 rootCfg.mux = kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2;
548 rootCfg.div = 1;
549 CLOCK_SetRootClock(kCLOCK_Root_Lpuart5, &rootCfg);
550
551 /* Configure LPUART6 using OSC_RC_48M_DIV2 */
552 rootCfg.mux = kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2;
553 rootCfg.div = 1;
554 CLOCK_SetRootClock(kCLOCK_Root_Lpuart6, &rootCfg);
555
556 /* Configure LPUART7 using OSC_RC_48M_DIV2 */
557 rootCfg.mux = kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2;
558 rootCfg.div = 1;
559 CLOCK_SetRootClock(kCLOCK_Root_Lpuart7, &rootCfg);
560
561 /* Configure LPUART8 using OSC_RC_48M_DIV2 */
562 rootCfg.mux = kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2;
563 rootCfg.div = 1;
564 CLOCK_SetRootClock(kCLOCK_Root_Lpuart8, &rootCfg);
565
566 /* Configure LPUART9 using OSC_RC_48M_DIV2 */
567 rootCfg.mux = kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2;
568 rootCfg.div = 1;
569 CLOCK_SetRootClock(kCLOCK_Root_Lpuart9, &rootCfg);
570
571 /* Configure LPUART10 using OSC_RC_48M_DIV2 */
572 rootCfg.mux = kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2;
573 rootCfg.div = 1;
574 CLOCK_SetRootClock(kCLOCK_Root_Lpuart10, &rootCfg);
575
576 /* Configure LPUART11 using OSC_RC_48M_DIV2 */
577 rootCfg.mux = kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2;
578 rootCfg.div = 1;
579 CLOCK_SetRootClock(kCLOCK_Root_Lpuart11, &rootCfg);
580
581 /* Configure LPUART12 using OSC_RC_48M_DIV2 */
582 rootCfg.mux = kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2;
583 rootCfg.div = 1;
584 CLOCK_SetRootClock(kCLOCK_Root_Lpuart12, &rootCfg);
585
586 /* Configure LPI2C1 using OSC_RC_48M_DIV2 */
587 rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2;
588 rootCfg.div = 1;
589 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg);
590
591 /* Configure LPI2C2 using OSC_RC_48M_DIV2 */
592 rootCfg.mux = kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2;
593 rootCfg.div = 1;
594 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c2, &rootCfg);
595
596 /* Configure LPI2C3 using OSC_RC_48M_DIV2 */
597 rootCfg.mux = kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2;
598 rootCfg.div = 1;
599 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c3, &rootCfg);
600
601 /* Configure LPI2C4 using OSC_RC_48M_DIV2 */
602 rootCfg.mux = kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2;
603 rootCfg.div = 1;
604 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c4, &rootCfg);
605
606 /* Configure LPI2C5 using OSC_RC_48M_DIV2 */
607 rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2;
608 rootCfg.div = 1;
609 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg);
610
611 /* Configure LPI2C6 using OSC_RC_48M_DIV2 */
612 rootCfg.mux = kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2;
613 rootCfg.div = 1;
614 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c6, &rootCfg);
615
616 /* Configure LPSPI1 using OSC_RC_48M_DIV2 */
617 rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2;
618 rootCfg.div = 1;
619 CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg);
620
621 /* Configure LPSPI2 using OSC_RC_48M_DIV2 */
622 rootCfg.mux = kCLOCK_LPSPI2_ClockRoot_MuxOscRc48MDiv2;
623 rootCfg.div = 1;
624 CLOCK_SetRootClock(kCLOCK_Root_Lpspi2, &rootCfg);
625
626 /* Configure LPSPI3 using OSC_RC_48M_DIV2 */
627 rootCfg.mux = kCLOCK_LPSPI3_ClockRoot_MuxOscRc48MDiv2;
628 rootCfg.div = 1;
629 CLOCK_SetRootClock(kCLOCK_Root_Lpspi3, &rootCfg);
630
631 /* Configure LPSPI4 using OSC_RC_48M_DIV2 */
632 rootCfg.mux = kCLOCK_LPSPI4_ClockRoot_MuxOscRc48MDiv2;
633 rootCfg.div = 1;
634 CLOCK_SetRootClock(kCLOCK_Root_Lpspi4, &rootCfg);
635
636 /* Configure LPSPI5 using OSC_RC_48M_DIV2 */
637 rootCfg.mux = kCLOCK_LPSPI5_ClockRoot_MuxOscRc48MDiv2;
638 rootCfg.div = 1;
639 CLOCK_SetRootClock(kCLOCK_Root_Lpspi5, &rootCfg);
640
641 /* Configure LPSPI6 using OSC_RC_48M_DIV2 */
642 rootCfg.mux = kCLOCK_LPSPI6_ClockRoot_MuxOscRc48MDiv2;
643 rootCfg.div = 1;
644 CLOCK_SetRootClock(kCLOCK_Root_Lpspi6, &rootCfg);
645
646 /* Configure EMV1 using OSC_RC_48M_DIV2 */
647 rootCfg.mux = kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2;
648 rootCfg.div = 1;
649 CLOCK_SetRootClock(kCLOCK_Root_Emv1, &rootCfg);
650
651 /* Configure EMV2 using OSC_RC_48M_DIV2 */
652 rootCfg.mux = kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2;
653 rootCfg.div = 1;
654 CLOCK_SetRootClock(kCLOCK_Root_Emv2, &rootCfg);
655
656 /* Configure ENET1 using OSC_RC_48M_DIV2 */
657 rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2;
658 rootCfg.div = 1;
659 CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg);
660
661 /* Configure ENET2 using OSC_RC_48M_DIV2 */
662 rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2;
663 rootCfg.div = 1;
664 CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg);
665
666 /* Configure ENET_25M using OSC_RC_48M_DIV2 */
667 rootCfg.mux = kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2;
668 rootCfg.div = 1;
669 CLOCK_SetRootClock(kCLOCK_Root_Enet_25m, &rootCfg);
670
671 /* Configure ENET_TIMER1 using OSC_RC_48M_DIV2 */
672 rootCfg.mux = kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2;
673 rootCfg.div = 1;
674 CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer1, &rootCfg);
675
676 /* Configure ENET_TIMER2 using OSC_RC_48M_DIV2 */
677 rootCfg.mux = kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2;
678 rootCfg.div = 1;
679 CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer2, &rootCfg);
680
681 /* Configure USDHC1 using OSC_RC_48M_DIV2 */
682 rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2;
683 rootCfg.div = 1;
684 CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg);
685
686 /* Configure USDHC2 using OSC_RC_48M_DIV2 */
687 rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2;
688 rootCfg.div = 1;
689 CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg);
690
691 /* Configure ASRC using OSC_RC_48M_DIV2 */
692 rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2;
693 rootCfg.div = 1;
694 CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg);
695
696 /* Configure MQS using OSC_RC_48M_DIV2 */
697 rootCfg.mux = kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2;
698 rootCfg.div = 1;
699 CLOCK_SetRootClock(kCLOCK_Root_Mqs, &rootCfg);
700
701 /* Configure MIC using OSC_RC_48M_DIV2 */
702 rootCfg.mux = kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2;
703 rootCfg.div = 1;
704 CLOCK_SetRootClock(kCLOCK_Root_Mic, &rootCfg);
705
706 /* Configure SPDIF using OSC_RC_48M_DIV2 */
707 rootCfg.mux = kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2;
708 rootCfg.div = 1;
709 CLOCK_SetRootClock(kCLOCK_Root_Spdif, &rootCfg);
710
711 /* Configure SAI1 using OSC_RC_48M_DIV2 */
712 rootCfg.mux = kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2;
713 rootCfg.div = 1;
714 CLOCK_SetRootClock(kCLOCK_Root_Sai1, &rootCfg);
715
716 /* Configure SAI2 using OSC_RC_48M_DIV2 */
717 rootCfg.mux = kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2;
718 rootCfg.div = 1;
719 CLOCK_SetRootClock(kCLOCK_Root_Sai2, &rootCfg);
720
721 /* Configure SAI3 using OSC_RC_48M_DIV2 */
722 rootCfg.mux = kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2;
723 rootCfg.div = 1;
724 CLOCK_SetRootClock(kCLOCK_Root_Sai3, &rootCfg);
725
726 /* Configure SAI4 using OSC_RC_48M_DIV2 */
727 rootCfg.mux = kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2;
728 rootCfg.div = 1;
729 CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg);
730
731 /* Configure GC355 using PLL_VIDEO_CLK */
732 rootCfg.mux = kCLOCK_GC355_ClockRoot_MuxVideoPllOut;
733 rootCfg.div = 2;
734 CLOCK_SetRootClock(kCLOCK_Root_Gc355, &rootCfg);
735
736 /* Configure LCDIF using OSC_RC_48M_DIV2 */
737 rootCfg.mux = kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2;
738 rootCfg.div = 1;
739 CLOCK_SetRootClock(kCLOCK_Root_Lcdif, &rootCfg);
740
741 /* Configure LCDIFV2 using OSC_RC_48M_DIV2 */
742 rootCfg.mux = kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2;
743 rootCfg.div = 1;
744 CLOCK_SetRootClock(kCLOCK_Root_Lcdifv2, &rootCfg);
745
746 /* Configure MIPI_REF using OSC_RC_48M_DIV2 */
747 rootCfg.mux = kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2;
748 rootCfg.div = 1;
749 CLOCK_SetRootClock(kCLOCK_Root_Mipi_Ref, &rootCfg);
750
751 /* Configure MIPI_ESC using OSC_RC_48M_DIV2 */
752 rootCfg.mux = kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2;
753 rootCfg.div = 1;
754 CLOCK_SetRootClock(kCLOCK_Root_Mipi_Esc, &rootCfg);
755
756 /* Configure CSI2 using OSC_RC_48M_DIV2 */
757 rootCfg.mux = kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2;
758 rootCfg.div = 1;
759 CLOCK_SetRootClock(kCLOCK_Root_Csi2, &rootCfg);
760
761 /* Configure CSI2_ESC using OSC_RC_48M_DIV2 */
762 rootCfg.mux = kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2;
763 rootCfg.div = 1;
764 CLOCK_SetRootClock(kCLOCK_Root_Csi2_Esc, &rootCfg);
765
766 /* Configure CSI2_UI using OSC_RC_48M_DIV2 */
767 rootCfg.mux = kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2;
768 rootCfg.div = 1;
769 CLOCK_SetRootClock(kCLOCK_Root_Csi2_Ui, &rootCfg);
770
771 /* Configure CSI using OSC_RC_48M_DIV2 */
772 rootCfg.mux = kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2;
773 rootCfg.div = 1;
774 CLOCK_SetRootClock(kCLOCK_Root_Csi, &rootCfg);
775
776 /* Configure CKO1 using OSC_RC_48M_DIV2 */
777 rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2;
778 rootCfg.div = 1;
779 CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg);
780
781 /* Configure CKO2 using OSC_RC_48M_DIV2 */
782 rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2;
783 rootCfg.div = 1;
784 CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg);
785
786 /* Set SAI1 MCLK1 clock source. */
787 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
788 /* Set SAI1 MCLK2 clock source. */
789 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 3);
790 /* Set SAI1 MCLK3 clock source. */
791 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
792 /* Set SAI2 MCLK3 clock source. */
793 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
794 /* Set SAI3 MCLK3 clock source. */
795 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
796
797 /* Set MQS configuration. */
798 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
799 /* Set ENET Ref clock source. */
800 IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK;
801 /* Set ENET_1G Tx clock source. */
802 IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK);
803 /* Set ENET_1G Ref clock source. */
804 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK;
805 /* Set GPT1 High frequency reference clock source. */
806 IOMUXC_GPR->GPR22 &= ~IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK;
807 /* Set GPT2 High frequency reference clock source. */
808 IOMUXC_GPR->GPR23 &= ~IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK;
809 /* Set GPT3 High frequency reference clock source. */
810 IOMUXC_GPR->GPR24 &= ~IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK;
811 /* Set GPT4 High frequency reference clock source. */
812 IOMUXC_GPR->GPR25 &= ~IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK;
813 /* Set GPT5 High frequency reference clock source. */
814 IOMUXC_GPR->GPR26 &= ~IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK;
815 /* Set GPT6 High frequency reference clock source. */
816 IOMUXC_GPR->GPR27 &= ~IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK;
817
818 #if __CORTEX_M == 7
819 SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7);
820 #else
821 SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M4);
822 #endif
823 }
824 /*******************************************************************************
825 ******************* Configuration BOARD_BootClockRUN_500M *********************
826 ******************************************************************************/
827 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
828 !!Configuration
829 name: BOARD_BootClockRUN_500M
830 outputs:
831 - {id: ACMP_CLK_ROOT.outFreq, value: 24 MHz}
832 - {id: ADC1_CLK_ROOT.outFreq, value: 24 MHz}
833 - {id: ADC2_CLK_ROOT.outFreq, value: 24 MHz}
834 - {id: ARM_PLL_CLK.outFreq, value: 498 MHz}
835 - {id: ASRC_CLK_ROOT.outFreq, value: 24 MHz}
836 - {id: AXI_CLK_ROOT.outFreq, value: 498 MHz}
837 - {id: BUS_CLK_ROOT.outFreq, value: 198 MHz}
838 - {id: BUS_LPSR_CLK_ROOT.outFreq, value: 120 MHz}
839 - {id: CAN1_CLK_ROOT.outFreq, value: 24 MHz}
840 - {id: CAN2_CLK_ROOT.outFreq, value: 24 MHz}
841 - {id: CAN3_CLK_ROOT.outFreq, value: 24 MHz}
842 - {id: CCM_CLKO1_CLK_ROOT.outFreq, value: 24 MHz}
843 - {id: CCM_CLKO2_CLK_ROOT.outFreq, value: 24 MHz}
844 - {id: CLK_1M.outFreq, value: 1 MHz}
845 - {id: CSI2_CLK_ROOT.outFreq, value: 24 MHz}
846 - {id: CSI2_ESC_CLK_ROOT.outFreq, value: 24 MHz}
847 - {id: CSI2_UI_CLK_ROOT.outFreq, value: 24 MHz}
848 - {id: CSI_CLK_ROOT.outFreq, value: 24 MHz}
849 - {id: CSSYS_CLK_ROOT.outFreq, value: 24 MHz}
850 - {id: CSTRACE_CLK_ROOT.outFreq, value: 132 MHz}
851 - {id: ELCDIF_CLK_ROOT.outFreq, value: 24 MHz}
852 - {id: EMV1_CLK_ROOT.outFreq, value: 24 MHz}
853 - {id: EMV2_CLK_ROOT.outFreq, value: 24 MHz}
854 - {id: ENET1_CLK_ROOT.outFreq, value: 24 MHz}
855 - {id: ENET2_CLK_ROOT.outFreq, value: 24 MHz}
856 - {id: ENET_1G_TX_CLK.outFreq, value: 24 MHz}
857 - {id: ENET_25M_CLK_ROOT.outFreq, value: 24 MHz}
858 - {id: ENET_TIMER1_CLK_ROOT.outFreq, value: 24 MHz}
859 - {id: ENET_TIMER2_CLK_ROOT.outFreq, value: 24 MHz}
860 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 24 MHz}
861 - {id: FLEXIO2_CLK_ROOT.outFreq, value: 24 MHz}
862 - {id: FLEXSPI1_CLK_ROOT.outFreq, value: 24 MHz}
863 - {id: FLEXSPI2_CLK_ROOT.outFreq, value: 24 MHz}
864 - {id: GC355_CLK_ROOT.outFreq, value: 492.0000125 MHz}
865 - {id: GPT1_CLK_ROOT.outFreq, value: 24 MHz}
866 - {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz}
867 - {id: GPT2_CLK_ROOT.outFreq, value: 24 MHz}
868 - {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz}
869 - {id: GPT3_CLK_ROOT.outFreq, value: 24 MHz}
870 - {id: GPT3_ipg_clk_highfreq.outFreq, value: 24 MHz}
871 - {id: GPT4_CLK_ROOT.outFreq, value: 24 MHz}
872 - {id: GPT4_ipg_clk_highfreq.outFreq, value: 24 MHz}
873 - {id: GPT5_CLK_ROOT.outFreq, value: 24 MHz}
874 - {id: GPT5_ipg_clk_highfreq.outFreq, value: 24 MHz}
875 - {id: GPT6_CLK_ROOT.outFreq, value: 24 MHz}
876 - {id: GPT6_ipg_clk_highfreq.outFreq, value: 24 MHz}
877 - {id: LCDIFV2_CLK_ROOT.outFreq, value: 24 MHz}
878 - {id: LPI2C1_CLK_ROOT.outFreq, value: 24 MHz}
879 - {id: LPI2C2_CLK_ROOT.outFreq, value: 24 MHz}
880 - {id: LPI2C3_CLK_ROOT.outFreq, value: 24 MHz}
881 - {id: LPI2C4_CLK_ROOT.outFreq, value: 24 MHz}
882 - {id: LPI2C5_CLK_ROOT.outFreq, value: 24 MHz}
883 - {id: LPI2C6_CLK_ROOT.outFreq, value: 24 MHz}
884 - {id: LPSPI1_CLK_ROOT.outFreq, value: 24 MHz}
885 - {id: LPSPI2_CLK_ROOT.outFreq, value: 24 MHz}
886 - {id: LPSPI3_CLK_ROOT.outFreq, value: 24 MHz}
887 - {id: LPSPI4_CLK_ROOT.outFreq, value: 24 MHz}
888 - {id: LPSPI5_CLK_ROOT.outFreq, value: 24 MHz}
889 - {id: LPSPI6_CLK_ROOT.outFreq, value: 24 MHz}
890 - {id: LPUART10_CLK_ROOT.outFreq, value: 24 MHz}
891 - {id: LPUART11_CLK_ROOT.outFreq, value: 24 MHz}
892 - {id: LPUART12_CLK_ROOT.outFreq, value: 24 MHz}
893 - {id: LPUART1_CLK_ROOT.outFreq, value: 24 MHz}
894 - {id: LPUART2_CLK_ROOT.outFreq, value: 24 MHz}
895 - {id: LPUART3_CLK_ROOT.outFreq, value: 24 MHz}
896 - {id: LPUART4_CLK_ROOT.outFreq, value: 24 MHz}
897 - {id: LPUART5_CLK_ROOT.outFreq, value: 24 MHz}
898 - {id: LPUART6_CLK_ROOT.outFreq, value: 24 MHz}
899 - {id: LPUART7_CLK_ROOT.outFreq, value: 24 MHz}
900 - {id: LPUART8_CLK_ROOT.outFreq, value: 24 MHz}
901 - {id: LPUART9_CLK_ROOT.outFreq, value: 24 MHz}
902 - {id: M4_CLK_ROOT.outFreq, value: 240 MHz}
903 - {id: M4_SYSTICK_CLK_ROOT.outFreq, value: 24 MHz}
904 - {id: M7_CLK_ROOT.outFreq, value: 498 MHz}
905 - {id: M7_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz}
906 - {id: MIC_CLK_ROOT.outFreq, value: 24 MHz}
907 - {id: MIPI_DSI_TX_CLK_ESC_ROOT.outFreq, value: 24 MHz}
908 - {id: MIPI_ESC_CLK_ROOT.outFreq, value: 24 MHz}
909 - {id: MIPI_REF_CLK_ROOT.outFreq, value: 24 MHz}
910 - {id: MQS_CLK_ROOT.outFreq, value: 24 MHz}
911 - {id: MQS_MCLK.outFreq, value: 24 MHz}
912 - {id: OSC_24M.outFreq, value: 24 MHz}
913 - {id: OSC_32K.outFreq, value: 32.768 kHz}
914 - {id: OSC_RC_16M.outFreq, value: 16 MHz}
915 - {id: OSC_RC_400M.outFreq, value: 400 MHz}
916 - {id: OSC_RC_48M.outFreq, value: 48 MHz}
917 - {id: OSC_RC_48M_DIV2.outFreq, value: 24 MHz}
918 - {id: PLL_VIDEO_CLK.outFreq, value: 984.000025 MHz}
919 - {id: SAI1_CLK_ROOT.outFreq, value: 24 MHz}
920 - {id: SAI1_MCLK1.outFreq, value: 24 MHz}
921 - {id: SAI1_MCLK3.outFreq, value: 24 MHz}
922 - {id: SAI2_CLK_ROOT.outFreq, value: 24 MHz}
923 - {id: SAI2_MCLK1.outFreq, value: 24 MHz}
924 - {id: SAI2_MCLK3.outFreq, value: 24 MHz}
925 - {id: SAI3_CLK_ROOT.outFreq, value: 24 MHz}
926 - {id: SAI3_MCLK1.outFreq, value: 24 MHz}
927 - {id: SAI3_MCLK3.outFreq, value: 24 MHz}
928 - {id: SAI4_CLK_ROOT.outFreq, value: 24 MHz}
929 - {id: SAI4_MCLK1.outFreq, value: 24 MHz}
930 - {id: SEMC_CLK_ROOT.outFreq, value: 198 MHz}
931 - {id: SPDIF_CLK_ROOT.outFreq, value: 24 MHz}
932 - {id: SYS_PLL2_CLK.outFreq, value: 528 MHz}
933 - {id: SYS_PLL2_PFD0_CLK.outFreq, value: 352 MHz}
934 - {id: SYS_PLL2_PFD1_CLK.outFreq, value: 594 MHz}
935 - {id: SYS_PLL2_PFD2_CLK.outFreq, value: 396 MHz}
936 - {id: SYS_PLL2_PFD3_CLK.outFreq, value: 396 MHz}
937 - {id: SYS_PLL3_CLK.outFreq, value: 480 MHz}
938 - {id: SYS_PLL3_DIV2_CLK.outFreq, value: 240 MHz}
939 - {id: SYS_PLL3_PFD0_CLK.outFreq, value: 8640/13 MHz}
940 - {id: SYS_PLL3_PFD1_CLK.outFreq, value: 8640/17 MHz}
941 - {id: SYS_PLL3_PFD2_CLK.outFreq, value: 270 MHz}
942 - {id: SYS_PLL3_PFD3_CLK.outFreq, value: 4320/11 MHz}
943 - {id: USDHC1_CLK_ROOT.outFreq, value: 24 MHz}
944 - {id: USDHC2_CLK_ROOT.outFreq, value: 24 MHz}
945 settings:
946 - {id: CoreBusClockRootsInitializationConfig, value: selectedCore}
947 - {id: ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG, value: Low}
948 - {id: ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG, value: Enabled}
949 - {id: ANADIG_PLL.ARM_PLL_POST_DIV.scale, value: '4'}
950 - {id: ANADIG_PLL.ARM_PLL_PREDIV.scale, value: '1', locked: true}
951 - {id: ANADIG_PLL.ARM_PLL_VDIV.scale, value: '166', locked: true}
952 - {id: ANADIG_PLL.PLL_AUDIO_BYPASS.sel, value: ANADIG_OSC.OSC_24M}
953 - {id: ANADIG_PLL.PLL_VIDEO.denom, value: '960000'}
954 - {id: ANADIG_PLL.PLL_VIDEO.div, value: '41'}
955 - {id: ANADIG_PLL.PLL_VIDEO.num, value: '1'}
956 - {id: ANADIG_PLL.SYS_PLL1_BYPASS.sel, value: ANADIG_OSC.OSC_24M}
957 - {id: ANADIG_PLL.SYS_PLL2.denom, value: '268435455'}
958 - {id: ANADIG_PLL.SYS_PLL2.div, value: '22'}
959 - {id: ANADIG_PLL.SYS_PLL2.num, value: '0'}
960 - {id: ANADIG_PLL.SYS_PLL2_PFD3_DIV.scale, value: '24'}
961 - {id: ANADIG_PLL.SYS_PLL2_SS_DIV.scale, value: '268435455'}
962 - {id: ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale, value: '22', locked: true}
963 - {id: ANADIG_PLL.SYS_PLL3_PFD3_MUL.scale, value: '18', locked: true}
964 - {id: ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG, value: Enabled}
965 - {id: ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG, value: Disabled}
966 - {id: ANADIG_PLL_PLL_VIDEO_CTRL0_POWERUP_CFG, value: Enabled}
967 - {id: ANADIG_PLL_SYS_PLL1_CTRL0_POWERUP_CFG, value: Disabled}
968 - {id: ANADIG_PLL_SYS_PLL1_CTRL_GATE_CFG, value: Disabled}
969 - {id: ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG, value: Enabled}
970 - {id: ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG, value: Enabled}
971 - {id: ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG, value: Enabled}
972 - {id: CCM.CLOCK_ROOT0.MUX.sel, value: ANADIG_PLL.ARM_PLL_CLK}
973 - {id: CCM.CLOCK_ROOT1.DIV.scale, value: '2'}
974 - {id: CCM.CLOCK_ROOT1.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
975 - {id: CCM.CLOCK_ROOT2.DIV.scale, value: '2'}
976 - {id: CCM.CLOCK_ROOT2.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD3_CLK}
977 - {id: CCM.CLOCK_ROOT25.DIV.scale, value: '22'}
978 - {id: CCM.CLOCK_ROOT25.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
979 - {id: CCM.CLOCK_ROOT26.DIV.scale, value: '22'}
980 - {id: CCM.CLOCK_ROOT26.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
981 - {id: CCM.CLOCK_ROOT3.DIV.scale, value: '4'}
982 - {id: CCM.CLOCK_ROOT3.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
983 - {id: CCM.CLOCK_ROOT4.DIV.scale, value: '3'}
984 - {id: CCM.CLOCK_ROOT4.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD1_CLK}
985 - {id: CCM.CLOCK_ROOT6.DIV.scale, value: '4'}
986 - {id: CCM.CLOCK_ROOT6.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
987 - {id: CCM.CLOCK_ROOT68.DIV.scale, value: '2'}
988 - {id: CCM.CLOCK_ROOT68.MUX.sel, value: ANADIG_PLL.PLL_VIDEO_CLK}
989 - {id: CCM.CLOCK_ROOT8.DIV.scale, value: '240'}
990 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
991
992 /*******************************************************************************
993 * Variables for BOARD_BootClockRUN_500M configuration
994 ******************************************************************************/
995
996 #if __CORTEX_M == 7
997 #define BYPASS_LDO_LPSR 1
998 #endif
999
1000 const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN_500M =
1001 {
1002 .postDivider = kCLOCK_PllPostDiv4, /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */
1003 .loopDivider = 166, /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */
1004 };
1005
1006 const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN_500M =
1007 {
1008 .mfd = 268435455, /* Denominator of spread spectrum */
1009 .ss = NULL, /* Spread spectrum parameter */
1010 .ssEnable = false, /* Enable spread spectrum or not */
1011 };
1012
1013 const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN_500M =
1014 {
1015 .loopDivider = 41, /* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */
1016 .postDivider = 0, /* Divider after PLL, should only be 1, 2, 4, 8, 16, 32 */
1017 .numerator = 1, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
1018 .denominator = 960000, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
1019 .ss = NULL, /* Spread spectrum parameter */
1020 .ssEnable = false, /* Enable spread spectrum or not */
1021 };
1022
1023 /*******************************************************************************
1024 * Code for BOARD_BootClockRUN_500M configuration
1025 ******************************************************************************/
BOARD_BootClockRUN_500M(void)1026 void BOARD_BootClockRUN_500M(void)
1027 {
1028 clock_root_config_t rootCfg = {0};
1029
1030 /* Set DCDC to DCM mode to improve the efficiency for light loading in run mode and transient performance with a big loading step. */
1031 DCDC_BootIntoDCM(DCDC);
1032
1033 #if defined(BYPASS_LDO_LPSR) && BYPASS_LDO_LPSR
1034 PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, true);
1035 PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS, true);
1036 #endif
1037
1038 /* Config CLK_1M */
1039 CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz);
1040
1041 /* Init OSC RC 16M */
1042 ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK;
1043
1044 /* Init OSC RC 400M */
1045 CLOCK_OSC_EnableOscRc400M();
1046 CLOCK_OSC_GateOscRc400M(false);
1047
1048 /* Init OSC RC 48M */
1049 CLOCK_OSC_EnableOsc48M(true);
1050 CLOCK_OSC_EnableOsc48MDiv2(true);
1051
1052 /* Config OSC 24M */
1053 ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0);
1054 /* Wait for 24M OSC to be stable. */
1055 while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK !=
1056 (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK))
1057 {
1058 }
1059
1060 /* Switch both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */
1061 #if __CORTEX_M == 7
1062 rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2;
1063 rootCfg.div = 1;
1064 CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
1065
1066 rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
1067 rootCfg.div = 1;
1068 CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
1069 #endif
1070
1071 #if __CORTEX_M == 4
1072 rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2;
1073 rootCfg.div = 1;
1074 CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
1075
1076 rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2;
1077 rootCfg.div = 1;
1078 CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
1079 #endif
1080
1081 /*
1082 * if DCD is used, please make sure the clock source of SEMC is not changed in the following PLL/PFD configuration code.
1083 */
1084 /* Init Arm Pll. */
1085 CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN_500M);
1086
1087 /* Bypass Sys Pll1. */
1088 CLOCK_SetPllBypass(kCLOCK_PllSys1, true);
1089
1090 /* DeInit Sys Pll1. */
1091 CLOCK_DeinitSysPll1();
1092
1093 /* Init Sys Pll2. */
1094 CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN_500M);
1095
1096 /* Init System Pll2 pfd0. */
1097 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27);
1098
1099 /* Init System Pll2 pfd1. */
1100 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16);
1101
1102 /* Init System Pll2 pfd2. */
1103 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
1104
1105 /* Init System Pll2 pfd3. */
1106 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 24);
1107
1108 /* Init Sys Pll3. */
1109 CLOCK_InitSysPll3();
1110
1111 /* Init System Pll3 pfd0. */
1112 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 13);
1113
1114 /* Init System Pll3 pfd1. */
1115 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 17);
1116
1117 /* Init System Pll3 pfd2. */
1118 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 32);
1119
1120 /* Init System Pll3 pfd3. */
1121 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22);
1122
1123 /* Bypass Audio Pll. */
1124 CLOCK_SetPllBypass(kCLOCK_PllAudio, true);
1125
1126 /* DeInit Audio Pll. */
1127 CLOCK_DeinitAudioPll();
1128
1129 /* Init Video Pll. */
1130 CLOCK_InitVideoPll(&videoPllConfig_BOARD_BootClockRUN_500M);
1131
1132 /* Module clock root configurations. */
1133 /* Configure M7 using ARM_PLL_CLK */
1134 #if __CORTEX_M == 7
1135 rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut;
1136 rootCfg.div = 1;
1137 CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
1138 #endif
1139
1140 /* Configure M4 using SYS_PLL3_CLK */
1141 #if __CORTEX_M == 4
1142 rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Out;
1143 rootCfg.div = 2;
1144 CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
1145 #endif
1146
1147 /* Configure BUS using SYS_PLL2_PFD3_CLK */
1148 rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll2Pfd3;
1149 rootCfg.div = 2;
1150 CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg);
1151
1152 /* Configure BUS_LPSR using SYS_PLL3_CLK */
1153 rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out;
1154 rootCfg.div = 4;
1155 CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
1156
1157 /* Configure SEMC using SYS_PLL2_PFD1_CLK */
1158 #ifndef SKIP_SEMC_INIT
1159 rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1;
1160 rootCfg.div = 3;
1161 CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg);
1162 #endif
1163
1164 #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
1165 #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
1166 UpdateSemcClock();
1167 #endif
1168 #endif
1169
1170 /* Configure CSSYS using OSC_RC_48M_DIV2 */
1171 rootCfg.mux = kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2;
1172 rootCfg.div = 1;
1173 CLOCK_SetRootClock(kCLOCK_Root_Cssys, &rootCfg);
1174
1175 /* Configure CSTRACE using SYS_PLL2_CLK */
1176 rootCfg.mux = kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out;
1177 rootCfg.div = 4;
1178 CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg);
1179
1180 /* Configure M4_SYSTICK using OSC_RC_48M_DIV2 */
1181 #if __CORTEX_M == 4
1182 rootCfg.mux = kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
1183 rootCfg.div = 1;
1184 CLOCK_SetRootClock(kCLOCK_Root_M4_Systick, &rootCfg);
1185 #endif
1186
1187 /* Configure M7_SYSTICK using OSC_RC_48M_DIV2 */
1188 #if __CORTEX_M == 7
1189 rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
1190 rootCfg.div = 240;
1191 CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
1192 #endif
1193
1194 /* Configure ADC1 using OSC_RC_48M_DIV2 */
1195 rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2;
1196 rootCfg.div = 1;
1197 CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg);
1198
1199 /* Configure ADC2 using OSC_RC_48M_DIV2 */
1200 rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2;
1201 rootCfg.div = 1;
1202 CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg);
1203
1204 /* Configure ACMP using OSC_RC_48M_DIV2 */
1205 rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2;
1206 rootCfg.div = 1;
1207 CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg);
1208
1209 /* Configure FLEXIO1 using OSC_RC_48M_DIV2 */
1210 rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2;
1211 rootCfg.div = 1;
1212 CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg);
1213
1214 /* Configure FLEXIO2 using OSC_RC_48M_DIV2 */
1215 rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2;
1216 rootCfg.div = 1;
1217 CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg);
1218
1219 /* Configure GPT1 using OSC_RC_48M_DIV2 */
1220 rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2;
1221 rootCfg.div = 1;
1222 CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg);
1223
1224 /* Configure GPT2 using OSC_RC_48M_DIV2 */
1225 rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2;
1226 rootCfg.div = 1;
1227 CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg);
1228
1229 /* Configure GPT3 using OSC_RC_48M_DIV2 */
1230 rootCfg.mux = kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2;
1231 rootCfg.div = 1;
1232 CLOCK_SetRootClock(kCLOCK_Root_Gpt3, &rootCfg);
1233
1234 /* Configure GPT4 using OSC_RC_48M_DIV2 */
1235 rootCfg.mux = kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2;
1236 rootCfg.div = 1;
1237 CLOCK_SetRootClock(kCLOCK_Root_Gpt4, &rootCfg);
1238
1239 /* Configure GPT5 using OSC_RC_48M_DIV2 */
1240 rootCfg.mux = kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2;
1241 rootCfg.div = 1;
1242 CLOCK_SetRootClock(kCLOCK_Root_Gpt5, &rootCfg);
1243
1244 /* Configure GPT6 using OSC_RC_48M_DIV2 */
1245 rootCfg.mux = kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2;
1246 rootCfg.div = 1;
1247 CLOCK_SetRootClock(kCLOCK_Root_Gpt6, &rootCfg);
1248
1249 /* Configure FLEXSPI1 using OSC_RC_48M_DIV2 */
1250 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) || defined(FLEXSPI_IN_USE))
1251 rootCfg.mux = kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2;
1252 rootCfg.div = 1;
1253 CLOCK_SetRootClock(kCLOCK_Root_Flexspi1, &rootCfg);
1254 #endif
1255
1256 /* Configure FLEXSPI2 using OSC_RC_48M_DIV2 */
1257 rootCfg.mux = kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2;
1258 rootCfg.div = 1;
1259 CLOCK_SetRootClock(kCLOCK_Root_Flexspi2, &rootCfg);
1260
1261 /* Configure CAN1 using OSC_RC_48M_DIV2 */
1262 rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2;
1263 rootCfg.div = 1;
1264 CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg);
1265
1266 /* Configure CAN2 using OSC_RC_48M_DIV2 */
1267 rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2;
1268 rootCfg.div = 1;
1269 CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg);
1270
1271 /* Configure CAN3 using OSC_RC_48M_DIV2 */
1272 rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2;
1273 rootCfg.div = 1;
1274 CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg);
1275
1276 /* Configure LPUART1 using SYS_PLL2_CLK */
1277 rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out;
1278 rootCfg.div = 22;
1279 CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg);
1280
1281 /* Configure LPUART2 using SYS_PLL2_CLK */
1282 rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out;
1283 rootCfg.div = 22;
1284 CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg);
1285
1286 /* Configure LPUART3 using OSC_RC_48M_DIV2 */
1287 rootCfg.mux = kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2;
1288 rootCfg.div = 1;
1289 CLOCK_SetRootClock(kCLOCK_Root_Lpuart3, &rootCfg);
1290
1291 /* Configure LPUART4 using OSC_RC_48M_DIV2 */
1292 rootCfg.mux = kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2;
1293 rootCfg.div = 1;
1294 CLOCK_SetRootClock(kCLOCK_Root_Lpuart4, &rootCfg);
1295
1296 /* Configure LPUART5 using OSC_RC_48M_DIV2 */
1297 rootCfg.mux = kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2;
1298 rootCfg.div = 1;
1299 CLOCK_SetRootClock(kCLOCK_Root_Lpuart5, &rootCfg);
1300
1301 /* Configure LPUART6 using OSC_RC_48M_DIV2 */
1302 rootCfg.mux = kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2;
1303 rootCfg.div = 1;
1304 CLOCK_SetRootClock(kCLOCK_Root_Lpuart6, &rootCfg);
1305
1306 /* Configure LPUART7 using OSC_RC_48M_DIV2 */
1307 rootCfg.mux = kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2;
1308 rootCfg.div = 1;
1309 CLOCK_SetRootClock(kCLOCK_Root_Lpuart7, &rootCfg);
1310
1311 /* Configure LPUART8 using OSC_RC_48M_DIV2 */
1312 rootCfg.mux = kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2;
1313 rootCfg.div = 1;
1314 CLOCK_SetRootClock(kCLOCK_Root_Lpuart8, &rootCfg);
1315
1316 /* Configure LPUART9 using OSC_RC_48M_DIV2 */
1317 rootCfg.mux = kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2;
1318 rootCfg.div = 1;
1319 CLOCK_SetRootClock(kCLOCK_Root_Lpuart9, &rootCfg);
1320
1321 /* Configure LPUART10 using OSC_RC_48M_DIV2 */
1322 rootCfg.mux = kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2;
1323 rootCfg.div = 1;
1324 CLOCK_SetRootClock(kCLOCK_Root_Lpuart10, &rootCfg);
1325
1326 /* Configure LPUART11 using OSC_RC_48M_DIV2 */
1327 rootCfg.mux = kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2;
1328 rootCfg.div = 1;
1329 CLOCK_SetRootClock(kCLOCK_Root_Lpuart11, &rootCfg);
1330
1331 /* Configure LPUART12 using OSC_RC_48M_DIV2 */
1332 rootCfg.mux = kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2;
1333 rootCfg.div = 1;
1334 CLOCK_SetRootClock(kCLOCK_Root_Lpuart12, &rootCfg);
1335
1336 /* Configure LPI2C1 using OSC_RC_48M_DIV2 */
1337 rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2;
1338 rootCfg.div = 1;
1339 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg);
1340
1341 /* Configure LPI2C2 using OSC_RC_48M_DIV2 */
1342 rootCfg.mux = kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2;
1343 rootCfg.div = 1;
1344 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c2, &rootCfg);
1345
1346 /* Configure LPI2C3 using OSC_RC_48M_DIV2 */
1347 rootCfg.mux = kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2;
1348 rootCfg.div = 1;
1349 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c3, &rootCfg);
1350
1351 /* Configure LPI2C4 using OSC_RC_48M_DIV2 */
1352 rootCfg.mux = kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2;
1353 rootCfg.div = 1;
1354 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c4, &rootCfg);
1355
1356 /* Configure LPI2C5 using OSC_RC_48M_DIV2 */
1357 rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2;
1358 rootCfg.div = 1;
1359 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg);
1360
1361 /* Configure LPI2C6 using OSC_RC_48M_DIV2 */
1362 rootCfg.mux = kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2;
1363 rootCfg.div = 1;
1364 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c6, &rootCfg);
1365
1366 /* Configure LPSPI1 using OSC_RC_48M_DIV2 */
1367 rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2;
1368 rootCfg.div = 1;
1369 CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg);
1370
1371 /* Configure LPSPI2 using OSC_RC_48M_DIV2 */
1372 rootCfg.mux = kCLOCK_LPSPI2_ClockRoot_MuxOscRc48MDiv2;
1373 rootCfg.div = 1;
1374 CLOCK_SetRootClock(kCLOCK_Root_Lpspi2, &rootCfg);
1375
1376 /* Configure LPSPI3 using OSC_RC_48M_DIV2 */
1377 rootCfg.mux = kCLOCK_LPSPI3_ClockRoot_MuxOscRc48MDiv2;
1378 rootCfg.div = 1;
1379 CLOCK_SetRootClock(kCLOCK_Root_Lpspi3, &rootCfg);
1380
1381 /* Configure LPSPI4 using OSC_RC_48M_DIV2 */
1382 rootCfg.mux = kCLOCK_LPSPI4_ClockRoot_MuxOscRc48MDiv2;
1383 rootCfg.div = 1;
1384 CLOCK_SetRootClock(kCLOCK_Root_Lpspi4, &rootCfg);
1385
1386 /* Configure LPSPI5 using OSC_RC_48M_DIV2 */
1387 rootCfg.mux = kCLOCK_LPSPI5_ClockRoot_MuxOscRc48MDiv2;
1388 rootCfg.div = 1;
1389 CLOCK_SetRootClock(kCLOCK_Root_Lpspi5, &rootCfg);
1390
1391 /* Configure LPSPI6 using OSC_RC_48M_DIV2 */
1392 rootCfg.mux = kCLOCK_LPSPI6_ClockRoot_MuxOscRc48MDiv2;
1393 rootCfg.div = 1;
1394 CLOCK_SetRootClock(kCLOCK_Root_Lpspi6, &rootCfg);
1395
1396 /* Configure EMV1 using OSC_RC_48M_DIV2 */
1397 rootCfg.mux = kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2;
1398 rootCfg.div = 1;
1399 CLOCK_SetRootClock(kCLOCK_Root_Emv1, &rootCfg);
1400
1401 /* Configure EMV2 using OSC_RC_48M_DIV2 */
1402 rootCfg.mux = kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2;
1403 rootCfg.div = 1;
1404 CLOCK_SetRootClock(kCLOCK_Root_Emv2, &rootCfg);
1405
1406 /* Configure ENET1 using OSC_RC_48M_DIV2 */
1407 rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2;
1408 rootCfg.div = 1;
1409 CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg);
1410
1411 /* Configure ENET2 using OSC_RC_48M_DIV2 */
1412 rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2;
1413 rootCfg.div = 1;
1414 CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg);
1415
1416 /* Configure ENET_25M using OSC_RC_48M_DIV2 */
1417 rootCfg.mux = kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2;
1418 rootCfg.div = 1;
1419 CLOCK_SetRootClock(kCLOCK_Root_Enet_25m, &rootCfg);
1420
1421 /* Configure ENET_TIMER1 using OSC_RC_48M_DIV2 */
1422 rootCfg.mux = kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2;
1423 rootCfg.div = 1;
1424 CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer1, &rootCfg);
1425
1426 /* Configure ENET_TIMER2 using OSC_RC_48M_DIV2 */
1427 rootCfg.mux = kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2;
1428 rootCfg.div = 1;
1429 CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer2, &rootCfg);
1430
1431 /* Configure USDHC1 using OSC_RC_48M_DIV2 */
1432 rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2;
1433 rootCfg.div = 1;
1434 CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg);
1435
1436 /* Configure USDHC2 using OSC_RC_48M_DIV2 */
1437 rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2;
1438 rootCfg.div = 1;
1439 CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg);
1440
1441 /* Configure ASRC using OSC_RC_48M_DIV2 */
1442 rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2;
1443 rootCfg.div = 1;
1444 CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg);
1445
1446 /* Configure MQS using OSC_RC_48M_DIV2 */
1447 rootCfg.mux = kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2;
1448 rootCfg.div = 1;
1449 CLOCK_SetRootClock(kCLOCK_Root_Mqs, &rootCfg);
1450
1451 /* Configure MIC using OSC_RC_48M_DIV2 */
1452 rootCfg.mux = kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2;
1453 rootCfg.div = 1;
1454 CLOCK_SetRootClock(kCLOCK_Root_Mic, &rootCfg);
1455
1456 /* Configure SPDIF using OSC_RC_48M_DIV2 */
1457 rootCfg.mux = kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2;
1458 rootCfg.div = 1;
1459 CLOCK_SetRootClock(kCLOCK_Root_Spdif, &rootCfg);
1460
1461 /* Configure SAI1 using OSC_RC_48M_DIV2 */
1462 rootCfg.mux = kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2;
1463 rootCfg.div = 1;
1464 CLOCK_SetRootClock(kCLOCK_Root_Sai1, &rootCfg);
1465
1466 /* Configure SAI2 using OSC_RC_48M_DIV2 */
1467 rootCfg.mux = kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2;
1468 rootCfg.div = 1;
1469 CLOCK_SetRootClock(kCLOCK_Root_Sai2, &rootCfg);
1470
1471 /* Configure SAI3 using OSC_RC_48M_DIV2 */
1472 rootCfg.mux = kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2;
1473 rootCfg.div = 1;
1474 CLOCK_SetRootClock(kCLOCK_Root_Sai3, &rootCfg);
1475
1476 /* Configure SAI4 using OSC_RC_48M_DIV2 */
1477 rootCfg.mux = kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2;
1478 rootCfg.div = 1;
1479 CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg);
1480
1481 /* Configure GC355 using PLL_VIDEO_CLK */
1482 rootCfg.mux = kCLOCK_GC355_ClockRoot_MuxVideoPllOut;
1483 rootCfg.div = 2;
1484 CLOCK_SetRootClock(kCLOCK_Root_Gc355, &rootCfg);
1485
1486 /* Configure LCDIF using OSC_RC_48M_DIV2 */
1487 rootCfg.mux = kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2;
1488 rootCfg.div = 1;
1489 CLOCK_SetRootClock(kCLOCK_Root_Lcdif, &rootCfg);
1490
1491 /* Configure LCDIFV2 using OSC_RC_48M_DIV2 */
1492 rootCfg.mux = kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2;
1493 rootCfg.div = 1;
1494 CLOCK_SetRootClock(kCLOCK_Root_Lcdifv2, &rootCfg);
1495
1496 /* Configure MIPI_REF using OSC_RC_48M_DIV2 */
1497 rootCfg.mux = kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2;
1498 rootCfg.div = 1;
1499 CLOCK_SetRootClock(kCLOCK_Root_Mipi_Ref, &rootCfg);
1500
1501 /* Configure MIPI_ESC using OSC_RC_48M_DIV2 */
1502 rootCfg.mux = kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2;
1503 rootCfg.div = 1;
1504 CLOCK_SetRootClock(kCLOCK_Root_Mipi_Esc, &rootCfg);
1505
1506 /* Configure CSI2 using OSC_RC_48M_DIV2 */
1507 rootCfg.mux = kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2;
1508 rootCfg.div = 1;
1509 CLOCK_SetRootClock(kCLOCK_Root_Csi2, &rootCfg);
1510
1511 /* Configure CSI2_ESC using OSC_RC_48M_DIV2 */
1512 rootCfg.mux = kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2;
1513 rootCfg.div = 1;
1514 CLOCK_SetRootClock(kCLOCK_Root_Csi2_Esc, &rootCfg);
1515
1516 /* Configure CSI2_UI using OSC_RC_48M_DIV2 */
1517 rootCfg.mux = kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2;
1518 rootCfg.div = 1;
1519 CLOCK_SetRootClock(kCLOCK_Root_Csi2_Ui, &rootCfg);
1520
1521 /* Configure CSI using OSC_RC_48M_DIV2 */
1522 rootCfg.mux = kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2;
1523 rootCfg.div = 1;
1524 CLOCK_SetRootClock(kCLOCK_Root_Csi, &rootCfg);
1525
1526 /* Configure CKO1 using OSC_RC_48M_DIV2 */
1527 rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2;
1528 rootCfg.div = 1;
1529 CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg);
1530
1531 /* Configure CKO2 using OSC_RC_48M_DIV2 */
1532 rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2;
1533 rootCfg.div = 1;
1534 CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg);
1535
1536 /* Set SAI1 MCLK1 clock source. */
1537 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
1538 /* Set SAI1 MCLK2 clock source. */
1539 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 3);
1540 /* Set SAI1 MCLK3 clock source. */
1541 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
1542 /* Set SAI2 MCLK3 clock source. */
1543 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
1544 /* Set SAI3 MCLK3 clock source. */
1545 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
1546
1547 /* Set MQS configuration. */
1548 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
1549 /* Set ENET Ref clock source. */
1550 IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK;
1551 /* Set ENET_1G Tx clock source. */
1552 IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK);
1553 /* Set ENET_1G Ref clock source. */
1554 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK;
1555 /* Set GPT1 High frequency reference clock source. */
1556 IOMUXC_GPR->GPR22 &= ~IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK;
1557 /* Set GPT2 High frequency reference clock source. */
1558 IOMUXC_GPR->GPR23 &= ~IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK;
1559 /* Set GPT3 High frequency reference clock source. */
1560 IOMUXC_GPR->GPR24 &= ~IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK;
1561 /* Set GPT4 High frequency reference clock source. */
1562 IOMUXC_GPR->GPR25 &= ~IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK;
1563 /* Set GPT5 High frequency reference clock source. */
1564 IOMUXC_GPR->GPR26 &= ~IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK;
1565 /* Set GPT6 High frequency reference clock source. */
1566 IOMUXC_GPR->GPR27 &= ~IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK;
1567
1568 #if __CORTEX_M == 7
1569 SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7);
1570 #else
1571 SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M4);
1572 #endif
1573 }
1574
