1 /**************************************************************************//** 2 * @file bmc_reg.h 3 * @version V3.00 4 * @brief BMC register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __BMC_REG_H__ 10 #define __BMC_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup BMC Biphase Mark Coding Controller (BMC) 23 Memory Mapped Structure for BMC Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var BMC_T::CTL 32 * Offset: 0x00 Biphase Mask Coding Control Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[0] |BMCEN |Biphase Mask Coding Enable 37 * | | |0 = Biphase Mask Coding function is Disabled. It is cleared after current frame data transfer done. 38 * | | |1 = Biphase Mask Coding function is Enabled. 39 * |[1] |BWADJ |Bit Width Adjustment 1.5 Time 40 * | | |0 = The bit time period of Logic '0' is same as Logic '1'. 41 * | | |1 = The bit time period of Logic '0' is 1.5 times as Logic '1'. 42 * | | |Note: When this bit is set, the PDMA 43 * |[2] |PREAM32 |Preamble Bit Number 32 44 * | | |0 = The bit number of Preamble is 64 bits. 45 * | | |1 = The bit number of Preamble is 32 bits. 46 * |[3] |DUMLVL |Dummy Bit Level 47 * | | |0 = The logic level of dummy bit is LOW. 48 * | | |1 = The logic level of dummy bit is HIGH. 49 * |[4] |DMAEN |PDMA Channel Enable 50 * | | |0 = PDMA function Disabled. 51 * | | |1 = PDMA function Enabled. 52 * |[8] |G0CHEN |BMC Group 0 Channel Enable 53 * | | |0 = BMC Channel 0~3 Disabled. 54 * | | |1 = BMC Channel 0~3 Enabled. 55 * |[9] |G1CHEN |BMC Group 1 Channel Enable 56 * | | |0 = BMC Channel 4~7 Disabled. 57 * | | |1 = BMC Channel 4~7 Enabled. 58 * |[10] |G2CHEN |BMC Group 2 Channel Enable 59 * | | |0 = BMC Channel 8~11 Disabled. 60 * | | |1 = BMC Channel 8~11 Enabled. 61 * |[11] |G3CHEN |BMC Group 3 Channel Enable 62 * | | |0 = BMC Channel 12~15 Disabled. 63 * | | |1 = BMC Channel 12~15 Enabled. 64 * |[12] |G4CHEN |BMC Group 4 Channel Enable 65 * | | |0 = BMC Channel 16~19 Disabled. 66 * | | |1 = BMC Channel 16~19 Enabled. 67 * |[13] |G5CHEN |BMC Group 5 Channel Enable 68 * | | |0 = BMC Channel 20~23 Disabled. 69 * | | |1 = BMC Channel 20~23 Enabled. 70 * |[14] |G6CHEN |BMC Group 6 Channel Enable 71 * | | |0 = BMC Channel 24~27 Disabled. 72 * | | |1 = BMC Channel 24~27 Enabled. 73 * |[15] |G7CHEN |BMC Group 7 Channel Enable 74 * | | |0 = BMC Channel 28~31 Disabled. 75 * | | |1 = BMC Channel 28~31 Enabled. 76 * |[24:16] |BTDIV |Bit Time Divider 77 * | | |These bit field indicates the half bit time divider for Biphase Mask Coding bit. 78 * | | |For example, if the HCLK is 200 MHz, the divider can be set as 0x64 79 * | | |It will generate 2 MHz reference clock and the Biphase Mask Coding transmitting data is sent according the reference divided clock. 80 * @var BMC_T::DNUM0 81 * Offset: 0x04 Biphase Mask Coding Dummy Bit Number Channel Group 0~3 Register 82 * --------------------------------------------------------------------------------------------------- 83 * |Bits |Field |Descriptions 84 * | :----: | :----: | :---- | 85 * |[7:0] |DNUMG0 |Dummy Number for Channel 0~3 86 * | | |These bit field defines the dummy bit number for the group of channel 0~3 87 * | | |Each dummy bit equal 8 bit data period. 88 * |[15:8] |DNUMG1 |Dummy Number for Channel 4~7 89 * | | |These bit field defines the dummy bit number for the group of channel 4~7 90 * | | |Each dummy bit equal 8 bit data period. 91 * |[23:16] |DNUMG2 |Dummy Number for Channel 8~11 92 * | | |These bit field defines the dummy bit number for the group of channel 8~11 93 * | | |Each dummy bit equal 8 bit data period. 94 * |[31:24] |DNUMG3 |Dummy Number for Channel 12~15 95 * | | |These bit field defines the dummy bit number for the group of channel 12~15 96 * | | |Each dummy bit equal 8 bit data period. 97 * @var BMC_T::DNUM1 98 * Offset: 0x08 Biphase Mask Coding Dummy Bit Number Channel Group 4~7 Register 99 * --------------------------------------------------------------------------------------------------- 100 * |Bits |Field |Descriptions 101 * | :----: | :----: | :---- | 102 * |[7:0] |DNUMG4 |Dummy Number for Channel 16~19 103 * | | |These bit field defines the dummy bit number for the group of channel 16~19 104 * | | |Each dummy bit equal 8 bit data period. 105 * |[15:8] |DNUMG5 |Dummy Number for Channel 20~23 106 * | | |These bit field defines the dummy bit number for the group of channel 20~23 107 * | | |Each dummy bit equal 8 bit data period. 108 * |[23:16] |DNUMG6 |Dummy Number for Channel 24~27 109 * | | |These bit field defines the dummy bit number for the group of channel 24~27 110 * | | |Each dummy bit equal 8 bit data period. 111 * |[31:24] |DNUMG7 |Dummy Number for Channel 28~31 112 * | | |These bit field defines the dummy bit number for the group of channel 28~31 113 * | | |Each dummy bit equal 8 bit data period. 114 * @var BMC_T::INTEN 115 * Offset: 0x0C Biphase Mask Coding Interrupt Enable Register 116 * --------------------------------------------------------------------------------------------------- 117 * |Bits |Field |Descriptions 118 * | :----: | :----: | :---- | 119 * |[0] |FTXDIEN |Frame Transmit Done Interrupt Enable Bit 120 * | | |0 = Frame transmit done interrupt Disabled. 121 * | | |1 = Frame transmit done interrupt Enabled. 122 * |[1] |TXUNDIEN |Transmit Data Under Run Interrupt Enable Bit 123 * | | |0 = Transmit data register under run interrupt Disabled. 124 * | | |1 = Transmit data register under run interrupt Enabled. 125 * @var BMC_T::INTSTS 126 * Offset: 0x10 Biphase Mask Coding Interrupt Status Register 127 * --------------------------------------------------------------------------------------------------- 128 * |Bits |Field |Descriptions 129 * | :----: | :----: | :---- | 130 * |[0] |FTXDIF |Frame Transmit Done Interrupt Flag 131 * | | |0 = No frame transmit done interrupt flag. 132 * | | |1 = Frame transmit done interrupt flag. Write 1 to clear. 133 * |[1] |TXUNDIF |Transmit Data Register Under Run Interrupt Flag 134 * | | |0 = No transmit data register under run interrupt flag. 135 * | | |1 = Transmit data register under interrupt flag. This bit is the OR function of BMC_INTSTS[15:8]. 136 * |[8] |G0TXUND |Channel 0~3 Transmit Data Under Run 137 * | | |0 = No Transmit data under run active in one of channel 0~3. 138 * | | |1 = Transmit data under run active in one of channel 0~3. Write 1 to clear. 139 140 * |[9] |G1TXUND |Channel 4~7 Transmit Data Under Run 141 * | | |0 = No Transmit data under run active in one of channel 4~7. 142 * | | |1 = Transmit data under run active in one of channel 4~7. Write 1 to clear. 143 * |[10] |G2TXUND |Channel 8~11 Transmit Data Under Run 144 * | | |0 = No Transmit data under run active in one of channel 8~11. 145 * | | |1 = Transmit data under run active in one of channel 8~11. Write 1 to clear. 146 * |[10] |G3TXUND |Channel 12~15 Transmit Data Under Run 147 * | | |0 = No Transmit data under run active in one of channel 12~15. 148 * | | |1 = Transmit data under run active in one of channel 12~15. Write 1 to clear. 149 * |[12] |G4TXUND |Channel 16~19 Transmit Data Under Run 150 * | | |0 = No Transmit data under run active in one of channel 16~19. 151 * | | |1 = Transmit data under run active in one of channel 16~19. Write 1 to clear. 152 * |[13] |G5TXUND |Channel 20~23 Transmit Data Under Run 153 * | | |0 = No Transmit data under run active in one of channel 20~23. 154 * | | |1 = Transmit data under run active in one of channel 20~23. Write 1 to clear. 155 * |[14] |G6TXUND |Channel 24~27 Transmit Data Under Run 156 * | | |0 = No Transmit data under run active in one of channel 24~27. 157 * | | |1 = Transmit data under run active in one of channel 24~27. Write 1 to clear. 158 * |[15] |G7TXUND |Channel 28~31 Transmit Data Under Run 159 * | | |0 = No Transmit data under run active in one of channel 28~31. 160 * | | |1 = Transmit data under run active in one of channel 28~31. Write 1 to clear. 161 * @var BMC_T::CHEMPTY 162 * Offset: 0x14 Biphase Mask Coding Channel Done Status Register 163 * --------------------------------------------------------------------------------------------------- 164 * |Bits |Field |Descriptions 165 * | :----: | :----: | :---- | 166 * |[0] |CH0EPT |BMC Channel 0 Current FIFO Empty 167 * | | |0 = The current transmitted FIFO no empty. 168 * | | |1 = The current transmitted FIFO empty. 169 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 170 * |[1] |CH1EPT |BMC Channel 1 Current FIFO Empty 171 * | | |0 = The current transmitted FIFO no empty. 172 * | | |1 = The current transmitted FIFO empty. 173 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 174 * |[2] |CH2EPT |BMC Channel 2 Current FIFO Empty 175 * | | |0 = The current transmitted FIFO no empty. 176 * | | |1 = The current transmitted FIFO empty. 177 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 178 * |[3] |CH3EPT |BMC Channel 3 Current FIFO Empty 179 * | | |0 = The current transmitted FIFO no empty. 180 * | | |1 = The current transmitted FIFO empty. 181 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 182 * |[4] |CH4EPT |BMC Channel 4 Current FIFO Empty 183 * | | |0 = The current transmitted FIFO no empty. 184 * | | |1 = The current transmitted FIFO empty. 185 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 186 * |[5] |CH5EPT |BMC Channel 5 Current FIFO Empty 187 * | | |0 = The current transmitted FIFO no empty. 188 * | | |1 = The current transmitted FIFO empty. 189 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 190 * |[6] |CH6EPT |BMC Channel 6 Current FIFO Empty 191 * | | |0 = The current transmitted FIFO no empty. 192 * | | |1 = The current transmitted FIFO empty. 193 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 194 * |[7] |CH7EPT |BMC Channel 7 Current FIFO Empty 195 * | | |0 = The current transmitted FIFO no empty. 196 * | | |1 = The current transmitted FIFO empty. 197 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 198 * |[8] |CH8EPT |BMC Channel 8 Current FIFO Empty 199 * | | |0 = The current transmitted FIFO no empty. 200 * | | |1 = The current transmitted FIFO empty. 201 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 202 * |[9] |CH9EPT |BMC Channel 9 Current FIFO Empty 203 * | | |0 = The current transmitted FIFO no empty. 204 * | | |1 = The current transmitted FIFO empty. 205 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 206 * |[10] |CH10EPT |BMC Channel 10 Current FIFO Empty 207 * | | |0 = The current transmitted FIFO no empty. 208 * | | |1 = The current transmitted FIFO empty. 209 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 210 * |[11] |CH11EPT |BMC Channel 11 Current FIFO Empty 211 * | | |0 = The current transmitted FIFO no empty. 212 * | | |1 = The current transmitted FIFO empty. 213 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 214 * |[12] |CH12EPT |BMC Channel 12 Current FIFO Empty 215 * | | |0 = The current transmitted FIFO no empty. 216 * | | |1 = The current transmitted FIFO empty. 217 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 218 * |[13] |CH13EPT |BMC Channel 13 Current FIFO Empty 219 * | | |0 = The current transmitted FIFO no empty. 220 * | | |1 = The current transmitted FIFO empty. 221 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 222 * |[14] |CH14EPT |BMC Channel 14 Current FIFO Empty 223 * | | |0 = The current transmitted FIFO no empty. 224 * | | |1 = The current transmitted FIFO empty. 225 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 226 * |[15] |CH15EPT |BMC Channel 15 Current FIFO Empty 227 * | | |0 = The current transmitted FIFO no empty. 228 * | | |1 = The current transmitted FIFO empty. 229 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 230 * |[16] |CH16EPT |BMC Channel 16 Current FIFO Empty 231 * | | |0 = The current transmitted FIFO no empty. 232 * | | |1 = The current transmitted FIFO empty. 233 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 234 * |[17] |CH17EPT |BMC Channel 17 Current FIFO Empty 235 * | | |0 = The current transmitted FIFO no empty. 236 * | | |1 = The current transmitted FIFO empty. 237 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 238 * |[18] |CH18EPT |BMC Channel 18 Current FIFO Empty 239 * | | |0 = The current transmitted FIFO no empty. 240 * | | |1 = The current transmitted FIFO empty. 241 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 242 * |[19] |CH19EPT |BMC Channel 19 Current FIFO Empty 243 * | | |0 = The current transmitted FIFO no empty. 244 * | | |1 = The current transmitted FIFO empty. 245 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 246 * |[20] |CH20EPT |BMC Channel 20 Current FIFO Empty 247 * | | |0 = The current transmitted FIFO no empty. 248 * | | |1 = The current transmitted FIFO empty. 249 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 250 * |[21] |CH21EPT |BMC Channel 21 Current FIFO Empty 251 * | | |0 = The current transmitted FIFO no empty. 252 * | | |1 = The current transmitted FIFO empty. 253 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 254 * |[22] |CH22EPT |BMC Channel 22 Current FIFO Empty 255 * | | |0 = The current transmitted FIFO no empty. 256 * | | |1 = The current transmitted FIFO empty. 257 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 258 * |[23] |CH23EPT |BMC Channel 23 Current FIFO Empty 259 * | | |0 = The current transmitted FIFO no empty. 260 * | | |1 = The current transmitted FIFO empty. 261 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 262 * |[24] |CH24EPT |BMC Channel 24 Current FIFO Empty 263 * | | |0 = The current transmitted FIFO no empty. 264 * | | |1 = The current transmitted FIFO empty. 265 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 266 * |[25] |CH25EPT |BMC Channel 25 Current FIFO Empty 267 * | | |0 = The current transmitted FIFO no empty. 268 * | | |1 = The current transmitted FIFO empty. 269 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 270 * |[26] |CH26EPT |BMC Channel 26 Current FIFO Empty 271 * | | |0 = The current transmitted FIFO no empty. 272 * | | |1 = The current transmitted FIFO empty. 273 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 274 * |[27] |CH27EPT |BMC Channel 27 Current FIFO Empty 275 * | | |0 = The current transmitted FIFO no empty. 276 * | | |1 = The current transmitted FIFO empty. 277 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 278 * |[28] |CH28EPT |BMC Channel 28 Current FIFO Empty 279 * | | |0 = The current transmitted FIFO no empty. 280 * | | |1 = The current transmitted FIFO empty. 281 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 282 * |[29] |CH29EPT |BMC Channel 29 Current FIFO Empty 283 * | | |0 = The current transmitted FIFO no empty. 284 * | | |1 = The current transmitted FIFO empty. 285 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 286 * |[30] |CH30EPT |BMC Channel 30 Current FIFO Empty 287 * | | |0 = The current transmitted FIFO no empty. 288 * | | |1 = The current transmitted FIFO empty. 289 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 290 * |[31] |CH31EPT |BMC Channel 31 Current FIFO Empty 291 * | | |0 = The current transmitted FIFO no empty. 292 * | | |1 = The current transmitted FIFO empty. 293 * | | |Note: This bit be clear automatically by writing the relative channel data (byte). 294 * @var BMC_T::TXDATG0 295 * Offset: 0x18 Biphase Mask Coding Transmit Data Group 0 Register 296 * --------------------------------------------------------------------------------------------------- 297 * |Bits |Field |Descriptions 298 * | :----: | :----: | :---- | 299 * |[4:0] |CH0_TXDAT |Biphase Mask Coding Channel 0 Transmit Data 300 * | | |The bits field indicates the transmit data buffer for channel 0. 301 * |[12:8] |CH1_TXDAT |Biphase Mask Coding Channel 1 Transmit Data 302 * | | |The bits field indicates the transmit data buffer for channel 1. 303 * |[20:16] |CH2_TXDAT |Biphase Mask Coding Channel 2 Transmit Data 304 * | | |The bits field indicates the transmit data buffer for channel 2. 305 * |[28:24] |CH3_TXDAT |Biphase Mask Coding Channel 3 Transmit Data 306 * | | |The bits field indicates the transmit data buffer for channel 3. 307 * @var BMC_T::TXDATG1 308 * Offset: 0x1C Biphase Mask Coding Transmit Data Group 1 Register 309 * --------------------------------------------------------------------------------------------------- 310 * |Bits |Field |Descriptions 311 * | :----: | :----: | :---- | 312 * |[4:0] |CH4_TXDAT |Biphase Mask Coding Channel 4 Transmit Data 313 * | | |The bits field indicates the transmit data buffer for channel 4. 314 * |[12:8] |CH5_TXDAT |Biphase Mask Coding Channel 5 Transmit Data 315 * | | |The bits field indicates the transmit data buffer for channel 5. 316 * |[20:16] |CH6_TXDAT |Biphase Mask Coding Channel 6 Transmit Data 317 * | | |The bits field indicates the transmit data buffer for channel 6. 318 * |[28:24] |CH7_TXDAT |Biphase Mask Coding Channel 7 Transmit Data 319 * | | |The bits field indicates the transmit data buffer for channel 7. 320 * @var BMC_T::TXDATG2 321 * Offset: 0x20 Biphase Mask Coding Transmit Data Group 2 Register 322 * --------------------------------------------------------------------------------------------------- 323 * |Bits |Field |Descriptions 324 * | :----: | :----: | :---- | 325 * |[4:0] |CH8_TXDAT |Biphase Mask Coding Channel 8 Transmit Data 326 * | | |The bits field indicates the transmit data buffer for channel 8. 327 * |[12:8] |CH9_TXDAT |Biphase Mask Coding Channel 9 Transmit Data 328 * | | |The bits field indicates the transmit data buffer for channel 9. 329 * |[20:16] |CH10_TXDAT|Biphase Mask Coding Channel 10 Transmit Data 330 * | | |The bits field indicates the transmit data buffer for channel 10. 331 * |[28:24] |CH11_TXDAT|Biphase Mask Coding Channel 11 Transmit Data 332 * | | |The bits field indicates the transmit data buffer for channel 11. 333 * @var BMC_T::TXDATG3 334 * Offset: 0x24 Biphase Mask Coding Transmit Data Group 3 Register 335 * --------------------------------------------------------------------------------------------------- 336 * |Bits |Field |Descriptions 337 * | :----: | :----: | :---- | 338 * |[4:0] |CH12_TXDAT|Biphase Mask Coding Channel 12 Transmit Data 339 * | | |The bits field indicates the transmit data buffer for channel 12. 340 * |[12:8] |CH13_TXDAT|Biphase Mask Coding Channel 13 Transmit Data 341 * | | |The bits field indicates the transmit data buffer for channel 13. 342 * |[20:16] |CH14_TXDAT|Biphase Mask Coding Channel 14 Transmit Data 343 * | | |The bits field indicates the transmit data buffer for channel 14. 344 * |[28:24] |CH15_TXDAT|Biphase Mask Coding Channel 15 Transmit Data 345 * | | |The bits field indicates the transmit data buffer for channel 15. 346 * @var BMC_T::TXDATG4 347 * Offset: 0x28 Biphase Mask Coding Transmit Data Group 4 Register 348 * --------------------------------------------------------------------------------------------------- 349 * |Bits |Field |Descriptions 350 * | :----: | :----: | :---- | 351 * |[4:0] |CH16_TXDAT|Biphase Mask Coding Channel 16 Transmit Data 352 * | | |The bits field indicates the transmit data buffer for channel 16. 353 * |[12:8] |CH17_TXDAT|Biphase Mask Coding Channel 17 Transmit Data 354 * | | |The bits field indicates the transmit data buffer for channel 17. 355 * |[20:16] |CH18_TXDAT|Biphase Mask Coding Channel 18 Transmit Data 356 * | | |The bits field indicates the transmit data buffer for channel 18. 357 * |[28:24] |CH19_TXDAT|Biphase Mask Coding Channel 19 Transmit Data 358 * | | |The bits field indicates the transmit data buffer for channel 19. 359 * @var BMC_T::TXDATG5 360 * Offset: 0x2C Biphase Mask Coding Transmit Data Group 5 Register 361 * --------------------------------------------------------------------------------------------------- 362 * |Bits |Field |Descriptions 363 * | :----: | :----: | :---- | 364 * |[4:0] |CH20_TXDAT|Biphase Mask Coding Channel 20 Transmit Data 365 * | | |The bits field indicates the transmit data buffer for channel 20. 366 * |[12:8] |CH21_TXDAT|Biphase Mask Coding Channel 21 Transmit Data 367 * | | |The bits field indicates the transmit data buffer for channel 21. 368 * |[20:16] |CH22_TXDAT|Biphase Mask Coding Channel 22 Transmit Data 369 * | | |The bits field indicates the transmit data buffer for channel 22. 370 * |[28:24] |CH23_TXDAT|Biphase Mask Coding Channel 23 Transmit Data 371 * | | |The bits field indicates the transmit data buffer for channel 23. 372 * @var BMC_T::TXDATG6 373 * Offset: 0x30 Biphase Mask Coding Transmit Data Group 6 Register 374 * --------------------------------------------------------------------------------------------------- 375 * |Bits |Field |Descriptions 376 * | :----: | :----: | :---- | 377 * |[4:0] |CH24_TXDAT|Biphase Mask Coding Channel 24 Transmit Data 378 * | | |The bits field indicates the transmit data buffer for channel 24. 379 * |[12:8] |CH25_TXDAT|Biphase Mask Coding Channel 25 Transmit Data 380 * | | |The bits field indicates the transmit data buffer for channel 25. 381 * |[20:16] |CH26_TXDAT|Biphase Mask Coding Channel 26 Transmit Data 382 * | | |The bits field indicates the transmit data buffer for channel 26. 383 * |[28:24] |CH27_TXDAT|Biphase Mask Coding Channel 27 Transmit Data 384 * | | |The bits field indicates the transmit data buffer for channel 27. 385 * @var BMC_T::TXDATG7 386 * Offset: 0x34 Biphase Mask Coding Transmit Data Group 7 Register 387 * --------------------------------------------------------------------------------------------------- 388 * |Bits |Field |Descriptions 389 * | :----: | :----: | :---- | 390 * |[4:0] |CH28_TXDAT|Biphase Mask Coding Channel 28 Transmit Data 391 * | | |The bits field indicates the transmit data buffer for channel 28. 392 * |[12:8] |CH29_TXDAT|Biphase Mask Coding Channel 29 Transmit Data 393 * | | |The bits field indicates the transmit data buffer for channel 29. 394 * |[20:16] |CH30_TXDAT|Biphase Mask Coding Channel 30 Transmit Data 395 * | | |The bits field indicates the transmit data buffer for channel 30. 396 * |[28:24] |CH31_TXDAT|Biphase Mask Coding Channel 31 Transmit Data 397 * | | |The bits field indicates the transmit data buffer for channel 31. 398 */ 399 __IO uint32_t CTL; /*!< [0x0000] Biphase Mask Coding Control Register */ 400 __IO uint32_t DNUM0; /*!< [0x0004] Biphase Mask Coding Dummy Bit Number Channel Group 0~3 Register */ 401 __IO uint32_t DNUM1; /*!< [0x0008] Biphase Mask Coding Dummy Bit Number Channel Group 4~7 Register */ 402 __IO uint32_t INTEN; /*!< [0x000c] Biphase Mask Coding Interrupt Enable Register */ 403 __IO uint32_t INTSTS; /*!< [0x0010] Biphase Mask Coding Interrupt Status Register */ 404 __IO uint32_t CHEMPTY; /*!< [0x0014] Biphase Mask Coding Channel Done Status Register */ 405 __O uint32_t TXDATG0; /*!< [0x0018] Biphase Mask Coding Transmit Data Group 0 Register */ 406 __O uint32_t TXDATG1; /*!< [0x001c] Biphase Mask Coding Transmit Data Group 1 Register */ 407 __O uint32_t TXDATG2; /*!< [0x0020] Biphase Mask Coding Transmit Data Group 2 Register */ 408 __O uint32_t TXDATG3; /*!< [0x0024] Biphase Mask Coding Transmit Data Group 3 Register */ 409 __O uint32_t TXDATG4; /*!< [0x0028] Biphase Mask Coding Transmit Data Group 4 Register */ 410 __O uint32_t TXDATG5; /*!< [0x002c] Biphase Mask Coding Transmit Data Group 5 Register */ 411 __O uint32_t TXDATG6; /*!< [0x0030] Biphase Mask Coding Transmit Data Group 6 Register */ 412 __O uint32_t TXDATG7; /*!< [0x0034] Biphase Mask Coding Transmit Data Group 7 Register */ 413 414 } BMC_T; 415 416 /** 417 @addtogroup BMC_CONST BMC Bit Field Definition 418 Constant Definitions for BMC Controller 419 @{ */ 420 421 #define BMC_CTL_BMCEN_Pos (0) /*!< BMC_T::CTL: BMCEN Position */ 422 #define BMC_CTL_BMCEN_Msk (0x1ul << BMC_CTL_BMCEN_Pos) /*!< BMC_T::CTL: BMCEN Mask */ 423 424 #define BMC_CTL_BWADJ_Pos (1) /*!< BMC_T::CTL: BWADJ Position */ 425 #define BMC_CTL_BWADJ_Msk (0x1ul << BMC_CTL_BWADJ_Pos) /*!< BMC_T::CTL: BWADJ Mask */ 426 427 #define BMC_CTL_PREAM32_Pos (2) /*!< BMC_T::CTL: PREAM32 Position */ 428 #define BMC_CTL_PREAM32_Msk (0x1ul << BMC_CTL_PREAM32_Pos) /*!< BMC_T::CTL: PREAM32 Mask */ 429 430 #define BMC_CTL_DUMLVL_Pos (3) /*!< BMC_T::CTL: DUMLVL Position */ 431 #define BMC_CTL_DUMLVL_Msk (0x1ul << BMC_CTL_DUMLVL_Pos) /*!< BMC_T::CTL: DUMLVL Mask */ 432 433 #define BMC_CTL_DMAEN_Pos (4) /*!< BMC_T::CTL: DMAEN Position */ 434 #define BMC_CTL_DMAEN_Msk (0x1ul << BMC_CTL_DMAEN_Pos) /*!< BMC_T::CTL: DMAEN Mask */ 435 436 #define BMC_CTL_G0CHEN_Pos (8) /*!< BMC_T::CTL: G0CHEN Position */ 437 #define BMC_CTL_G0CHEN_Msk (0x1ul << BMC_CTL_G0CHEN_Pos) /*!< BMC_T::CTL: G0CHEN Mask */ 438 439 #define BMC_CTL_G1CHEN_Pos (9) /*!< BMC_T::CTL: G1CHEN Position */ 440 #define BMC_CTL_G1CHEN_Msk (0x1ul << BMC_CTL_G1CHEN_Pos) /*!< BMC_T::CTL: G1CHEN Mask */ 441 442 #define BMC_CTL_G2CHEN_Pos (10) /*!< BMC_T::CTL: G2CHEN Position */ 443 #define BMC_CTL_G2CHEN_Msk (0x1ul << BMC_CTL_G2CHEN_Pos) /*!< BMC_T::CTL: G2CHEN Mask */ 444 445 #define BMC_CTL_G3CHEN_Pos (11) /*!< BMC_T::CTL: G3CHEN Position */ 446 #define BMC_CTL_G3CHEN_Msk (0x1ul << BMC_CTL_G3CHEN_Pos) /*!< BMC_T::CTL: G3CHEN Mask */ 447 448 #define BMC_CTL_G4CHEN_Pos (12) /*!< BMC_T::CTL: G4CHEN Position */ 449 #define BMC_CTL_G4CHEN_Msk (0x1ul << BMC_CTL_G4CHEN_Pos) /*!< BMC_T::CTL: G4CHEN Mask */ 450 451 #define BMC_CTL_G5CHEN_Pos (13) /*!< BMC_T::CTL: G5CHEN Position */ 452 #define BMC_CTL_G5CHEN_Msk (0x1ul << BMC_CTL_G5CHEN_Pos) /*!< BMC_T::CTL: G5CHEN Mask */ 453 454 #define BMC_CTL_G6CHEN_Pos (14) /*!< BMC_T::CTL: G6CHEN Position */ 455 #define BMC_CTL_G6CHEN_Msk (0x1ul << BMC_CTL_G6CHEN_Pos) /*!< BMC_T::CTL: G6CHEN Mask */ 456 457 #define BMC_CTL_G7CHEN_Pos (15) /*!< BMC_T::CTL: G7CHEN Position */ 458 #define BMC_CTL_G7CHEN_Msk (0x1ul << BMC_CTL_G7CHEN_Pos) /*!< BMC_T::CTL: G7CHEN Mask */ 459 460 #define BMC_CTL_BTDIV_Pos (16) /*!< BMC_T::CTL: BTDIV Position */ 461 #define BMC_CTL_BTDIV_Msk (0x1fful << BMC_CTL_BTDIV_Pos) /*!< BMC_T::CTL: BTDIV Mask */ 462 463 #define BMC_DNUM0_DNUMG0_Pos (0) /*!< BMC_T::DNUM0: DNUMG0 Position */ 464 #define BMC_DNUM0_DNUMG0_Msk (0xfful << BMC_DNUM0_DNUMG0_Pos) /*!< BMC_T::DNUM0: DNUMG0 Mask */ 465 466 #define BMC_DNUM0_DNUMG1_Pos (8) /*!< BMC_T::DNUM0: DNUMG1 Position */ 467 #define BMC_DNUM0_DNUMG1_Msk (0xfful << BMC_DNUM0_DNUMG1_Pos) /*!< BMC_T::DNUM0: DNUMG1 Mask */ 468 469 #define BMC_DNUM0_DNUMG2_Pos (16) /*!< BMC_T::DNUM0: DNUMG2 Position */ 470 #define BMC_DNUM0_DNUMG2_Msk (0xfful << BMC_DNUM0_DNUMG2_Pos) /*!< BMC_T::DNUM0: DNUMG2 Mask */ 471 472 #define BMC_DNUM0_DNUMG3_Pos (24) /*!< BMC_T::DNUM0: DNUMG3 Position */ 473 #define BMC_DNUM0_DNUMG3_Msk (0xfful << BMC_DNUM0_DNUMG3_Pos) /*!< BMC_T::DNUM0: DNUMG3 Mask */ 474 475 #define BMC_DNUM1_DNUMG4_Pos (0) /*!< BMC_T::DNUM1: DNUMG4 Position */ 476 #define BMC_DNUM1_DNUMG4_Msk (0xfful << BMC_DNUM1_DNUMG4_Pos) /*!< BMC_T::DNUM1: DNUMG4 Mask */ 477 478 #define BMC_DNUM1_DNUMG5_Pos (8) /*!< BMC_T::DNUM1: DNUMG5 Position */ 479 #define BMC_DNUM1_DNUMG5_Msk (0xfful << BMC_DNUM1_DNUMG5_Pos) /*!< BMC_T::DNUM1: DNUMG5 Mask */ 480 481 #define BMC_DNUM1_DNUMG6_Pos (16) /*!< BMC_T::DNUM1: DNUMG6 Position */ 482 #define BMC_DNUM1_DNUMG6_Msk (0xfful << BMC_DNUM1_DNUMG6_Pos) /*!< BMC_T::DNUM1: DNUMG6 Mask */ 483 484 #define BMC_DNUM1_DNUMG7_Pos (24) /*!< BMC_T::DNUM1: DNUMG7 Position */ 485 #define BMC_DNUM1_DNUMG7_Msk (0xfful << BMC_DNUM1_DNUMG7_Pos) /*!< BMC_T::DNUM1: DNUMG7 Mask */ 486 487 #define BMC_INTEN_FTXDIEN_Pos (0) /*!< BMC_T::INTEN: FTXDIEN Position */ 488 #define BMC_INTEN_FTXDIEN_Msk (0x1ul << BMC_INTEN_FTXDIEN_Pos) /*!< BMC_T::INTEN: FTXDIEN Mask */ 489 490 #define BMC_INTEN_TXUNDIEN_Pos (1) /*!< BMC_T::INTEN: TXUNDIEN Position */ 491 #define BMC_INTEN_TXUNDIEN_Msk (0x1ul << BMC_INTEN_TXUNDIEN_Pos) /*!< BMC_T::INTEN: TXUNDIEN Mask */ 492 493 #define BMC_INTSTS_FTXDIF_Pos (0) /*!< BMC_T::INTSTS: FTXDIF Position */ 494 #define BMC_INTSTS_FTXDIF_Msk (0x1ul << BMC_INTSTS_FTXDIF_Pos) /*!< BMC_T::INTSTS: FTXDIF Mask */ 495 496 #define BMC_INTSTS_TXUNDIF_Pos (1) /*!< BMC_T::INTSTS: TXUNDIF Position */ 497 #define BMC_INTSTS_TXUNDIF_Msk (0x1ul << BMC_INTSTS_TXUNDIF_Pos) /*!< BMC_T::INTSTS: TXUNDIF Mask */ 498 499 #define BMC_INTSTS_G0TXUND_Pos (8) /*!< BMC_T::INTSTS: G0TXUND Position */ 500 #define BMC_INTSTS_G0TXUND_Msk (0x1ul << BMC_INTSTS_G0TXUND_Pos) /*!< BMC_T::INTSTS: G0TXUND Mask */ 501 502 #define BMC_INTSTS_G1TXUND_Pos (9) /*!< BMC_T::INTSTS: G1TXUND Position */ 503 #define BMC_INTSTS_G1TXUND_Msk (0x1ul << BMC_INTSTS_G1TXUND_Pos) /*!< BMC_T::INTSTS: G1TXUND Mask */ 504 505 #define BMC_INTSTS_G2TXUND_Pos (10) /*!< BMC_T::INTSTS: G2TXUND Position */ 506 #define BMC_INTSTS_G2TXUND_Msk (0x1ul << BMC_INTSTS_G2TXUND_Pos) /*!< BMC_T::INTSTS: G2TXUND Mask */ 507 508 #define BMC_INTSTS_G3TXUND_Pos (11) /*!< BMC_T::INTSTS: G3TXUND Position */ 509 #define BMC_INTSTS_G3TXUND_Msk (0x1ul << BMC_INTSTS_G3TXUND_Pos) /*!< BMC_T::INTSTS: G3TXUND Mask */ 510 511 #define BMC_INTSTS_G4TXUND_Pos (12) /*!< BMC_T::INTSTS: G4TXUND Position */ 512 #define BMC_INTSTS_G4TXUND_Msk (0x1ul << BMC_INTSTS_G4TXUND_Pos) /*!< BMC_T::INTSTS: G4TXUND Mask */ 513 514 #define BMC_INTSTS_G5TXUND_Pos (13) /*!< BMC_T::INTSTS: G5TXUND Position */ 515 #define BMC_INTSTS_G5TXUND_Msk (0x1ul << BMC_INTSTS_G5TXUND_Pos) /*!< BMC_T::INTSTS: G5TXUND Mask */ 516 517 #define BMC_INTSTS_G6TXUND_Pos (14) /*!< BMC_T::INTSTS: G6TXUND Position */ 518 #define BMC_INTSTS_G6TXUND_Msk (0x1ul << BMC_INTSTS_G6TXUND_Pos) /*!< BMC_T::INTSTS: G6TXUND Mask */ 519 520 #define BMC_INTSTS_G7TXUND_Pos (15) /*!< BMC_T::INTSTS: G7TXUND Position */ 521 #define BMC_INTSTS_G7TXUND_Msk (0x1ul << BMC_INTSTS_G7TXUND_Pos) /*!< BMC_T::INTSTS: G7TXUND Mask */ 522 523 #define BMC_CHEMPTY_CH0EPT_Pos (0) /*!< BMC_T::CHEMPTY: CH0EPT Position */ 524 #define BMC_CHEMPTY_CH0EPT_Msk (0x1ul << BMC_CHEMPTY_CH0EPT_Pos) /*!< BMC_T::CHEMPTY: CH0EPT Mask */ 525 526 #define BMC_CHEMPTY_CH1EPT_Pos (1) /*!< BMC_T::CHEMPTY: CH1EPT Position */ 527 #define BMC_CHEMPTY_CH1EPT_Msk (0x1ul << BMC_CHEMPTY_CH1EPT_Pos) /*!< BMC_T::CHEMPTY: CH1EPT Mask */ 528 529 #define BMC_CHEMPTY_CH2EPT_Pos (2) /*!< BMC_T::CHEMPTY: CH2EPT Position */ 530 #define BMC_CHEMPTY_CH2EPT_Msk (0x1ul << BMC_CHEMPTY_CH2EPT_Pos) /*!< BMC_T::CHEMPTY: CH2EPT Mask */ 531 532 #define BMC_CHEMPTY_CH3EPT_Pos (3) /*!< BMC_T::CHEMPTY: CH3EPT Position */ 533 #define BMC_CHEMPTY_CH3EPT_Msk (0x1ul << BMC_CHEMPTY_CH3EPT_Pos) /*!< BMC_T::CHEMPTY: CH3EPT Mask */ 534 535 #define BMC_CHEMPTY_CH4EPT_Pos (4) /*!< BMC_T::CHEMPTY: CH4EPT Position */ 536 #define BMC_CHEMPTY_CH4EPT_Msk (0x1ul << BMC_CHEMPTY_CH4EPT_Pos) /*!< BMC_T::CHEMPTY: CH4EPT Mask */ 537 538 #define BMC_CHEMPTY_CH5EPT_Pos (5) /*!< BMC_T::CHEMPTY: CH5EPT Position */ 539 #define BMC_CHEMPTY_CH5EPT_Msk (0x1ul << BMC_CHEMPTY_CH5EPT_Pos) /*!< BMC_T::CHEMPTY: CH5EPT Mask */ 540 541 #define BMC_CHEMPTY_CH6EPT_Pos (6) /*!< BMC_T::CHEMPTY: CH6EPT Position */ 542 #define BMC_CHEMPTY_CH6EPT_Msk (0x1ul << BMC_CHEMPTY_CH6EPT_Pos) /*!< BMC_T::CHEMPTY: CH6EPT Mask */ 543 544 #define BMC_CHEMPTY_CH7EPT_Pos (7) /*!< BMC_T::CHEMPTY: CH7EPT Position */ 545 #define BMC_CHEMPTY_CH7EPT_Msk (0x1ul << BMC_CHEMPTY_CH7EPT_Pos) /*!< BMC_T::CHEMPTY: CH7EPT Mask */ 546 547 #define BMC_CHEMPTY_CH8EPT_Pos (8) /*!< BMC_T::CHEMPTY: CH8EPT Position */ 548 #define BMC_CHEMPTY_CH8EPT_Msk (0x1ul << BMC_CHEMPTY_CH8EPT_Pos) /*!< BMC_T::CHEMPTY: CH8EPT Mask */ 549 550 #define BMC_CHEMPTY_CH9EPT_Pos (9) /*!< BMC_T::CHEMPTY: CH9EPT Position */ 551 #define BMC_CHEMPTY_CH9EPT_Msk (0x1ul << BMC_CHEMPTY_CH9EPT_Pos) /*!< BMC_T::CHEMPTY: CH9EPT Mask */ 552 553 #define BMC_CHEMPTY_CH10EPT_Pos (10) /*!< BMC_T::CHEMPTY: CH10EPT Position */ 554 #define BMC_CHEMPTY_CH10EPT_Msk (0x1ul << BMC_CHEMPTY_CH10EPT_Pos) /*!< BMC_T::CHEMPTY: CH10EPT Mask */ 555 556 #define BMC_CHEMPTY_CH11EPT_Pos (11) /*!< BMC_T::CHEMPTY: CH11EPT Position */ 557 #define BMC_CHEMPTY_CH11EPT_Msk (0x1ul << BMC_CHEMPTY_CH11EPT_Pos) /*!< BMC_T::CHEMPTY: CH11EPT Mask */ 558 559 #define BMC_CHEMPTY_CH12EPT_Pos (12) /*!< BMC_T::CHEMPTY: CH12EPT Position */ 560 #define BMC_CHEMPTY_CH12EPT_Msk (0x1ul << BMC_CHEMPTY_CH12EPT_Pos) /*!< BMC_T::CHEMPTY: CH12EPT Mask */ 561 562 #define BMC_CHEMPTY_CH13EPT_Pos (13) /*!< BMC_T::CHEMPTY: CH13EPT Position */ 563 #define BMC_CHEMPTY_CH13EPT_Msk (0x1ul << BMC_CHEMPTY_CH13EPT_Pos) /*!< BMC_T::CHEMPTY: CH13EPT Mask */ 564 565 #define BMC_CHEMPTY_CH14EPT_Pos (14) /*!< BMC_T::CHEMPTY: CH14EPT Position */ 566 #define BMC_CHEMPTY_CH14EPT_Msk (0x1ul << BMC_CHEMPTY_CH14EPT_Pos) /*!< BMC_T::CHEMPTY: CH14EPT Mask */ 567 568 #define BMC_CHEMPTY_CH15EPT_Pos (15) /*!< BMC_T::CHEMPTY: CH15EPT Position */ 569 #define BMC_CHEMPTY_CH15EPT_Msk (0x1ul << BMC_CHEMPTY_CH15EPT_Pos) /*!< BMC_T::CHEMPTY: CH15EPT Mask */ 570 571 #define BMC_CHEMPTY_CH16EPT_Pos (16) /*!< BMC_T::CHEMPTY: CH16EPT Position */ 572 #define BMC_CHEMPTY_CH16EPT_Msk (0x1ul << BMC_CHEMPTY_CH16EPT_Pos) /*!< BMC_T::CHEMPTY: CH16EPT Mask */ 573 574 #define BMC_CHEMPTY_CH17EPT_Pos (17) /*!< BMC_T::CHEMPTY: CH17EPT Position */ 575 #define BMC_CHEMPTY_CH17EPT_Msk (0x1ul << BMC_CHEMPTY_CH17EPT_Pos) /*!< BMC_T::CHEMPTY: CH17EPT Mask */ 576 577 #define BMC_CHEMPTY_CH18EPT_Pos (18) /*!< BMC_T::CHEMPTY: CH18EPT Position */ 578 #define BMC_CHEMPTY_CH18EPT_Msk (0x1ul << BMC_CHEMPTY_CH18EPT_Pos) /*!< BMC_T::CHEMPTY: CH18EPT Mask */ 579 580 #define BMC_CHEMPTY_CH19EPT_Pos (19) /*!< BMC_T::CHEMPTY: CH19EPT Position */ 581 #define BMC_CHEMPTY_CH19EPT_Msk (0x1ul << BMC_CHEMPTY_CH19EPT_Pos) /*!< BMC_T::CHEMPTY: CH19EPT Mask */ 582 583 #define BMC_CHEMPTY_CH20EPT_Pos (20) /*!< BMC_T::CHEMPTY: CH20EPT Position */ 584 #define BMC_CHEMPTY_CH20EPT_Msk (0x1ul << BMC_CHEMPTY_CH20EPT_Pos) /*!< BMC_T::CHEMPTY: CH20EPT Mask */ 585 586 #define BMC_CHEMPTY_CH21EPT_Pos (21) /*!< BMC_T::CHEMPTY: CH21EPT Position */ 587 #define BMC_CHEMPTY_CH21EPT_Msk (0x1ul << BMC_CHEMPTY_CH21EPT_Pos) /*!< BMC_T::CHEMPTY: CH21EPT Mask */ 588 589 #define BMC_CHEMPTY_CH22EPT_Pos (22) /*!< BMC_T::CHEMPTY: CH22EPT Position */ 590 #define BMC_CHEMPTY_CH22EPT_Msk (0x1ul << BMC_CHEMPTY_CH22EPT_Pos) /*!< BMC_T::CHEMPTY: CH22EPT Mask */ 591 592 #define BMC_CHEMPTY_CH23EPT_Pos (23) /*!< BMC_T::CHEMPTY: CH23EPT Position */ 593 #define BMC_CHEMPTY_CH23EPT_Msk (0x1ul << BMC_CHEMPTY_CH23EPT_Pos) /*!< BMC_T::CHEMPTY: CH23EPT Mask */ 594 595 #define BMC_CHEMPTY_CH24EPT_Pos (24) /*!< BMC_T::CHEMPTY: CH24EPT Position */ 596 #define BMC_CHEMPTY_CH24EPT_Msk (0x1ul << BMC_CHEMPTY_CH24EPT_Pos) /*!< BMC_T::CHEMPTY: CH24EPT Mask */ 597 598 #define BMC_CHEMPTY_CH25EPT_Pos (25) /*!< BMC_T::CHEMPTY: CH25EPT Position */ 599 #define BMC_CHEMPTY_CH25EPT_Msk (0x1ul << BMC_CHEMPTY_CH25EPT_Pos) /*!< BMC_T::CHEMPTY: CH25EPT Mask */ 600 601 #define BMC_CHEMPTY_CH26EPT_Pos (26) /*!< BMC_T::CHEMPTY: CH26EPT Position */ 602 #define BMC_CHEMPTY_CH26EPT_Msk (0x1ul << BMC_CHEMPTY_CH26EPT_Pos) /*!< BMC_T::CHEMPTY: CH26EPT Mask */ 603 604 #define BMC_CHEMPTY_CH27EPT_Pos (27) /*!< BMC_T::CHEMPTY: CH27EPT Position */ 605 #define BMC_CHEMPTY_CH27EPT_Msk (0x1ul << BMC_CHEMPTY_CH27EPT_Pos) /*!< BMC_T::CHEMPTY: CH27EPT Mask */ 606 607 #define BMC_CHEMPTY_CH28EPT_Pos (28) /*!< BMC_T::CHEMPTY: CH28EPT Position */ 608 #define BMC_CHEMPTY_CH28EPT_Msk (0x1ul << BMC_CHEMPTY_CH28EPT_Pos) /*!< BMC_T::CHEMPTY: CH28EPT Mask */ 609 610 #define BMC_CHEMPTY_CH29EPT_Pos (29) /*!< BMC_T::CHEMPTY: CH29EPT Position */ 611 #define BMC_CHEMPTY_CH29EPT_Msk (0x1ul << BMC_CHEMPTY_CH29EPT_Pos) /*!< BMC_T::CHEMPTY: CH29EPT Mask */ 612 613 #define BMC_CHEMPTY_CH30EPT_Pos (30) /*!< BMC_T::CHEMPTY: CH30EPT Position */ 614 #define BMC_CHEMPTY_CH30EPT_Msk (0x1ul << BMC_CHEMPTY_CH30EPT_Pos) /*!< BMC_T::CHEMPTY: CH30EPT Mask */ 615 616 #define BMC_CHEMPTY_CH31EPT_Pos (31) /*!< BMC_T::CHEMPTY: CH31EPT Position */ 617 #define BMC_CHEMPTY_CH31EPT_Msk (0x1ul << BMC_CHEMPTY_CH31EPT_Pos) /*!< BMC_T::CHEMPTY: CH31EPT Mask */ 618 619 #define BMC_TXDATG0_CH0_TXDAT_Pos (0) /*!< BMC_T::TXDATG0: CH0_TXDAT Position */ 620 #define BMC_TXDATG0_CH0_TXDAT_Msk (0x1ful << BMC_TXDATG0_CH0_TXDAT_Pos) /*!< BMC_T::TXDATG0: CH0_TXDAT Mask */ 621 622 #define BMC_TXDATG0_CH1_TXDAT_Pos (8) /*!< BMC_T::TXDATG0: CH1_TXDAT Position */ 623 #define BMC_TXDATG0_CH1_TXDAT_Msk (0x1ful << BMC_TXDATG0_CH1_TXDAT_Pos) /*!< BMC_T::TXDATG0: CH1_TXDAT Mask */ 624 625 #define BMC_TXDATG0_CH2_TXDAT_Pos (16) /*!< BMC_T::TXDATG0: CH2_TXDAT Position */ 626 #define BMC_TXDATG0_CH2_TXDAT_Msk (0x1ful << BMC_TXDATG0_CH2_TXDAT_Pos) /*!< BMC_T::TXDATG0: CH2_TXDAT Mask */ 627 628 #define BMC_TXDATG0_CH3_TXDAT_Pos (24) /*!< BMC_T::TXDATG0: CH3_TXDAT Position */ 629 #define BMC_TXDATG0_CH3_TXDAT_Msk (0x1ful << BMC_TXDATG0_CH3_TXDAT_Pos) /*!< BMC_T::TXDATG0: CH3_TXDAT Mask */ 630 631 #define BMC_TXDATG1_CH4_TXDAT_Pos (0) /*!< BMC_T::TXDATG1: CH4_TXDAT Position */ 632 #define BMC_TXDATG1_CH4_TXDAT_Msk (0x1ful << BMC_TXDATG1_CH4_TXDAT_Pos) /*!< BMC_T::TXDATG1: CH4_TXDAT Mask */ 633 634 #define BMC_TXDATG1_CH5_TXDAT_Pos (8) /*!< BMC_T::TXDATG1: CH5_TXDAT Position */ 635 #define BMC_TXDATG1_CH5_TXDAT_Msk (0x1ful << BMC_TXDATG1_CH5_TXDAT_Pos) /*!< BMC_T::TXDATG1: CH5_TXDAT Mask */ 636 637 #define BMC_TXDATG1_CH6_TXDAT_Pos (16) /*!< BMC_T::TXDATG1: CH6_TXDAT Position */ 638 #define BMC_TXDATG1_CH6_TXDAT_Msk (0x1ful << BMC_TXDATG1_CH6_TXDAT_Pos) /*!< BMC_T::TXDATG1: CH6_TXDAT Mask */ 639 640 #define BMC_TXDATG1_CH7_TXDAT_Pos (24) /*!< BMC_T::TXDATG1: CH7_TXDAT Position */ 641 #define BMC_TXDATG1_CH7_TXDAT_Msk (0x1ful << BMC_TXDATG1_CH7_TXDAT_Pos) /*!< BMC_T::TXDATG1: CH7_TXDAT Mask */ 642 643 #define BMC_TXDATG2_CH8_TXDAT_Pos (0) /*!< BMC_T::TXDATG2: CH8_TXDAT Position */ 644 #define BMC_TXDATG2_CH8_TXDAT_Msk (0x1ful << BMC_TXDATG2_CH8_TXDAT_Pos) /*!< BMC_T::TXDATG2: CH8_TXDAT Mask */ 645 646 #define BMC_TXDATG2_CH9_TXDAT_Pos (8) /*!< BMC_T::TXDATG2: CH9_TXDAT Position */ 647 #define BMC_TXDATG2_CH9_TXDAT_Msk (0x1ful << BMC_TXDATG2_CH9_TXDAT_Pos) /*!< BMC_T::TXDATG2: CH9_TXDAT Mask */ 648 649 #define BMC_TXDATG2_CH10_TXDAT_Pos (16) /*!< BMC_T::TXDATG2: CH10_TXDAT Position */ 650 #define BMC_TXDATG2_CH10_TXDAT_Msk (0x1ful << BMC_TXDATG2_CH10_TXDAT_Pos) /*!< BMC_T::TXDATG2: CH10_TXDAT Mask */ 651 652 #define BMC_TXDATG2_CH11_TXDAT_Pos (24) /*!< BMC_T::TXDATG2: CH11_TXDAT Position */ 653 #define BMC_TXDATG2_CH11_TXDAT_Msk (0x1ful << BMC_TXDATG2_CH11_TXDAT_Pos) /*!< BMC_T::TXDATG2: CH11_TXDAT Mask */ 654 655 #define BMC_TXDATG3_CH12_TXDAT_Pos (0) /*!< BMC_T::TXDATG3: CH12_TXDAT Position */ 656 #define BMC_TXDATG3_CH12_TXDAT_Msk (0x1ful << BMC_TXDATG3_CH12_TXDAT_Pos) /*!< BMC_T::TXDATG3: CH12_TXDAT Mask */ 657 658 #define BMC_TXDATG3_CH13_TXDAT_Pos (8) /*!< BMC_T::TXDATG3: CH13_TXDAT Position */ 659 #define BMC_TXDATG3_CH13_TXDAT_Msk (0x1ful << BMC_TXDATG3_CH13_TXDAT_Pos) /*!< BMC_T::TXDATG3: CH13_TXDAT Mask */ 660 661 #define BMC_TXDATG3_CH14_TXDAT_Pos (16) /*!< BMC_T::TXDATG3: CH14_TXDAT Position */ 662 #define BMC_TXDATG3_CH14_TXDAT_Msk (0x1ful << BMC_TXDATG3_CH14_TXDAT_Pos) /*!< BMC_T::TXDATG3: CH14_TXDAT Mask */ 663 664 #define BMC_TXDATG3_CH15_TXDAT_Pos (24) /*!< BMC_T::TXDATG3: CH15_TXDAT Position */ 665 #define BMC_TXDATG3_CH15_TXDAT_Msk (0x1ful << BMC_TXDATG3_CH15_TXDAT_Pos) /*!< BMC_T::TXDATG3: CH15_TXDAT Mask */ 666 667 #define BMC_TXDATG4_CH16_TXDAT_Pos (0) /*!< BMC_T::TXDATG4: CH16_TXDAT Position */ 668 #define BMC_TXDATG4_CH16_TXDAT_Msk (0x1ful << BMC_TXDATG4_CH16_TXDAT_Pos) /*!< BMC_T::TXDATG4: CH16_TXDAT Mask */ 669 670 #define BMC_TXDATG4_CH17_TXDAT_Pos (8) /*!< BMC_T::TXDATG4: CH17_TXDAT Position */ 671 #define BMC_TXDATG4_CH17_TXDAT_Msk (0x1ful << BMC_TXDATG4_CH17_TXDAT_Pos) /*!< BMC_T::TXDATG4: CH17_TXDAT Mask */ 672 673 #define BMC_TXDATG4_CH18_TXDAT_Pos (16) /*!< BMC_T::TXDATG4: CH18_TXDAT Position */ 674 #define BMC_TXDATG4_CH18_TXDAT_Msk (0x1ful << BMC_TXDATG4_CH18_TXDAT_Pos) /*!< BMC_T::TXDATG4: CH18_TXDAT Mask */ 675 676 #define BMC_TXDATG4_CH19_TXDAT_Pos (24) /*!< BMC_T::TXDATG4: CH19_TXDAT Position */ 677 #define BMC_TXDATG4_CH19_TXDAT_Msk (0x1ful << BMC_TXDATG4_CH19_TXDAT_Pos) /*!< BMC_T::TXDATG4: CH19_TXDAT Mask */ 678 679 #define BMC_TXDATG5_CH20_TXDAT_Pos (0) /*!< BMC_T::TXDATG5: CH20_TXDAT Position */ 680 #define BMC_TXDATG5_CH20_TXDAT_Msk (0x1ful << BMC_TXDATG5_CH20_TXDAT_Pos) /*!< BMC_T::TXDATG5: CH20_TXDAT Mask */ 681 682 #define BMC_TXDATG5_CH21_TXDAT_Pos (8) /*!< BMC_T::TXDATG5: CH21_TXDAT Position */ 683 #define BMC_TXDATG5_CH21_TXDAT_Msk (0x1ful << BMC_TXDATG5_CH21_TXDAT_Pos) /*!< BMC_T::TXDATG5: CH21_TXDAT Mask */ 684 685 #define BMC_TXDATG5_CH22_TXDAT_Pos (16) /*!< BMC_T::TXDATG5: CH22_TXDAT Position */ 686 #define BMC_TXDATG5_CH22_TXDAT_Msk (0x1ful << BMC_TXDATG5_CH22_TXDAT_Pos) /*!< BMC_T::TXDATG5: CH22_TXDAT Mask */ 687 688 #define BMC_TXDATG5_CH23_TXDAT_Pos (24) /*!< BMC_T::TXDATG5: CH23_TXDAT Position */ 689 #define BMC_TXDATG5_CH23_TXDAT_Msk (0x1ful << BMC_TXDATG5_CH23_TXDAT_Pos) /*!< BMC_T::TXDATG5: CH23_TXDAT Mask */ 690 691 #define BMC_TXDATG6_CH24_TXDAT_Pos (0) /*!< BMC_T::TXDATG6: CH24_TXDAT Position */ 692 #define BMC_TXDATG6_CH24_TXDAT_Msk (0x1ful << BMC_TXDATG6_CH24_TXDAT_Pos) /*!< BMC_T::TXDATG6: CH24_TXDAT Mask */ 693 694 #define BMC_TXDATG6_CH25_TXDAT_Pos (8) /*!< BMC_T::TXDATG6: CH25_TXDAT Position */ 695 #define BMC_TXDATG6_CH25_TXDAT_Msk (0x1ful << BMC_TXDATG6_CH25_TXDAT_Pos) /*!< BMC_T::TXDATG6: CH25_TXDAT Mask */ 696 697 #define BMC_TXDATG6_CH26_TXDAT_Pos (16) /*!< BMC_T::TXDATG6: CH26_TXDAT Position */ 698 #define BMC_TXDATG6_CH26_TXDAT_Msk (0x1ful << BMC_TXDATG6_CH26_TXDAT_Pos) /*!< BMC_T::TXDATG6: CH26_TXDAT Mask */ 699 700 #define BMC_TXDATG6_CH27_TXDAT_Pos (24) /*!< BMC_T::TXDATG6: CH27_TXDAT Position */ 701 #define BMC_TXDATG6_CH27_TXDAT_Msk (0x1ful << BMC_TXDATG6_CH27_TXDAT_Pos) /*!< BMC_T::TXDATG6: CH27_TXDAT Mask */ 702 703 #define BMC_TXDATG7_CH28_TXDAT_Pos (0) /*!< BMC_T::TXDATG7: CH28_TXDAT Position */ 704 #define BMC_TXDATG7_CH28_TXDAT_Msk (0x1ful << BMC_TXDATG7_CH28_TXDAT_Pos) /*!< BMC_T::TXDATG7: CH28_TXDAT Mask */ 705 706 #define BMC_TXDATG7_CH29_TXDAT_Pos (8) /*!< BMC_T::TXDATG7: CH29_TXDAT Position */ 707 #define BMC_TXDATG7_CH29_TXDAT_Msk (0x1ful << BMC_TXDATG7_CH29_TXDAT_Pos) /*!< BMC_T::TXDATG7: CH29_TXDAT Mask */ 708 709 #define BMC_TXDATG7_CH30_TXDAT_Pos (16) /*!< BMC_T::TXDATG7: CH30_TXDAT Position */ 710 #define BMC_TXDATG7_CH30_TXDAT_Msk (0x1ful << BMC_TXDATG7_CH30_TXDAT_Pos) /*!< BMC_T::TXDATG7: CH30_TXDAT Mask */ 711 712 #define BMC_TXDATG7_CH31_TXDAT_Pos (24) /*!< BMC_T::TXDATG7: CH31_TXDAT Position */ 713 #define BMC_TXDATG7_CH31_TXDAT_Msk (0x1ful << BMC_TXDATG7_CH31_TXDAT_Pos) /*!< BMC_T::TXDATG7: CH31_TXDAT Mask */ 714 715 716 /**@}*/ /* BMC_CONST */ 717 /**@}*/ /* end of BMC register group */ 718 /**@}*/ /* end of REGISTER group */ 719 720 #if defined ( __CC_ARM ) 721 #pragma no_anon_unions 722 #endif 723 724 #endif /* __BMC_REG_H__ */ 725 726
