1 /***************************************************************************//** 2 * \file cy_device.h 3 * \version 2.30 4 * 5 * This file specifies the structure for core and peripheral block HW base 6 * addresses, versions, and parameters. 7 * 8 ******************************************************************************** 9 * \copyright 10 * Copyright 2018-2020 Cypress Semiconductor Corporation 11 * SPDX-License-Identifier: Apache-2.0 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 *******************************************************************************/ 25 26 #ifndef CY_DEVICE_H_ 27 #define CY_DEVICE_H_ 28 29 #include <stdint.h> 30 #include <stddef.h> 31 32 #include "ip/cyip_cpuss.h" 33 #include "ip/cyip_cpuss_v2.h" 34 #include "ip/cyip_flashc.h" 35 #include "ip/cyip_flashc_v2.h" 36 #include "ip/cyip_gpio.h" 37 #include "ip/cyip_gpio_v2.h" 38 #include "ip/cyip_hsiom.h" 39 #include "ip/cyip_hsiom_v2.h" 40 #include "ip/cyip_sflash.h" 41 #include "ip/cyip_srss.h" 42 #include "ip/cyip_backup.h" 43 #include "ip/cyip_peri.h" 44 #include "ip/cyip_peri_v2.h" 45 #include "ip/cyip_peri_ms_v2.h" 46 #include "ip/cyip_profile.h" 47 #include "ip/cyip_prot.h" 48 #include "ip/cyip_prot_v2.h" 49 #include "ip/cyip_ipc.h" 50 #include "ip/cyip_ipc_v2.h" 51 #include "ip/cyip_udb.h" 52 #include "ip/cyip_dw.h" 53 #include "ip/cyip_dw_v2.h" 54 #include "ip/cyip_dmac_v2.h" 55 #include "ip/cyip_i2s.h" 56 #include "ip/cyip_pdm.h" 57 #include "ip/cyip_lcd.h" 58 #include "ip/cyip_lcd_v2.h" 59 #include "ip/cyip_sdhc.h" 60 #include "ip/cyip_canfd.h" 61 #include "ip/cyip_smartio.h" 62 #include "ip/cyip_tcpwm.h" 63 #include "ip/cyip_tcpwm_v2.h" 64 #include "ip/cyip_ctbm.h" 65 #include "ip/cyip_ctbm_v2.h" 66 #include "ip/cyip_ctdac.h" 67 #include "ip/cyip_ctdac_v2.h" 68 #include "ip/cyip_sar.h" 69 #include "ip/cyip_sar_v2.h" 70 #include "ip/cyip_pass.h" 71 #include "ip/cyip_pass_v2.h" 72 #include "cy_device_headers.h" 73 74 /* Device descriptor type */ 75 typedef struct 76 { 77 /* Base HW addresses */ 78 uint32_t cpussBase; 79 uint32_t flashcBase; 80 uint32_t periBase; 81 uint32_t udbBase; 82 uint32_t protBase; 83 uint32_t hsiomBase; 84 uint32_t gpioBase; 85 uint32_t passBase; 86 uint32_t ipcBase; 87 uint32_t cryptoBase; 88 uint32_t sar0Base; 89 90 /* IP block versions: [7:4] major, [3:0] minor */ 91 uint8_t cpussVersion; 92 uint8_t cryptoVersion; 93 uint8_t dwVersion; 94 uint8_t ipcVersion; 95 uint8_t periVersion; 96 uint8_t srssVersion; 97 uint8_t passVersion; 98 99 /* Parameters */ 100 uint8_t cpussIpcNr; 101 uint8_t cpussIpcIrqNr; 102 uint8_t cpussDw0ChNr; 103 uint8_t cpussDw1ChNr; 104 uint8_t cpussFlashPaSize; 105 int16_t cpussIpc0Irq; 106 int16_t cpussFmIrq; 107 int16_t cpussNotConnectedIrq; 108 uint8_t srssNumClkpath; 109 uint8_t srssNumPll; 110 uint8_t srssNumHfroot; 111 uint8_t srssIsPiloPresent; 112 uint8_t periClockNr; 113 uint8_t smifDeviceNr; 114 uint8_t passSarChannels; 115 uint8_t epMonitorNr; 116 uint8_t udbPresent; 117 uint8_t sysPmSimoPresent; 118 uint32_t protBusMasterMask; 119 uint32_t cryptoMemSize; 120 uint8_t flashRwwRequired; 121 uint8_t flashPipeRequired; 122 uint8_t flashWriteDelay; 123 uint8_t flashProgramDelay; 124 uint8_t flashEraseDelay; 125 uint8_t flashCtlMainWs0Freq; 126 uint8_t flashCtlMainWs1Freq; 127 uint8_t flashCtlMainWs2Freq; 128 uint8_t flashCtlMainWs3Freq; 129 uint8_t flashCtlMainWs4Freq; 130 uint8_t tcpwmCC1Present; 131 uint8_t tcpwmAMCPresent; 132 uint8_t tcpwmSMCPrecent; 133 134 /* Peripheral register offsets */ 135 136 /* DW registers */ 137 uint16_t dwChOffset; 138 uint16_t dwChSize; 139 uint8_t dwChCtlPrioPos; 140 uint8_t dwChCtlPreemptablePos; 141 uint8_t dwStatusChIdxPos; 142 uint32_t dwStatusChIdxMsk; 143 144 /* PERI registers */ 145 uint16_t periTrCmdOffset; 146 uint16_t periTrCmdGrSelMsk; 147 uint16_t periTrGrOffset; 148 uint16_t periTrGrSize; 149 150 uint8_t periDivCmdDivSelMsk; 151 uint8_t periDivCmdTypeSelPos; 152 uint8_t periDivCmdPaDivSelPos; 153 uint8_t periDivCmdPaTypeSelPos; 154 155 uint16_t periDiv8CtlOffset; 156 uint16_t periDiv16CtlOffset; 157 uint16_t periDiv16_5CtlOffset; 158 uint16_t periDiv24_5CtlOffset; 159 160 /* GPIO registers */ 161 uint8_t gpioPrtIntrCfgOffset; 162 uint8_t gpioPrtCfgOffset; 163 uint8_t gpioPrtCfgInOffset; 164 uint8_t gpioPrtCfgOutOffset; 165 uint8_t gpioPrtCfgSioOffset; 166 167 /* CPUSS registers */ 168 uint32_t cpussCm0ClockCtlOffset; 169 uint32_t cpussCm4ClockCtlOffset; 170 uint32_t cpussCm4StatusOffset; 171 uint32_t cpussCm0StatusOffset; 172 uint32_t cpussCm4PwrCtlOffset; 173 uint32_t cpussTrimRamCtlOffset; 174 uint32_t cpussTrimRomCtlOffset; 175 uint32_t cpussSysTickCtlOffset; 176 uint16_t cpussCm0NmiCtlOffset; 177 uint16_t cpussCm4NmiCtlOffset; 178 uint16_t cpussRomCtl; 179 uint16_t cpussRam0Ctl0; 180 uint16_t cpussRam1Ctl0; 181 uint16_t cpussRam2Ctl0; 182 uint16_t cpussRam0PwrCtl; 183 uint16_t cpussRam1PwrCtl; 184 uint16_t cpussRam2PwrCtl; 185 186 /* IPC registers */ 187 uint16_t ipcStructSize; 188 uint32_t ipcLockStatusOffset; 189 } cy_stc_device_t; 190 191 /******************************************************************************* 192 * Global Variables 193 *******************************************************************************/ 194 195 extern const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_01; 196 extern const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_02; 197 extern const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_03; 198 extern const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_04; 199 extern const cy_stc_device_t * cy_device; 200 201 202 /******************************************************************************* 203 * Function Prototypes 204 *******************************************************************************/ 205 206 void Cy_PDL_Init(const cy_stc_device_t * device); 207 208 209 /******************************************************************************* 210 * Register Access Helper Macros 211 *******************************************************************************/ 212 213 #define CY_CRYPTO_V1 (0x20U > cy_device->cryptoVersion) /* true if the mxcrypto version is 1.x */ 214 215 #define CY_SRSS_V1_3 (0x13U == cy_device->srssVersion) 216 #define CY_SRSS_MFO_PRESENT (CY_SRSS_V1_3) 217 218 #define CY_SRSS_PILO_PRESENT (1U == cy_device->srssIsPiloPresent) 219 220 #define CY_SRSS_NUM_CLKPATH ((uint32_t)(cy_device->srssNumClkpath)) 221 #define CY_SRSS_NUM_PLL ((uint32_t)(cy_device->srssNumPll)) 222 #define CY_SRSS_NUM_HFROOT ((uint32_t)(cy_device->srssNumHfroot)) 223 224 #define SRSS_PWR_CTL (((SRSS_V1_Type *) SRSS)->PWR_CTL) 225 #define SRSS_PWR_HIBERNATE (((SRSS_V1_Type *) SRSS)->PWR_HIBERNATE) 226 #define SRSS_PWR_TRIM_PWRSYS_CTL (((SRSS_V1_Type *) SRSS)->PWR_TRIM_PWRSYS_CTL) 227 #define SRSS_PWR_BUCK_CTL (((SRSS_V1_Type *) SRSS)->PWR_BUCK_CTL) 228 #define SRSS_PWR_BUCK_CTL2 (((SRSS_V1_Type *) SRSS)->PWR_BUCK_CTL2) 229 #define SRSS_PWR_TRIM_WAKE_CTL (((SRSS_V1_Type *) SRSS)->PWR_TRIM_WAKE_CTL) 230 #define SRSS_PWR_LVD_CTL (((SRSS_V1_Type *) SRSS)->PWR_LVD_CTL) 231 #define SRSS_PWR_LVD_STATUS (((SRSS_V1_Type *) SRSS)->PWR_LVD_STATUS) 232 #define SRSS_WDT_CTL (((SRSS_V1_Type *) SRSS)->WDT_CTL) 233 #define SRSS_WDT_CNT (((SRSS_V1_Type *) SRSS)->WDT_CNT) 234 #define SRSS_WDT_MATCH (((SRSS_V1_Type *) SRSS)->WDT_MATCH) 235 #define SRSS_CLK_DSI_SELECT (((SRSS_V1_Type *) SRSS)->CLK_DSI_SELECT) 236 #define SRSS_CLK_PATH_SELECT (((SRSS_V1_Type *) SRSS)->CLK_PATH_SELECT) 237 #define SRSS_CLK_ROOT_SELECT (((SRSS_V1_Type *) SRSS)->CLK_ROOT_SELECT) 238 #define SRSS_CLK_CSV_HF_LIMIT(clk) (((SRSS_V1_Type *) SRSS)->CLK_CSV[(clk)].HF_LIMIT) 239 #define SRSS_CLK_CSV_HF_CTL(clk) (((SRSS_V1_Type *) SRSS)->CLK_CSV[(clk)].HF_CTL) 240 #define SRSS_CLK_SELECT (((SRSS_V1_Type *) SRSS)->CLK_SELECT) 241 #define SRSS_CLK_TIMER_CTL (((SRSS_V1_Type *) SRSS)->CLK_TIMER_CTL) 242 #define SRSS_CLK_CSV_WCO_CTL (((SRSS_V1_Type *) SRSS)->CLK_CSV_WCO_CTL) 243 #define SRSS_CLK_ILO_CONFIG (((SRSS_V1_Type *) SRSS)->CLK_ILO_CONFIG) 244 #define SRSS_CLK_OUTPUT_SLOW (((SRSS_V1_Type *) SRSS)->CLK_OUTPUT_SLOW) 245 #define SRSS_CLK_OUTPUT_FAST (((SRSS_V1_Type *) SRSS)->CLK_OUTPUT_FAST) 246 #define SRSS_CLK_CAL_CNT1 (((SRSS_V1_Type *) SRSS)->CLK_CAL_CNT1) 247 #define SRSS_CLK_CAL_CNT2 (((SRSS_V1_Type *) SRSS)->CLK_CAL_CNT2) 248 #define SRSS_CLK_ECO_CONFIG (((SRSS_V1_Type *) SRSS)->CLK_ECO_CONFIG) 249 #define SRSS_CLK_ECO_STATUS (((SRSS_V1_Type *) SRSS)->CLK_ECO_STATUS) 250 #define SRSS_CLK_PILO_CONFIG (((SRSS_V1_Type *) SRSS)->CLK_PILO_CONFIG) 251 #define SRSS_CLK_MF_SELECT (((SRSS_V1_Type *) SRSS)->CLK_MF_SELECT) /* for CY_SRSS_V1_3 only */ 252 #define SRSS_CLK_MFO_CONFIG (((SRSS_V1_Type *) SRSS)->CLK_MFO_CONFIG) /* for CY_SRSS_V1_3 only */ 253 #define SRSS_CLK_FLL_CONFIG (((SRSS_V1_Type *) SRSS)->CLK_FLL_CONFIG) 254 #define SRSS_CLK_FLL_CONFIG2 (((SRSS_V1_Type *) SRSS)->CLK_FLL_CONFIG2) 255 #define SRSS_CLK_FLL_CONFIG3 (((SRSS_V1_Type *) SRSS)->CLK_FLL_CONFIG3) 256 #define SRSS_CLK_FLL_CONFIG4 (((SRSS_V1_Type *) SRSS)->CLK_FLL_CONFIG4) 257 #define SRSS_CLK_FLL_STATUS (((SRSS_V1_Type *) SRSS)->CLK_FLL_STATUS) 258 #define SRSS_CLK_PLL_CONFIG (((SRSS_V1_Type *) SRSS)->CLK_PLL_CONFIG) 259 #define SRSS_CLK_PLL_STATUS (((SRSS_V1_Type *) SRSS)->CLK_PLL_STATUS) 260 #define SRSS_SRSS_INTR (((SRSS_V1_Type *) SRSS)->SRSS_INTR) 261 #define SRSS_SRSS_INTR_SET (((SRSS_V1_Type *) SRSS)->SRSS_INTR_SET) 262 #define SRSS_SRSS_INTR_CFG (((SRSS_V1_Type *) SRSS)->SRSS_INTR_CFG) 263 #define SRSS_SRSS_INTR_MASK (((SRSS_V1_Type *) SRSS)->SRSS_INTR_MASK) 264 #define SRSS_SRSS_INTR_MASKED (((SRSS_V1_Type *) SRSS)->SRSS_INTR_MASKED) 265 #define SRSS_CLK_TRIM_ILO_CTL (((SRSS_V1_Type *) SRSS)->CLK_TRIM_ILO_CTL) 266 #define SRSS_CLK_TRIM_ECO_CTL (((SRSS_V1_Type *) SRSS)->CLK_TRIM_ECO_CTL) 267 268 #define SRSS_RES_CAUSE (((SRSS_V1_Type *) SRSS)->RES_CAUSE) 269 #define SRSS_RES_CAUSE2 (((SRSS_V1_Type *) SRSS)->RES_CAUSE2) 270 271 #define SRSS_TST_DDFT_SLOW_CTL_REG (*(volatile uint32_t *) 0x40260108U) 272 #define SRSS_TST_DDFT_FAST_CTL_REG (*(volatile uint32_t *) 0x40260104U) 273 274 #define SRSS_TST_DDFT_SLOW_CTL_MASK (0x00001F1EU) 275 #define SRSS_TST_DDFT_FAST_CTL_MASK (62U) 276 277 /******************************************************************************* 278 * BACKUP 279 *******************************************************************************/ 280 281 #define BACKUP_PMIC_CTL (((BACKUP_V1_Type *) BACKUP)->PMIC_CTL) 282 #define BACKUP_CTL (((BACKUP_V1_Type *) BACKUP)->CTL) 283 #define BACKUP_RTC_TIME (((BACKUP_V1_Type *) BACKUP)->RTC_TIME) 284 #define BACKUP_RTC_DATE (((BACKUP_V1_Type *) BACKUP)->RTC_DATE) 285 #define BACKUP_RTC_RW (((BACKUP_V1_Type *) BACKUP)->RTC_RW) 286 #define BACKUP_ALM1_TIME (((BACKUP_V1_Type *) BACKUP)->ALM1_TIME) 287 #define BACKUP_ALM1_DATE (((BACKUP_V1_Type *) BACKUP)->ALM1_DATE) 288 #define BACKUP_ALM2_TIME (((BACKUP_V1_Type *) BACKUP)->ALM2_TIME) 289 #define BACKUP_ALM2_DATE (((BACKUP_V1_Type *) BACKUP)->ALM2_DATE) 290 #define BACKUP_STATUS (((BACKUP_V1_Type *) BACKUP)->STATUS) 291 #define BACKUP_INTR (((BACKUP_V1_Type *) BACKUP)->INTR) 292 #define BACKUP_INTR_SET (((BACKUP_V1_Type *) BACKUP)->INTR_SET) 293 #define BACKUP_INTR_MASK (((BACKUP_V1_Type *) BACKUP)->INTR_MASK) 294 #define BACKUP_INTR_MASKED (((BACKUP_V1_Type *) BACKUP)->INTR_MASKED) 295 #define BACKUP_RESET (((BACKUP_V1_Type *) BACKUP)->RESET) 296 #define BACKUP_TRIM (((BACKUP_V1_Type *) BACKUP)->TRIM) 297 298 /******************************************************************************* 299 * CANFD 300 *******************************************************************************/ 301 302 #define CANFD_CTL(base) (((CANFD_V1_Type *)(base))->CTL) 303 #define CANFD_STATUS(base) (((CANFD_V1_Type *)(base))->STATUS) 304 #define CANFD_NBTP(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.NBTP) 305 #define CANFD_IR(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.IR) 306 #define CANFD_IE(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.IE) 307 #define CANFD_ILS(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.ILS) 308 #define CANFD_ILE(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.ILE) 309 #define CANFD_CCCR(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.CCCR) 310 #define CANFD_SIDFC(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.SIDFC) 311 #define CANFD_XIDFC(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.XIDFC) 312 #define CANFD_XIDAM(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.XIDAM) 313 #define CANFD_RXESC(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.RXESC) 314 #define CANFD_RXF0C(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.RXF0C) 315 #define CANFD_RXF1C(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.RXF1C) 316 #define CANFD_RXFTOP_CTL(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].RXFTOP_CTL) 317 #define CANFD_RXBC(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.RXBC) 318 #define CANFD_TXESC(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXESC) 319 #define CANFD_TXEFC(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXEFC) 320 #define CANFD_TXBC(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXBC) 321 #define CANFD_DBTP(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.DBTP) 322 #define CANFD_TDCR(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TDCR) 323 #define CANFD_GFC(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.GFC) 324 #define CANFD_TXBRP(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXBRP) 325 #define CANFD_TXBAR(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXBAR) 326 #define CANFD_TXBCR(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXBCR) 327 #define CANFD_TXBTO(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXBTO) 328 #define CANFD_TXBCF(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXBCF) 329 #define CANFD_TXBTIE(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXBTIE) 330 #define CANFD_TXBCIE(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXBCIE) 331 #define CANFD_NDAT1(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.NDAT1) 332 #define CANFD_NDAT2(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.NDAT2) 333 #define CANFD_RXF0S(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.RXF0S) 334 #define CANFD_RXFTOP0_DATA(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].RXFTOP0_DATA) 335 #define CANFD_RXFTOP1_DATA(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].RXFTOP1_DATA) 336 #define CANFD_RXF0A(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.RXF0A) 337 #define CANFD_RXF1S(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.RXF1S) 338 #define CANFD_RXF1A(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.RXF1A) 339 #define CANFD_PSR(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.PSR) 340 #define CANFD_TEST(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TEST) 341 #define CANFD_CREL(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.CREL) 342 343 #define CY_CANFD_CHANNELS_NUM (0x1UL) 344 345 346 /******************************************************************************* 347 * FLASHC 348 *******************************************************************************/ 349 350 #define FLASHC_FM_CTL_ANA_CTL0 (((FLASHC_V1_Type *) cy_device->flashcBase)->FM_CTL.ANA_CTL0) 351 #define FLASHC_FM_CTL_BOOKMARK (((FLASHC_V1_Type *) cy_device->flashcBase)->FM_CTL.BOOKMARK) 352 #define FLASHC_FLASH_CMD (((FLASHC_V1_Type *) cy_device->flashcBase)->FLASH_CMD) 353 #define FLASHC_FLASH_CTL (((FLASHC_V1_Type *) cy_device->flashcBase)->FLASH_CTL) 354 #define FLASHC_BIST_DATA_0 (((FLASHC_V1_Type *) cy_device->flashcBase)->BIST_DATA[0U]) 355 #define FLASHC_BIST_STATUS (((FLASHC_V1_Type *) cy_device->flashcBase)->BIST_STATUS) 356 357 358 /******************************************************************************* 359 * SFLASH 360 *******************************************************************************/ 361 362 #define SFLASH_DIE_YEAR (((SFLASH_V1_Type *) SFLASH)->DIE_YEAR) 363 #define SFLASH_DIE_MINOR (((SFLASH_V1_Type *) SFLASH)->DIE_MINOR) 364 #define SFLASH_DIE_SORT (((SFLASH_V1_Type *) SFLASH)->DIE_SORT) 365 #define SFLASH_DIE_Y (((SFLASH_V1_Type *) SFLASH)->DIE_Y) 366 #define SFLASH_DIE_X (((SFLASH_V1_Type *) SFLASH)->DIE_X) 367 #define SFLASH_DIE_WAFER (((SFLASH_V1_Type *) SFLASH)->DIE_WAFER) 368 #define SFLASH_DIE_LOT(val) (((SFLASH_V1_Type *) SFLASH)->DIE_LOT[(val)]) 369 #define SFLASH_FAMILY_ID (((SFLASH_V1_Type *) SFLASH)->FAMILY_ID) 370 #define SFLASH_SI_REVISION_ID (((SFLASH_V1_Type *) SFLASH)->SI_REVISION_ID) 371 #define SFLASH_PWR_TRIM_WAKE_CTL (((SFLASH_V1_Type *) SFLASH)->PWR_TRIM_WAKE_CTL) 372 #define SFLASH_LDO_0P9V_TRIM (((SFLASH_V1_Type *) SFLASH)->LDO_0P9V_TRIM) 373 #define SFLASH_LDO_1P1V_TRIM (((SFLASH_V1_Type *) SFLASH)->LDO_1P1V_TRIM) 374 #define SFLASH_BLE_DEVICE_ADDRESS (((SFLASH_V1_Type *) SFLASH)->BLE_DEVICE_ADDRESS) 375 #define SFLASH_SILICON_ID (((SFLASH_V1_Type *) SFLASH)->SILICON_ID) 376 #define SFLASH_SINGLE_CORE (*(volatile uint8_t *) (SFLASH_BASE + 0xBU)) 377 378 379 #define SFLASH_CPUSS_TRIM_ROM_CTL_LP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_LP) 380 #define SFLASH_CPUSS_TRIM_RAM_CTL_LP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_LP) 381 #define SFLASH_CPUSS_TRIM_ROM_CTL_ULP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_ULP) 382 #define SFLASH_CPUSS_TRIM_RAM_CTL_ULP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_ULP) 383 #define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_LP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_HALF_LP) 384 #define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_LP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_HALF_LP) 385 #define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_ULP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_HALF_ULP) 386 #define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_ULP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_HALF_ULP) 387 388 389 #define SFLASH_CSD0_ADC_VREF0_TRIM (((SFLASH_V1_Type *) SFLASH)->CSDV2_CSD0_ADC_VREF0) 390 #define SFLASH_CSD0_ADC_VREF1_TRIM (((SFLASH_V1_Type *) SFLASH)->CSDV2_CSD0_ADC_VREF1) 391 #define SFLASH_CSD0_ADC_VREF2_TRIM (((SFLASH_V1_Type *) SFLASH)->CSDV2_CSD0_ADC_VREF2) 392 393 394 /******************************************************************************* 395 * CPUSS 396 *******************************************************************************/ 397 398 #define CY_CPUSS_V1 (0x20U > cy_device->cpussVersion) 399 400 #define CY_CPUSS_NOT_CONNECTED_IRQN ((uint32_t)(cy_device->cpussNotConnectedIrq)) 401 #define CY_CPUSS_DISCONNECTED_IRQN ((cy_en_intr_t)CY_CPUSS_NOT_CONNECTED_IRQN) 402 #define CY_CPUSS_UNCONNECTED_IRQN ((IRQn_Type)CY_CPUSS_NOT_CONNECTED_IRQN) 403 404 #define CPUSS_CM0_CLOCK_CTL (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussCm0ClockCtlOffset)) 405 #define CPUSS_CM4_CLOCK_CTL (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussCm4ClockCtlOffset)) 406 #define CPUSS_CM4_STATUS (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussCm4StatusOffset)) 407 #define CPUSS_CM0_STATUS (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussCm0StatusOffset)) 408 #define CPUSS_CM4_PWR_CTL (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussCm4PwrCtlOffset)) 409 #define CPUSS_TRIM_RAM_CTL (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussTrimRamCtlOffset)) 410 #define CPUSS_TRIM_ROM_CTL (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussTrimRomCtlOffset)) 411 #define CPUSS_SYSTICK_CTL (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussSysTickCtlOffset)) 412 413 #define CPUSS_ROM_CTL (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussRomCtl)) 414 #define CPUSS_RAM0_CTL0 (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussRam0Ctl0)) 415 #define CPUSS_RAM1_CTL0 (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussRam1Ctl0)) 416 #define CPUSS_RAM2_CTL0 (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussRam2Ctl0)) 417 #define CPUSS_RAM0_PWR_CTL(macroIdx) (((volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussRam0PwrCtl))[(macroIdx)]) 418 #define CPUSS_RAM1_PWR_CTL (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussRam1PwrCtl)) 419 #define CPUSS_RAM2_PWR_CTL (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussRam2PwrCtl)) 420 421 #define CPUSS_CM0_NMI_CTL(nmi) (((volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussCm0NmiCtlOffset))[(nmi)]) 422 #define CPUSS_CM4_NMI_CTL(nmi) (((volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussCm4NmiCtlOffset))[(nmi)]) 423 424 /* used in V1 code only */ 425 #define CPUSS_CM0_INT_CTL ((volatile uint32_t *) &(((CPUSS_V1_Type *)(cy_device->cpussBase))->CM0_INT_CTL0)) 426 427 /* used in V2 code only */ 428 #define CPUSS_CM0_SYSTEM_INT_CTL (((CPUSS_V2_Type *)(cy_device->cpussBase))->CM0_SYSTEM_INT_CTL) 429 #define CPUSS_CM0_INT_STATUS ((volatile const uint32_t *) &(((CPUSS_V2_Type *)(cy_device->cpussBase))->CM0_INT0_STATUS)) 430 431 #define CPUSS_SRAM_COUNT (1u + CPUSS_RAMC1_PRESENT + CPUSS_RAMC2_PRESENT) 432 433 /* ARM core registers */ 434 #define SYSTICK_CTRL (((SysTick_Type *)SysTick)->CTRL) 435 #define SYSTICK_LOAD (((SysTick_Type *)SysTick)->LOAD) 436 #define SYSTICK_VAL (((SysTick_Type *)SysTick)->VAL) 437 #define SCB_SCR (((SCB_Type *)SCB)->SCR) 438 439 #define UDB_UDBIF_BANK_CTL (((UDB_V1_Type *) cy_device->udbBase)->UDBIF.BANK_CTL) 440 #define UDB_BCTL_MDCLK_EN (((UDB_V1_Type *) cy_device->udbBase)->BCTL.MDCLK_EN) 441 #define UDB_BCTL_MBCLK_EN (((UDB_V1_Type *) cy_device->udbBase)->BCTL.MBCLK_EN) 442 #define UDB_BCTL_BOTSEL_L (((UDB_V1_Type *) cy_device->udbBase)->BCTL.BOTSEL_L) 443 #define UDB_BCTL_BOTSEL_U (((UDB_V1_Type *) cy_device->udbBase)->BCTL.BOTSEL_U) 444 #define UDB_BCTL_QCLK_EN_0 (((UDB_V1_Type *) cy_device->udbBase)->BCTL.QCLK_EN[0U]) 445 #define UDB_BCTL_QCLK_EN_1 (((UDB_V1_Type *) cy_device->udbBase)->BCTL.QCLK_EN[1U]) 446 #define UDB_BCTL_QCLK_EN_2 (((UDB_V1_Type *) cy_device->udbBase)->BCTL.QCLK_EN[2U]) 447 448 449 /******************************************************************************* 450 * LPCOMP 451 *******************************************************************************/ 452 453 #define LPCOMP_CMP0_CTRL(base) (((LPCOMP_V1_Type *)(base))->CMP0_CTRL) 454 #define LPCOMP_CMP1_CTRL(base) (((LPCOMP_V1_Type *)(base))->CMP1_CTRL) 455 #define LPCOMP_CMP0_SW_CLEAR(base) (((LPCOMP_V1_Type *)(base))->CMP0_SW_CLEAR) 456 #define LPCOMP_CMP1_SW_CLEAR(base) (((LPCOMP_V1_Type *)(base))->CMP1_SW_CLEAR) 457 #define LPCOMP_CMP0_SW(base) (((LPCOMP_V1_Type *)(base))->CMP0_SW) 458 #define LPCOMP_CMP1_SW(base) (((LPCOMP_V1_Type *)(base))->CMP1_SW) 459 #define LPCOMP_STATUS(base) (((LPCOMP_V1_Type *)(base))->STATUS) 460 #define LPCOMP_CONFIG(base) (((LPCOMP_V1_Type *)(base))->CONFIG) 461 #define LPCOMP_INTR(base) (((LPCOMP_V1_Type *)(base))->INTR) 462 #define LPCOMP_INTR_SET(base) (((LPCOMP_V1_Type *)(base))->INTR_SET) 463 #define LPCOMP_INTR_MASK(base) (((LPCOMP_V1_Type *)(base))->INTR_MASK) 464 #define LPCOMP_INTR_MASKED(base) (((LPCOMP_V1_Type *)(base))->INTR_MASKED) 465 466 467 /******************************************************************************* 468 * MCWDT 469 *******************************************************************************/ 470 471 #define MCWDT_STRUCT_MCWDT_CNTLOW(base) (((MCWDT_STRUCT_V1_Type *)(base))->MCWDT_CNTLOW) 472 #define MCWDT_STRUCT_MCWDT_CNTHIGH(base) (((MCWDT_STRUCT_V1_Type *)(base))->MCWDT_CNTHIGH) 473 #define MCWDT_STRUCT_MCWDT_MATCH(base) (((MCWDT_STRUCT_V1_Type *)(base))->MCWDT_MATCH) 474 #define MCWDT_STRUCT_MCWDT_CONFIG(base) (((MCWDT_STRUCT_V1_Type *)(base))->MCWDT_CONFIG) 475 #define MCWDT_STRUCT_MCWDT_LOCK(base) (((MCWDT_STRUCT_V1_Type *)(base))->MCWDT_LOCK) 476 #define MCWDT_STRUCT_MCWDT_CTL(base) (((MCWDT_STRUCT_V1_Type *)(base))->MCWDT_CTL) 477 #define MCWDT_STRUCT_MCWDT_INTR(base) (((MCWDT_STRUCT_V1_Type *)(base))->MCWDT_INTR) 478 #define MCWDT_STRUCT_MCWDT_INTR_SET(base) (((MCWDT_STRUCT_V1_Type *)(base))->MCWDT_INTR_SET) 479 #define MCWDT_STRUCT_MCWDT_INTR_MASK(base) (((MCWDT_STRUCT_V1_Type *)(base))->MCWDT_INTR_MASK) 480 #define MCWDT_STRUCT_MCWDT_INTR_MASKED(base) (((MCWDT_STRUCT_V1_Type *)(base))->MCWDT_INTR_MASKED) 481 482 483 /******************************************************************************* 484 * TCPWM 485 *******************************************************************************/ 486 487 #define TCPWM_CTRL_SET(base) (((TCPWM_V1_Type *)(base))->CTRL_SET) 488 #define TCPWM_CTRL_CLR(base) (((TCPWM_V1_Type *)(base))->CTRL_CLR) 489 #define TCPWM_CMD_START(base) (((TCPWM_V1_Type *)(base))->CMD_START) 490 #define TCPWM_CMD_RELOAD(base) (((TCPWM_V1_Type *)(base))->CMD_RELOAD) 491 #define TCPWM_CMD_STOP(base) (((TCPWM_V1_Type *)(base))->CMD_STOP) 492 #define TCPWM_CMD_CAPTURE(base) (((TCPWM_V1_Type *)(base))->CMD_CAPTURE) 493 494 #define TCPWM_CNT_CTRL(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].CTRL) 495 #define TCPWM_CNT_CC(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].CC) 496 #define TCPWM_CNT_CC_BUFF(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].CC_BUFF) 497 #define TCPWM_CNT_COUNTER(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].COUNTER) 498 #define TCPWM_CNT_PERIOD(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].PERIOD) 499 #define TCPWM_CNT_PERIOD_BUFF(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].PERIOD_BUFF) 500 #define TCPWM_CNT_STATUS(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].STATUS) 501 #define TCPWM_CNT_INTR(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].INTR) 502 #define TCPWM_CNT_INTR_SET(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].INTR_SET) 503 #define TCPWM_CNT_INTR_MASK(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].INTR_MASK) 504 #define TCPWM_CNT_INTR_MASKED(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].INTR_MASKED) 505 #define TCPWM_CNT_TR_CTRL0(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].TR_CTRL0) 506 #define TCPWM_CNT_TR_CTRL1(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].TR_CTRL1) 507 #define TCPWM_CNT_TR_CTRL2(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].TR_CTRL2) 508 509 #define TCPWM_GRP_CC1(grp) ((((cy_device->tcpwmCC1Present) >> (grp)) & 0x01U) != 0U) 510 #define TCPWM_GRP_AMC(grp) ((((cy_device->tcpwmAMCPresent) >> (grp)) & 0x01U) != 0U) 511 #define TCPWM_GRP_SMC(grp) ((((cy_device->tcpwmSMCPrecent) >> (grp)) & 0x01U) != 0U) 512 513 #define TCPWM_GRP_CNT_GET_GRP(cntNum) ((cntNum )/ 256U) 514 515 #define TCPWM_GRP_CNT_CTRL(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CTRL) 516 #define TCPWM_GRP_CNT_STATUS(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].STATUS) 517 #define TCPWM_GRP_CNT_COUNTER(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].COUNTER) 518 #define TCPWM_GRP_CNT_CC0(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CC0) 519 #define TCPWM_GRP_CNT_CC0_BUFF(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CC0_BUFF) 520 #define TCPWM_GRP_CNT_CC1(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CC1) 521 #define TCPWM_GRP_CNT_CC1_BUFF(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CC1_BUFF) 522 #define TCPWM_GRP_CNT_PERIOD(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].PERIOD) 523 #define TCPWM_GRP_CNT_PERIOD_BUFF(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].PERIOD_BUFF) 524 #define TCPWM_GRP_CNT_LINE_SEL(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].LINE_SEL) 525 #define TCPWM_GRP_CNT_LINE_SEL_BUFF(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].LINE_SEL_BUFF) 526 #define TCPWM_GRP_CNT_DT(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].DT) 527 #define TCPWM_GRP_CNT_TR_CMD(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_CMD) 528 #define TCPWM_GRP_CNT_TR_IN_SEL0(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_IN_SEL0) 529 #define TCPWM_GRP_CNT_TR_IN_SEL1(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_IN_SEL1) 530 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_IN_EDGE_SEL) 531 #define TCPWM_GRP_CNT_TR_PWM_CTRL(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_PWM_CTRL) 532 #define TCPWM_GRP_CNT_TR_OUT_SEL(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_OUT_SEL) 533 #define TCPWM_GRP_CNT_INTR(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].INTR) 534 #define TCPWM_GRP_CNT_INTR_SET(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].INTR_SET) 535 #define TCPWM_GRP_CNT_INTR_MASK(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].INTR_MASK) 536 #define TCPWM_GRP_CNT_INTR_MASKED(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].INTR_MASKED) 537 538 539 /******************************************************************************* 540 * SAR 541 *******************************************************************************/ 542 543 #define CY_SAR_INSTANCES (2UL) 544 #define CY_SAR0_BASE ((SAR_Type*)(cy_device->sar0Base)) 545 #define CY_SAR_INSTANCE(base) ((CY_SAR0_BASE == (base)) ? 0UL : 1UL) 546 547 #define SAR_SAMPLE_CTRL(base) (((SAR_V1_Type *)(base))->SAMPLE_CTRL) 548 #define SAR_SAMPLE_TIME01(base) (((SAR_V1_Type *)(base))->SAMPLE_TIME01) 549 #define SAR_SAMPLE_TIME23(base) (((SAR_V1_Type *)(base))->SAMPLE_TIME23) 550 551 #define SAR_RANGE_THRES(base) (((SAR_V1_Type *)(base))->RANGE_THRES) 552 #define SAR_RANGE_COND(base) (((SAR_V1_Type *)(base))->RANGE_COND) 553 #define SAR_RANGE_INTR(base) (((SAR_V1_Type *)(base))->RANGE_INTR) 554 #define SAR_RANGE_INTR_SET(base) (((SAR_V1_Type *)(base))->RANGE_INTR_SET) 555 556 #define SAR_RANGE_INTR_MASK(base) (((SAR_V1_Type *)(base))->RANGE_INTR_MASK) 557 #define SAR_RANGE_INTR_MASKED(base) (((SAR_V1_Type *)(base))->RANGE_INTR_MASKED) 558 559 #define SAR_CHAN_EN(base) (((SAR_V1_Type *)(base))->CHAN_EN) 560 #define SAR_CHAN_CONFIG(base, chan) (((SAR_V1_Type *)(base))->CHAN_CONFIG[(chan)]) 561 #define SAR_CHAN_RESULT(base, chan ) (((SAR_V1_Type *)(base))->CHAN_RESULT[(chan)]) 562 #define SAR_CHAN_RESULT_UPDATED(base) (((SAR_V1_Type *)(base))->CHAN_RESULT_UPDATED) 563 564 #define SAR_INTR(base) (((SAR_V1_Type *)(base))->INTR) 565 #define SAR_INTR_MASK(base) (((SAR_V1_Type *)(base))->INTR_MASK) 566 #define SAR_INTR_MASKED(base) (((SAR_V1_Type *)(base))->INTR_MASKED) 567 #define SAR_INTR_SET(base) (((SAR_V1_Type *)(base))->INTR_SET) 568 #define SAR_INTR_CAUSE(base) (((SAR_V1_Type *)(base))->INTR_CAUSE) 569 570 #define SAR_MUX_SWITCH_CLEAR0(base) (((SAR_V1_Type *)(base))->MUX_SWITCH_CLEAR0) 571 #define SAR_MUX_SWITCH0(base) (((SAR_V1_Type *)(base))->MUX_SWITCH0) 572 #define SAR_MUX_SWITCH_SQ_CTRL(base) (((SAR_V1_Type *)(base))->MUX_SWITCH_SQ_CTRL) 573 #define SAR_MUX_SWITCH_DS_CTRL(base) (((SAR_V1_Type *)(base))->MUX_SWITCH_DS_CTRL) 574 575 #define SAR_ANA_TRIM0(base) (((SAR_V1_Type *)(base))->ANA_TRIM0) 576 #define SAR_CTRL(base) (((SAR_V1_Type *)(base))->CTRL) 577 #define SAR_STATUS(base) (((SAR_V1_Type *)(base))->STATUS) 578 #define SAR_START_CTRL(base) (((SAR_V1_Type *)(base))->START_CTRL) 579 580 #define SAR_SATURATE_INTR(base) (((SAR_V1_Type *)(base))->SATURATE_INTR) 581 #define SAR_SATURATE_INTR_MASK(base) (((SAR_V1_Type *)(base))->SATURATE_INTR_MASK) 582 #define SAR_SATURATE_INTR_MASKED(base) (((SAR_V1_Type *)(base))->SATURATE_INTR_MASKED) 583 #define SAR_SATURATE_INTR_SET(base) (((SAR_V1_Type *)(base))->SATURATE_INTR_SET) 584 585 #define SAR_INJ_CHAN_CONFIG(base) (((SAR_V1_Type *)(base))->INJ_CHAN_CONFIG) 586 #define SAR_INJ_RESULT(base) (((SAR_V1_Type *)(base))->INJ_RESULT) 587 588 589 /******************************************************************************* 590 * SDHC 591 *******************************************************************************/ 592 593 #define SDHC_WRAP_CTL(base) (((SDHC_V1_Type *)(base))->WRAP.CTL) 594 #define SDHC_CORE_SDMASA_R(base) (((SDHC_V1_Type *)(base))->CORE.SDMASA_R) 595 #define SDHC_CORE_BLOCKSIZE_R(base) (((SDHC_V1_Type *)(base))->CORE.BLOCKSIZE_R) 596 #define SDHC_CORE_BLOCKCOUNT_R(base) (((SDHC_V1_Type *)(base))->CORE.BLOCKCOUNT_R) 597 #define SDHC_CORE_ARGUMENT_R(base) (((SDHC_V1_Type *)(base))->CORE.ARGUMENT_R) 598 #define SDHC_CORE_XFER_MODE_R(base) (((SDHC_V1_Type *)(base))->CORE.XFER_MODE_R) 599 #define SDHC_CORE_CMD_R(base) (((SDHC_V1_Type *)(base))->CORE.CMD_R) 600 #define SDHC_CORE_RESP01_R(base) (((SDHC_V1_Type *)(base))->CORE.RESP01_R) 601 #define SDHC_CORE_RESP23_R(base) (((SDHC_V1_Type *)(base))->CORE.RESP23_R) 602 #define SDHC_CORE_RESP45_R(base) (((SDHC_V1_Type *)(base))->CORE.RESP45_R) 603 #define SDHC_CORE_RESP67_R(base) (((SDHC_V1_Type *)(base))->CORE.RESP67_R) 604 #define SDHC_CORE_BUF_DATA_R(base) (((SDHC_V1_Type *)(base))->CORE.BUF_DATA_R) 605 #define SDHC_CORE_PSTATE_REG(base) (((SDHC_V1_Type *)(base))->CORE.PSTATE_REG) 606 #define SDHC_CORE_HOST_CTRL1_R(base) (((SDHC_V1_Type *)(base))->CORE.HOST_CTRL1_R) 607 #define SDHC_CORE_PWR_CTRL_R(base) (((SDHC_V1_Type *)(base))->CORE.PWR_CTRL_R) 608 #define SDHC_CORE_BGAP_CTRL_R(base) (((SDHC_V1_Type *)(base))->CORE.BGAP_CTRL_R) 609 #define SDHC_CORE_WUP_CTRL_R(base) (((SDHC_V1_Type *)(base))->CORE.WUP_CTRL_R) 610 #define SDHC_CORE_CLK_CTRL_R(base) (((SDHC_V1_Type *)(base))->CORE.CLK_CTRL_R) 611 #define SDHC_CORE_TOUT_CTRL_R(base) (((SDHC_V1_Type *)(base))->CORE.TOUT_CTRL_R) 612 #define SDHC_CORE_SW_RST_R(base) (((SDHC_V1_Type *)(base))->CORE.SW_RST_R) 613 #define SDHC_CORE_NORMAL_INT_STAT_R(base) (((SDHC_V1_Type *)(base))->CORE.NORMAL_INT_STAT_R) 614 #define SDHC_CORE_ERROR_INT_STAT_R(base) (((SDHC_V1_Type *)(base))->CORE.ERROR_INT_STAT_R) 615 #define SDHC_CORE_NORMAL_INT_STAT_EN_R(base) (((SDHC_V1_Type *)(base))->CORE.NORMAL_INT_STAT_EN_R) 616 #define SDHC_CORE_ERROR_INT_STAT_EN_R(base) (((SDHC_V1_Type *)(base))->CORE.ERROR_INT_STAT_EN_R) 617 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R(base) (((SDHC_V1_Type *)(base))->CORE.NORMAL_INT_SIGNAL_EN_R) 618 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R(base) (((SDHC_V1_Type *)(base))->CORE.ERROR_INT_SIGNAL_EN_R) 619 #define SDHC_CORE_AUTO_CMD_STAT_R(base) (((SDHC_V1_Type *)(base))->CORE.AUTO_CMD_STAT_R) 620 #define SDHC_CORE_HOST_CTRL2_R(base) (((SDHC_V1_Type *)(base))->CORE.HOST_CTRL2_R) 621 #define SDHC_CORE_CAPABILITIES1_R(base) (((SDHC_V1_Type *)(base))->CORE.CAPABILITIES1_R) 622 #define SDHC_CORE_CAPABILITIES2_R(base) (((SDHC_V1_Type *)(base))->CORE.CAPABILITIES2_R) 623 #define SDHC_CORE_CURR_CAPABILITIES1_R(base) (((SDHC_V1_Type *)(base))->CORE.CURR_CAPABILITIES1_R) 624 #define SDHC_CORE_CURR_CAPABILITIES2_R(base) (((SDHC_V1_Type *)(base))->CORE.CURR_CAPABILITIES2_R) 625 #define SDHC_CORE_ADMA_ERR_STAT_R(base) (((SDHC_V1_Type *)(base))->CORE.ADMA_ERR_STAT_R) 626 #define SDHC_CORE_ADMA_SA_LOW_R(base) (((SDHC_V1_Type *)(base))->CORE.ADMA_SA_LOW_R) 627 #define SDHC_CORE_ADMA_ID_LOW_R(base) (((SDHC_V1_Type *)(base))->CORE.ADMA_ID_LOW_R) 628 #define SDHC_CORE_EMMC_CTRL_R(base) (((SDHC_V1_Type *)(base))->CORE.EMMC_CTRL_R) 629 #define SDHC_CORE_GP_OUT_R(base) (((SDHC_V1_Type *)(base))->CORE.GP_OUT_R) 630 631 632 /******************************************************************************* 633 * SMARTIO 634 *******************************************************************************/ 635 636 #define SMARTIO_PRT_CTL(base) (((SMARTIO_PRT_Type *)(base))->CTL) 637 #define SMARTIO_PRT_SYNC_CTL(base) (((SMARTIO_PRT_Type *)(base))->SYNC_CTL) 638 #define SMARTIO_PRT_LUT_SEL(base, idx) (((SMARTIO_PRT_Type *)(base))->LUT_SEL[idx]) 639 #define SMARTIO_PRT_LUT_CTL(base, idx) (((SMARTIO_PRT_Type *)(base))->LUT_CTL[idx]) 640 #define SMARTIO_PRT_DU_SEL(base) (((SMARTIO_PRT_Type *)(base))->DU_SEL) 641 #define SMARTIO_PRT_DU_CTL(base) (((SMARTIO_PRT_Type *)(base))->DU_CTL) 642 #define SMARTIO_PRT_DATA(base) (((SMARTIO_PRT_Type *)(base))->DATA) 643 644 645 /******************************************************************************* 646 * SMIF 647 *******************************************************************************/ 648 649 #define SMIF_DEVICE_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->CTL) 650 #define SMIF_DEVICE_ADDR(base) (((SMIF_DEVICE_V1_Type *)(base))->ADDR) 651 #define SMIF_DEVICE_ADDR_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->ADDR_CTL) 652 #define SMIF_DEVICE_MASK(base) (((SMIF_DEVICE_V1_Type *)(base))->MASK) 653 #define SMIF_DEVICE_RD_CMD_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->RD_CMD_CTL) 654 #define SMIF_DEVICE_RD_ADDR_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->RD_ADDR_CTL) 655 #define SMIF_DEVICE_RD_MODE_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->RD_MODE_CTL) 656 #define SMIF_DEVICE_RD_DUMMY_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->RD_DUMMY_CTL) 657 #define SMIF_DEVICE_RD_DATA_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->RD_DATA_CTL) 658 #define SMIF_DEVICE_WR_CMD_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->WR_CMD_CTL) 659 #define SMIF_DEVICE_WR_ADDR_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->WR_ADDR_CTL) 660 #define SMIF_DEVICE_WR_MODE_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->WR_MODE_CTL) 661 #define SMIF_DEVICE_WR_DUMMY_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->WR_DUMMY_CTL) 662 #define SMIF_DEVICE_WR_DATA_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->WR_DATA_CTL) 663 664 #define SMIF_DEVICE_IDX(base, deviceIndex) (((SMIF_V1_Type *)(base))->DEVICE[deviceIndex]) 665 666 #define SMIF_DEVICE_IDX_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).CTL) 667 #define SMIF_DEVICE_IDX_ADDR(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).ADDR) 668 #define SMIF_DEVICE_IDX_ADDR_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).ADDR_CTL) 669 #define SMIF_DEVICE_IDX_MASK(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).MASK) 670 #define SMIF_DEVICE_IDX_RD_CMD_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).RD_CMD_CTL) 671 #define SMIF_DEVICE_IDX_RD_ADDR_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).RD_ADDR_CTL) 672 #define SMIF_DEVICE_IDX_RD_MODE_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).RD_MODE_CTL) 673 #define SMIF_DEVICE_IDX_RD_DUMMY_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).RD_DUMMY_CTL) 674 #define SMIF_DEVICE_IDX_RD_DATA_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).RD_DATA_CTL) 675 #define SMIF_DEVICE_IDX_WR_CMD_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).WR_CMD_CTL) 676 #define SMIF_DEVICE_IDX_WR_ADDR_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).WR_ADDR_CTL) 677 #define SMIF_DEVICE_IDX_WR_MODE_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).WR_MODE_CTL) 678 #define SMIF_DEVICE_IDX_WR_DUMMY_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).WR_DUMMY_CTL) 679 #define SMIF_DEVICE_IDX_WR_DATA_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).WR_DATA_CTL) 680 681 #define SMIF_CTL(base) (((SMIF_V1_Type *)(base))->CTL) 682 #define SMIF_STATUS(base) (((SMIF_V1_Type *)(base))->STATUS) 683 #define SMIF_TX_DATA_FIFO_CTL(base) (((SMIF_V1_Type *)(base))->TX_DATA_FIFO_CTL) 684 #define SMIF_RX_DATA_FIFO_CTL(base) (((SMIF_V1_Type *)(base))->RX_DATA_FIFO_CTL) 685 #define SMIF_TX_DATA_FIFO_WR1(base) (((SMIF_V1_Type *)(base))->TX_DATA_FIFO_WR1) 686 #define SMIF_TX_DATA_FIFO_WR2(base) (((SMIF_V1_Type *)(base))->TX_DATA_FIFO_WR2) 687 #define SMIF_TX_DATA_FIFO_WR4(base) (((SMIF_V1_Type *)(base))->TX_DATA_FIFO_WR4) 688 #define SMIF_RX_DATA_FIFO_RD1(base) (((SMIF_V1_Type *)(base))->RX_DATA_FIFO_RD1) 689 #define SMIF_RX_DATA_FIFO_RD2(base) (((SMIF_V1_Type *)(base))->RX_DATA_FIFO_RD2) 690 #define SMIF_RX_DATA_FIFO_RD4(base) (((SMIF_V1_Type *)(base))->RX_DATA_FIFO_RD4) 691 #define SMIF_TX_CMD_FIFO_WR(base) (((SMIF_V1_Type *)(base))->TX_CMD_FIFO_WR) 692 #define SMIF_TX_CMD_FIFO_STATUS(base) (((SMIF_V1_Type *)(base))->TX_CMD_FIFO_STATUS) 693 #define SMIF_RX_DATA_FIFO_STATUS(base) (((SMIF_V1_Type *)(base))->RX_DATA_FIFO_STATUS) 694 #define SMIF_TX_DATA_FIFO_STATUS(base) (((SMIF_V1_Type *)(base))->TX_DATA_FIFO_STATUS) 695 #define SMIF_INTR(base) (((SMIF_V1_Type *)(base))->INTR) 696 #define SMIF_INTR_SET(base) (((SMIF_V1_Type *)(base))->INTR_SET) 697 #define SMIF_INTR_MASK(base) (((SMIF_V1_Type *)(base))->INTR_MASK) 698 #define SMIF_INTR_MASKED(base) (((SMIF_V1_Type *)(base))->INTR_MASKED) 699 #define SMIF_CRYPTO_INPUT0(base) (((SMIF_V1_Type *)(base))->CRYPTO_INPUT0) 700 #define SMIF_CRYPTO_OUTPUT0(base) (((SMIF_V1_Type *)(base))->CRYPTO_OUTPUT0) 701 #define SMIF_CRYPTO_OUTPUT1(base) (((SMIF_V1_Type *)(base))->CRYPTO_OUTPUT1) 702 #define SMIF_CRYPTO_OUTPUT2(base) (((SMIF_V1_Type *)(base))->CRYPTO_OUTPUT2) 703 #define SMIF_CRYPTO_OUTPUT3(base) (((SMIF_V1_Type *)(base))->CRYPTO_OUTPUT3) 704 #define SMIF_CRYPTO_CMD(base) (((SMIF_V1_Type *)(base))->CRYPTO_CMD) 705 #define SMIF_SLOW_CA_CTL(base) (((SMIF_V1_Type *)(base))->SLOW_CA_CTL) 706 #define SMIF_FAST_CA_CTL(base) (((SMIF_V1_Type *)(base))->FAST_CA_CTL) 707 #define SMIF_SLOW_CA_CMD(base) (((SMIF_V1_Type *)(base))->SLOW_CA_CMD) 708 #define SMIF_FAST_CA_CMD(base) (((SMIF_V1_Type *)(base))->FAST_CA_CMD) 709 710 711 /******************************************************************************* 712 * DW 713 *******************************************************************************/ 714 715 #define CY_DW_V1 (0x20U > cy_device->dwVersion) 716 #define CY_DW_CRC (0x20U <= cy_device->dwVersion) 717 #define CY_DW0_BASE ((DW_Type*) 0x40280000UL) 718 #define CY_DW0_CH_NR (cy_device->cpussDw0ChNr) 719 #define CY_DW1_CH_NR (cy_device->cpussDw1ChNr) 720 721 #define CY_DW_CH_CTL_PRIO_Pos ((uint32_t)(cy_device->dwChCtlPrioPos)) 722 #define CY_DW_CH_CTL_PRIO_Msk ((uint32_t)(0x3UL << CY_DW_CH_CTL_PRIO_Pos)) 723 #define CY_DW_CH_CTL_PREEMPTABLE_Pos ((uint32_t)(cy_device->dwChCtlPreemptablePos)) 724 #define CY_DW_CH_CTL_PREEMPTABLE_Msk ((uint32_t)(0x1UL << CY_DW_CH_CTL_PREEMPTABLE_Pos)) 725 #define CY_DW_STATUS_CH_IDX_Pos ((uint32_t)(cy_device->dwStatusChIdxPos)) 726 #define CY_DW_STATUS_CH_IDX_Msk (cy_device->dwStatusChIdxMsk) 727 728 #define DW_CTL(base) (((DW_Type*)(base))->CTL) 729 #define DW_STATUS(base) (((DW_Type const*)(base))->STATUS) 730 #define DW_DESCR_SRC(base) (((DW_Type*)(base))->ACT_DESCR_SRC) 731 #define DW_DESCR_DST(base) (((DW_Type*)(base))->ACT_DESCR_DST) 732 733 #define DW_CRC_CTL(base) (((DW_V2_Type*)(base))->CRC_CTL) 734 #define DW_CRC_DATA_CTL(base) (((DW_V2_Type*)(base))->CRC_DATA_CTL) 735 #define DW_CRC_REM_CTL(base) (((DW_V2_Type*)(base))->CRC_REM_CTL) 736 #define DW_CRC_POL_CTL(base) (((DW_V2_Type*)(base))->CRC_POL_CTL) 737 #define DW_CRC_LFSR_CTL(base) (((DW_V2_Type*)(base))->CRC_LFSR_CTL) 738 739 #define DW_CH(base, chan) ((DW_CH_STRUCT_V2_Type*)((uint32_t)(base) + cy_device->dwChOffset + ((chan) * cy_device->dwChSize))) 740 #define DW_CH_CTL(base, chan) (DW_CH(base, chan)->CH_CTL) 741 #define DW_CH_STATUS(base, chan) (DW_CH(base, chan)->CH_STATUS) 742 #define DW_CH_IDX(base, chan) (DW_CH(base, chan)->CH_IDX) 743 #define DW_CH_CURR_PTR(base, chan) (DW_CH(base, chan)->CH_CURR_PTR) 744 745 #define DW_CH_INTR(base, chan) (DW_CH(base, chan)->INTR) 746 #define DW_CH_INTR_SET(base, chan) (DW_CH(base, chan)->INTR_SET) 747 #define DW_CH_INTR_MASK(base, chan) (DW_CH(base, chan)->INTR_MASK) 748 #define DW_CH_INTR_MASKED(base, chan) (DW_CH(base, chan)->INTR_MASKED) 749 750 751 /******************************************************************************* 752 * DMAC 753 *******************************************************************************/ 754 755 #define CY_DMAC_CH_NR (4UL) 756 #define DMAC_CTL(base) (((DMAC_V2_Type*)(base))->CTL) 757 #define DMAC_ACTIVE(base) (((DMAC_V2_Type const*)(base))->ACTIVE) 758 #define DMAC_CH(base, chan) (&(((DMAC_V2_Type*)(base))->CH[(chan)])) 759 #define DMAC_CH_CTL(base, chan) (DMAC_CH(base, chan)->CTL) 760 #define DMAC_CH_IDX(base, chan) (DMAC_CH(base, chan)->IDX) 761 #define DMAC_CH_CURR(base, chan) (DMAC_CH(base, chan)->CURR) 762 #define DMAC_CH_DESCR_SRC(base, chan) (DMAC_CH(base, chan)->DESCR_SRC) 763 #define DMAC_CH_DESCR_DST(base, chan) (DMAC_CH(base, chan)->DESCR_DST) 764 #define DMAC_CH_INTR(base, chan) (DMAC_CH(base, chan)->INTR) 765 #define DMAC_CH_INTR_SET(base, chan) (DMAC_CH(base, chan)->INTR_SET) 766 #define DMAC_CH_INTR_MASK(base, chan) (DMAC_CH(base, chan)->INTR_MASK) 767 #define DMAC_CH_INTR_MASKED(base, chan) (DMAC_CH(base, chan)->INTR_MASKED) 768 769 770 /******************************************************************************* 771 * PERI 772 *******************************************************************************/ 773 #define CY_PERI_BASE ((PERI_V1_Type *) cy_device->periBase) 774 775 #define CY_PERI_V1 (0x20U > cy_device->periVersion) /* true if the mxperi version is 1.x */ 776 #define CY_PERI_V2_TR_GR_SIZE (sizeof(PERI_TR_GR_V2_Type)) 777 #define CY_PERI_TR_CTL_NUM ((uint32_t)cy_device->periTrGrSize / sizeof(uint32_t)) 778 #define CY_PERI_TR_CTL_SEL_Pos (0UL) 779 #define CY_PERI_TR_CTL_SEL_Msk ((uint32_t)CY_PERI_TR_CTL_NUM - 1UL) 780 #define CY_PERI_TR_CMD_GROUP_SEL_Pos (PERI_TR_CMD_GROUP_SEL_Pos) 781 #define CY_PERI_TR_CMD_GROUP_SEL_Msk ((uint32_t)cy_device->periTrCmdGrSelMsk) 782 783 #define PERI_TR_CMD (*(volatile uint32_t*)((uint32_t)cy_device->periBase + \ 784 (uint32_t)cy_device->periTrCmdOffset)) 785 #define PERI_TR_GR_TR_CTL(group, trCtl) (*(volatile uint32_t*)((uint32_t)cy_device->periBase + \ 786 (uint32_t)cy_device->periTrGrOffset + \ 787 ((group) * (uint32_t)cy_device->periTrGrSize) + \ 788 ((trCtl) * (uint32_t)sizeof(uint32_t)))) 789 790 #define CY_PERI_CLOCK_NR ((uint32_t)(cy_device->periClockNr)) 791 792 #define PERI_DIV_CMD ((CY_PERI_BASE)->DIV_CMD) 793 794 #define CY_PERI_DIV_CMD_DIV_SEL_Pos (PERI_DIV_CMD_DIV_SEL_Pos) 795 #define CY_PERI_DIV_CMD_DIV_SEL_Msk ((uint32_t)(cy_device->periDivCmdDivSelMsk)) 796 #define CY_PERI_DIV_CMD_TYPE_SEL_Pos ((uint32_t)(cy_device->periDivCmdTypeSelPos)) 797 #define CY_PERI_DIV_CMD_TYPE_SEL_Msk ((uint32_t)(0x3UL << CY_PERI_DIV_CMD_TYPE_SEL_Pos)) 798 #define CY_PERI_DIV_CMD_PA_DIV_SEL_Pos ((uint32_t)(cy_device->periDivCmdPaDivSelPos)) 799 #define CY_PERI_DIV_CMD_PA_DIV_SEL_Msk ((uint32_t)(CY_PERI_DIV_CMD_DIV_SEL_Msk << CY_PERI_DIV_CMD_PA_DIV_SEL_Pos)) 800 #define CY_PERI_DIV_CMD_PA_TYPE_SEL_Pos ((uint32_t)(cy_device->periDivCmdPaTypeSelPos)) 801 #define CY_PERI_DIV_CMD_PA_TYPE_SEL_Msk ((uint32_t)(0x3UL << CY_PERI_DIV_CMD_PA_TYPE_SEL_Pos)) 802 803 #define PERI_CLOCK_CTL ((CY_PERI_BASE)->CLOCK_CTL) 804 805 #define CY_PERI_CLOCK_CTL_DIV_SEL_Pos (PERI_CLOCK_CTL_DIV_SEL_Pos) 806 #define CY_PERI_CLOCK_CTL_DIV_SEL_Msk (CY_PERI_DIV_CMD_DIV_SEL_Msk) 807 #define CY_PERI_CLOCK_CTL_TYPE_SEL_Pos (CY_PERI_DIV_CMD_TYPE_SEL_Pos) 808 #define CY_PERI_CLOCK_CTL_TYPE_SEL_Msk (CY_PERI_DIV_CMD_TYPE_SEL_Msk) 809 810 #define PERI_DIV_8_CTL ((volatile uint32_t *)((uint32_t)(cy_device->periBase) + (uint32_t)(cy_device->periDiv8CtlOffset))) 811 #define PERI_DIV_16_CTL ((volatile uint32_t *)((uint32_t)(cy_device->periBase) + (uint32_t)(cy_device->periDiv16CtlOffset))) 812 #define PERI_DIV_16_5_CTL ((volatile uint32_t *)((uint32_t)(cy_device->periBase) + (uint32_t)(cy_device->periDiv16_5CtlOffset))) 813 #define PERI_DIV_24_5_CTL ((volatile uint32_t *)((uint32_t)(cy_device->periBase) + (uint32_t)(cy_device->periDiv24_5CtlOffset))) 814 815 #define PERI_GR_SL_CTL(udbGroupNr) ((CY_PERI_BASE)->GR[udbGroupNr].SL_CTL) 816 817 #define PERI_PPU_PR_ADDR0(base) (((PERI_PPU_PR_V1_Type *) (base))->ADDR0) 818 #define PERI_PPU_PR_ATT0(base) (((PERI_PPU_PR_V1_Type *) (base))->ATT0) 819 #define PERI_PPU_PR_ATT1(base) (((PERI_PPU_PR_V1_Type *) (base))->ATT1) 820 821 #define PERI_PPU_GR_ADDR0(base) (((PERI_PPU_GR_V1_Type *) (base))->ADDR0) 822 #define PERI_PPU_GR_ATT0(base) (((PERI_PPU_GR_V1_Type *) (base))->ATT0) 823 #define PERI_PPU_GR_ATT1(base) (((PERI_PPU_GR_V1_Type *) (base))->ATT1) 824 825 #define PERI_GR_PPU_SL_ADDR0(base) (((PERI_GR_PPU_SL_V1_Type *) (base))->ADDR0) 826 #define PERI_GR_PPU_SL_ATT0(base) (((PERI_GR_PPU_SL_V1_Type *) (base))->ATT0) 827 #define PERI_GR_PPU_SL_ATT1(base) (((PERI_GR_PPU_SL_V1_Type *) (base))->ATT1) 828 829 #define PERI_GR_PPU_RG_ADDR0(base) (((PERI_GR_PPU_RG_V1_Type *) (base))->ADDR0) 830 #define PERI_GR_PPU_RG_ATT0(base) (((PERI_GR_PPU_RG_V1_Type *) (base))->ATT0) 831 #define PERI_GR_PPU_RG_ATT1(base) (((PERI_GR_PPU_RG_V1_Type *) (base))->ATT1) 832 833 #define PERI_MS_PPU_PR_SL_ADDR(base) (((PERI_MS_PPU_PR_V2_Type *) (base))->SL_ADDR) 834 #define PERI_MS_PPU_PR_SL_SIZE(base) (((PERI_MS_PPU_PR_V2_Type *) (base))->SL_SIZE) 835 #define PERI_MS_PPU_PR_MS_ATT(base) ((volatile uint32_t *) &(((PERI_MS_PPU_PR_V2_Type *)(base))->MS_ATT0)) 836 #define PERI_MS_PPU_PR_SL_ATT(base) ((volatile uint32_t *) &(((PERI_MS_PPU_PR_V2_Type *)(base))->SL_ATT0)) 837 #define PERI_MS_PPU_FX_MS_ATT(base) ((volatile uint32_t *) &(((PERI_MS_PPU_FX_V2_Type *)(base))->MS_ATT0)) 838 #define PERI_MS_PPU_FX_SL_ATT(base) ((volatile uint32_t *) &(((PERI_MS_PPU_FX_V2_Type *)(base))->SL_ATT0)) 839 840 #define PROT_PERI_PPU_PR_STRUCT_IDX_ATT0(stcIdx) ((CY_PERI_BASE)->PPU_PR[(stcIdx)].ATT0) 841 #define PROT_PERI_PPU_PR_STRUCT_IDX_ATT1(stcIdx) ((CY_PERI_BASE)->PPU_PR[(stcIdx)].ATT1) 842 843 #define PROT_PERI_PPU_PR_STRUCT_IDX(stcIdx) ((PERI_PPU_PR_Type*) &(CY_PERI_BASE)->PPU_PR[(stcIdx)]) 844 845 846 /******************************************************************************* 847 * PROT 848 *******************************************************************************/ 849 #define CY_PROT_BASE (cy_device->protBase) 850 851 #define CY_PROT_PC_MAX (8UL) 852 #define CY_PROT_BUS_MASTER_MASK (cy_device->protBusMasterMask) 853 #define PROT_MPU_MS_CTL(mpu) (((PROT_Type*)CY_PROT_BASE)->CYMPU[(mpu)].MS_CTL) 854 #define PROT_MPU_MPU_STRUCT_ADDR(base) (((PROT_MPU_MPU_STRUCT_Type *) (base))->ADDR) 855 #define PROT_MPU_MPU_STRUCT_ATT(base) (((PROT_MPU_MPU_STRUCT_Type *) (base))->ATT) 856 857 #define PROT_SMPU_SMPU_STRUCT_ADDR0(base) (((PROT_SMPU_SMPU_STRUCT_Type *) (base))->ADDR0) 858 #define PROT_SMPU_SMPU_STRUCT_ADDR1(base) (((PROT_SMPU_SMPU_STRUCT_Type *) (base))->ADDR1) 859 #define PROT_SMPU_SMPU_STRUCT_ATT0(base) (((PROT_SMPU_SMPU_STRUCT_Type *) (base))->ATT0) 860 #define PROT_SMPU_SMPU_STRUCT_ATT1(base) (((PROT_SMPU_SMPU_STRUCT_Type *) (base))->ATT1) 861 862 #define PROT_SMPU_SMPU_STRUCT_IDX_ATT0(stcIdx) (((PROT_SMPU_Type *) CY_PROT_BASE)->SMPU_STRUCT[(stcIdx)].ATT0) 863 #define PROT_SMPU_SMPU_STRUCT_IDX_ATT1(stcIdx) (((PROT_SMPU_Type *) CY_PROT_BASE)->SMPU_STRUCT[(stcIdx)].ATT1) 864 #define PROT_SMPU_SMPU_STRUCT_IDX(stcIdx) (((PROT_SMPU_SMPU_STRUCT_Type *) &((PROT_SMPU_Type *) CY_PROT_BASE)->SMPU_STRUCT[(stcIdx)])) 865 866 867 /******************************************************************************* 868 * IOSS 869 *******************************************************************************/ 870 871 #define CY_GPIO_BASE ((uint32_t)(cy_device->gpioBase)) 872 873 #define GPIO_INTR_CAUSE0 (((GPIO_V1_Type*)(cy_device->gpioBase))->INTR_CAUSE0) 874 #define GPIO_INTR_CAUSE1 (((GPIO_V1_Type*)(cy_device->gpioBase))->INTR_CAUSE1) 875 #define GPIO_INTR_CAUSE2 (((GPIO_V1_Type*)(cy_device->gpioBase))->INTR_CAUSE2) 876 #define GPIO_INTR_CAUSE3 (((GPIO_V1_Type*)(cy_device->gpioBase))->INTR_CAUSE3) 877 878 #define GPIO_PRT_OUT(base) (((GPIO_PRT_Type*)(base))->OUT) 879 #define GPIO_PRT_OUT_CLR(base) (((GPIO_PRT_Type*)(base))->OUT_CLR) 880 #define GPIO_PRT_OUT_SET(base) (((GPIO_PRT_Type*)(base))->OUT_SET) 881 #define GPIO_PRT_OUT_INV(base) (((GPIO_PRT_Type*)(base))->OUT_INV) 882 #define GPIO_PRT_IN(base) (((GPIO_PRT_Type*)(base))->IN) 883 #define GPIO_PRT_INTR(base) (((GPIO_PRT_Type*)(base))->INTR) 884 #define GPIO_PRT_INTR_MASK(base) (((GPIO_PRT_Type*)(base))->INTR_MASK) 885 #define GPIO_PRT_INTR_MASKED(base) (((GPIO_PRT_Type*)(base))->INTR_MASKED) 886 #define GPIO_PRT_INTR_SET(base) (((GPIO_PRT_Type*)(base))->INTR_SET) 887 888 #define GPIO_PRT_INTR_CFG(base) (*(volatile uint32_t *)((uint32_t)(base) + (uint32_t)(cy_device->gpioPrtIntrCfgOffset))) 889 #define GPIO_PRT_CFG(base) (*(volatile uint32_t *)((uint32_t)(base) + (uint32_t)(cy_device->gpioPrtCfgOffset))) 890 #define GPIO_PRT_CFG_IN(base) (*(volatile uint32_t *)((uint32_t)(base) + (uint32_t)(cy_device->gpioPrtCfgInOffset))) 891 #define GPIO_PRT_CFG_OUT(base) (*(volatile uint32_t *)((uint32_t)(base) + (uint32_t)(cy_device->gpioPrtCfgOutOffset))) 892 #define GPIO_PRT_CFG_SIO(base) (*(volatile uint32_t *)((uint32_t)(base) + (uint32_t)(cy_device->gpioPrtCfgSioOffset))) 893 894 #define CY_HSIOM_BASE ((uint32_t)(cy_device->hsiomBase)) 895 896 #define HSIOM_PRT_PORT_SEL0(base) (((HSIOM_PRT_V1_Type *)(base))->PORT_SEL0) 897 #define HSIOM_PRT_PORT_SEL1(base) (((HSIOM_PRT_V1_Type *)(base))->PORT_SEL1) 898 899 #define HSIOM_AMUX_SPLIT_CTL(switchCtrl) (((HSIOM_V1_Type *) CY_HSIOM_BASE)->AMUX_SPLIT_CTL[switchCtrl]) 900 901 902 /******************************************************************************* 903 * I2S 904 *******************************************************************************/ 905 906 #define REG_I2S_CTL(base) (((I2S_V1_Type*)(base))->CTL) 907 #define REG_I2S_CMD(base) (((I2S_V1_Type*)(base))->CMD) 908 #define REG_I2S_CLOCK_CTL(base) (((I2S_V1_Type*)(base))->CLOCK_CTL) 909 #define REG_I2S_TR_CTL(base) (((I2S_V1_Type*)(base))->TR_CTL) 910 #define REG_I2S_TX_CTL(base) (((I2S_V1_Type*)(base))->TX_CTL) 911 #define REG_I2S_TX_FIFO_CTL(base) (((I2S_V1_Type*)(base))->TX_FIFO_CTL) 912 #define REG_I2S_TX_FIFO_STATUS(base) (((I2S_V1_Type*)(base))->TX_FIFO_STATUS) 913 #define REG_I2S_TX_FIFO_WR(base) (((I2S_V1_Type*)(base))->TX_FIFO_WR) 914 #define REG_I2S_TX_WATCHDOG(base) (((I2S_V1_Type*)(base))->TX_WATCHDOG) 915 #define REG_I2S_RX_CTL(base) (((I2S_V1_Type*)(base))->RX_CTL) 916 #define REG_I2S_RX_FIFO_CTL(base) (((I2S_V1_Type*)(base))->RX_FIFO_CTL) 917 #define REG_I2S_RX_FIFO_STATUS(base) (((I2S_V1_Type*)(base))->RX_FIFO_STATUS) 918 #define REG_I2S_RX_FIFO_RD(base) (((I2S_V1_Type*)(base))->RX_FIFO_RD) 919 #define REG_I2S_RX_FIFO_RD_SILENT(base) (((I2S_V1_Type*)(base))->RX_FIFO_RD_SILENT) 920 #define REG_I2S_RX_WATCHDOG(base) (((I2S_V1_Type*)(base))->RX_WATCHDOG) 921 #define REG_I2S_INTR(base) (((I2S_V1_Type*)(base))->INTR) 922 #define REG_I2S_INTR_SET(base) (((I2S_V1_Type*)(base))->INTR_SET) 923 #define REG_I2S_INTR_MASK(base) (((I2S_V1_Type*)(base))->INTR_MASK) 924 #define REG_I2S_INTR_MASKED(base) (((I2S_V1_Type*)(base))->INTR_MASKED) 925 926 927 /******************************************************************************* 928 * PDM 929 *******************************************************************************/ 930 931 #define PDM_PCM_CTL(base) (((PDM_V1_Type*)(base))->CTL) 932 #define PDM_PCM_CMD(base) (((PDM_V1_Type*)(base))->CMD) 933 #define PDM_PCM_CLOCK_CTL(base) (((PDM_V1_Type*)(base))->CLOCK_CTL) 934 #define PDM_PCM_MODE_CTL(base) (((PDM_V1_Type*)(base))->MODE_CTL) 935 #define PDM_PCM_DATA_CTL(base) (((PDM_V1_Type*)(base))->DATA_CTL) 936 #define PDM_PCM_TR_CTL(base) (((PDM_V1_Type*)(base))->TR_CTL) 937 #define PDM_PCM_INTR_MASK(base) (((PDM_V1_Type*)(base))->INTR_MASK) 938 #define PDM_PCM_INTR_MASKED(base) (((PDM_V1_Type*)(base))->INTR_MASKED) 939 #define PDM_PCM_INTR(base) (((PDM_V1_Type*)(base))->INTR) 940 #define PDM_PCM_INTR_SET(base) (((PDM_V1_Type*)(base))->INTR_SET) 941 #define PDM_PCM_RX_FIFO_STATUS(base) (((PDM_V1_Type*)(base))->RX_FIFO_STATUS) 942 #define PDM_PCM_RX_FIFO_CTL(base) (((PDM_V1_Type*)(base))->RX_FIFO_CTL) 943 #define PDM_PCM_RX_FIFO_RD(base) (((PDM_V1_Type*)(base))->RX_FIFO_RD) 944 #define PDM_PCM_RX_FIFO_RD_SILENT(base) (((PDM_V1_Type*)(base))->RX_FIFO_RD_SILENT) 945 946 947 /******************************************************************************* 948 * LCD 949 *******************************************************************************/ 950 951 #define LCD_OCTET_NUM (8U) /* LCD_NUMPORTS - number of octets supporting up to 4 COMs */ 952 #define LCD_OCTET_NUM_8 (8U) /* LCD_NUMPORTS8 - number of octets supporting up to 8 COMs */ 953 #define LCD_OCTET_NUM_16 (0U) /* LCD_NUMPORTS16 - number of octets supporting up to 16 COMs */ 954 #define LCD_COM_NUM (8U) /* LCD_CHIP_TOP_COM_NR - maximum number of commons */ 955 956 #define LCD_ID(base) (((LCD_V1_Type*)(base))->ID) 957 #define LCD_CONTROL(base) (((LCD_V1_Type*)(base))->CONTROL) 958 #define LCD_DIVIDER(base) (((LCD_V1_Type*)(base))->DIVIDER) 959 #define LCD_DATA0(base) (((LCD_V1_Type*)(base))->DATA0) 960 #define LCD_DATA1(base) (((LCD_V1_Type*)(base))->DATA1) 961 #define LCD_DATA2(base) (((LCD_V1_Type*)(base))->DATA2) 962 #define LCD_DATA3(base) (((LCD_V1_Type*)(base))->DATA3) 963 964 965 /******************************************************************************* 966 * IPC 967 *******************************************************************************/ 968 969 #define CY_IPC_V1 (0x20u > cy_device->ipcVersion) /* true if the IPC version is 1.x */ 970 971 #define REG_IPC_STRUCT_ACQUIRE(base) (((IPC_STRUCT_Type*)(base))->ACQUIRE) 972 #define REG_IPC_STRUCT_RELEASE(base) (((IPC_STRUCT_Type*)(base))->RELEASE) 973 #define REG_IPC_STRUCT_NOTIFY(base) (((IPC_STRUCT_Type*)(base))->NOTIFY) 974 #if (CY_IP_M4CPUSS_VERSION == 1U) 975 #define REG_IPC_STRUCT_DATA(base) (((IPC_STRUCT_V1_Type*)(base))->DATA) 976 #else 977 #define REG_IPC_STRUCT_DATA(base) (((IPC_STRUCT_V2_Type*)(base))->DATA0) 978 #endif 979 #define REG_IPC_STRUCT_DATA1(base) (((IPC_STRUCT_V2_Type*)(base))->DATA1) 980 #define REG_IPC_STRUCT_LOCK_STATUS(base) (*(volatile uint32_t*)((uint32_t)(base) + cy_device->ipcLockStatusOffset)) 981 982 #define REG_IPC_INTR_STRUCT_INTR(base) (((IPC_INTR_STRUCT_Type*)(base))->INTR) 983 #define REG_IPC_INTR_STRUCT_INTR_SET(base) (((IPC_INTR_STRUCT_Type*)(base))->INTR_SET) 984 #define REG_IPC_INTR_STRUCT_INTR_MASK(base) (((IPC_INTR_STRUCT_Type*)(base))->INTR_MASK) 985 #define REG_IPC_INTR_STRUCT_INTR_MASKED(base) (((IPC_INTR_STRUCT_Type*)(base))->INTR_MASKED) 986 987 #define CY_IPC_STRUCT_PTR(ipcIndex) ((IPC_STRUCT_Type*)(cy_device->ipcBase + (cy_device->ipcStructSize * (ipcIndex)))) 988 #define CY_IPC_INTR_STRUCT_PTR(ipcIntrIndex) &(((IPC_Type *)cy_device->ipcBase)->INTR_STRUCT[ipcIntrIndex]) 989 990 #define CY_IPC_CHANNELS (uint32_t)(cy_device->cpussIpcNr) 991 #define CY_IPC_INTERRUPTS (uint32_t)(cy_device->cpussIpcIrqNr) 992 993 /* IPC channel definitions */ 994 #define CY_IPC_CHAN_SYSCALL_CM0 (0U) /* System calls for the CM0 processor */ 995 #define CY_IPC_CHAN_SYSCALL_CM4 (1U) /* System calls for the 1st non-CM0 processor */ 996 #define CY_IPC_CHAN_SYSCALL_DAP (2UL) /* System calls for the DAP */ 997 #define CY_IPC_CHAN_SEMA (3UL) /* IPC data channel for the Semaphores */ 998 #define CY_IPC_CHAN_PRA (4UL) /* IPC data channel for PRA */ 999 #define CY_IPC_CHAN_CYPIPE_EP0 (5UL) /* IPC data channel for CYPIPE EP0 */ 1000 #define CY_IPC_CHAN_CYPIPE_EP1 (6UL) /* IPC data channel for CYPIPE EP1 */ 1001 #define CY_IPC_CHAN_DDFT (7UL) /* IPC data channel for DDFT */ 1002 1003 /* IPC Notify interrupts definitions */ 1004 #define CY_IPC_INTR_SYSCALL1 (0UL) 1005 #define CY_IPC_INTR_CYPIPE_EP0 (3UL) 1006 #define CY_IPC_INTR_CYPIPE_EP1 (4UL) 1007 #define CY_IPC_INTR_PRA (5UL) 1008 #define CY_IPC_INTR_SPARE (7UL) 1009 1010 /* Endpoint indexes in the pipe array */ 1011 #define CY_IPC_EP_CYPIPE_CM0_ADDR (0UL) 1012 #define CY_IPC_EP_CYPIPE_CM4_ADDR (1UL) 1013 1014 1015 /******************************************************************************* 1016 * CTB 1017 *******************************************************************************/ 1018 1019 #define CTBM_CTB_CTRL(base) (((CTBM_V1_Type *) (base))->CTB_CTRL) 1020 #define CTBM_CTB_SW_DS_CTRL(base) (((CTBM_V1_Type *) (base))->CTB_SW_DS_CTRL) 1021 #define CTBM_CTB_SW_SQ_CTRL(base) (((CTBM_V1_Type *) (base))->CTB_SW_SQ_CTRL) 1022 #define CTBM_CTD_SW(base) (((CTBM_V1_Type *) (base))->CTD_SW) 1023 #define CTBM_CTD_SW_CLEAR(base) (((CTBM_V1_Type *) (base))->CTD_SW_CLEAR) 1024 #define CTBM_COMP_STAT(base) (((CTBM_V1_Type *) (base))->COMP_STAT) 1025 #define CTBM_OA0_SW_CLEAR(base) (((CTBM_V1_Type *) (base))->OA0_SW_CLEAR) 1026 #define CTBM_OA1_SW_CLEAR(base) (((CTBM_V1_Type *) (base))->OA1_SW_CLEAR) 1027 #define CTBM_OA0_SW(base) (((CTBM_V1_Type *) (base))->OA0_SW) 1028 #define CTBM_OA1_SW(base) (((CTBM_V1_Type *) (base))->OA1_SW) 1029 #define CTBM_OA_RES0_CTRL(base) (((CTBM_V1_Type *) (base))->OA_RES0_CTRL) 1030 #define CTBM_OA_RES1_CTRL(base) (((CTBM_V1_Type *) (base))->OA_RES1_CTRL) 1031 #define CTBM_OA0_COMP_TRIM(base) (((CTBM_V1_Type *) (base))->OA0_COMP_TRIM) 1032 #define CTBM_OA1_COMP_TRIM(base) (((CTBM_V1_Type *) (base))->OA1_COMP_TRIM) 1033 #define CTBM_OA0_OFFSET_TRIM(base) (((CTBM_V1_Type *) (base))->OA0_OFFSET_TRIM) 1034 #define CTBM_OA1_OFFSET_TRIM(base) (((CTBM_V1_Type *) (base))->OA1_OFFSET_TRIM) 1035 #define CTBM_OA0_SLOPE_OFFSET_TRIM(base) (((CTBM_V1_Type *) (base))->OA0_SLOPE_OFFSET_TRIM) 1036 #define CTBM_OA1_SLOPE_OFFSET_TRIM(base) (((CTBM_V1_Type *) (base))->OA1_SLOPE_OFFSET_TRIM) 1037 #define CTBM_INTR(base) (((CTBM_V1_Type *) (base))->INTR) 1038 #define CTBM_INTR_SET(base) (((CTBM_V1_Type *) (base))->INTR_SET) 1039 #define CTBM_INTR_MASK(base) (((CTBM_V1_Type *) (base))->INTR_MASK) 1040 #define CTBM_INTR_MASKED(base) (((CTBM_V1_Type *) (base))->INTR_MASKED) 1041 1042 1043 /******************************************************************************* 1044 * CTDAC 1045 *******************************************************************************/ 1046 1047 #define CTDAC_CTDAC_CTRL(base) (((CTDAC_V1_Type *) (base))->CTDAC_CTRL) 1048 #define CTDAC_CTDAC_SW(base) (((CTDAC_V1_Type *) (base))->CTDAC_SW) 1049 #define CTDAC_CTDAC_SW_CLEAR(base) (((CTDAC_V1_Type *) (base))->CTDAC_SW_CLEAR) 1050 #define CTDAC_CTDAC_VAL(base) (((CTDAC_V1_Type *) (base))->CTDAC_VAL) 1051 #define CTDAC_CTDAC_VAL_NXT(base) (((CTDAC_V1_Type *) (base))->CTDAC_VAL_NXT) 1052 #define CTDAC_INTR(base) (((CTDAC_V1_Type *) (base))->INTR) 1053 #define CTDAC_INTR_SET(base) (((CTDAC_V1_Type *) (base))->INTR_SET) 1054 #define CTDAC_INTR_MASK(base) (((CTDAC_V1_Type *) (base))->INTR_MASK) 1055 #define CTDAC_INTR_MASKED(base) (((CTDAC_V1_Type *) (base))->INTR_MASKED) 1056 1057 1058 /******************************************************************************* 1059 * SYSANALOG 1060 *******************************************************************************/ 1061 1062 #define CY_PASS_V1 (0x20U > cy_device->passVersion) 1063 #define CY_PASS_ADDR ((PASS_Type*)cy_device->passBase) 1064 #define CY_PASS_V2_ADDR ((PASS_V2_Type*)cy_device->passBase) 1065 #define CY_PASS_BASE(sarBase) ((NULL != (sarBase)) ? ((PASS_V2_Type*) cy_device->passBase) : NULL) /* temporary solution for single pass instance */ 1066 1067 #define PASS_AREF_AREF_CTRL (((PASS_V1_Type*) CY_PASS_ADDR)->AREF.AREF_CTRL) 1068 #define PASS_INTR_CAUSE(passBase) (((PASS_V1_Type*) (passBase))->INTR_CAUSE) 1069 #define PASS_CTBM_CLOCK_SEL(passBase) (((PASS_V2_Type*) (passBase))->CTBM_CLOCK_SEL) 1070 #define PASS_DPSLP_CLOCK_SEL(passBase) (((PASS_V2_Type*) (passBase))->DPSLP_CLOCK_SEL) 1071 #define PASS_LPOSC_CTRL(passBase) (((PASS_V2_Type*) (passBase))->LPOSC.CTRL) 1072 #define PASS_LPOSC_CONFIG(passBase) (((PASS_V2_Type*) (passBase))->LPOSC.CONFIG) 1073 #define PASS_TIMER_CTRL(passBase) (((PASS_V2_Type*) (passBase))->TIMER.CTRL) 1074 #define PASS_TIMER_CONFIG(passBase) (((PASS_V2_Type*) (passBase))->TIMER.CONFIG) 1075 #define PASS_TIMER_PERIOD(passBase) (((PASS_V2_Type*) (passBase))->TIMER.PERIOD) 1076 1077 #define PASS_SAR_SIMULT_CTRL(passBase) (((PASS_V2_Type*) (passBase))->SAR_SIMULT_CTRL) 1078 #define PASS_SAR_TR_SCAN_CNT(passBase) (((PASS_V2_Type*) (passBase))->SAR_TR_SCAN_CNT) 1079 #define PASS_SAR_OVR_CTRL(passBase) (((PASS_V2_Type*) (passBase))->SAR_OVR_CTRL) 1080 #define PASS_SAR_SIMULT_FW_START_CTRL(passBase) (((PASS_V2_Type*) (passBase))->SAR_SIMULT_FW_START_CTRL) 1081 #define PASS_ANA_PWR_CFG(passBase) (((PASS_V2_Type*) (passBase))->ANA_PWR_CFG) 1082 #define PASS_SAR_TR_OUT_CTRL(passBase) (((PASS_V2_Type*) (passBase))->SAR_TR_OUT_CTRL) 1083 1084 #define PASS_SAR_DPSLP_CTRL(sarBase) (((PASS_V2_Type*) cy_device->passBase)->SAR_DPSLP_CTRL[CY_SAR_INSTANCE(sarBase)]) 1085 #define PASS_SAR_CLOCK_SEL(sarBase) (((PASS_V2_Type*) cy_device->passBase)->SAR_CLOCK_SEL[CY_SAR_INSTANCE(sarBase)]) 1086 1087 #define PASS_FIFO_BASE(sarBase) ((PASS_FIFO_V2_Type*)&(((PASS_V2_Type*)cy_device->passBase)->FIFO[CY_SAR_INSTANCE(sarBase)])) 1088 #define PASS_FIFO_CTRL(sarBase) (PASS_FIFO_BASE(sarBase)->CTRL) 1089 #define PASS_FIFO_CONFIG(sarBase) (PASS_FIFO_BASE(sarBase)->CONFIG) 1090 #define PASS_FIFO_LEVEL(sarBase) (PASS_FIFO_BASE(sarBase)->LEVEL) 1091 #define PASS_FIFO_USED(sarBase) (PASS_FIFO_BASE(sarBase)->USED) 1092 #define PASS_FIFO_RD_DATA(sarBase) (PASS_FIFO_BASE(sarBase)->RD_DATA) 1093 #define PASS_FIFO_INTR(sarBase) (PASS_FIFO_BASE(sarBase)->INTR) 1094 #define PASS_FIFO_INTR_SET(sarBase) (PASS_FIFO_BASE(sarBase)->INTR_SET) 1095 #define PASS_FIFO_INTR_MASK(sarBase) (PASS_FIFO_BASE(sarBase)->INTR_MASK) 1096 #define PASS_FIFO_INTR_MASKED(sarBase) (PASS_FIFO_BASE(sarBase)->INTR_MASKED) 1097 1098 /******************************************************************************* 1099 * SCB 1100 *******************************************************************************/ 1101 1102 #define SCB_CTRL(base) (((CySCB_V1_Type*) (base))->CTRL) 1103 #define SCB_SPI_CTRL(base) (((CySCB_V1_Type*) (base))->SPI_CTRL) 1104 #define SCB_SPI_STATUS(base) (((CySCB_V1_Type*) (base))->SPI_STATUS) 1105 #define SCB_UART_CTRL(base) (((CySCB_V1_Type*) (base))->UART_CTRL) 1106 #define SCB_UART_TX_CTRL(base) (((CySCB_V1_Type*) (base))->UART_TX_CTRL) 1107 #define SCB_UART_RX_CTRL(base) (((CySCB_V1_Type*) (base))->UART_RX_CTRL) 1108 #define SCB_UART_FLOW_CTRL(base) (((CySCB_V1_Type*) (base))->UART_FLOW_CTRL) 1109 #define SCB_I2C_CTRL(base) (((CySCB_V1_Type*) (base))->I2C_CTRL) 1110 #define SCB_I2C_STATUS(base) (((CySCB_V1_Type*) (base))->I2C_STATUS) 1111 #define SCB_I2C_M_CMD(base) (((CySCB_V1_Type*) (base))->I2C_M_CMD) 1112 #define SCB_I2C_S_CMD(base) (((CySCB_V1_Type*) (base))->I2C_S_CMD) 1113 #define SCB_I2C_CFG(base) (((CySCB_V1_Type*) (base))->I2C_CFG) 1114 #define SCB_TX_CTRL(base) (((CySCB_V1_Type*) (base))->TX_CTRL) 1115 #define SCB_TX_FIFO_CTRL(base) (((CySCB_V1_Type*) (base))->TX_FIFO_CTRL) 1116 #define SCB_TX_FIFO_STATUS(base) (((CySCB_V1_Type*) (base))->TX_FIFO_STATUS) 1117 #define SCB_TX_FIFO_WR(base) (((CySCB_V1_Type*) (base))->TX_FIFO_WR) 1118 #define SCB_RX_CTRL(base) (((CySCB_V1_Type*) (base))->RX_CTRL) 1119 #define SCB_RX_FIFO_CTRL(base) (((CySCB_V1_Type*) (base))->RX_FIFO_CTRL) 1120 #define SCB_RX_FIFO_STATUS(base) (((CySCB_V1_Type*) (base))->RX_FIFO_STATUS) 1121 #define SCB_RX_MATCH(base) (((CySCB_V1_Type*) (base))->RX_MATCH) 1122 #define SCB_RX_FIFO_RD(base) (((CySCB_V1_Type*) (base))->RX_FIFO_RD) 1123 #define SCB_INTR_CAUSE(base) (((CySCB_V1_Type*) (base))->INTR_CAUSE) 1124 #define SCB_INTR_I2C_EC(base) (((CySCB_V1_Type*) (base))->INTR_I2C_EC) 1125 #define SCB_INTR_I2C_EC_MASK(base) (((CySCB_V1_Type*) (base))->INTR_I2C_EC_MASK) 1126 #define SCB_INTR_I2C_EC_MASKED(base) (((CySCB_V1_Type*) (base))->INTR_I2C_EC_MASKED) 1127 #define SCB_INTR_SPI_EC(base) (((CySCB_V1_Type*) (base))->INTR_SPI_EC) 1128 #define SCB_INTR_SPI_EC_MASK(base) (((CySCB_V1_Type*) (base))->INTR_SPI_EC_MASK) 1129 #define SCB_INTR_SPI_EC_MASKED(base) (((CySCB_V1_Type*) (base))->INTR_SPI_EC_MASKED) 1130 #define SCB_INTR_M(base) (((CySCB_V1_Type*) (base))->INTR_M) 1131 #define SCB_INTR_M_SET(base) (((CySCB_V1_Type*) (base))->INTR_M_SET) 1132 #define SCB_INTR_M_MASK(base) (((CySCB_V1_Type*) (base))->INTR_M_MASK) 1133 #define SCB_INTR_M_MASKED(base) (((CySCB_V1_Type*) (base))->INTR_M_MASKED) 1134 #define SCB_INTR_S(base) (((CySCB_V1_Type*) (base))->INTR_S) 1135 #define SCB_INTR_S_SET(base) (((CySCB_V1_Type*) (base))->INTR_S_SET) 1136 #define SCB_INTR_S_MASK(base) (((CySCB_V1_Type*) (base))->INTR_S_MASK) 1137 #define SCB_INTR_S_MASKED(base) (((CySCB_V1_Type*) (base))->INTR_S_MASKED) 1138 #define SCB_INTR_TX(base) (((CySCB_V1_Type*) (base))->INTR_TX) 1139 #define SCB_INTR_TX_SET(base) (((CySCB_V1_Type*) (base))->INTR_TX_SET) 1140 #define SCB_INTR_TX_MASK(base) (((CySCB_V1_Type*) (base))->INTR_TX_MASK) 1141 #define SCB_INTR_TX_MASKED(base) (((CySCB_V1_Type*) (base))->INTR_TX_MASKED) 1142 #define SCB_INTR_RX(base) (((CySCB_V1_Type*) (base))->INTR_RX) 1143 #define SCB_INTR_RX_SET(base) (((CySCB_V1_Type*) (base))->INTR_RX_SET) 1144 #define SCB_INTR_RX_MASK(base) (((CySCB_V1_Type*) (base))->INTR_RX_MASK) 1145 #define SCB_INTR_RX_MASKED(base) (((CySCB_V1_Type*) (base))->INTR_RX_MASKED) 1146 1147 1148 /******************************************************************************* 1149 * PROFILE 1150 *******************************************************************************/ 1151 1152 #define CY_EP_MONITOR_COUNT ((uint32_t)(cy_device->epMonitorNr)) 1153 #define CY_EP_CNT_NR (8UL) 1154 #define PROFILE_CTL (((PROFILE_V1_Type*) PROFILE_BASE)->CTL) 1155 #define PROFILE_STATUS (((PROFILE_V1_Type*) PROFILE_BASE)->STATUS) 1156 #define PROFILE_CMD (((PROFILE_V1_Type*) PROFILE_BASE)->CMD) 1157 #define PROFILE_INTR (((PROFILE_V1_Type*) PROFILE_BASE)->INTR) 1158 #define PROFILE_INTR_MASK (((PROFILE_V1_Type*) PROFILE_BASE)->INTR_MASK) 1159 #define PROFILE_INTR_MASKED (((PROFILE_V1_Type*) PROFILE_BASE)->INTR_MASKED) 1160 #define PROFILE_CNT_STRUCT (((PROFILE_V1_Type*) PROFILE_BASE)->CNT_STRUCT) 1161 1162 1163 /******************************************************************************* 1164 * BLE 1165 *******************************************************************************/ 1166 1167 #define BLE_RCB_INTR (((BLE_V1_Type *) BLE_BASE)->RCB.INTR) 1168 #define BLE_RCB_TX_FIFO_WR (((BLE_V1_Type *) BLE_BASE)->RCB.TX_FIFO_WR) 1169 #define BLE_RCB_RX_FIFO_RD (((BLE_V1_Type *) BLE_BASE)->RCB.RX_FIFO_RD) 1170 #define BLE_RCB_CTRL (((BLE_V1_Type *) BLE_BASE)->RCB.CTRL) 1171 #define BLE_RCB_RCBLL_CTRL (((BLE_V1_Type *) BLE_BASE)->RCB.RCBLL.CTRL) 1172 #define BLE_BLESS_XTAL_CLK_DIV_CONFIG (((BLE_V1_Type *) BLE_BASE)->BLESS.XTAL_CLK_DIV_CONFIG) 1173 #define BLE_BLESS_MT_CFG (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_CFG) 1174 #define BLE_BLESS_MT_STATUS (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_STATUS) 1175 #define BLE_BLESS_MT_DELAY_CFG (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_DELAY_CFG) 1176 #define BLE_BLESS_MT_DELAY_CFG2 (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_DELAY_CFG2) 1177 #define BLE_BLESS_MT_DELAY_CFG3 (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_DELAY_CFG3) 1178 #define BLE_BLESS_MT_VIO_CTRL (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_VIO_CTRL) 1179 #define BLE_BLESS_LL_CLK_EN (((BLE_V1_Type *) BLE_BASE)->BLESS.LL_CLK_EN) 1180 #define BLE_BLESS_MISC_EN_CTRL (((BLE_V1_Type *) BLE_BASE)->BLESS.MISC_EN_CTRL) 1181 #define BLE_BLESS_INTR_STAT (((BLE_V1_Type *) BLE_BASE)->BLESS.INTR_STAT) 1182 #define BLE_BLELL_EVENT_INTR (((BLE_V1_Type *) BLE_BASE)->BLELL.EVENT_INTR) 1183 #define BLE_BLELL_CONN_INTR (((BLE_V1_Type *) BLE_BASE)->BLELL.CONN_INTR) 1184 #define BLE_BLELL_CONN_EXT_INTR (((BLE_V1_Type *) BLE_BASE)->BLELL.CONN_EXT_INTR) 1185 #define BLE_BLELL_SCAN_INTR (((BLE_V1_Type *) BLE_BASE)->BLELL.SCAN_INTR) 1186 #define BLE_BLELL_ADV_INTR (((BLE_V1_Type *) BLE_BASE)->BLELL.ADV_INTR) 1187 1188 1189 /******************************************************************************* 1190 * USBFS Device 1191 *******************************************************************************/ 1192 1193 #define USBFS_DEV_CR0(base) (((USBFS_V1_Type *)(base))->USBDEV.CR0) 1194 #define USBFS_DEV_CR1(base) (((USBFS_V1_Type *)(base))->USBDEV.CR1) 1195 #define USBFS_DEV_USBIO_CR0(base) (((USBFS_V1_Type *)(base))->USBDEV.USBIO_CR0) 1196 #define USBFS_DEV_USBIO_CR2(base) (((USBFS_V1_Type *)(base))->USBDEV.USBIO_CR2) 1197 #define USBFS_DEV_USBIO_CR1(base) (((USBFS_V1_Type *)(base))->USBDEV.USBIO_CR1) 1198 #define USBFS_DEV_USB_CLK_EN(base) (((USBFS_V1_Type *)(base))->USBDEV.USB_CLK_EN) 1199 #define USBFS_DEV_BUS_RST_CNT(base) (((USBFS_V1_Type *)(base))->USBDEV.BUS_RST_CNT) 1200 #define USBFS_DEV_OSCLK_DR0(base) (((USBFS_V1_Type *)(base))->USBDEV.EP_TYPE) 1201 #define USBFS_DEV_OSCLK_DR1(base) (((USBFS_V1_Type *)(base))->USBDEV.OSCLK_DR0) 1202 #define USBFS_DEV_SOF0(base) (((USBFS_V1_Type *)(base))->USBDEV.SOF0) 1203 #define USBFS_DEV_SOF1(base) (((USBFS_V1_Type *)(base))->USBDEV.SOF1) 1204 #define USBFS_DEV_SOF16(base) (((USBFS_V1_Type *)(base))->USBDEV.OSCLK_DR1) 1205 #define USBFS_DEV_OSCLK_DR16(base) (((USBFS_V1_Type *)(base))->USBDEV.SOF16) 1206 #define USBFS_DEV_ARB_CFG(base) (((USBFS_V1_Type *)(base))->USBDEV.ARB_CFG) 1207 #define USBFS_DEV_DYN_RECONFIG(base) (((USBFS_V1_Type *)(base))->USBDEV.DYN_RECONFIG) 1208 #define USBFS_DEV_BUF_SIZE(base) (((USBFS_V1_Type *)(base))->USBDEV.BUF_SIZE) 1209 #define USBFS_DEV_EP_ACTIVE(base) (((USBFS_V1_Type *)(base))->USBDEV.EP_ACTIVE) 1210 #define USBFS_DEV_EP_TYPE(base) (((USBFS_V1_Type *)(base))->USBDEV.EP_TYPE) 1211 #define USBFS_DEV_CWA16(base) (((USBFS_V1_Type *)(base))->USBDEV.CWA16) 1212 #define USBFS_DEV_CWA(base) (((USBFS_V1_Type *)(base))->USBDEV.CWA) 1213 #define USBFS_DEV_CWA_MSB(base) (((USBFS_V1_Type *)(base))->USBDEV.CWA_MSB) 1214 #define USBFS_DEV_DMA_THRES16(base) (((USBFS_V1_Type *)(base))->USBDEV.DMA_THRES16) 1215 #define USBFS_DEV_DMA_THRES(base) (((USBFS_V1_Type *)(base))->USBDEV.DMA_THRES) 1216 #define USBFS_DEV_DMA_THRES_MSB(base) (((USBFS_V1_Type *)(base))->USBDEV.DMA_THRES_MSB) 1217 1218 #define USBFS_DEV_SIE_EP_INT_EN(base) (((USBFS_V1_Type *)(base))->USBDEV.SIE_EP_INT_EN) 1219 #define USBFS_DEV_SIE_EP_INT_SR(base) (((USBFS_V1_Type *)(base))->USBDEV.SIE_EP_INT_SR) 1220 #define USBFS_DEV_ARB_INT_EN(base) (((USBFS_V1_Type *)(base))->USBDEV.ARB_INT_EN) 1221 #define USBFS_DEV_ARB_INT_SR(base) (((USBFS_V1_Type *)(base))->USBDEV.ARB_INT_SR) 1222 1223 #define USBFS_DEV_EP0_CR(base) (((USBFS_V1_Type *)(base))->USBDEV.EP0_CR) 1224 #define USBFS_DEV_EP0_CNT(base) (((USBFS_V1_Type *)(base))->USBDEV.EP0_CNT) 1225 #define USBFS_DEV_EP0_DR(base, idx) (((USBFS_V1_Type *)(base))->USBDEV.EP0_DR[idx]) 1226 1227 #define USBFS_DEV_MEM_DATA(base, idx) (((USBFS_V1_Type *)(base))->USBDEV.MEM[idx]) 1228 1229 #define USBFS_DEV_SIE_REGS_BASE (0x30U) 1230 #define USBFS_DEV_SIE_REGS_SIZE (0x40U) 1231 #define USBFS_DEV_SIE_EP_CNT0_OFFSET (0x00U) 1232 #define USBFS_DEV_SIE_EP_CNT1_OFFSET (0x04U) 1233 #define USBFS_DEV_SIE_EP_CR0_OFFSET (0x08U) 1234 #define USBFS_DEV_SIE_REGS(base, endpoint) ((uint32_t)(base) + USBFS_DEV_SIE_REGS_BASE + ((endpoint) * USBFS_DEV_SIE_REGS_SIZE)) 1235 1236 #define USBFS_DEV_SIE_EP_CNT0(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_SIE_REGS(base, endpoint) + \ 1237 USBFS_DEV_SIE_EP_CNT0_OFFSET)) 1238 #define USBFS_DEV_SIE_EP_CNT1(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_SIE_REGS(base, endpoint) + \ 1239 USBFS_DEV_SIE_EP_CNT1_OFFSET)) 1240 #define USBFS_DEV_SIE_EP_CR0(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_SIE_REGS(base, endpoint) + \ 1241 USBFS_DEV_SIE_EP_CR0_OFFSET)) 1242 1243 #define USBFS_DEV_ARB_REGS_BASE (0x200U) 1244 #define USBFS_DEV_ARB_REGS_SIZE (0x40U) 1245 #define USBFS_DEV_ARB_EP_CFG_OFFSET (0x00U) 1246 #define USBFS_DEV_ARB_EP_INT_EN_OFFSET (0x04U) 1247 #define USBFS_DEV_ARB_EP_SR_OFFSET (0x08U) 1248 #define USBFS_DEV_ARB_RW_WA_OFFSET (0x10U) 1249 #define USBFS_DEV_ARB_RW_WA_MSB_OFFSET (0x14U) 1250 #define USBFS_DEV_ARB_RW_RA_OFFSET (0x18U) 1251 #define USBFS_DEV_ARB_RW_RA_MSB_OFFSET (0x1CU) 1252 #define USBFS_DEV_ARB_RW_DR_OFFSET (0x20U) 1253 #define USBFS_DEV_ARB_REGS(base, endpoint) ((uint32_t)(base) + USBFS_DEV_ARB_REGS_BASE + ((endpoint) * USBFS_DEV_ARB_REGS_SIZE)) 1254 1255 #define USBFS_DEV_ARB_EP_CFG(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \ 1256 USBFS_DEV_ARB_EP_CFG_OFFSET)) 1257 #define USBFS_DEV_ARB_EP_INT_EN(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \ 1258 USBFS_DEV_ARB_EP_INT_EN_OFFSET)) 1259 #define USBFS_DEV_ARB_EP_SR(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \ 1260 USBFS_DEV_ARB_EP_SR_OFFSET)) 1261 #define USBFS_DEV_ARB_RW_WA(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \ 1262 USBFS_DEV_ARB_RW_WA_OFFSET)) 1263 #define USBFS_DEV_ARB_RW_WA_MSB(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \ 1264 USBFS_DEV_ARB_RW_WA_MSB_OFFSET)) 1265 #define USBFS_DEV_ARB_RW_RA(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \ 1266 USBFS_DEV_ARB_RW_RA_OFFSET)) 1267 #define USBFS_DEV_ARB_RW_RA_MSB(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \ 1268 USBFS_DEV_ARB_RW_RA_MSB_OFFSET)) 1269 #define USBFS_DEV_ARB_RW_DR(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \ 1270 USBFS_DEV_ARB_RW_DR_OFFSET)) 1271 1272 #define USBFS_DEV_ARB_REGS16_BASE (0x1210U) 1273 #define USBFS_DEV_ARB_REGS16_SIZE (0x40U) 1274 #define USBFS_DEV_ARB_RW_WA16_OFFSET (0x00U) 1275 #define USBFS_DEV_ARB_RW_RA16_OFFSET (0x08U) 1276 #define USBFS_DEV_ARB_RW_DR16_OFFSET (0x10U) 1277 #define USBFS_DEV_ARB_REGS_16(base, endpoint) ((uint32_t)(base) + USBFS_DEV_ARB_REGS16_BASE + ((endpoint) * USBFS_DEV_ARB_REGS16_SIZE)) 1278 1279 #define USBFS_DEV_ARB_RW_WA16(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS_16(base, endpoint) + \ 1280 USBFS_DEV_ARB_RW_WA16_OFFSET)) 1281 #define USBFS_DEV_ARB_RW_RA16(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS_16(base, endpoint) + \ 1282 USBFS_DEV_ARB_RW_RA16_OFFSET)) 1283 #define USBFS_DEV_ARB_RW_DR16(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS_16(base, endpoint) + \ 1284 USBFS_DEV_ARB_RW_DR16_OFFSET)) 1285 1286 #define USBFS_DEV_LPM_POWER_CTL(base) (((USBFS_V1_Type *)(base))->USBLPM.POWER_CTL) 1287 #define USBFS_DEV_LPM_USBIO_CTL(base) (((USBFS_V1_Type *)(base))->USBLPM.USBIO_CTL) 1288 #define USBFS_DEV_LPM_FLOW_CTL(base) (((USBFS_V1_Type *)(base))->USBLPM.FLOW_CTL) 1289 #define USBFS_DEV_LPM_LPM_CTL(base) (((USBFS_V1_Type *)(base))->USBLPM.LPM_CTL) 1290 #define USBFS_DEV_LPM_LPM_STAT(base) (((USBFS_V1_Type const *)(base))->USBLPM.LPM_STAT) 1291 #define USBFS_DEV_LPM_INTR_SIE(base) (((USBFS_V1_Type *)(base))->USBLPM.INTR_SIE) 1292 #define USBFS_DEV_LPM_INTR_SIE_SET(base) (((USBFS_V1_Type *)(base))->USBLPM.INTR_SIE_SET) 1293 #define USBFS_DEV_LPM_INTR_SIE_MASK(base) (((USBFS_V1_Type *)(base))->USBLPM.INTR_SIE_MASK) 1294 #define USBFS_DEV_LPM_INTR_SIE_MASKED(base) (((USBFS_V1_Type *)(base))->USBLPM.INTR_SIE_MASKED) 1295 #define USBFS_DEV_LPM_INTR_LVL_SEL(base) (((USBFS_V1_Type *)(base))->USBLPM.INTR_LVL_SEL) 1296 #define USBFS_DEV_LPM_INTR_CAUSE_HI(base) (((USBFS_V1_Type const *)(base))->USBLPM.INTR_CAUSE_HI) 1297 #define USBFS_DEV_LPM_INTR_CAUSE_MED(base) (((USBFS_V1_Type const *)(base))->USBLPM.INTR_CAUSE_MED) 1298 #define USBFS_DEV_LPM_INTR_CAUSE_LO(base) (((USBFS_V1_Type const *)(base))->USBLPM.INTR_CAUSE_LO) 1299 #define USBFS_DEV_LPM_DFT_CTL(base) (((USBFS_V1_Type *)(base))->USBLPM.DFT_CTL) 1300 1301 #define USBFS_HOST_CTL0(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_CTL0) 1302 #define USBFS_HOST_CTL1(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_CTL1) 1303 #define USBFS_HOST_CTL2(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_CTL2) 1304 #define USBFS_HOST_ERR(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_ERR) 1305 #define USBFS_HOST_STATUS(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_STATUS) 1306 #define USBFS_HOST_FCOMP(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_FCOMP) 1307 #define USBFS_HOST_RTIMER(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_RTIMER) 1308 #define USBFS_HOST_ADDR(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_ADDR) 1309 #define USBFS_HOST_EOF(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EOF) 1310 #define USBFS_HOST_FRAME(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_FRAME) 1311 #define USBFS_HOST_TOKEN(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_TOKEN) 1312 #define USBFS_HOST_EP1_CTL(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP1_CTL) 1313 #define USBFS_HOST_EP1_STATUS(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP1_STATUS) 1314 #define USBFS_HOST_EP1_RW1_DR(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP1_RW1_DR) 1315 #define USBFS_HOST_EP1_RW2_DR(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP1_RW2_DR) 1316 #define USBFS_HOST_EP2_CTL(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP2_CTL) 1317 #define USBFS_HOST_EP2_STATUS(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP2_STATUS) 1318 #define USBFS_HOST_EP2_RW1_DR(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP2_RW1_DR) 1319 #define USBFS_HOST_EP2_RW2_DR(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP2_RW2_DR) 1320 #define USBFS_HOST_LVL1_SEL(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_LVL1_SEL) 1321 #define USBFS_HOST_LVL2_SEL(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_LVL2_SEL) 1322 #define USBFS_INTR_USBHOST_CAUSE_HI(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_CAUSE_HI) 1323 #define USBFS_INTR_USBHOST_CAUSE_MED(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_CAUSE_MED) 1324 #define USBFS_INTR_USBHOST_CAUSE_LO(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_CAUSE_LO) 1325 #define USBFS_INTR_HOST_EP_CAUSE_HI(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_CAUSE_HI) 1326 #define USBFS_INTR_HOST_EP_CAUSE_MED(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_CAUSE_MED) 1327 #define USBFS_INTR_HOST_EP_CAUSE_LO(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_CAUSE_LO) 1328 #define USBFS_INTR_USBHOST(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST) 1329 #define USBFS_INTR_USBHOST_SET(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_SET) 1330 #define USBFS_INTR_USBHOST_MASK(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_MASK) 1331 #define USBFS_INTR_USBHOST_MASKED(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_MASKED) 1332 #define USBFS_INTR_HOST_EP(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP) 1333 #define USBFS_INTR_HOST_EP_SET(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_SET) 1334 #define USBFS_INTR_HOST_EP_MASK(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_MASK) 1335 #define USBFS_INTR_HOST_EP_MASKED(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_MASKED) 1336 #define USBFS_HOST_DMA_ENBL(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_DMA_ENBL) 1337 #define USBFS_HOST_EP1_BLK(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP1_BLK) 1338 #define USBFS_HOST_EP2_BLK(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP2_BLK) 1339 1340 #endif /* CY_DEVICE_H_ */ 1341 1342 /* [] END OF FILE */ 1343
