1 /* USER CODE BEGIN Header */
2 /**
3   ******************************************************************************
4   * @file    bleplat_cntr.c
5   * @author  GPM WBL Application Team
6   * @brief   This file provides implementation of BLE controller interface.
7   *          WARNING: This module is used by Bluetooth LE stack. Do not use this
8   *          module while Bluetooth LE stack is active.
9   ******************************************************************************
10   * @attention
11   *
12   * Copyright (c) 2024 STMicroelectronics.
13   * All rights reserved.
14   *
15   * This software is licensed under terms that can be found in the LICENSE file
16   * in the root directory of this software component.
17   * If no LICENSE file comes with this software, it is provided AS-IS.
18   *
19   ******************************************************************************
20   */
21 /* USER CODE END Header */
22 
23 /* Includes ------------------------------------------------------------------*/
24 #include "stm32wb0x.h"
25 #include "bleplat_cntr.h"
26 #include <string.h>
27 
28 /** @defgroup BLE_Platform_Controller  BLE Manager
29 * @{
30 */
31 
32 /** @defgroup BLE_Platform_Controller_TypesDefinitions Private Type Definitions
33 * @{
34 */
35 /**
36 * @}
37 */
38 
39 /** @defgroup BLE_Platform_Controller_Private_Defines Private Defines
40 * @{
41 */
42 
43 #define ATOMIC_SECTION_BEGIN() uint32_t uwPRIMASK_Bit = __get_PRIMASK(); \
44 __disable_irq(); \
45   /* Must be called in the same or in a lower scope of ATOMIC_SECTION_BEGIN */
46 #define ATOMIC_SECTION_END() __set_PRIMASK(uwPRIMASK_Bit)
47 
48 #define MAX_PA_LEVEL    31
49 #define HP_PA_LEVEL     32 /* Fake PA level that can be reached in high power mode. */
50 
51 #ifndef CONV_ADR
52 #define CONV_ADR(ADDR) ((uint8_t*)(ADDR))
53 #endif
54 
55 #ifndef LL_PHY_CODED
56 #define LL_PHY_CODED 0x04U
57 #endif
58 
59 #define ANY_HW_ERROR_INTERRUPT_Msk ( \
60         BLUE_STATUSREG_ADDPOINTERROR_Msk      |  \
61         BLUE_STATUSREG_RXOVERFLOWERROR_Msk    |  \
62         BLUE_STATUSREG_TXERROR_0_Msk          |  \
63         BLUE_STATUSREG_TXERROR_1_Msk          |  \
64         BLUE_STATUSREG_TXERROR_2_Msk          |  \
65         BLUE_STATUSREG_TXERROR_3_Msk          |  \
66         BLUE_STATUSREG_TXERROR_4_Msk          |  \
67         BLUE_STATUSREG_ALLTABLEREADYERROR_Msk | \
68         BLUE_STATUSREG_TXDATAREADYERROR_Msk   | \
69         BLUE_STATUSREG_NOACTIVELERROR_Msk     | \
70         BLUE_STATUSREG_SEMATIMEOUTERROR_Msk   | \
71         BLUE_STATUSREG_ACTIVE2ERROR_Msk       | \
72         BLUE_STATUSREG_CONFIGERROR_Msk          \
73         )
74 
75 #define WAKEUPINITDELAY_MT                   (64U)
76 #define TIMER12_INIT_DELAY_CAL               (63U)
77 #define TIMER2_INIT_DELAY_NO_CAL              (9U)
78 #define RCV_LEN_MARGIN_US                    (16U)
79 #define TX_DELAY_START                       (16U)
80 #define TX_DELAY_END                         (16U)
81 
82 #define RADIO_FSM_RX_DELAY_CAL               (90U)
83 #define RADIO_FSM_RX_DELAY_NO_CAL            (50U)
84 #define RADIO_FSM_TX_DELAY_CAL               (92U)
85 #define RADIO_FSM_TX_DELAY_NO_CAL            (52U)
86 
87 #define RECEIVE_CAL_DELAY_CHECK              (RADIO_FSM_RX_DELAY_CAL)
88 #define RECEIVE_NO_CAL_DELAY_CHECK           (RADIO_FSM_RX_DELAY_NO_CAL)
89 #define TRANSMIT_CAL_DELAY_CHECK             (RADIO_FSM_TX_DELAY_CAL - 2U)
90 #define TRANSMIT_NO_CAL_DELAY_CHECK          (RADIO_FSM_TX_DELAY_NO_CAL - 2U)
91 
92 #define CONFIG_END_DURATION                  (20U)
93 #define TX_DATA_READY_CHECK                   (5U)
94 #define TX_READY_TIMEOUT                      (4U)
95 
96 #ifndef LL_PHY_CODED
97 #define LL_PHY_CODED 0x04U
98 #endif
99 
100 #ifndef CONV_ADR
101 #define CONV_ADR(ADDR) ((uint8_t*)(ADDR))
102 #endif
103 
104 #ifndef BLUE_TRANS_STRUCT_PTR_CAST
105 #define BLUE_TRANS_STRUCT_PTR_CAST(PTR) ((BlueTransStruct*)(void*)(uint8_t*)(PTR))
106 #endif
107 
108 #define PHY_1MBPS          (0x0U)
109 #define PHY_2MBPS          (0x1U)
110 #define PHY_CODED_S2       (0x6U)
111 #define PHY_CODED_S8       (0x4U)
112 
113 #define BIT_TX_SKIP (0x0UL)
114 
115 /**
116 * @}
117 */
118 
119 /** @defgroup BLE_Platform_Controller_Private_Variables Private Variables
120 * @{
121 */
122 
123 /**
124 * @}
125 */
126 
127 /** @defgroup BLE_Platform_Controller_External_Variables External Variables
128 * @{
129 */
130 /**
131 * @}
132 */
133 
134 /** @defgroup BLE_Platform_Controller_Private_FunctionPrototypes Private Function Prototypes
135 * @{
136 */
137 
138 /**
139 * @}
140 */
141 
142 /** @defgroup BLE_Platform_Controller_Private_Functions Private Functions
143 * @{
144 */
145 
146 /**
147 * @}
148 */
149 
150 /** @defgroup BLE_Platform_Controller_Public_Functions Public Functions
151 * @{
152 */
153 
BLEPLAT_CNTR_Init(void)154 BLEPLAT_CNTR_ResultStatus BLEPLAT_CNTR_Init(void)
155 {
156 
157   return BLEPLAT_CNTR_SUCCESS;
158 }
159 
BLEPLAT_CNTR_Deinit(void)160 BLEPLAT_CNTR_ResultStatus BLEPLAT_CNTR_Deinit(void)
161 {
162 
163   return BLEPLAT_CNTR_SUCCESS;
164 }
165 
166 /* Moved from the Stack library to the application environment
167  *
168  */
169 /* Calculate the Timeout to be programmed on Timer2 to obtain a give T_IFS
170  * when the next packet is a transmit one
171 */
BLEPLAT_CNTR_GetTimer2TimeoutForIfs(uint32_t T_Ifs,BLEPLAT_CNTR_Transaction Transaction,uint8_t Cal_Enabled)172 uint32_t BLEPLAT_CNTR_GetTimer2TimeoutForIfs(uint32_t T_Ifs, BLEPLAT_CNTR_Transaction Transaction, uint8_t Cal_Enabled)
173 {
174     uint32_t Timeout = T_Ifs;
175     uint32_t Tx_Delay_Comp;
176     uint32_t Init_Delay=0;
177 
178     if(Transaction == BLEPLAT_CNTR_RxTx)
179     {
180         /* The correction values below have been determined by sniffer
181          * T_IFS measurements in connection, initiating and active
182          * scanning
183          */
184 #ifdef STM32WB05
185         const int32_t Adjust_Value = 4;
186 #else
187         const int32_t Adjust_Value = 6;
188 #endif
189         Tx_Delay_Comp = (TX_DELAY_START>>3) + Adjust_Value;
190     }
191     else if(Transaction == BLEPLAT_CNTR_TxRx)
192     {
193         /* The correction values below have been set to correspond to the hardcoded
194          * values used in prrevious versions of the stack.
195          * They could be optimized after careful analysis of timing margins and
196          * AGC behavior.
197          */
198 #ifdef STM32WB05
199         const int32_t Adjust_Value = 4;
200 #else
201         const int32_t Adjust_Value = 4;
202 #endif
203         Tx_Delay_Comp = (TX_DELAY_END>>3) + Adjust_Value;
204     }
205     else if(Transaction == BLEPLAT_CNTR_TxTx)
206     {
207         /* The correction values below have been determined by sniffer
208          * T_IFS measurements in extended advertising (AUX_CHAIN_IND)
209          */
210 #ifdef STM32WB05
211         const int32_t Adjust_Value = 1;
212 #else
213         const int32_t Adjust_Value = 2;
214 #endif
215         Tx_Delay_Comp = ((TX_DELAY_START + TX_DELAY_END)>>3) + Adjust_Value;
216     }
217     else
218     {
219         Tx_Delay_Comp = 0;
220     }
221 
222     if((Transaction == BLEPLAT_CNTR_RxTx) || (Transaction == BLEPLAT_CNTR_TxTx))
223     {
224         if(Cal_Enabled == TRUE)
225         {
226             Init_Delay = TIMER12_INIT_DELAY_CAL + RADIO_FSM_TX_DELAY_CAL;
227         }
228         else
229         {
230             Init_Delay = TIMER2_INIT_DELAY_NO_CAL + RADIO_FSM_TX_DELAY_NO_CAL;
231         }
232     }
233     else if((Transaction == BLEPLAT_CNTR_TxRx) || (Transaction == BLEPLAT_CNTR_RxRx))
234     {
235         /* The calculation below is based on the following sequence:
236          * - When Timer2 expires the sequencer performs the 1st initialization step and sends
237          *   a take_req to the radio
238          * - When TIMER12_INIT_DELAY_CAL or TIMER2_INIT_DELAY_NO_CAL expire the sequencer sends
239          *   a tx_rx_req to the radio
240          * - When the radio FSM reaches the RX state (after RADIO_FSM_RX_DELAY_CAL or
241          *   RADIO_FSM_RX_DELAY_NO_CAL) the demodulator is turned on
242          *
243          * The sum of Timer2 timeout +  TIMER(1)2_INIT_DELAY(_NO)_CAL + RADIO_FSM_RX_DELAY(_NO)_CAL
244          * must be equal to the T IFS.
245          *
246          * The current calculation of Timer2 for TX-RX events is slightly conservative
247          * since it soes not consider the delay from digital modulator to antenna and from
248          * antenna to digital demodulator. As a consequence the demodulator is turned on
249          * a few microseconds earlier than stricty needed.
250          */
251         if(Cal_Enabled == TRUE)
252         {
253             Init_Delay = TIMER12_INIT_DELAY_CAL + RADIO_FSM_RX_DELAY_CAL;
254         }
255         else
256         {
257             Init_Delay = TIMER2_INIT_DELAY_NO_CAL + RADIO_FSM_RX_DELAY_NO_CAL;
258         }
259     }
260     else
261     {
262     }
263 
264     Timeout -= (Init_Delay + Tx_Delay_Comp);
265 
266     return Timeout;
267 }
268 
BLEPLAT_CNTR_ClearInterrupt(uint32_t x)269 void BLEPLAT_CNTR_ClearInterrupt(uint32_t x)
270 {
271     LL_RADIO_BlueSetInterrupt1RegRegister(x);
272 }
273 
BLEPLAT_CNTR_ClearSemareq(void)274 void BLEPLAT_CNTR_ClearSemareq(void)
275 {
276     LL_RADIO_BlueSetClearSemaphoreRequest(0x1U);
277 }
278 
BLEPLAT_CNTR_TxRxSkip(void)279 void BLEPLAT_CNTR_TxRxSkip(void)
280 {
281     LL_RADIO_BlueSetTxRxSkip(0x1U);
282 }
283 
BLEPLAT_CNTR_GetCipherTextPtr()284 uint32_t* BLEPLAT_CNTR_GetCipherTextPtr()
285 {
286     return (uint32_t*)&BLUE->MANAESCIPHERTEXT0REG;
287 }
288 
BLEPLAT_CNTR_GetClrTextPtr()289 uint32_t* BLEPLAT_CNTR_GetClrTextPtr()
290 {
291     return (uint32_t*)&BLUE->MANAESCLEARTEXT0REG;
292 }
293 
BLEPLAT_CNTR_GetEncKeyPtr()294 uint32_t* BLEPLAT_CNTR_GetEncKeyPtr()
295 {
296     return (uint32_t*)&BLUE->MANAESKEY0REG;
297 }
298 
BLEPLAT_CNTR_GetEncryptDoneStatus()299 uint8_t BLEPLAT_CNTR_GetEncryptDoneStatus()
300 {
301     return (uint8_t)!LL_RADIO_BlueGetManAESStatusBusy();
302 }
303 
BLEPLAT_CNTR_GetIqsamplesMissingError(void)304 uint8_t BLEPLAT_CNTR_GetIqsamplesMissingError(void)
305 {
306 #if defined(STM32WB09) || defined(STM32WB05)
307   return (uint8_t)LL_RADIO_GetIQSamplesMissingError();
308 #elif defined(STM32WB06) || defined(STM32WB07)
309   return (uint8_t)0;
310 #endif
311 }
312 
BLEPLAT_CNTR_GetIqsamplesNumber(void)313 uint8_t BLEPLAT_CNTR_GetIqsamplesNumber(void)
314 {
315 #if defined(STM32WB09) || defined(STM32WB05)
316   return (uint8_t)LL_RADIO_GetIQSamplesNumber();
317 #elif defined(STM32WB06) || defined(STM32WB07)
318   return (uint8_t)0;
319 #endif
320 }
321 
BLEPLAT_CNTR_getIqsamplesReady(void)322 uint8_t BLEPLAT_CNTR_getIqsamplesReady(void)
323 {
324 #if defined(STM32WB09) || defined(STM32WB05)
325     return (uint8_t)LL_RADIO_GetIQSamplesReady();
326 #elif defined(STM32WB06) || defined(STM32WB07)
327   return (uint8_t)0;
328 #endif
329 }
330 
BLEPLAT_CNTR_GetIsrLatency()331 uint8_t BLEPLAT_CNTR_GetIsrLatency()
332 {
333     return (uint8_t)LL_RADIO_BlueGetInterrupt1Latency();
334 }
335 
BLEPLAT_CNTR_GetTimercapture()336 uint32_t BLEPLAT_CNTR_GetTimercapture()
337 {
338     return LL_RADIO_BlueGetTimerCapture();
339 }
340 
BLEPLAT_CNTR_GlobDisableBlue()341 void BLEPLAT_CNTR_GlobDisableBlue()
342 {
343     LL_RADIO_GlobalDisableBlue();
344 }
345 
BLEPLAT_CNTR_GlobEnableBlue()346 void BLEPLAT_CNTR_GlobEnableBlue()
347 {
348     LL_RADIO_GlobalEnableBlue();
349 }
350 
BLEPLAT_CNTR_GlobEnableIntnoactivelerrorInt()351 void BLEPLAT_CNTR_GlobEnableIntnoactivelerrorInt()
352 {
353    LL_RADIO_NoActiveLErrorInterrupt_Enable();
354 }
355 
BLEPLAT_CNTR_GlobEnableOverrunAct2Int()356 void BLEPLAT_CNTR_GlobEnableOverrunAct2Int()
357 {
358     LL_RADIO_Active2ErrorInterrupt_Enable();
359 }
360 
BLEPLAT_CNTR_GlobGetDefaultAntennaid()361 uint8_t BLEPLAT_CNTR_GlobGetDefaultAntennaid()
362 {
363 #if defined(GLOBAL_WORD6_DEFAULTANTENNAID_Msk)
364     return (uint8_t)LL_RADIO_GetDefaultAntennaID();
365 #else
366     return (uint8_t)0;
367 #endif
368 }
369 
BLEPLAT_CNTR_GlobGetWakeupinitdelay()370 uint8_t BLEPLAT_CNTR_GlobGetWakeupinitdelay()
371 {
372     return (uint8_t) LL_RADIO_GetWakeupInitDelay();
373 }
374 
BLEPLAT_CNTR_GlobReloadRadioConfigP()375 void BLEPLAT_CNTR_GlobReloadRadioConfigP()
376 {
377     *(uint32_t*)(RRM_BASE + 0x10U) = 0x01U;
378 }
379 
BLEPLAT_CNTR_GlobSetChkflagautoclearena()380 void BLEPLAT_CNTR_GlobSetChkflagautoclearena()
381 {
382     LL_RADIO_ChkFlagAutoclearEnable_Enable();
383 }
384 
BLEPLAT_CNTR_GlobSetDefaultAntennaid(uint8_t x)385 void BLEPLAT_CNTR_GlobSetDefaultAntennaid(uint8_t x)
386 {
387 #if defined(GLOBAL_WORD6_DEFAULTANTENNAID_Msk)
388     LL_RADIO_SetDefaultAntennaID((uint32_t)x);
389 #else
390     /* nothing to do */
391 #endif
392 }
393 
BLEPLAT_CNTR_GlobSetInitRadioDelayTxCal(uint8_t x)394 void BLEPLAT_CNTR_GlobSetInitRadioDelayTxCal(uint8_t x)
395 {
396     LL_RADIO_SetTransmitCalDelayChk((uint32_t) x);
397 }
398 
BLEPLAT_CNTR_GlobSetInitRadioDelayTxNocal(uint8_t x)399 void BLEPLAT_CNTR_GlobSetInitRadioDelayTxNocal(uint8_t x)
400 {
401     LL_RADIO_SetTransmitNoCalDelayChk((uint32_t) x);
402 }
403 
BLEPLAT_CNTR_GlobSetRadioConfigP(volatile uint32_t * x)404 void BLEPLAT_CNTR_GlobSetRadioConfigP(volatile uint32_t* x)
405 {
406     LL_RADIO_SetRadioConfigurationAddressPointer(x[0]);
407 }
408 
BLEPLAT_CNTR_GlobSetWakeupinitdelay(uint8_t x)409 void BLEPLAT_CNTR_GlobSetWakeupinitdelay(uint8_t x)
410 {
411     LL_RADIO_SetWakeupInitDelay((uint32_t) x);
412 }
413 
BLEPLAT_CNTR_GlobWriteConfigEnd(uint8_t x)414 void BLEPLAT_CNTR_GlobWriteConfigEnd(uint8_t x)
415 {
416     LL_RADIO_SetConfigurationEndDuration((uint32_t) x);
417 }
418 
BLEPLAT_CNTR_GlobWritePeriodslow(uint16_t x)419 void BLEPLAT_CNTR_GlobWritePeriodslow(uint16_t x)
420 {
421     /* nothing to do */
422 }
423 
BLEPLAT_CNTR_GlobWriteRcvdelay(uint8_t x)424 void BLEPLAT_CNTR_GlobWriteRcvdelay(uint8_t x)
425 {
426     LL_RADIO_SetReceivedCalDelayChk((uint32_t) x);
427 }
428 
BLEPLAT_CNTR_GlobWriteRcvdelay1(uint8_t x)429 void BLEPLAT_CNTR_GlobWriteRcvdelay1(uint8_t x)
430 {
431     LL_RADIO_SetReceivedNoCalDelayChk((uint32_t) x);
432 }
433 
BLEPLAT_CNTR_GlobWriteSlot(uint8_t slotNo)434 void BLEPLAT_CNTR_GlobWriteSlot(uint8_t slotNo)
435 {
436     LL_RADIO_SetCurrentConnectionMachineNumber((uint32_t) slotNo);
437 }
438 
BLEPLAT_CNTR_GlobWriteTimer12initdelaycal(uint8_t x)439 void BLEPLAT_CNTR_GlobWriteTimer12initdelaycal(uint8_t x)
440 {
441     LL_RADIO_SetTimer12InitDelayCal((uint32_t) x);
442 }
443 
BLEPLAT_CNTR_GlobWriteTimer2initdelaynocal(uint8_t x)444 void BLEPLAT_CNTR_GlobWriteTimer2initdelaynocal(uint8_t x)
445 {
446     LL_RADIO_SetTimer12InitDelayNoCal((uint32_t) x);
447 }
448 
BLEPLAT_CNTR_GlobWriteTxDataReadyCheck(uint8_t x)449 void BLEPLAT_CNTR_GlobWriteTxDataReadyCheck(uint8_t x)
450 {
451     LL_RADIO_SetTxDataReadyCheck((uint32_t) x);
452 }
453 
BLEPLAT_CNTR_GlobWriteTxReadyTimeout(uint8_t x)454 void BLEPLAT_CNTR_GlobWriteTxReadyTimeout(uint8_t x)
455 {
456 	LL_RADIO_SetTransmissionReadyTimeout((uint32_t) x);
457 }
458 
BLEPLAT_CNTR_GlobWriteTxdelay(uint8_t x)459 void BLEPLAT_CNTR_GlobWriteTxdelay(uint8_t x)
460 {
461     LL_RADIO_SetTxDelayStart((uint32_t) x);
462 }
463 
BLEPLAT_CNTR_GlobWriteTxdelayEnd(uint8_t x)464 void BLEPLAT_CNTR_GlobWriteTxdelayEnd(uint8_t x)
465 {
466     LL_RADIO_SetTxDelayEnd((uint32_t) x);
467 }
468 
BLEPLAT_CNTR_IntGetIntStatusAnyHwError(uint32_t x)469 uint32_t BLEPLAT_CNTR_IntGetIntStatusAnyHwError(uint32_t x)
470 {
471     return (uint32_t)(x & ANY_HW_ERROR_INTERRUPT_Msk);
472 }
473 
BLEPLAT_CNTR_IntGetIntStatusRxOverflowError(uint32_t x)474 uint32_t BLEPLAT_CNTR_IntGetIntStatusRxOverflowError(uint32_t x)
475 {
476     return (uint32_t)(x & BLUE_STATUSREG_RXOVERFLOWERROR_Msk);
477 }
478 
BLEPLAT_CNTR_IntGetIntStatusBitAct2Error(uint32_t x)479 uint32_t BLEPLAT_CNTR_IntGetIntStatusBitAct2Error(uint32_t x)
480 {
481     return (uint32_t)(x & BLUE_STATUSREG_ACTIVE2ERROR_Msk);
482 }
483 
BLEPLAT_CNTR_IntGetIntStatusBitTimerOverrun(uint32_t x)484 uint32_t BLEPLAT_CNTR_IntGetIntStatusBitTimerOverrun(uint32_t x)
485 {
486     return 0;
487 }
488 
489 #if defined(BLUE_STATUSREG_RCVCRCERR_Msk)
BLEPLAT_CNTR_IntGetIntStatusCrcErr(uint32_t x)490 uint32_t BLEPLAT_CNTR_IntGetIntStatusCrcErr(uint32_t x)
491 {
492     return (uint32_t)(x & BLUE_STATUSREG_RCVCRCERR_Msk);
493 }
494 #endif
495 
496 #if defined(BLUE_STATUSREG_DONE_Msk)
BLEPLAT_CNTR_IntGetIntStatusDone(uint32_t x)497 uint32_t BLEPLAT_CNTR_IntGetIntStatusDone(uint32_t x)
498 {
499 	return (uint32_t)(x & BLUE_STATUSREG_DONE_Msk);
500 }
501 #endif
502 
503 #if defined(BLUE_STATUSREG_ENCERROR_Msk)
BLEPLAT_CNTR_IntGetIntStatusEncErr(uint32_t x)504 uint32_t BLEPLAT_CNTR_IntGetIntStatusEncErr(uint32_t x)
505 {
506     return (uint32_t)(x & BLUE_STATUSREG_ENCERROR_Msk);
507 }
508 #endif
509 
510 #if defined(BLUE_STATUSREG_RCVLENGTHERROR_Msk)
BLEPLAT_CNTR_IntGetIntStatusLenErr(uint32_t x)511 uint32_t BLEPLAT_CNTR_IntGetIntStatusLenErr(uint32_t x)
512 {
513     return (uint32_t)(x & BLUE_STATUSREG_RCVLENGTHERROR_Msk);
514 }
515 #endif
516 
517 #if defined(BLUE_STATUSREG_NOACTIVELERROR_Msk)
BLEPLAT_CNTR_IntGetIntStatusNoactiveError(uint32_t x)518 uint32_t BLEPLAT_CNTR_IntGetIntStatusNoactiveError(uint32_t x)
519 {
520     return (uint32_t)(x & BLUE_STATUSREG_NOACTIVELERROR_Msk);
521 }
522 #endif
523 
524 #if defined(BLUE_STATUSREG_TXRXSKIP_Msk)
BLEPLAT_CNTR_IntGetIntStatusTxRxSkip(uint32_t x)525 uint32_t BLEPLAT_CNTR_IntGetIntStatusTxRxSkip(uint32_t x)
526 {
527     return (uint32_t)(x & BLUE_STATUSREG_TXRXSKIP_Msk);
528 }
529 #endif
530 
531 #if defined(BLUE_STATUSREG_TXERROR_1_Msk)
BLEPLAT_CNTR_IntGetIntStatusTxError1(uint32_t x)532 uint32_t BLEPLAT_CNTR_IntGetIntStatusTxError1(uint32_t x)
533 {
534     return (uint32_t)(x & BLUE_STATUSREG_TXERROR_1_Msk);
535 }
536 #endif
537 
538 #if defined(BLUE_STATUSREG_TXERROR_3_Msk)
BLEPLAT_CNTR_IntGetIntStatusTxError3(uint32_t x)539 uint32_t BLEPLAT_CNTR_IntGetIntStatusTxError3(uint32_t x)
540 {
541     return (uint32_t)(x & BLUE_STATUSREG_TXERROR_3_Msk);
542 }
543 #endif
544 
545 #if defined(BLUE_STATUSREG_RCVOK_Msk)
BLEPLAT_CNTR_IntGetIntStatusRxOk(uint32_t x)546 uint32_t BLEPLAT_CNTR_IntGetIntStatusRxOk(uint32_t x)
547 {
548     return (uint32_t)(x & BLUE_STATUSREG_RCVOK_Msk);
549 }
550 #endif
551 
552 #if defined(BLUE_STATUSREG_RCVTIMEOUT_Msk)
BLEPLAT_CNTR_IntGetIntStatusTimeout(uint32_t x)553 uint32_t BLEPLAT_CNTR_IntGetIntStatusTimeout(uint32_t x)
554 {
555     return (uint32_t)(x & BLUE_STATUSREG_RCVTIMEOUT_Msk);
556 }
557 #endif
558 
559 #if defined(BLUE_STATUSREG_TIMECAPTURETRIG_Msk)
BLEPLAT_CNTR_IntGetIntStatusTrigRcv(uint32_t x)560 uint32_t BLEPLAT_CNTR_IntGetIntStatusTrigRcv(uint32_t x)
561 {
562     return (uint32_t)(x & BLUE_STATUSREG_TIMECAPTURETRIG_Msk);
563 }
564 #endif
565 
566 #if defined(BLUE_STATUSREG_PREVTRANSMIT_Msk)
BLEPLAT_CNTR_IntGetIntStatusTxDone(uint32_t x)567 uint32_t BLEPLAT_CNTR_IntGetIntStatusTxDone(uint32_t x)
568 {
569     return (uint32_t)(x & BLUE_STATUSREG_PREVTRANSMIT_Msk);
570 }
571 #endif
572 
573 #if defined(BLUE_STATUSREG_TXOK_Msk)
BLEPLAT_CNTR_IntGetIntStatusTxOk(uint32_t x)574 uint32_t BLEPLAT_CNTR_IntGetIntStatusTxOk(uint32_t x)
575 {
576     return (uint32_t)(x & BLUE_STATUSREG_TXOK_Msk);
577 }
578 #endif
579 
BLEPLAT_CNTR_PacketClrCrcinitSel(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)580 void BLEPLAT_CNTR_PacketClrCrcinitSel(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
581 {
582     LL_RADIO_SetCRCInitializationSelector((TXRXPACK_TypeDef*)packetP, (uint32_t) 0x0);
583 }
584 
BLEPLAT_CNTR_PacketClrCteSamplingEn(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)585 void BLEPLAT_CNTR_PacketClrCteSamplingEn(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
586 {
587 #if defined(STM32WB05) || defined(STM32WB09)
588   LL_RADIO_SetCTEAndSamplingEnable((TXRXPACK_TypeDef*)packetP, 0x0);
589 #elif defined(STM32WB06) || defined(STM32WB07)
590   /* nothing to do */
591 #endif
592 }
593 
BLEPLAT_CNTR_PacketClrIncChan(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)594 void BLEPLAT_CNTR_PacketClrIncChan(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
595 {
596     LL_RADIO_IncrementerChannel_Disable((TXRXPACK_TypeDef*)packetP);
597 }
598 
BLEPLAT_CNTR_PacketClrPllTrig(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)599 void BLEPLAT_CNTR_PacketClrPllTrig(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
600 {
601     LL_RADIO_SetCalibrationRequest((TXRXPACK_TypeDef*)packetP, (uint32_t) 0x0);
602 }
603 
BLEPLAT_CNTR_PacketDisableWhitening(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)604 void BLEPLAT_CNTR_PacketDisableWhitening(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
605 {
606     LL_RADIO_SetDisableWhitening((TXRXPACK_TypeDef*)packetP, (uint32_t) 0x1);
607 }
608 
BLEPLAT_CNTR_PacketGetCteSamplingEn(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)609 uint8_t BLEPLAT_CNTR_PacketGetCteSamplingEn(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
610 {
611 #if defined(STM32WB05) || defined(STM32WB09)
612   return (uint8_t)LL_RADIO_GetCTEAndSamplingEnable((TXRXPACK_TypeDef *)packetP);
613 #elif defined(STM32WB06) || defined(STM32WB07)
614   return (uint8_t)0;
615 #endif
616 
617 }
618 
BLEPLAT_CNTR_PacketGetDataPtr(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)619 uint8_t* BLEPLAT_CNTR_PacketGetDataPtr(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
620 {
621     return (uint8_t*)CONV_ADR(LL_RADIO_GetDataPointer((TXRXPACK_TypeDef*)packetP));
622 }
623 
BLEPLAT_CNTR_PacketInitTo0(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)624 void BLEPLAT_CNTR_PacketInitTo0(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
625 {
626     memset((void*)packetP, 0, sizeof(TXRXPACK_WORD_TypeDef));
627 }
628 
BLEPLAT_CNTR_PacketSetAdvPduFormat(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)629 void BLEPLAT_CNTR_PacketSetAdvPduFormat(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
630 {
631     LL_RADIO_SetAdvertise((TXRXPACK_TypeDef*)packetP, (uint32_t) 0x1);
632 }
633 
BLEPLAT_CNTR_PacketSetCrcinitSel(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)634 void BLEPLAT_CNTR_PacketSetCrcinitSel(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
635 {
636     LL_RADIO_SetCRCInitializationSelector((TXRXPACK_TypeDef*)packetP, (uint32_t) 0x1);
637 }
638 
BLEPLAT_CNTR_PacketSetCteSamplingEn(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)639 void BLEPLAT_CNTR_PacketSetCteSamplingEn(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
640 {
641 #if defined(STM32WB05) || defined(STM32WB09)
642   LL_RADIO_SetCTEAndSamplingEnable((TXRXPACK_TypeDef*)packetP, 0x01);
643 #elif defined(STM32WB06) || defined(STM32WB07)
644   /* nothing to do */
645 #endif
646 }
647 
BLEPLAT_CNTR_PacketSetDataPduFormat(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)648 void BLEPLAT_CNTR_PacketSetDataPduFormat(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
649 {
650      LL_RADIO_SetAdvertise((TXRXPACK_TypeDef*)packetP, (uint32_t) 0x0);
651 }
652 
BLEPLAT_CNTR_PacketSetDataPtr(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP,void * dataP)653 void BLEPLAT_CNTR_PacketSetDataPtr(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP, void* dataP)
654 {
655     LL_RADIO_SetDataPointer((TXRXPACK_TypeDef*)packetP, BLUE_DATA_PTR_CAST(dataP));
656 }
657 
BLEPLAT_CNTR_PacketSetIncChan(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)658 void BLEPLAT_CNTR_PacketSetIncChan(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
659 {
660     LL_RADIO_IncrementerChannel_Enable((TXRXPACK_TypeDef*)packetP);
661 }
662 
BLEPLAT_CNTR_PacketSetIntCrcErr(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)663 void BLEPLAT_CNTR_PacketSetIntCrcErr(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
664 {
665     LL_RADIO_IntRcvCRCErr_Enable((TXRXPACK_TypeDef*)packetP);
666 }
667 
BLEPLAT_CNTR_PacketSetIntDone(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)668 void BLEPLAT_CNTR_PacketSetIntDone(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
669 {
670     LL_RADIO_IntDone_Enable((TXRXPACK_TypeDef*)packetP);
671 }
672 
BLEPLAT_CNTR_PacketSetIntRcvOk(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)673 void BLEPLAT_CNTR_PacketSetIntRcvOk(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
674 {
675     LL_RADIO_IntRcvOk_Enable((TXRXPACK_TypeDef*)packetP);
676 }
677 
BLEPLAT_CNTR_PacketSetIntTimeout(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)678 void BLEPLAT_CNTR_PacketSetIntTimeout(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
679 {
680     LL_RADIO_IntRcvTimeout_Enable((TXRXPACK_TypeDef*)packetP);
681 }
682 
BLEPLAT_CNTR_PacketSetIntTrigRcv(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)683 void BLEPLAT_CNTR_PacketSetIntTrigRcv(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
684 {
685   LL_RADIO_SetIntTimeCapture((TXRXPACK_TypeDef*)packetP, (uint32_t) 0x1U);
686 }
687 
BLEPLAT_CNTR_PacketSetIntTxOk(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)688 void BLEPLAT_CNTR_PacketSetIntTxOk(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
689 {
690     LL_RADIO_SetIntTxOk((TXRXPACK_TypeDef*)packetP, (uint32_t) 0x1);
691 }
692 
BLEPLAT_CNTR_PacketSetKeepsemareq(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)693 void BLEPLAT_CNTR_PacketSetKeepsemareq(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
694 {
695     LL_RADIO_SetKeepSemaRequest((TXRXPACK_TypeDef*)packetP, (uint32_t) 0x1);
696 }
697 
BLEPLAT_CNTR_PacketSetNextPtr(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP,BLEPLAT_CNTR_TXRXPACK_TypeDef * packetNextP)698 void BLEPLAT_CNTR_PacketSetNextPtr(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP, BLEPLAT_CNTR_TXRXPACK_TypeDef* packetNextP)
699 {
700     LL_RADIO_SetNextPointer((TXRXPACK_TypeDef*)packetP, (uint32_t) BLUE_STRUCT_PTR_CAST((TXRXPACK_TypeDef*)packetNextP));
701 }
702 
BLEPLAT_CNTR_PacketSetNextRxMode(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)703 void BLEPLAT_CNTR_PacketSetNextRxMode(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
704 {
705     LL_RADIO_SetNextTxMode((TXRXPACK_TypeDef*)packetP, (uint32_t) 0x0);
706 }
707 
BLEPLAT_CNTR_PacketSetNextSlot(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP,uint8_t slot)708 void BLEPLAT_CNTR_PacketSetNextSlot(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP, uint8_t slot)
709 {
710     /* nothing to do */
711 }
712 
BLEPLAT_CNTR_PacketSetNextTxMode(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)713 void BLEPLAT_CNTR_PacketSetNextTxMode(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
714 {
715     LL_RADIO_SetNextTxMode((TXRXPACK_TypeDef*)packetP, (uint32_t) 0x1);
716 }
717 
BLEPLAT_CNTR_PacketSetNsEn(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)718 void BLEPLAT_CNTR_PacketSetNsEn(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
719 {
720     LL_RADIO_AutomaticSnNesnHardwareMechanism_Enable((TXRXPACK_TypeDef*)packetP);
721 }
722 
BLEPLAT_CNTR_PacketSetPllTrig(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)723 void BLEPLAT_CNTR_PacketSetPllTrig(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
724 {
725     LL_RADIO_SetCalibrationRequest((TXRXPACK_TypeDef*)packetP, (uint32_t) 0x1);
726 }
727 
BLEPLAT_CNTR_PacketSetRxReady(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)728 void BLEPLAT_CNTR_PacketSetRxReady(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
729 {
730     LL_RADIO_SetAllTableDataReady((TXRXPACK_TypeDef*)packetP, (uint32_t) 0x1);
731 }
732 
BLEPLAT_CNTR_PacketSetTimeout(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP,uint32_t x)733 void BLEPLAT_CNTR_PacketSetTimeout(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP, uint32_t x)
734 {
735     LL_RADIO_SetTimer2Triggering((TXRXPACK_TypeDef*)packetP, x);
736 }
737 
BLEPLAT_CNTR_PacketSetTimer2Active(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)738 void BLEPLAT_CNTR_PacketSetTimer2Active(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
739 {
740     LL_RADIO_Timer2_Enable((TXRXPACK_TypeDef*)packetP);
741 }
742 
BLEPLAT_CNTR_PacketSetTimerTrigDone(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)743 void BLEPLAT_CNTR_PacketSetTimerTrigDone(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
744 {
745     LL_RADIO_SetTrigDone((TXRXPACK_TypeDef*)packetP, (uint32_t) 0x1);
746 }
747 
BLEPLAT_CNTR_PacketSetTimerTrigRcv(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)748 void BLEPLAT_CNTR_PacketSetTimerTrigRcv(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
749 {
750     LL_RADIO_SetTrigRcv((TXRXPACK_TypeDef*)packetP, (uint32_t) 0x1);
751 }
752 
BLEPLAT_CNTR_PacketSetTxReady(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)753 void BLEPLAT_CNTR_PacketSetTxReady(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
754 {
755     LL_RADIO_SetTransmissionDataReady((TXRXPACK_TypeDef*)packetP, (uint32_t) 0x1);
756     LL_RADIO_SetAllTableDataReady((TXRXPACK_TypeDef*)packetP, (uint32_t) 0x1);
757 }
758 
BLEPLAT_CNTR_SetRadioConfig(uint8_t * value)759 void BLEPLAT_CNTR_SetRadioConfig(uint8_t* value)
760 {
761     /* nothing to do */
762 }
763 
BLEPLAT_CNTR_SetRcvLen(BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP,uint32_t rcvLen)764 void BLEPLAT_CNTR_SetRcvLen(BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP, uint32_t rcvLen)
765 {
766   (void)packetP;
767   LL_RADIO_SetReceiveWindowTimeout((uint32_t) (rcvLen & 0xFFFFFU));
768 }
769 
BLEPLAT_CNTR_SmCteOff(uint8_t smNo)770 void BLEPLAT_CNTR_SmCteOff(uint8_t smNo)
771 {
772 #if defined(STM32WB05) || defined(STM32WB09)
773   LL_RADIO_SetCTEDisable(smNo, 0x01);
774 #elif defined(STM32WB06) || defined(STM32WB07)
775   /* nothing to do */
776 #endif
777 }
778 
BLEPLAT_CNTR_SmCteOn(uint8_t smNo)779 void BLEPLAT_CNTR_SmCteOn(uint8_t smNo)
780 {
781 #if defined(STM32WB05) || defined(STM32WB09)
782   LL_RADIO_SetCTEDisable(smNo, 0x00);
783 #elif defined(STM32WB06) || defined(STM32WB07)
784   /* nothing to do */
785 #endif
786 }
787 
BLEPLAT_CNTR_SmEnRadioConfig(uint8_t smNo,uint32_t enable)788 void BLEPLAT_CNTR_SmEnRadioConfig(uint8_t smNo, uint32_t enable)
789 {
790     if(enable)
791 	    LL_RADIO_RadioCommandList_Enable(smNo);
792 	else
793 	    LL_RADIO_RadioCommandList_Disable(smNo);
794 }
795 
BLEPLAT_CNTR_SmEncOff(uint8_t smNo)796 void BLEPLAT_CNTR_SmEncOff(uint8_t smNo)
797 {
798     LL_RADIO_Encryption_Disable(smNo);
799     LL_RADIO_ReceiveEncryptionErrorInterrupt_Disable(smNo);
800 }
801 
BLEPLAT_CNTR_SmEncOn(uint8_t smNo)802 void BLEPLAT_CNTR_SmEncOn(uint8_t smNo)
803 {
804     LL_RADIO_Encryption_Enable(smNo);
805     LL_RADIO_ReceiveEncryptionErrorInterrupt_Enable(smNo);
806 }
807 
BLEPLAT_CNTR_SmGetAccessAddr(uint8_t smNo)808 uint32_t BLEPLAT_CNTR_SmGetAccessAddr(uint8_t smNo)
809 {
810     return LL_RADIO_GetAccessAddress(smNo);
811 }
812 
BLEPLAT_CNTR_SmGetChannelMap(uint8_t smNo,uint8_t * chanMap)813 void BLEPLAT_CNTR_SmGetChannelMap(uint8_t smNo, uint8_t* chanMap)
814 {
815     chanMap[0] = (uint8_t)(LL_RADIO_GetUsedChannelFlags_15_0(smNo));
816     chanMap[1] = (uint8_t)(LL_RADIO_GetUsedChannelFlags_15_0(smNo) >> 8U);
817     chanMap[2] = (uint8_t)(LL_RADIO_GetUsedChannelFlags_36_16(smNo));
818     chanMap[3] = (uint8_t)(LL_RADIO_GetUsedChannelFlags_36_16(smNo) >> 8U);
819     chanMap[4] = (uint8_t)(LL_RADIO_GetUsedChannelFlags_36_16(smNo) >> 16U);
820 }
821 
BLEPLAT_CNTR_SmGetCteAntennaPatternLen(uint8_t smNo)822 uint8_t BLEPLAT_CNTR_SmGetCteAntennaPatternLen(uint8_t smNo)
823 {
824 #if defined(STM32WB05) || defined(STM32WB09)
825     return (uint8_t)LL_RADIO_GetAntennaPatternLength(smNo);
826 #elif defined(STM32WB06) || defined(STM32WB07)
827   return (uint8_t)0;
828 #endif
829 }
830 
BLEPLAT_CNTR_SmGetCteAodNaoa(uint8_t smNo)831 uint8_t BLEPLAT_CNTR_SmGetCteAodNaoa(uint8_t smNo)
832 {
833 #if defined(STM32WB05) || defined(STM32WB09)
834     return (uint8_t)LL_RADIO_GetAodNaoa(smNo);
835 #elif defined(STM32WB06) || defined(STM32WB07)
836   return (uint8_t)0;
837 #endif
838 }
839 
BLEPLAT_CNTR_SmGetCteSlotWidth(uint8_t smNo)840 uint8_t BLEPLAT_CNTR_SmGetCteSlotWidth(uint8_t smNo)
841 {
842 #if defined(STM32WB05) || defined(STM32WB09)
843   return (uint8_t)LL_RADIO_GetCTESlotWidth(smNo);
844 #elif defined(STM32WB06) || defined(STM32WB07)
845   return (uint8_t)0;
846 #endif
847 }
848 
BLEPLAT_CNTR_SmGetCteStatus(uint8_t smNo)849 uint8_t BLEPLAT_CNTR_SmGetCteStatus(uint8_t smNo)
850 {
851 #if defined(STM32WB05) || defined(STM32WB09)
852     return (uint8_t)LL_RADIO_GetCTEDisable(smNo);
853 #elif defined(STM32WB06) || defined(STM32WB07)
854   return (uint8_t)0;
855 #endif
856 }
857 
BLEPLAT_CNTR_SmGetCteTime(uint8_t smNo)858 uint8_t BLEPLAT_CNTR_SmGetCteTime(uint8_t smNo)
859 {
860 #if defined(STM32WB05) || defined(STM32WB09)
861   return (uint8_t)LL_RADIO_GetCTETime(smNo);
862 #elif defined(STM32WB06) || defined(STM32WB07)
863   return (uint8_t)0;
864 #endif
865 }
866 
BLEPLAT_CNTR_SmGetEncIvPtr(uint8_t smNo)867 uint32_t* BLEPLAT_CNTR_SmGetEncIvPtr(uint8_t smNo)
868 {
869     return (uint32_t*)&(bluedata + smNo)->ENCRYPTIV[0];
870 }
871 
BLEPLAT_CNTR_SmGetEncKeyPtr(uint8_t smNo)872 uint32_t* BLEPLAT_CNTR_SmGetEncKeyPtr(uint8_t smNo)
873 {
874 	return (uint32_t*)&(bluedata + smNo)->ENCRYPTK[0];
875 }
876 
BLEPLAT_CNTR_SmGetEncStatus(uint8_t smNo)877 uint8_t BLEPLAT_CNTR_SmGetEncStatus(uint8_t smNo)
878 {
879     return (uint8_t)LL_RADIO_Encryption_IsEnabled(smNo);
880 }
881 
BLEPLAT_CNTR_SmGetHopIncr(uint8_t smNo)882 uint8_t BLEPLAT_CNTR_SmGetHopIncr(uint8_t smNo)
883 {
884     return (uint8_t)LL_RADIO_GetHopIncrement(smNo);
885 }
886 
BLEPLAT_CNTR_SmGetMode(uint8_t smNo)887 uint8_t BLEPLAT_CNTR_SmGetMode(uint8_t smNo)
888 {
889     return LL_RADIO_TxMode_IsEnabled(smNo);
890 }
891 
BLEPLAT_CNTR_SmGetPrevRxPacketDataPtr(uint8_t smNo)892 uint8_t* BLEPLAT_CNTR_SmGetPrevRxPacketDataPtr(uint8_t smNo)
893 {
894     return (uint8_t*)CONV_ADR(BLUE_TRANS_STRUCT_PTR_CAST(LL_RADIO_GetRcvPointPrevious(smNo))->DATAPTR);
895 }
896 
BLEPLAT_CNTR_SmGetPrevRxPacketPtr(uint8_t smNo)897 BLEPLAT_CNTR_TXRXPACK_TypeDef* BLEPLAT_CNTR_SmGetPrevRxPacketPtr(uint8_t smNo)
898 {
899     return (BLEPLAT_CNTR_TXRXPACK_TypeDef*)BLUE_TRANS_STRUCT_PTR_CAST(CONV_ADR(LL_RADIO_GetRcvPointPrevious(smNo)));
900 }
901 
BLEPLAT_CNTR_SmGetPrevTxPacketDataPtr(uint8_t smNo)902 uint8_t* BLEPLAT_CNTR_SmGetPrevTxPacketDataPtr(uint8_t smNo)
903 {
904     return (uint8_t*)CONV_ADR(BLUE_TRANS_STRUCT_PTR_CAST(LL_RADIO_GetTxPointPrevious(smNo))->DATAPTR);
905 }
906 
BLEPLAT_CNTR_SmGetPrevTxPacketPtr(uint8_t smNo)907 BLEPLAT_CNTR_TXRXPACK_TypeDef* BLEPLAT_CNTR_SmGetPrevTxPacketPtr(uint8_t smNo)
908 {
909     return (BLEPLAT_CNTR_TXRXPACK_TypeDef*)BLUE_TRANS_STRUCT_PTR_CAST(CONV_ADR(LL_RADIO_GetTxPointPrevious(smNo)));
910 }
911 
BLEPLAT_CNTR_SmGetRemapChan(uint8_t smNo)912 uint8_t BLEPLAT_CNTR_SmGetRemapChan(uint8_t smNo)
913 {
914     return (uint8_t)LL_RADIO_GetRemapChannel(smNo);
915 }
916 
BLEPLAT_CNTR_SmGetRxCount(uint8_t smNo,uint32_t * packetCount)917 void BLEPLAT_CNTR_SmGetRxCount(uint8_t smNo, uint32_t* packetCount)
918 {
919 
920     packetCount[0] = LL_RADIO_GetPacketCounterRx_23_0(smNo);
921     packetCount[0] = packetCount[0] | ((uint32_t)LL_RADIO_GetPacketCounterRx_39_24(smNo) << 24U);
922     packetCount[1] = LL_RADIO_GetPacketCounterRx_39_24(smNo) >> 8U;
923 }
924 
BLEPLAT_CNTR_SmGetRxPhy(uint8_t smNo)925 uint8_t BLEPLAT_CNTR_SmGetRxPhy(uint8_t smNo)
926 {
927     return (uint8_t)LL_RADIO_GetReceptionPhy(smNo);
928 }
929 
BLEPLAT_CNTR_SmGetTxPacketPtr(uint8_t smNo)930 BLEPLAT_CNTR_TXRXPACK_TypeDef* BLEPLAT_CNTR_SmGetTxPacketPtr(uint8_t smNo)
931 {
932     return (BLEPLAT_CNTR_TXRXPACK_TypeDef*)BLUE_TRANS_STRUCT_PTR_CAST(CONV_ADR(LL_RADIO_GetTxPoint(smNo)));
933 }
934 
BLEPLAT_CNTR_SmGetTxPhy(uint8_t smNo)935 uint8_t BLEPLAT_CNTR_SmGetTxPhy(uint8_t smNo)
936 {
937     return (uint8_t)LL_RADIO_GetTransmissionPhy(smNo);
938 }
939 
BLEPLAT_CNTR_SmGetTxPwr(uint8_t smNo)940 uint8_t BLEPLAT_CNTR_SmGetTxPwr(uint8_t smNo)
941 {
942     uint8_t pa_level = LL_RADIO_GetPAPower(smNo);
943 
944 #if defined(STM32WB09)
945     if (LL_RADIO_TxHp_IsEnabled(smNo) && (pa_level == MAX_PA_LEVEL))
946     {
947         pa_level = HP_PA_LEVEL;
948     }
949 #endif
950     return pa_level;
951 }
952 
BLEPLAT_CNTR_SmGetUnmappedChan(uint8_t smNo)953 uint8_t BLEPLAT_CNTR_SmGetUnmappedChan(uint8_t smNo)
954 {
955     return (uint8_t)LL_RADIO_GetUnmappedChannel(smNo);
956 }
957 
BLEPLAT_CNTR_SmInitTo0(uint8_t smNo)958 void BLEPLAT_CNTR_SmInitTo0(uint8_t smNo)
959 {
960   memset((void*)&bluedata[smNo], 0, sizeof(STATMACH_TypeDef));
961   BLEPLAT_CNTR_SmEnRadioConfig(smNo, 0x01);
962 }
963 
BLEPLAT_CNTR_SmSetAccessAddr(uint8_t smNo,uint32_t x)964 void BLEPLAT_CNTR_SmSetAccessAddr(uint8_t smNo, uint32_t x)
965 {
966     LL_RADIO_SetAccessAddress(smNo, x);
967 }
968 
BLEPLAT_CNTR_SmSetChannelMap(uint8_t smNo,uint8_t * chanMap)969 void BLEPLAT_CNTR_SmSetChannelMap(uint8_t smNo, uint8_t* chanMap)
970 {
971     uint32_t value = (uint32_t)chanMap[0] | ((uint32_t)chanMap[1] << 8U);
972     LL_RADIO_SetUsedChannelFlags_15_0(smNo, value);
973     value = (uint32_t)chanMap[2] | ((uint32_t)chanMap[3] << 8U) | ((uint32_t)chanMap[4] << 16U);
974     LL_RADIO_SetUsedChannelFlags_36_16(smNo, value);
975 }
976 
BLEPLAT_CNTR_SmSetCrcInit(uint8_t smNo,uint32_t x)977 void BLEPLAT_CNTR_SmSetCrcInit(uint8_t smNo, uint32_t x)
978 {
979   LL_RADIO_SetCRCInitializationValue(smNo, x);
980 }
981 
BLEPLAT_CNTR_SmSetCteAntennaPatternLen(uint8_t smNo,uint8_t antPattLen)982 void BLEPLAT_CNTR_SmSetCteAntennaPatternLen(uint8_t smNo, uint8_t antPattLen)
983 {
984 #if defined(STM32WB05) || defined(STM32WB09)
985   LL_RADIO_SetAntennaPatternLength(smNo, (uint32_t) antPattLen);
986 #elif defined(STM32WB06) || defined(STM32WB07)
987   /* nothing to do */
988 #endif
989 }
990 
BLEPLAT_CNTR_SmGetCteAntennaPatternPtr(uint8_t smNo)991 uint32_t BLEPLAT_CNTR_SmGetCteAntennaPatternPtr(uint8_t smNo)
992 {
993 #if defined(STM32WB05) || defined(STM32WB09)
994   return LL_RADIO_GetAntennaPatternPtr(smNo);
995 #elif defined(STM32WB06) || defined(STM32WB07)
996   return 0x00UL;
997 #endif
998 }
999 
BLEPLAT_CNTR_SmSetCteAntennaPatternPtr(uint8_t smNo,uint8_t * antPattP)1000 void BLEPLAT_CNTR_SmSetCteAntennaPatternPtr(uint8_t smNo, uint8_t* antPattP)
1001 {
1002 #if defined(STM32WB05) || defined(STM32WB09)
1003   LL_RADIO_SetAntennaPatternPtr(smNo, (uint32_t)(uintptr_t)antPattP);
1004 #elif defined(STM32WB06) || defined(STM32WB07)
1005   /* nothing to do */
1006 #endif
1007 }
1008 
BLEPLAT_CNTR_SmSetCteAoa(uint8_t smNo)1009 void BLEPLAT_CNTR_SmSetCteAoa(uint8_t smNo)
1010 {
1011 #if defined(STM32WB05) || defined(STM32WB09)
1012   LL_RADIO_SetAodNaoa(smNo, 0x0);
1013 #elif defined(STM32WB06) || defined(STM32WB07)
1014   /* nothing to do */
1015 #endif
1016 }
1017 
BLEPLAT_CNTR_SmSetCteAod(uint8_t smNo)1018 void BLEPLAT_CNTR_SmSetCteAod(uint8_t smNo)
1019 {
1020 #if defined(STM32WB05) || defined(STM32WB09)
1021   LL_RADIO_SetAodNaoa(smNo, 0x01);
1022 #elif defined(STM32WB06) || defined(STM32WB07)
1023   /* nothing to do */
1024 #endif
1025 }
1026 
BLEPLAT_CNTR_SmSetCteIqsamplesPtr(uint8_t smNo,uint32_t * iqSamplesP)1027 void BLEPLAT_CNTR_SmSetCteIqsamplesPtr(uint8_t smNo, uint32_t* iqSamplesP)
1028 {
1029 #if defined(STM32WB05) || defined(STM32WB09)
1030   LL_RADIO_SetIQSamplesPtr(smNo, (uint32_t)(uintptr_t)iqSamplesP);
1031 #elif defined(STM32WB06) || defined(STM32WB07)
1032   /* nothing to do */
1033 #endif
1034 }
1035 
BLEPLAT_CNTR_SmSetCteMaxIqsamplesNumb(uint8_t smNo,uint8_t iqsamplesNumb)1036 void BLEPLAT_CNTR_SmSetCteMaxIqsamplesNumb(uint8_t smNo, uint8_t iqsamplesNumb)
1037 {
1038 #if defined(STM32WB05) || defined(STM32WB09)
1039   LL_RADIO_SetMaximumIQSamplesNumber(smNo, (uint32_t) iqsamplesNumb);
1040 #elif defined(STM32WB06) || defined(STM32WB07)
1041   /* nothing to do */
1042 #endif
1043 }
1044 
BLEPLAT_CNTR_SmSetCteSlotWidth(uint8_t smNo,uint32_t cteSlot)1045 void BLEPLAT_CNTR_SmSetCteSlotWidth(uint8_t smNo, uint32_t cteSlot)
1046 {
1047 #if defined(STM32WB05) || defined(STM32WB09)
1048   LL_RADIO_SetCTESlotWidth(smNo, cteSlot);
1049 #elif defined(STM32WB06) || defined(STM32WB07)
1050   /* nothing to do */
1051 #endif
1052 }
1053 
BLEPLAT_CNTR_SmSetCteTime(uint8_t smNo,uint8_t cteTime)1054 void BLEPLAT_CNTR_SmSetCteTime(uint8_t smNo, uint8_t cteTime)
1055 {
1056 #if defined(STM32WB05) || defined(STM32WB09)
1057   LL_RADIO_SetCTETime(smNo, (uint32_t) cteTime);
1058 #elif defined(STM32WB06) || defined(STM32WB07)
1059   /* nothing to do */
1060 #endif
1061 }
1062 
BLEPLAT_CNTR_SmSetDataLength(uint8_t smNo,uint8_t length)1063 void BLEPLAT_CNTR_SmSetDataLength(uint8_t smNo, uint8_t length)
1064 {
1065     LL_RADIO_SetMaximumReceiveLength(smNo, (uint32_t) length);
1066 }
1067 
BLEPLAT_CNTR_SmSetDataLengthExtnEn(uint8_t smNo)1068 void BLEPLAT_CNTR_SmSetDataLengthExtnEn(uint8_t smNo)
1069 {
1070     /* nothing to do */
1071 }
1072 
BLEPLAT_CNTR_SmSetHopIncr(uint8_t smNo,uint8_t x)1073 void BLEPLAT_CNTR_SmSetHopIncr(uint8_t smNo, uint8_t x)
1074 {
1075     LL_RADIO_SetHopIncrement(smNo, (uint32_t) x);
1076 }
1077 
BLEPLAT_CNTR_SmSetRemapChan(uint8_t smNo,uint8_t chan)1078 void BLEPLAT_CNTR_SmSetRemapChan(uint8_t smNo, uint8_t chan)
1079 {
1080     LL_RADIO_SetRemapChannel(smNo, chan);
1081 }
1082 
BLEPLAT_CNTR_SmSetRxCount(uint8_t smNo,uint32_t * packetCount)1083 void BLEPLAT_CNTR_SmSetRxCount(uint8_t smNo, uint32_t* packetCount)
1084 {
1085     LL_RADIO_SetPacketCounterRx_23_0(smNo, (uint32_t) packetCount[0]);
1086     uint32_t value = (uint32_t)(packetCount[1] << 8U) | (uint32_t)(packetCount[0] >> 24U);
1087     LL_RADIO_SetPacketCounterRx_39_24(smNo, value);
1088 }
1089 
BLEPLAT_CNTR_SmSetRxCountDirectionBit(uint8_t smNo)1090 void BLEPLAT_CNTR_SmSetRxCountDirectionBit(uint8_t smNo)
1091 {
1092     uint32_t value = LL_RADIO_GetPacketCounterRx_39_24(smNo) | 0x8000U;
1093     LL_RADIO_SetPacketCounterRx_39_24(smNo, value);
1094 }
1095 
BLEPLAT_CNTR_SmSetRxMode(uint8_t smNo)1096 void BLEPLAT_CNTR_SmSetRxMode(uint8_t smNo)
1097 {
1098     LL_RADIO_TxMode_Disable(smNo);
1099 }
1100 
BLEPLAT_CNTR_SmSetRxPacketPtr(uint8_t smNo,BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)1101 void BLEPLAT_CNTR_SmSetRxPacketPtr(uint8_t smNo, BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
1102 {
1103     LL_RADIO_SetRcvPoint(smNo, (uint32_t) BLUE_STRUCT_PTR_CAST((TXRXPACK_TypeDef*)packetP));
1104 }
1105 
BLEPLAT_CNTR_SmSetRxPhy(uint8_t smNo,uint8_t rxPhy)1106 void BLEPLAT_CNTR_SmSetRxPhy(uint8_t smNo, uint8_t rxPhy)
1107 {
1108     LL_RADIO_SetReceptionPhy(smNo, (uint32_t) rxPhy);
1109 }
1110 
BLEPLAT_CNTR_SmSetTxCount(uint8_t smNo,uint32_t * packetCount)1111 void BLEPLAT_CNTR_SmSetTxCount(uint8_t smNo, uint32_t* packetCount)
1112 {
1113     LL_RADIO_SetPacketCounterTx_31_0(smNo, (uint32_t) packetCount[0]);
1114     LL_RADIO_SetPacketCounterTx_39_32(smNo, (uint32_t) packetCount[1]);
1115 }
1116 
BLEPLAT_CNTR_SmSetTxCountDirectionBit(uint8_t smNo)1117 void BLEPLAT_CNTR_SmSetTxCountDirectionBit(uint8_t smNo)
1118 {
1119     uint32_t value =  (LL_RADIO_GetPacketCounterTx_39_32(smNo) | 0x00000080U);
1120     LL_RADIO_SetPacketCounterTx_39_32(smNo,  value);
1121 }
1122 
BLEPLAT_CNTR_SmSetTxMode(uint8_t smNo)1123 void BLEPLAT_CNTR_SmSetTxMode(uint8_t smNo)
1124 {
1125     LL_RADIO_TxMode_Enable(smNo);
1126 }
1127 
BLEPLAT_CNTR_SmSetTxPacketPtr(uint8_t smNo,BLEPLAT_CNTR_TXRXPACK_TypeDef * packetP)1128 void BLEPLAT_CNTR_SmSetTxPacketPtr(uint8_t smNo, BLEPLAT_CNTR_TXRXPACK_TypeDef* packetP)
1129 {
1130     LL_RADIO_SetTxPoint(smNo, (uint32_t) BLUE_STRUCT_PTR_CAST((TXRXPACK_TypeDef*)packetP));
1131 }
1132 
BLEPLAT_CNTR_SmSetTxPhy(uint8_t smNo,uint8_t txPhy)1133 void BLEPLAT_CNTR_SmSetTxPhy(uint8_t smNo, uint8_t txPhy)
1134 {
1135     LL_RADIO_SetTransmissionPhy(smNo, (uint32_t) txPhy);
1136 }
1137 
BLEPLAT_CNTR_SmEnTxHp(uint8_t smNo,uint8_t enable)1138 void BLEPLAT_CNTR_SmEnTxHp(uint8_t smNo, uint8_t enable)
1139 {
1140 #if defined(STM32WB09)
1141   if(enable)
1142   {
1143     LL_RADIO_TxHp_Enable(smNo);
1144   }
1145   else
1146   {
1147     LL_RADIO_TxHp_Disable(smNo);
1148   }
1149 #endif
1150 }
1151 
1152 /* Consider PA Level 32 the one used to enable high power. */
BLEPLAT_CNTR_SmSetTxPwr(uint8_t smNo,uint8_t paLevel)1153 void BLEPLAT_CNTR_SmSetTxPwr(uint8_t smNo, uint8_t paLevel)
1154 {
1155 #if defined(STM32WB09)
1156   if(paLevel == HP_PA_LEVEL)
1157   {
1158     LL_RADIO_TxHp_Enable(smNo);
1159     paLevel = MAX_PA_LEVEL;
1160   }
1161   else
1162   {
1163     LL_RADIO_TxHp_Disable(smNo);
1164   }
1165 #endif
1166 
1167   LL_RADIO_SetPAPower(smNo, (uint32_t) paLevel);
1168 }
1169 
BLEPLAT_CNTR_SmSetUnmappedChan(uint8_t smNo,uint8_t chan)1170 void BLEPLAT_CNTR_SmSetUnmappedChan(uint8_t smNo, uint8_t chan)
1171 {
1172     LL_RADIO_SetUnmappedChannel(smNo, (uint32_t) chan);
1173 }
1174 
BLEPLAT_CNTR_SmToggleNesn(uint8_t smNo)1175 void BLEPLAT_CNTR_SmToggleNesn(uint8_t smNo)
1176 {
1177   LL_RADIO_ToggleNextExpectedSequenceNumber(smNo);
1178 }
1179 
BLEPLAT_CNTR_SmToggleSn(uint8_t smNo)1180 void BLEPLAT_CNTR_SmToggleSn(uint8_t smNo)
1181 {
1182     LL_RADIO_ToggleSequenceNumber(smNo);
1183 }
1184 
BLEPLAT_CNTR_StartEncrypt()1185 void BLEPLAT_CNTR_StartEncrypt()
1186 {
1187      LL_RADIO_BlueSetManAESCmdStart(0x1U);
1188 }
1189 
BLEPLAT_CNTR_TimeDiff(uint32_t x,uint32_t y)1190 uint32_t BLEPLAT_CNTR_TimeDiff(uint32_t x, uint32_t y)
1191 {
1192     return (uint32_t)(x - y);
1193 }
1194 
BLEPLAT_CNTR_DemodDelaySt(uint8_t RxPHY)1195 uint8_t BLEPLAT_CNTR_DemodDelaySt(uint8_t RxPHY)
1196 {
1197     return (uint8_t)((LL_PHY_CODED == RxPHY) ? 0x9DU : 0x12U);
1198 }
1199 
1200 /**
1201 * @}
1202 */
1203 
1204 /**
1205 * @}
1206 */
1207