1 /*
2  * Copyright (c) 2019-2024 Arm Limited. All rights reserved.
3  * Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company)
4  * or an affiliate of Cypress Semiconductor Corporation. All rights reserved.
5  *
6  * Licensed under the Apache License, Version 2.0 (the "License");
7  * you may not use this file except in compliance with the License.
8  * You may obtain a copy of the License at
9  *
10  *     http://www.apache.org/licenses/LICENSE-2.0
11  *
12  * Unless required by applicable law or agreed to in writing, software
13  * distributed under the License is distributed on an "AS IS" BASIS,
14  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15  * See the License for the specific language governing permissions and
16  * limitations under the License.
17  */
18 
19 #ifndef __REGION_DEFS_H__
20 #define __REGION_DEFS_H__
21 
22 #include "flash_layout.h"
23 #include "platform_base_address.h"
24 #include "rse_memory_sizes.h"
25 
26 /* RSE memory layout is as follows during BL1
27  *      |----------------------------------------|
28  * DTCM | BOOT_SHARED | BL1_1_DATA | BL1_2_DATA  |
29  *      |----------------------------------------|
30  *
31  *      |----------------------------------------|
32  * ITCM | BL1_2_CODE  |                          |
33  *      |----------------------------------------|
34  *
35  *      |---------------------------------------------------------
36  * VM0  |                                                        |
37  *      |---------------------------------------------------------
38  *      |---------------------------------------------------------
39  * VM1  |                                                        |
40  *      |---------------------------------------------------------
41  *
42  * If the size of VM0 and VM1 are larger than 64KiB, the size of BL1 code/data
43  * and BL2 code can be increased to fill the extra space.
44  *
45  * RSE memory layout is as follows during BL2
46  *      |----------------------------------------|
47  * DTCM | BOOT_SHARED |                          |
48  *      |----------------------------------------|
49  *
50  *      |---------------------------------------------------------
51  * VM0  | BL2_CODE                                               |
52  *      |---------------------------------------------------------
53  *      |---------------------------------------------------------
54  * VM1  |  XIP tables  | BL2_DATA                                |
55  *      |---------------------------------------------------------
56  *
57  * If the size of VM0 and VM1 are larger than 64KiB, the size of BL2 code can be
58  * increased to fill the extra space. Note that BL2 code is aligned to the start
59  * of S_DATA, so under non-XIP mode it will not start at the beginning of VM0.
60  *
61  * RSE memory layout is as follows during Runtime with XIP mode enabled
62  *      |----------------------------------------|
63  * DTCM | BOOT_SHARED |                          |
64  *      |----------------------------------------|
65  *
66  *      |---------------------------------------------------------
67  * VM0  | S_DATA                                                 |
68  *      |---------------------------------------------------------
69  *      |---------------------------------------------------------
70  * VM1  | S_DATA                     | NS_DATA                   |
71  *      |---------------------------------------------------------
72  *
73  * RSE memory layout is as follows during Runtime with XIP mode disabled. Note
74  * that each SRAM must be at least 512KiB in this mode (64KiB data and 384KiB
75  * code, for each of secure and non-secure).
76  *      |----------------------------------------|
77  * DTCM | BOOT_SHARED |                          |
78  *      |----------------------------------------|
79  *
80  *      |----------------------------------------------------------------------|
81  * VM0  | S_CODE                                           | S_DATA            |
82  *      |----------------------------------------------------------------------|
83  *      |----------------------------------------------------------------------|
84  * VM1  |  NS_DATA          | NS_CODE                                          |
85  *      |----------------------------------------------------------------------|
86  */
87 
88 #define BL1_1_HEAP_SIZE         (0x0001000)
89 #define BL1_1_MSP_STACK_SIZE    (0x0001800)
90 
91 #define BL1_2_HEAP_SIZE         (0x0001000)
92 #define BL1_2_MSP_STACK_SIZE    (0x0001800)
93 
94 #define BL2_HEAP_SIZE           (0x0001000)
95 #define BL2_MSP_STACK_SIZE      (0x0001800)
96 
97 #define S_HEAP_SIZE             (0x0001000)
98 #define S_MSP_STACK_SIZE        (0x0000800)
99 
100 #define NS_HEAP_SIZE            (0x0001000)
101 #define NS_STACK_SIZE           (0x0001000)
102 
103 /* This size of buffer is big enough to store an array of all the
104  * boot records/measurements which is encoded in CBOR format.
105  */
106 #define TFM_ATTEST_BOOT_RECORDS_MAX_SIZE    (0x400)
107 
108 #define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_4_OFFSET)
109 
110 /* Boot partition structure if MCUBoot is used:
111  * 0x0_0000 Bootloader header
112  * 0x0_0400 Image area
113  * 0x5_0000 Trailer
114  */
115 /* IMAGE_CODE_SIZE is the space available for the software binary image.
116  * It is less than the FLASH_S_PARTITION_SIZE + FLASH_NS_PARTITION_SIZE
117  * because we reserve space for the image header and trailer introduced
118  * by the bootloader.
119  */
120 #define IMAGE_BL2_CODE_SIZE \
121             (FLASH_BL2_PARTITION_SIZE - BL1_HEADER_SIZE - BL1_TRAILER_SIZE)
122 
123 #define IMAGE_S_CODE_SIZE \
124             (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
125 
126 #define IMAGE_NS_CODE_SIZE \
127             (FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
128 
129 /* Secure regions */
130 /* Secure Code executes from VM0, or XIP from flash via the SIC */
131 #ifdef RSE_XIP
132 #define S_CODE_START    (RSE_RUNTIME_S_XIP_BASE_S)
133 #define S_CODE_SIZE     (FLASH_S_PARTITION_SIZE)
134 #else
135 #define S_CODE_START    (S_IMAGE_LOAD_ADDRESS + BL2_HEADER_SIZE)
136 #define S_CODE_SIZE     (IMAGE_S_CODE_SIZE)
137 #endif /* RSE_XIP */
138 #define S_CODE_LIMIT    (S_CODE_START + S_CODE_SIZE - 1)
139 
140 /* Secure Data stored in VM0. Size defined in flash layout */
141 #ifdef RSE_XIP
142 #define S_DATA_START    (VM0_BASE_S)
143 #define S_DATA_SIZE     (VM0_SIZE + VM1_SIZE - NS_DATA_SIZE)
144 #else
145 #define S_DATA_START    (VM0_BASE_S + FLASH_S_PARTITION_SIZE)
146 #define S_DATA_SIZE     (VM0_SIZE - FLASH_S_PARTITION_SIZE)
147 #endif /* RSE_XIP */
148 #define S_DATA_LIMIT    (S_DATA_START + S_DATA_SIZE - 1)
149 
150 /* Size of vector table: 111 interrupt handlers + 4 bytes MSP initial value */
151 #define S_CODE_VECTOR_TABLE_SIZE    (0x1C0)
152 
153 /* Non-secure regions */
154 /* Non-Secure Code executes from VM1, or XIP from flash via the SIC */
155 #ifdef RSE_XIP
156 #define NS_CODE_START   (RSE_RUNTIME_NS_XIP_BASE_NS)
157 #define NS_CODE_SIZE    (FLASH_NS_PARTITION_SIZE)
158 #else
159 #define NS_CODE_START   (NS_DATA_START + NS_DATA_SIZE + BL2_HEADER_SIZE)
160 #define NS_CODE_SIZE    (IMAGE_NS_CODE_SIZE)
161 #endif /* RSE_XIP */
162 #define NS_CODE_LIMIT   (NS_CODE_START + NS_CODE_SIZE - 1)
163 
164 /* Non-Secure Data stored after secure data, or in VM1 if not in XIP mode. */
165 #ifdef RSE_XIP
166 #define NS_DATA_START   (VM0_BASE_NS + S_DATA_SIZE)
167 #else
168 #define NS_DATA_START   (VM1_BASE_NS)
169 /* In the case of non-XIP configs, the NS data section size is controlled by the
170  * size of the NS image (with the NS image plus data section taking up the whole
171  * of VM1) so platforms should instead alter the size of the NS image.
172  */
173 #undef  NS_DATA_SIZE
174 #define NS_DATA_SIZE    (VM1_SIZE - FLASH_NS_PARTITION_SIZE)
175 #endif
176 #define NS_DATA_LIMIT   (NS_DATA_START + NS_DATA_SIZE - 1)
177 
178 /* NS partition information is used for MPC and SAU configuration */
179 #ifdef RSE_XIP
180 #define NS_PARTITION_START RSE_RUNTIME_NS_XIP_BASE_NS
181 #else
182 #define NS_PARTITION_START (NS_DATA_START + NS_DATA_SIZE)
183 #endif /* RSE_XIP */
184 #define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE)
185 
186 #define SECONDARY_PARTITION_START (FWU_HOST_IMAGE_BASE_S)
187 #define SECONDARY_PARTITION_SIZE (HOST_IMAGE_MAX_SIZE)
188 
189 /* Bootloader regions */
190 /* BL1_1 is XIP from ROM */
191 #define BL1_1_CODE_START  (ROM_BASE_S)
192 #define BL1_1_CODE_SIZE   (0x10000) /* 64 KiB */
193 #define BL1_1_CODE_LIMIT  (BL1_1_CODE_START + BL1_1_CODE_SIZE - 1)
194 
195 #define PROVISIONING_DATA_START (BL1_1_CODE_START + BL1_1_CODE_SIZE)
196 #define PROVISIONING_DATA_SIZE  (0x2400) /* 9 KB */
197 #define PROVISIONING_DATA_LIMIT (PROVISIONING_DATA_START + PROVISIONING_DATA_SIZE - 1)
198 
199 /* BL1_2 is in the ITCM */
200 #define BL1_2_CODE_START  (ITCM_BASE_S)
201 #define BL1_2_CODE_SIZE   (0x2000) /* 8 KiB */
202 #define BL1_2_CODE_LIMIT  (BL1_2_CODE_START + BL1_2_CODE_SIZE - 1)
203 
204 /* BL2 is aligned to the start of the combined secure/non-secure data region */
205 #define BL2_IMAGE_START   (S_DATA_START)
206 #define BL2_CODE_START    (BL2_IMAGE_START + BL1_HEADER_SIZE)
207 #define BL2_CODE_SIZE     (IMAGE_BL2_CODE_SIZE)
208 #define BL2_CODE_LIMIT    (BL2_CODE_START + BL2_CODE_SIZE - 1)
209 
210 #if FLASH_BL2_PARTITION_SIZE + BL2_DATA_SIZE + XIP_TABLE_SIZE > VM0_SIZE + VM1_SIZE
211 #error FLASH_BL2_PARTITION_SIZE + BL2_DATA_SIZE + 2 * FLASH_SIC_TABLE_SIZE is too large to fit in RSE SRAM
212 #endif
213 
214 /* BL1 data is in DTCM */
215 #define BL1_1_DATA_START  (BOOT_TFM_SHARED_DATA_BASE + BOOT_TFM_SHARED_DATA_SIZE)
216 #define BL1_1_DATA_SIZE   ((DTCM_SIZE - BOOT_TFM_SHARED_DATA_SIZE) / 2)
217 #define BL1_1_DATA_LIMIT  (BL1_1_DATA_START + BL1_1_DATA_SIZE - 1)
218 
219 #define BL1_2_DATA_START  (BL1_1_DATA_START + BL1_1_DATA_SIZE)
220 #define BL1_2_DATA_SIZE   ((DTCM_SIZE - BOOT_TFM_SHARED_DATA_SIZE) / 2)
221 #define BL1_2_DATA_LIMIT  (BL1_2_DATA_START + BL1_2_DATA_SIZE - 1)
222 
223 /* XIP data goes after the BL2 image */
224 #define BL2_XIP_TABLES_START (BL2_IMAGE_START + FLASH_BL2_PARTITION_SIZE)
225 #define BL2_XIP_TABLES_SIZE  (FLASH_SIC_TABLE_SIZE * 2)
226 #define BL2_XIP_TABLES_LIMIT (BL2_XIP_TABLES_START + BL2_XIP_TABLES_SIZE - 1)
227 
228 /* BL2 data is after the code. TODO FIXME this should be in DTCM once the CC3XX
229  * runtime driver supports DMA remapping.
230  */
231 #define BL2_DATA_START    (BL2_XIP_TABLES_START + BL2_XIP_TABLES_SIZE)
232 #define BL2_DATA_SIZE     (VM0_SIZE + VM1_SIZE - BL2_XIP_TABLES_SIZE - FLASH_BL2_PARTITION_SIZE)
233 #define BL2_DATA_LIMIT    (BL2_DATA_START + BL2_DATA_SIZE - 1)
234 
235 /* Store boot data at the start of the DTCM. */
236 #define BOOT_TFM_SHARED_DATA_BASE DTCM_BASE_S
237 #define BOOT_TFM_SHARED_DATA_SIZE (0x600)
238 #define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \
239                                     BOOT_TFM_SHARED_DATA_SIZE - 1)
240 
241 #define PROVISIONING_BUNDLE_CODE_START VM0_BASE_S
242 #define PROVISIONING_BUNDLE_VALUES_START (BL1_2_DATA_START)
243 #define PROVISIONING_BUNDLE_DATA_START (PROVISIONING_BUNDLE_VALUES_START + \
244                                         PROVISIONING_BUNDLE_VALUES_SIZE)
245 #define PROVISIONING_BUNDLE_DATA_SIZE (BL1_2_DATA_SIZE - \
246                                        PROVISIONING_BUNDLE_VALUES_SIZE)
247 
248 #define CM_PROVISIONING_BUNDLE_START (VM0_BASE_S + OTP_DMA_ICS_SIZE)
249 #define DM_PROVISIONING_BUNDLE_START VM1_BASE_S
250 
251 #if PROVISIONING_BUNDLE_CODE_SIZE + PROVISIONING_BUNDLE_VALUES_SIZE + OTP_DMA_ICS_SIZE > VM0_SIZE
252 #error Provisioning bundle is too large for slot
253 #endif
254 
255 #endif /* __REGION_DEFS_H__ */
256