1 /* 2 * Copyright (c) 2022 Esco Medical ApS 3 * Copyright (c) 2020 TDK Invensense 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 #ifndef ZEPHYR_DRIVERS_SENSOR_ICM42670_REG_H_ 9 #define ZEPHYR_DRIVERS_SENSOR_ICM42670_REG_H_ 10 11 #include <zephyr/sys/util.h> 12 13 /* Helper macros for addressing registers in MREG1-3, see datasheet section 13 */ 14 #define REG_MADDR_BASE 0x0028 15 #define REG_MREG1_SHIFT 8 16 #define REG_MREG2_SHIFT 9 17 #define REG_MREG3_SHIFT 10 18 #define REG_BANK0_OFFSET 0x0000 19 #define REG_MREG1_OFFSET (REG_MADDR_BASE << REG_MREG1_SHIFT) 20 #define REG_MREG2_OFFSET (REG_MADDR_BASE << REG_MREG2_SHIFT) 21 #define REG_MREG3_OFFSET (REG_MADDR_BASE << REG_MREG3_SHIFT) 22 #define REG_ADDRESS_MASK GENMASK(7, 0) 23 #define REG_BANK_MASK GENMASK(15, 8) 24 #define REG_SPI_READ_BIT BIT(7) 25 #define MREG_R_W_WAIT_US 20 /* 10us, but use 20us to be on the safe side */ 26 27 /* BANK 0 */ 28 #define REG_MCLK_RDY (REG_BANK0_OFFSET | 0x00) 29 #define REG_DEVICE_CONFIG (REG_BANK0_OFFSET | 0x01) 30 #define REG_SIGNAL_PATH_RESET (REG_BANK0_OFFSET | 0x02) 31 #define REG_DRIVE_CONFIG1 (REG_BANK0_OFFSET | 0x03) 32 #define REG_DRIVE_CONFIG2 (REG_BANK0_OFFSET | 0x04) 33 #define REG_DRIVE_CONFIG3 (REG_BANK0_OFFSET | 0x05) 34 #define REG_INT_CONFIG (REG_BANK0_OFFSET | 0x06) 35 #define REG_TEMP_DATA1 (REG_BANK0_OFFSET | 0x09) 36 #define REG_TEMP_DATA0 (REG_BANK0_OFFSET | 0x0a) 37 #define REG_ACCEL_DATA_X1 (REG_BANK0_OFFSET | 0x0b) 38 #define REG_ACCEL_DATA_X0 (REG_BANK0_OFFSET | 0x0c) 39 #define REG_ACCEL_DATA_Y1 (REG_BANK0_OFFSET | 0x0d) 40 #define REG_ACCEL_DATA_Y0 (REG_BANK0_OFFSET | 0x0e) 41 #define REG_ACCEL_DATA_Z1 (REG_BANK0_OFFSET | 0x0f) 42 #define REG_ACCEL_DATA_Z0 (REG_BANK0_OFFSET | 0x10) 43 #define REG_GYRO_DATA_X1 (REG_BANK0_OFFSET | 0x11) 44 #define REG_GYRO_DATA_X0 (REG_BANK0_OFFSET | 0x12) 45 #define REG_GYRO_DATA_Y1 (REG_BANK0_OFFSET | 0x13) 46 #define REG_GYRO_DATA_Y0 (REG_BANK0_OFFSET | 0x14) 47 #define REG_GYRO_DATA_Z1 (REG_BANK0_OFFSET | 0x15) 48 #define REG_GYRO_DATA_Z0 (REG_BANK0_OFFSET | 0x16) 49 #define REG_TMST_FSYNCH (REG_BANK0_OFFSET | 0x17) 50 #define REG_TMST_FSYNCL (REG_BANK0_OFFSET | 0x18) 51 #define REG_APEX_DATA4 (REG_BANK0_OFFSET | 0x1d) 52 #define REG_APEX_DATA5 (REG_BANK0_OFFSET | 0x1e) 53 #define REG_PWR_MGMT0 (REG_BANK0_OFFSET | 0x1f) 54 #define REG_GYRO_CONFIG0 (REG_BANK0_OFFSET | 0x20) 55 #define REG_ACCEL_CONFIG0 (REG_BANK0_OFFSET | 0x21) 56 #define REG_TEMP_CONFIG0 (REG_BANK0_OFFSET | 0x22) 57 #define REG_GYRO_CONFIG1 (REG_BANK0_OFFSET | 0x23) 58 #define REG_ACCEL_CONFIG1 (REG_BANK0_OFFSET | 0x24) 59 #define REG_APEX_CONFIG0 (REG_BANK0_OFFSET | 0x25) 60 #define REG_APEX_CONFIG1 (REG_BANK0_OFFSET | 0x26) 61 #define REG_WOM_CONFIG (REG_BANK0_OFFSET | 0x27) 62 #define REG_FIFO_CONFIG1 (REG_BANK0_OFFSET | 0x28) 63 #define REG_FIFO_CONFIG2 (REG_BANK0_OFFSET | 0x29) 64 #define REG_FIFO_CONFIG3 (REG_BANK0_OFFSET | 0x2a) 65 #define REG_INT_SOURCE0 (REG_BANK0_OFFSET | 0x2b) 66 #define REG_INT_SOURCE1 (REG_BANK0_OFFSET | 0x2c) 67 #define REG_INT_SOURCE3 (REG_BANK0_OFFSET | 0x2d) 68 #define REG_INT_SOURCE4 (REG_BANK0_OFFSET | 0x2e) 69 #define REG_FIFO_LOST_PKT0 (REG_BANK0_OFFSET | 0x2f) 70 #define REG_FIFO_LOST_PKT1 (REG_BANK0_OFFSET | 0x30) 71 #define REG_APEX_DATA0 (REG_BANK0_OFFSET | 0x31) 72 #define REG_APEX_DATA1 (REG_BANK0_OFFSET | 0x32) 73 #define REG_APEX_DATA2 (REG_BANK0_OFFSET | 0x33) 74 #define REG_APEX_DATA3 (REG_BANK0_OFFSET | 0x34) 75 #define REG_INTF_CONFIG0 (REG_BANK0_OFFSET | 0x35) 76 #define REG_INTF_CONFIG1 (REG_BANK0_OFFSET | 0x36) 77 #define REG_INT_STATUS_DRDY (REG_BANK0_OFFSET | 0x39) 78 #define REG_INT_STATUS (REG_BANK0_OFFSET | 0x3a) 79 #define REG_INT_STATUS2 (REG_BANK0_OFFSET | 0x3b) 80 #define REG_INT_STATUS3 (REG_BANK0_OFFSET | 0x3c) 81 #define REG_FIFO_COUNTH (REG_BANK0_OFFSET | 0x3d) 82 #define REG_FIFO_COUNTL (REG_BANK0_OFFSET | 0x3e) 83 #define REG_FIFO_DATA (REG_BANK0_OFFSET | 0x3f) 84 #define REG_WHO_AM_I (REG_BANK0_OFFSET | 0x75) 85 #define REG_BLK_SEL_W (REG_BANK0_OFFSET | 0x79) 86 #define REG_MADDR_W (REG_BANK0_OFFSET | 0x7a) 87 #define REG_M_W (REG_BANK0_OFFSET | 0x7b) 88 #define REG_BLK_SEL_R (REG_BANK0_OFFSET | 0x7c) 89 #define REG_MADDR_R (REG_BANK0_OFFSET | 0x7d) 90 #define REG_M_R (REG_BANK0_OFFSET | 0x7e) 91 92 /* MREG1 */ 93 #define REG_TMST_CONFIG1 (REG_MREG1_OFFSET | 0x00) 94 #define REG_FIFO_CONFIG5 (REG_MREG1_OFFSET | 0x01) 95 #define REG_FIFO_CONFIG6 (REG_MREG1_OFFSET | 0x02) 96 #define REG_FSYNC_CONFIG (REG_MREG1_OFFSET | 0x03) 97 #define REG_INT_CONFIG0 (REG_MREG1_OFFSET | 0x04) 98 #define REG_INT_CONFIG1 (REG_MREG1_OFFSET | 0x05) 99 #define REG_SENSOR_CONFIG3 (REG_MREG1_OFFSET | 0x06) 100 #define REG_ST_CONFIG (REG_MREG1_OFFSET | 0x13) 101 #define REG_SELFTEST (REG_MREG1_OFFSET | 0x14) 102 #define REG_INTF_CONFIG6 (REG_MREG1_OFFSET | 0x23) 103 #define REG_INTF_CONFIG10 (REG_MREG1_OFFSET | 0x25) 104 #define REG_INTF_CONFIG7 (REG_MREG1_OFFSET | 0x28) 105 #define REG_OTP_CONFIG (REG_MREG1_OFFSET | 0x2b) 106 #define REG_INT_SOURCE6 (REG_MREG1_OFFSET | 0x2f) 107 #define REG_INT_SOURCE7 (REG_MREG1_OFFSET | 0x30) 108 #define REG_INT_SOURCE8 (REG_MREG1_OFFSET | 0x31) 109 #define REG_INT_SOURCE9 (REG_MREG1_OFFSET | 0x32) 110 #define REG_INT_SOURCE10 (REG_MREG1_OFFSET | 0x33) 111 #define REG_APEX_CONFIG2 (REG_MREG1_OFFSET | 0x44) 112 #define REG_APEX_CONFIG3 (REG_MREG1_OFFSET | 0x45) 113 #define REG_APEX_CONFIG4 (REG_MREG1_OFFSET | 0x46) 114 #define REG_APEX_CONFIG5 (REG_MREG1_OFFSET | 0x47) 115 #define REG_APEX_CONFIG9 (REG_MREG1_OFFSET | 0x48) 116 #define REG_APEX_CONFIG10 (REG_MREG1_OFFSET | 0x49) 117 #define REG_APEX_CONFIG11 (REG_MREG1_OFFSET | 0x4a) 118 #define REG_ACCEL_WOM_X_THR (REG_MREG1_OFFSET | 0x4b) 119 #define REG_ACCEL_WOM_Y_THR (REG_MREG1_OFFSET | 0x4c) 120 #define REG_ACCEL_WOM_Z_THR (REG_MREG1_OFFSET | 0x4d) 121 #define REG_OFFSET_USER0 (REG_MREG1_OFFSET | 0x4e) 122 #define REG_OFFSET_USER1 (REG_MREG1_OFFSET | 0x4f) 123 #define REG_OFFSET_USER2 (REG_MREG1_OFFSET | 0x50) 124 #define REG_OFFSET_USER3 (REG_MREG1_OFFSET | 0x51) 125 #define REG_OFFSET_USER4 (REG_MREG1_OFFSET | 0x52) 126 #define REG_OFFSET_USER5 (REG_MREG1_OFFSET | 0x53) 127 #define REG_OFFSET_USER6 (REG_MREG1_OFFSET | 0x54) 128 #define REG_OFFSET_USER7 (REG_MREG1_OFFSET | 0x55) 129 #define REG_OFFSET_USER8 (REG_MREG1_OFFSET | 0x56) 130 #define REG_ST_STATUS1 (REG_MREG1_OFFSET | 0x63) 131 #define REG_ST_STATUS2 (REG_MREG1_OFFSET | 0x64) 132 #define REG_FDR_CONFIG (REG_MREG1_OFFSET | 0x66) 133 #define REG_APEX_CONFIG12 (REG_MREG1_OFFSET | 0x67) 134 135 /* MREG2 */ 136 #define REG_OTP_CTRL7 (REG_MREG2_OFFSET | 0x06) 137 138 /* MREG3 */ 139 #define REG_XA_ST_DATA3 (REG_MREG3_OFFSET | 0x00) 140 #define REG_YA_ST_DATA3 (REG_MREG3_OFFSET | 0x01) 141 #define REG_ZA_ST_DATA3 (REG_MREG3_OFFSET | 0x02) 142 #define REG_XG_ST_DATA3 (REG_MREG3_OFFSET | 0x03) 143 #define REG_YG_ST_DATA3 (REG_MREG3_OFFSET | 0x04) 144 #define REG_ZG_ST_DATA3 (REG_MREG3_OFFSET | 0x05) 145 146 /* Bank0 REG_MCLK_RDY */ 147 #define BIT_MCLK_RDY BIT(3) 148 149 /* Bank0 REG_DEVICE_CONFIG */ 150 #define BIT_SPI_AP_4WIRE BIT(2) 151 #define BIT_SPI_MODE BIT(0) 152 153 /* Bank0 REG_SIGNAL_PATH_RESET */ 154 #define BIT_FIFO_FLUSH BIT(2) 155 #define BIT_SOFT_RESET BIT(4) 156 157 /* Bank0 REG_INST_STATUS */ 158 #define BIT_STATUS_RESET_DONE_INT BIT(4) 159 160 /* Bank0 REG_INT_CONFIG */ 161 #define BIT_INT1_POLARITY BIT(0) 162 #define BIT_INT1_DRIVE_CIRCUIT BIT(1) 163 #define BIT_INT1_MODE BIT(2) 164 #define BIT_INT2_POLARITY BIT(3) 165 #define BIT_INT2_DRIVE_CIRCUIT BIT(4) 166 #define BIT_INT2_MODE BIT(5) 167 168 /* Bank0 REG_PWR_MGMT_0 */ 169 #define MASK_ACCEL_MODE GENMASK(1, 0) 170 #define BIT_ACCEL_MODE_OFF 0x00 171 #define BIT_ACCEL_MODE_LPM 0x02 172 #define BIT_ACCEL_MODE_LNM 0x03 173 #define MASK_GYRO_MODE GENMASK(3, 2) 174 #define BIT_GYRO_MODE_OFF 0x00 175 #define BIT_GYRO_MODE_STBY 0x01 176 #define BIT_GYRO_MODE_LNM 0x03 177 #define BIT_IDLE BIT(4) 178 #define BIT_ACCEL_LP_CLK_SEL BIT(7) 179 180 /* Bank0 REG_INT_SOURCE0 */ 181 #define BIT_INT_AGC_RDY_INT1_EN BIT(0) 182 #define BIT_INT_FIFO_FULL_INT1_EN BIT(1) 183 #define BIT_INT_FIFO_THS_INT1_EN BIT(2) 184 #define BIT_INT_DRDY_INT1_EN BIT(3) 185 #define BIT_INT_RESET_DONE_INT1_EN BIT(4) 186 #define BIT_INT_PLL_RDY_INT1_EN BIT(5) 187 #define BIT_INT_FSYNC_INT1_EN BIT(6) 188 #define BIT_INT_ST_INT1_EN BIT(7) 189 190 /* Bank0 REG_INT_STATUS_DRDY */ 191 #define BIT_INT_STATUS_DATA_DRDY BIT(0) 192 193 /* Bank9 REG_INTF_CONFIG1 */ 194 #define BIT_I3C_SDR_EN BIT(3) 195 #define BIT_I3C_DDR_EN BIT(2) 196 #define MASK_CLKSEL GENMASK(1, 0) 197 #define BIT_CLKSEL_INT_RC 0x00 198 #define BIT_CLKSEL_PLL_OR_RC 0x01 199 #define BIT_CLKSEL_DISABLE 0x11 200 201 /* Bank0 REG_INT_STATUS */ 202 #define BIT_INT_STATUS_AGC_RDY BIT(0) 203 #define BIT_INT_STATUS_FIFO_FULL BIT(1) 204 #define BIT_INT_STATUS_FIFO_THS BIT(2) 205 #define BIT_INT_STATUS_RESET_DONE BIT(4) 206 #define BIT_INT_STATUS_PLL_RDY BIT(5) 207 #define BIT_INT_STATUS_FSYNC BIT(6) 208 #define BIT_INT_STATUS_ST BIT(7) 209 210 /* Bank0 REG_INT_STATUS2 */ 211 #define BIT_INT_STATUS_WOM_Z BIT(0) 212 #define BIT_INT_STATUS_WOM_Y BIT(1) 213 #define BIT_INT_STATUS_WOM_X BIT(2) 214 #define BIT_INT_STATUS_SMD BIT(3) 215 216 /* Bank0 REG_INT_STATUS3 */ 217 #define BIT_INT_STATUS_LOWG_DET BIT(1) 218 #define BIT_INT_STATUS_FF_DET BIT(2) 219 #define BIT_INT_STATUS_TILT_DET BIT(3) 220 #define BIT_INT_STATUS_STEP_CNT_OVFL BIT(4) 221 #define BIT_INT_STATUS_STEP_DET BIT(5) 222 223 /* Bank0 REG_ACCEL_CONFIG0 */ 224 #define MASK_ACCEL_UI_FS_SEL GENMASK(6, 5) 225 #define BIT_ACCEL_UI_FS_16 0x00 226 #define BIT_ACCEL_UI_FS_8 0x01 227 #define BIT_ACCEL_UI_FS_4 0x02 228 #define BIT_ACCEL_UI_FS_2 0x03 229 #define MASK_ACCEL_ODR GENMASK(3, 0) 230 #define BIT_ACCEL_ODR_1600 0x05 231 #define BIT_ACCEL_ODR_800 0x06 232 #define BIT_ACCEL_ODR_400 0x07 233 #define BIT_ACCEL_ODR_200 0x08 234 #define BIT_ACCEL_ODR_100 0x09 235 #define BIT_ACCEL_ODR_50 0x0A 236 #define BIT_ACCEL_ODR_25 0x0B 237 #define BIT_ACCEL_ODR_12 0x0C 238 #define BIT_ACCEL_ODR_6 0x0D 239 #define BIT_ACCEL_ODR_3 0x0E 240 #define BIT_ACCEL_ODR_1 0x0F 241 242 /* Bank0 REG_GYRO_CONFIG0 */ 243 #define MASK_GYRO_UI_FS_SEL GENMASK(6, 5) 244 #define BIT_GYRO_UI_FS_2000 0x00 245 #define BIT_GYRO_UI_FS_1000 0x01 246 #define BIT_GYRO_UI_FS_500 0x02 247 #define BIT_GYRO_UI_FS_250 0x03 248 #define MASK_GYRO_ODR GENMASK(3, 0) 249 #define BIT_GYRO_ODR_1600 0x05 250 #define BIT_GYRO_ODR_800 0x06 251 #define BIT_GYRO_ODR_400 0x07 252 #define BIT_GYRO_ODR_200 0x08 253 #define BIT_GYRO_ODR_100 0x09 254 #define BIT_GYRO_ODR_50 0x0A 255 #define BIT_GYRO_ODR_25 0x0B 256 #define BIT_GYRO_ODR_12 0x0C 257 258 /* misc. defines */ 259 #define WHO_AM_I_ICM42670 0x67 260 #define MIN_ACCEL_SENS_SHIFT 11 261 #define ACCEL_DATA_SIZE 6 262 #define GYRO_DATA_SIZE 6 263 #define TEMP_DATA_SIZE 2 264 #define MCLK_POLL_INTERVAL_US 250 265 #define MCLK_POLL_ATTEMPTS 100 266 #define SOFT_RESET_TIME_MS 2 /* 1ms + elbow room */ 267 268 #endif /* ZEPHYR_DRIVERS_SENSOR_ICM42670_REG_H_ */ 269
