1 /***************************************************************************//** 2 * \file cyip_flashc.h 3 * 4 * \brief 5 * FLASHC IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_FLASHC_H_ 28 #define _CYIP_FLASHC_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * FLASHC 34 *******************************************************************************/ 35 36 #define FLASHC_FM_CTL_SECTION_SIZE 0x00001000UL 37 #define FLASHC_SECTION_SIZE 0x00010000UL 38 39 /** 40 * \brief Flash Macro Registers (FLASHC_FM_CTL) 41 */ 42 typedef struct { 43 __IOM uint32_t FM_CTL; /*!< 0x00000000 Flash macro control */ 44 __IM uint32_t STATUS; /*!< 0x00000004 Status */ 45 __IOM uint32_t FM_ADDR; /*!< 0x00000008 Flash macro address */ 46 __IM uint32_t GEOMETRY; /*!< 0x0000000C Regular flash geometry */ 47 __IM uint32_t GEOMETRY_SUPERVISORY; /*!< 0x00000010 Supervisory flash geometry */ 48 __IOM uint32_t TIMER_CTL; /*!< 0x00000014 Timer control */ 49 __IOM uint32_t ANA_CTL0; /*!< 0x00000018 Analog control 0 */ 50 __IOM uint32_t ANA_CTL1; /*!< 0x0000001C Analog control 1 */ 51 __IM uint32_t GEOMETRY_GEN; /*!< 0x00000020 N/A, DNU */ 52 __IOM uint32_t TEST_CTL; /*!< 0x00000024 Test mode control */ 53 __IOM uint32_t WAIT_CTL; /*!< 0x00000028 Wiat State control */ 54 __IM uint32_t MONITOR_STATUS; /*!< 0x0000002C Monitor Status */ 55 __IOM uint32_t SCRATCH_CTL; /*!< 0x00000030 Scratch Control */ 56 __IOM uint32_t HV_CTL; /*!< 0x00000034 High voltage control */ 57 __OM uint32_t ACLK_CTL; /*!< 0x00000038 Aclk control */ 58 __IOM uint32_t INTR; /*!< 0x0000003C Interrupt */ 59 __IOM uint32_t INTR_SET; /*!< 0x00000040 Interrupt set */ 60 __IOM uint32_t INTR_MASK; /*!< 0x00000044 Interrupt mask */ 61 __IM uint32_t INTR_MASKED; /*!< 0x00000048 Interrupt masked */ 62 __OM uint32_t FM_HV_DATA_ALL; /*!< 0x0000004C Flash macro high Voltage page latches data (for all page 63 latches) */ 64 __IOM uint32_t CAL_CTL0; /*!< 0x00000050 Cal control BG LO trim bits */ 65 __IOM uint32_t CAL_CTL1; /*!< 0x00000054 Cal control BG HI trim bits */ 66 __IOM uint32_t CAL_CTL2; /*!< 0x00000058 Cal control BG LO&HI ipref trim, ref sel, fm_active, turbo_ext */ 67 __IOM uint32_t CAL_CTL3; /*!< 0x0000005C Cal control osc trim bits, idac, sdac, itim, bdac. */ 68 __OM uint32_t BOOKMARK; /*!< 0x00000060 Bookmark register - keeps the current FW HV seq */ 69 __IM uint32_t RESERVED[7]; 70 __IOM uint32_t RED_CTL01; /*!< 0x00000080 Redundancy Control normal sectors 0,1 */ 71 __IOM uint32_t RED_CTL23; /*!< 0x00000084 Redundancy Controll normal sectors 2,3 */ 72 __IOM uint32_t RED_CTL45; /*!< 0x00000088 Redundancy Controll normal sectors 4,5 */ 73 __IOM uint32_t RED_CTL67; /*!< 0x0000008C Redundancy Controll normal sectors 6,7 */ 74 __IOM uint32_t RED_CTL_SM01; /*!< 0x00000090 Redundancy Controll special sectors 0,1 */ 75 __IM uint32_t RESERVED1[27]; 76 __IM uint32_t TM_CMPR[32]; /*!< 0x00000100 Do Not Use */ 77 __IM uint32_t RESERVED2[416]; 78 __IOM uint32_t FM_HV_DATA[256]; /*!< 0x00000800 Flash macro high Voltage page latches data */ 79 __IM uint32_t FM_MEM_DATA[256]; /*!< 0x00000C00 Flash macro memory sense amplifier and column decoder data */ 80 } FLASHC_FM_CTL_V1_Type; /*!< Size = 4096 (0x1000) */ 81 82 /** 83 * \brief Flash controller (FLASHC) 84 */ 85 typedef struct { 86 __IOM uint32_t FLASH_CTL; /*!< 0x00000000 Control */ 87 __IOM uint32_t FLASH_PWR_CTL; /*!< 0x00000004 Flash power control */ 88 __IOM uint32_t FLASH_CMD; /*!< 0x00000008 Command */ 89 __IM uint32_t RESERVED[61]; 90 __IOM uint32_t BIST_CTL; /*!< 0x00000100 BIST control */ 91 __IOM uint32_t BIST_CMD; /*!< 0x00000104 BIST command */ 92 __IOM uint32_t BIST_ADDR_START; /*!< 0x00000108 BIST address start register */ 93 __IOM uint32_t BIST_DATA[8]; /*!< 0x0000010C BIST data register(s) */ 94 __IM uint32_t BIST_DATA_ACT[8]; /*!< 0x0000012C BIST data actual register(s) */ 95 __IM uint32_t BIST_DATA_EXP[8]; /*!< 0x0000014C BIST data expected register(s) */ 96 __IM uint32_t BIST_ADDR; /*!< 0x0000016C BIST address register */ 97 __IOM uint32_t BIST_STATUS; /*!< 0x00000170 BIST status register */ 98 __IM uint32_t RESERVED1[163]; 99 __IOM uint32_t CM0_CA_CTL0; /*!< 0x00000400 CM0+ cache control */ 100 __IOM uint32_t CM0_CA_CTL1; /*!< 0x00000404 CM0+ cache control */ 101 __IOM uint32_t CM0_CA_CTL2; /*!< 0x00000408 CM0+ cache control */ 102 __IOM uint32_t CM0_CA_CMD; /*!< 0x0000040C CM0+ cache command */ 103 __IM uint32_t RESERVED2[12]; 104 __IM uint32_t CM0_CA_STATUS0; /*!< 0x00000440 CM0+ cache status 0 */ 105 __IM uint32_t CM0_CA_STATUS1; /*!< 0x00000444 CM0+ cache status 1 */ 106 __IM uint32_t CM0_CA_STATUS2; /*!< 0x00000448 CM0+ cache status 2 */ 107 __IM uint32_t RESERVED3[13]; 108 __IOM uint32_t CM4_CA_CTL0; /*!< 0x00000480 CM4 cache control */ 109 __IOM uint32_t CM4_CA_CTL1; /*!< 0x00000484 CM4 cache control */ 110 __IOM uint32_t CM4_CA_CTL2; /*!< 0x00000488 CM4 cache control */ 111 __IOM uint32_t CM4_CA_CMD; /*!< 0x0000048C CM4 cache command */ 112 __IM uint32_t RESERVED4[12]; 113 __IM uint32_t CM4_CA_STATUS0; /*!< 0x000004C0 CM4 cache status 0 */ 114 __IM uint32_t CM4_CA_STATUS1; /*!< 0x000004C4 CM4 cache status 1 */ 115 __IM uint32_t CM4_CA_STATUS2; /*!< 0x000004C8 CM4 cache status 2 */ 116 __IM uint32_t RESERVED5[13]; 117 __IOM uint32_t CRYPTO_BUFF_CTL; /*!< 0x00000500 Cryptography buffer control */ 118 __IM uint32_t RESERVED6; 119 __IOM uint32_t CRYPTO_BUFF_CMD; /*!< 0x00000508 Cryptography buffer command */ 120 __IM uint32_t RESERVED7[29]; 121 __IOM uint32_t DW0_BUFF_CTL; /*!< 0x00000580 Datawire 0 buffer control */ 122 __IM uint32_t RESERVED8; 123 __IOM uint32_t DW0_BUFF_CMD; /*!< 0x00000588 Datawire 0 buffer command */ 124 __IM uint32_t RESERVED9[29]; 125 __IOM uint32_t DW1_BUFF_CTL; /*!< 0x00000600 Datawire 1 buffer control */ 126 __IM uint32_t RESERVED10; 127 __IOM uint32_t DW1_BUFF_CMD; /*!< 0x00000608 Datawire 1 buffer command */ 128 __IM uint32_t RESERVED11[29]; 129 __IOM uint32_t DAP_BUFF_CTL; /*!< 0x00000680 Debug access port buffer control */ 130 __IM uint32_t RESERVED12; 131 __IOM uint32_t DAP_BUFF_CMD; /*!< 0x00000688 Debug access port buffer command */ 132 __IM uint32_t RESERVED13[29]; 133 __IOM uint32_t EXT_MS0_BUFF_CTL; /*!< 0x00000700 External master 0 buffer control */ 134 __IM uint32_t RESERVED14; 135 __IOM uint32_t EXT_MS0_BUFF_CMD; /*!< 0x00000708 External master 0 buffer command */ 136 __IM uint32_t RESERVED15[29]; 137 __IOM uint32_t EXT_MS1_BUFF_CTL; /*!< 0x00000780 External master 1 buffer control */ 138 __IM uint32_t RESERVED16; 139 __IOM uint32_t EXT_MS1_BUFF_CMD; /*!< 0x00000788 External master 1 buffer command */ 140 __IM uint32_t RESERVED17[14877]; 141 FLASHC_FM_CTL_V1_Type FM_CTL; /*!< 0x0000F000 Flash Macro Registers */ 142 } FLASHC_V1_Type; /*!< Size = 65536 (0x10000) */ 143 144 145 /* FLASHC_FM_CTL.FM_CTL */ 146 #define FLASHC_FM_CTL_FM_CTL_FM_MODE_Pos 0UL 147 #define FLASHC_FM_CTL_FM_CTL_FM_MODE_Msk 0xFUL 148 #define FLASHC_FM_CTL_FM_CTL_FM_SEQ_Pos 8UL 149 #define FLASHC_FM_CTL_FM_CTL_FM_SEQ_Msk 0x300UL 150 #define FLASHC_FM_CTL_FM_CTL_DAA_MUX_SEL_Pos 16UL 151 #define FLASHC_FM_CTL_FM_CTL_DAA_MUX_SEL_Msk 0x7F0000UL 152 #define FLASHC_FM_CTL_FM_CTL_IF_SEL_Pos 24UL 153 #define FLASHC_FM_CTL_FM_CTL_IF_SEL_Msk 0x1000000UL 154 #define FLASHC_FM_CTL_FM_CTL_WR_EN_Pos 25UL 155 #define FLASHC_FM_CTL_FM_CTL_WR_EN_Msk 0x2000000UL 156 /* FLASHC_FM_CTL.STATUS */ 157 #define FLASHC_FM_CTL_STATUS_HV_TIMER_RUNNING_Pos 0UL 158 #define FLASHC_FM_CTL_STATUS_HV_TIMER_RUNNING_Msk 0x1UL 159 #define FLASHC_FM_CTL_STATUS_HV_REGS_ISOLATED_Pos 1UL 160 #define FLASHC_FM_CTL_STATUS_HV_REGS_ISOLATED_Msk 0x2UL 161 #define FLASHC_FM_CTL_STATUS_ILLEGAL_HVOP_Pos 2UL 162 #define FLASHC_FM_CTL_STATUS_ILLEGAL_HVOP_Msk 0x4UL 163 #define FLASHC_FM_CTL_STATUS_TURBO_N_Pos 3UL 164 #define FLASHC_FM_CTL_STATUS_TURBO_N_Msk 0x8UL 165 #define FLASHC_FM_CTL_STATUS_WR_EN_MON_Pos 4UL 166 #define FLASHC_FM_CTL_STATUS_WR_EN_MON_Msk 0x10UL 167 #define FLASHC_FM_CTL_STATUS_IF_SEL_MON_Pos 5UL 168 #define FLASHC_FM_CTL_STATUS_IF_SEL_MON_Msk 0x20UL 169 /* FLASHC_FM_CTL.FM_ADDR */ 170 #define FLASHC_FM_CTL_FM_ADDR_RA_Pos 0UL 171 #define FLASHC_FM_CTL_FM_ADDR_RA_Msk 0xFFFFUL 172 #define FLASHC_FM_CTL_FM_ADDR_BA_Pos 16UL 173 #define FLASHC_FM_CTL_FM_ADDR_BA_Msk 0xFF0000UL 174 #define FLASHC_FM_CTL_FM_ADDR_AXA_Pos 24UL 175 #define FLASHC_FM_CTL_FM_ADDR_AXA_Msk 0x1000000UL 176 /* FLASHC_FM_CTL.GEOMETRY */ 177 #define FLASHC_FM_CTL_GEOMETRY_WORD_SIZE_LOG2_Pos 0UL 178 #define FLASHC_FM_CTL_GEOMETRY_WORD_SIZE_LOG2_Msk 0xFUL 179 #define FLASHC_FM_CTL_GEOMETRY_PAGE_SIZE_LOG2_Pos 4UL 180 #define FLASHC_FM_CTL_GEOMETRY_PAGE_SIZE_LOG2_Msk 0xF0UL 181 #define FLASHC_FM_CTL_GEOMETRY_ROW_COUNT_Pos 8UL 182 #define FLASHC_FM_CTL_GEOMETRY_ROW_COUNT_Msk 0xFFFF00UL 183 #define FLASHC_FM_CTL_GEOMETRY_BANK_COUNT_Pos 24UL 184 #define FLASHC_FM_CTL_GEOMETRY_BANK_COUNT_Msk 0xFF000000UL 185 /* FLASHC_FM_CTL.GEOMETRY_SUPERVISORY */ 186 #define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_WORD_SIZE_LOG2_Pos 0UL 187 #define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_WORD_SIZE_LOG2_Msk 0xFUL 188 #define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_PAGE_SIZE_LOG2_Pos 4UL 189 #define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_PAGE_SIZE_LOG2_Msk 0xF0UL 190 #define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_ROW_COUNT_Pos 8UL 191 #define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_ROW_COUNT_Msk 0xFFFF00UL 192 #define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_BANK_COUNT_Pos 24UL 193 #define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_BANK_COUNT_Msk 0xFF000000UL 194 /* FLASHC_FM_CTL.TIMER_CTL */ 195 #define FLASHC_FM_CTL_TIMER_CTL_PERIOD_Pos 0UL 196 #define FLASHC_FM_CTL_TIMER_CTL_PERIOD_Msk 0xFFFFUL 197 #define FLASHC_FM_CTL_TIMER_CTL_SCALE_Pos 16UL 198 #define FLASHC_FM_CTL_TIMER_CTL_SCALE_Msk 0x10000UL 199 #define FLASHC_FM_CTL_TIMER_CTL_PUMP_CLOCK_SEL_Pos 24UL 200 #define FLASHC_FM_CTL_TIMER_CTL_PUMP_CLOCK_SEL_Msk 0x1000000UL 201 #define FLASHC_FM_CTL_TIMER_CTL_PRE_PROG_Pos 25UL 202 #define FLASHC_FM_CTL_TIMER_CTL_PRE_PROG_Msk 0x2000000UL 203 #define FLASHC_FM_CTL_TIMER_CTL_PRE_PROG_CSL_Pos 26UL 204 #define FLASHC_FM_CTL_TIMER_CTL_PRE_PROG_CSL_Msk 0x4000000UL 205 #define FLASHC_FM_CTL_TIMER_CTL_PUMP_EN_Pos 29UL 206 #define FLASHC_FM_CTL_TIMER_CTL_PUMP_EN_Msk 0x20000000UL 207 #define FLASHC_FM_CTL_TIMER_CTL_ACLK_EN_Pos 30UL 208 #define FLASHC_FM_CTL_TIMER_CTL_ACLK_EN_Msk 0x40000000UL 209 #define FLASHC_FM_CTL_TIMER_CTL_TIMER_EN_Pos 31UL 210 #define FLASHC_FM_CTL_TIMER_CTL_TIMER_EN_Msk 0x80000000UL 211 /* FLASHC_FM_CTL.ANA_CTL0 */ 212 #define FLASHC_FM_CTL_ANA_CTL0_CSLDAC_Pos 8UL 213 #define FLASHC_FM_CTL_ANA_CTL0_CSLDAC_Msk 0x700UL 214 #define FLASHC_FM_CTL_ANA_CTL0_VCC_SEL_Pos 24UL 215 #define FLASHC_FM_CTL_ANA_CTL0_VCC_SEL_Msk 0x1000000UL 216 #define FLASHC_FM_CTL_ANA_CTL0_FLIP_AMUXBUS_AB_Pos 27UL 217 #define FLASHC_FM_CTL_ANA_CTL0_FLIP_AMUXBUS_AB_Msk 0x8000000UL 218 /* FLASHC_FM_CTL.ANA_CTL1 */ 219 #define FLASHC_FM_CTL_ANA_CTL1_MDAC_Pos 0UL 220 #define FLASHC_FM_CTL_ANA_CTL1_MDAC_Msk 0xFFUL 221 #define FLASHC_FM_CTL_ANA_CTL1_PDAC_Pos 16UL 222 #define FLASHC_FM_CTL_ANA_CTL1_PDAC_Msk 0xF0000UL 223 #define FLASHC_FM_CTL_ANA_CTL1_NDAC_Pos 24UL 224 #define FLASHC_FM_CTL_ANA_CTL1_NDAC_Msk 0xF000000UL 225 #define FLASHC_FM_CTL_ANA_CTL1_VPROT_OVERRIDE_Pos 28UL 226 #define FLASHC_FM_CTL_ANA_CTL1_VPROT_OVERRIDE_Msk 0x10000000UL 227 #define FLASHC_FM_CTL_ANA_CTL1_R_GRANT_CTL_Pos 29UL 228 #define FLASHC_FM_CTL_ANA_CTL1_R_GRANT_CTL_Msk 0x20000000UL 229 #define FLASHC_FM_CTL_ANA_CTL1_RST_SFT_HVPL_Pos 30UL 230 #define FLASHC_FM_CTL_ANA_CTL1_RST_SFT_HVPL_Msk 0x40000000UL 231 /* FLASHC_FM_CTL.GEOMETRY_GEN */ 232 #define FLASHC_FM_CTL_GEOMETRY_GEN_DNU_0X20_1_Pos 1UL 233 #define FLASHC_FM_CTL_GEOMETRY_GEN_DNU_0X20_1_Msk 0x2UL 234 #define FLASHC_FM_CTL_GEOMETRY_GEN_DNU_0X20_2_Pos 2UL 235 #define FLASHC_FM_CTL_GEOMETRY_GEN_DNU_0X20_2_Msk 0x4UL 236 #define FLASHC_FM_CTL_GEOMETRY_GEN_DNU_0X20_3_Pos 3UL 237 #define FLASHC_FM_CTL_GEOMETRY_GEN_DNU_0X20_3_Msk 0x8UL 238 /* FLASHC_FM_CTL.TEST_CTL */ 239 #define FLASHC_FM_CTL_TEST_CTL_TEST_MODE_Pos 0UL 240 #define FLASHC_FM_CTL_TEST_CTL_TEST_MODE_Msk 0x1FUL 241 #define FLASHC_FM_CTL_TEST_CTL_PN_CTL_Pos 8UL 242 #define FLASHC_FM_CTL_TEST_CTL_PN_CTL_Msk 0x100UL 243 #define FLASHC_FM_CTL_TEST_CTL_TM_PE_Pos 9UL 244 #define FLASHC_FM_CTL_TEST_CTL_TM_PE_Msk 0x200UL 245 #define FLASHC_FM_CTL_TEST_CTL_TM_DISPOS_Pos 10UL 246 #define FLASHC_FM_CTL_TEST_CTL_TM_DISPOS_Msk 0x400UL 247 #define FLASHC_FM_CTL_TEST_CTL_TM_DISNEG_Pos 11UL 248 #define FLASHC_FM_CTL_TEST_CTL_TM_DISNEG_Msk 0x800UL 249 #define FLASHC_FM_CTL_TEST_CTL_EN_CLK_MON_Pos 16UL 250 #define FLASHC_FM_CTL_TEST_CTL_EN_CLK_MON_Msk 0x10000UL 251 #define FLASHC_FM_CTL_TEST_CTL_CSL_DEBUG_Pos 17UL 252 #define FLASHC_FM_CTL_TEST_CTL_CSL_DEBUG_Msk 0x20000UL 253 #define FLASHC_FM_CTL_TEST_CTL_ENABLE_OSC_Pos 18UL 254 #define FLASHC_FM_CTL_TEST_CTL_ENABLE_OSC_Msk 0x40000UL 255 #define FLASHC_FM_CTL_TEST_CTL_UNSCRAMBLE_WA_Pos 31UL 256 #define FLASHC_FM_CTL_TEST_CTL_UNSCRAMBLE_WA_Msk 0x80000000UL 257 /* FLASHC_FM_CTL.WAIT_CTL */ 258 #define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_MEM_RD_Pos 0UL 259 #define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_MEM_RD_Msk 0xFUL 260 #define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_HV_RD_Pos 8UL 261 #define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_HV_RD_Msk 0xF00UL 262 #define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_HV_WR_Pos 16UL 263 #define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_HV_WR_Msk 0x70000UL 264 /* FLASHC_FM_CTL.MONITOR_STATUS */ 265 #define FLASHC_FM_CTL_MONITOR_STATUS_POS_PUMP_VLO_Pos 1UL 266 #define FLASHC_FM_CTL_MONITOR_STATUS_POS_PUMP_VLO_Msk 0x2UL 267 #define FLASHC_FM_CTL_MONITOR_STATUS_NEG_PUMP_VHI_Pos 2UL 268 #define FLASHC_FM_CTL_MONITOR_STATUS_NEG_PUMP_VHI_Msk 0x4UL 269 /* FLASHC_FM_CTL.SCRATCH_CTL */ 270 #define FLASHC_FM_CTL_SCRATCH_CTL_DUMMY32_Pos 0UL 271 #define FLASHC_FM_CTL_SCRATCH_CTL_DUMMY32_Msk 0xFFFFFFFFUL 272 /* FLASHC_FM_CTL.HV_CTL */ 273 #define FLASHC_FM_CTL_HV_CTL_TIMER_CLOCK_FREQ_Pos 0UL 274 #define FLASHC_FM_CTL_HV_CTL_TIMER_CLOCK_FREQ_Msk 0xFFUL 275 /* FLASHC_FM_CTL.ACLK_CTL */ 276 #define FLASHC_FM_CTL_ACLK_CTL_ACLK_GEN_Pos 0UL 277 #define FLASHC_FM_CTL_ACLK_CTL_ACLK_GEN_Msk 0x1UL 278 /* FLASHC_FM_CTL.INTR */ 279 #define FLASHC_FM_CTL_INTR_TIMER_EXPIRED_Pos 0UL 280 #define FLASHC_FM_CTL_INTR_TIMER_EXPIRED_Msk 0x1UL 281 /* FLASHC_FM_CTL.INTR_SET */ 282 #define FLASHC_FM_CTL_INTR_SET_TIMER_EXPIRED_Pos 0UL 283 #define FLASHC_FM_CTL_INTR_SET_TIMER_EXPIRED_Msk 0x1UL 284 /* FLASHC_FM_CTL.INTR_MASK */ 285 #define FLASHC_FM_CTL_INTR_MASK_TIMER_EXPIRED_Pos 0UL 286 #define FLASHC_FM_CTL_INTR_MASK_TIMER_EXPIRED_Msk 0x1UL 287 /* FLASHC_FM_CTL.INTR_MASKED */ 288 #define FLASHC_FM_CTL_INTR_MASKED_TIMER_EXPIRED_Pos 0UL 289 #define FLASHC_FM_CTL_INTR_MASKED_TIMER_EXPIRED_Msk 0x1UL 290 /* FLASHC_FM_CTL.FM_HV_DATA_ALL */ 291 #define FLASHC_FM_CTL_FM_HV_DATA_ALL_DATA32_Pos 0UL 292 #define FLASHC_FM_CTL_FM_HV_DATA_ALL_DATA32_Msk 0xFFFFFFFFUL 293 /* FLASHC_FM_CTL.CAL_CTL0 */ 294 #define FLASHC_FM_CTL_CAL_CTL0_VCT_TRIM_LO_HV_Pos 0UL 295 #define FLASHC_FM_CTL_CAL_CTL0_VCT_TRIM_LO_HV_Msk 0x1FUL 296 #define FLASHC_FM_CTL_CAL_CTL0_CDAC_LO_HV_Pos 5UL 297 #define FLASHC_FM_CTL_CAL_CTL0_CDAC_LO_HV_Msk 0xE0UL 298 #define FLASHC_FM_CTL_CAL_CTL0_VBG_TRIM_LO_HV_Pos 8UL 299 #define FLASHC_FM_CTL_CAL_CTL0_VBG_TRIM_LO_HV_Msk 0x1F00UL 300 #define FLASHC_FM_CTL_CAL_CTL0_VBG_TC_TRIM_LO_HV_Pos 13UL 301 #define FLASHC_FM_CTL_CAL_CTL0_VBG_TC_TRIM_LO_HV_Msk 0xE000UL 302 #define FLASHC_FM_CTL_CAL_CTL0_IPREF_TRIM_LO_HV_Pos 16UL 303 #define FLASHC_FM_CTL_CAL_CTL0_IPREF_TRIM_LO_HV_Msk 0xF0000UL 304 /* FLASHC_FM_CTL.CAL_CTL1 */ 305 #define FLASHC_FM_CTL_CAL_CTL1_VCT_TRIM_HI_HV_Pos 0UL 306 #define FLASHC_FM_CTL_CAL_CTL1_VCT_TRIM_HI_HV_Msk 0x1FUL 307 #define FLASHC_FM_CTL_CAL_CTL1_CDAC_HI_HV_Pos 5UL 308 #define FLASHC_FM_CTL_CAL_CTL1_CDAC_HI_HV_Msk 0xE0UL 309 #define FLASHC_FM_CTL_CAL_CTL1_VBG_TRIM_HI_HV_Pos 8UL 310 #define FLASHC_FM_CTL_CAL_CTL1_VBG_TRIM_HI_HV_Msk 0x1F00UL 311 #define FLASHC_FM_CTL_CAL_CTL1_VBG_TC_TRIM_HI_HV_Pos 13UL 312 #define FLASHC_FM_CTL_CAL_CTL1_VBG_TC_TRIM_HI_HV_Msk 0xE000UL 313 #define FLASHC_FM_CTL_CAL_CTL1_IPREF_TRIM_HI_HV_Pos 16UL 314 #define FLASHC_FM_CTL_CAL_CTL1_IPREF_TRIM_HI_HV_Msk 0xF0000UL 315 /* FLASHC_FM_CTL.CAL_CTL2 */ 316 #define FLASHC_FM_CTL_CAL_CTL2_ICREF_TRIM_LO_HV_Pos 0UL 317 #define FLASHC_FM_CTL_CAL_CTL2_ICREF_TRIM_LO_HV_Msk 0x1FUL 318 #define FLASHC_FM_CTL_CAL_CTL2_ICREF_TC_TRIM_LO_HV_Pos 5UL 319 #define FLASHC_FM_CTL_CAL_CTL2_ICREF_TC_TRIM_LO_HV_Msk 0xE0UL 320 #define FLASHC_FM_CTL_CAL_CTL2_ICREF_TRIM_HI_HV_Pos 8UL 321 #define FLASHC_FM_CTL_CAL_CTL2_ICREF_TRIM_HI_HV_Msk 0x1F00UL 322 #define FLASHC_FM_CTL_CAL_CTL2_ICREF_TC_TRIM_HI_HV_Pos 13UL 323 #define FLASHC_FM_CTL_CAL_CTL2_ICREF_TC_TRIM_HI_HV_Msk 0xE000UL 324 #define FLASHC_FM_CTL_CAL_CTL2_VREF_SEL_HV_Pos 16UL 325 #define FLASHC_FM_CTL_CAL_CTL2_VREF_SEL_HV_Msk 0x10000UL 326 #define FLASHC_FM_CTL_CAL_CTL2_IREF_SEL_HV_Pos 17UL 327 #define FLASHC_FM_CTL_CAL_CTL2_IREF_SEL_HV_Msk 0x20000UL 328 #define FLASHC_FM_CTL_CAL_CTL2_FM_ACTIVE_HV_Pos 18UL 329 #define FLASHC_FM_CTL_CAL_CTL2_FM_ACTIVE_HV_Msk 0x40000UL 330 #define FLASHC_FM_CTL_CAL_CTL2_TURBO_EXT_HV_Pos 19UL 331 #define FLASHC_FM_CTL_CAL_CTL2_TURBO_EXT_HV_Msk 0x80000UL 332 /* FLASHC_FM_CTL.CAL_CTL3 */ 333 #define FLASHC_FM_CTL_CAL_CTL3_OSC_TRIM_HV_Pos 0UL 334 #define FLASHC_FM_CTL_CAL_CTL3_OSC_TRIM_HV_Msk 0xFUL 335 #define FLASHC_FM_CTL_CAL_CTL3_OSC_RANGE_TRIM_HV_Pos 4UL 336 #define FLASHC_FM_CTL_CAL_CTL3_OSC_RANGE_TRIM_HV_Msk 0x10UL 337 #define FLASHC_FM_CTL_CAL_CTL3_IDAC_HV_Pos 5UL 338 #define FLASHC_FM_CTL_CAL_CTL3_IDAC_HV_Msk 0x1E0UL 339 #define FLASHC_FM_CTL_CAL_CTL3_SDAC_HV_Pos 9UL 340 #define FLASHC_FM_CTL_CAL_CTL3_SDAC_HV_Msk 0x600UL 341 #define FLASHC_FM_CTL_CAL_CTL3_ITIM_HV_Pos 11UL 342 #define FLASHC_FM_CTL_CAL_CTL3_ITIM_HV_Msk 0x7800UL 343 #define FLASHC_FM_CTL_CAL_CTL3_VDDHI_HV_Pos 15UL 344 #define FLASHC_FM_CTL_CAL_CTL3_VDDHI_HV_Msk 0x8000UL 345 #define FLASHC_FM_CTL_CAL_CTL3_TURBO_PULSEW_HV_Pos 16UL 346 #define FLASHC_FM_CTL_CAL_CTL3_TURBO_PULSEW_HV_Msk 0x30000UL 347 #define FLASHC_FM_CTL_CAL_CTL3_BGLO_EN_HV_Pos 18UL 348 #define FLASHC_FM_CTL_CAL_CTL3_BGLO_EN_HV_Msk 0x40000UL 349 #define FLASHC_FM_CTL_CAL_CTL3_BGHI_EN_HV_Pos 19UL 350 #define FLASHC_FM_CTL_CAL_CTL3_BGHI_EN_HV_Msk 0x80000UL 351 /* FLASHC_FM_CTL.BOOKMARK */ 352 #define FLASHC_FM_CTL_BOOKMARK_BOOKMARK_Pos 0UL 353 #define FLASHC_FM_CTL_BOOKMARK_BOOKMARK_Msk 0xFFFFFFFFUL 354 /* FLASHC_FM_CTL.RED_CTL01 */ 355 #define FLASHC_FM_CTL_RED_CTL01_RED_ADDR_0_Pos 0UL 356 #define FLASHC_FM_CTL_RED_CTL01_RED_ADDR_0_Msk 0xFFUL 357 #define FLASHC_FM_CTL_RED_CTL01_RED_EN_0_Pos 8UL 358 #define FLASHC_FM_CTL_RED_CTL01_RED_EN_0_Msk 0x100UL 359 #define FLASHC_FM_CTL_RED_CTL01_RED_ADDR_1_Pos 16UL 360 #define FLASHC_FM_CTL_RED_CTL01_RED_ADDR_1_Msk 0xFF0000UL 361 #define FLASHC_FM_CTL_RED_CTL01_RED_EN_1_Pos 24UL 362 #define FLASHC_FM_CTL_RED_CTL01_RED_EN_1_Msk 0x1000000UL 363 /* FLASHC_FM_CTL.RED_CTL23 */ 364 #define FLASHC_FM_CTL_RED_CTL23_RED_ADDR_2_Pos 0UL 365 #define FLASHC_FM_CTL_RED_CTL23_RED_ADDR_2_Msk 0xFFUL 366 #define FLASHC_FM_CTL_RED_CTL23_RED_EN_2_Pos 8UL 367 #define FLASHC_FM_CTL_RED_CTL23_RED_EN_2_Msk 0x100UL 368 #define FLASHC_FM_CTL_RED_CTL23_RED_ADDR_3_Pos 16UL 369 #define FLASHC_FM_CTL_RED_CTL23_RED_ADDR_3_Msk 0xFF0000UL 370 #define FLASHC_FM_CTL_RED_CTL23_RED_EN_3_Pos 24UL 371 #define FLASHC_FM_CTL_RED_CTL23_RED_EN_3_Msk 0x1000000UL 372 /* FLASHC_FM_CTL.RED_CTL45 */ 373 #define FLASHC_FM_CTL_RED_CTL45_DNU_45_1_Pos 0UL 374 #define FLASHC_FM_CTL_RED_CTL45_DNU_45_1_Msk 0x1UL 375 #define FLASHC_FM_CTL_RED_CTL45_REG_ACT_HV_Pos 1UL 376 #define FLASHC_FM_CTL_RED_CTL45_REG_ACT_HV_Msk 0x2UL 377 #define FLASHC_FM_CTL_RED_CTL45_DNU_45_3_Pos 2UL 378 #define FLASHC_FM_CTL_RED_CTL45_DNU_45_3_Msk 0x4UL 379 #define FLASHC_FM_CTL_RED_CTL45_FDIV_TRIM_HV_0_Pos 3UL 380 #define FLASHC_FM_CTL_RED_CTL45_FDIV_TRIM_HV_0_Msk 0x8UL 381 #define FLASHC_FM_CTL_RED_CTL45_DNU_45_5_Pos 4UL 382 #define FLASHC_FM_CTL_RED_CTL45_DNU_45_5_Msk 0x10UL 383 #define FLASHC_FM_CTL_RED_CTL45_FDIV_TRIM_HV_1_Pos 5UL 384 #define FLASHC_FM_CTL_RED_CTL45_FDIV_TRIM_HV_1_Msk 0x20UL 385 #define FLASHC_FM_CTL_RED_CTL45_DNU_45_6_Pos 6UL 386 #define FLASHC_FM_CTL_RED_CTL45_DNU_45_6_Msk 0x40UL 387 #define FLASHC_FM_CTL_RED_CTL45_VLIM_TRIM_HV_0_Pos 7UL 388 #define FLASHC_FM_CTL_RED_CTL45_VLIM_TRIM_HV_0_Msk 0x80UL 389 #define FLASHC_FM_CTL_RED_CTL45_DNU_45_8_Pos 8UL 390 #define FLASHC_FM_CTL_RED_CTL45_DNU_45_8_Msk 0x100UL 391 #define FLASHC_FM_CTL_RED_CTL45_DNU_45_23_16_Pos 16UL 392 #define FLASHC_FM_CTL_RED_CTL45_DNU_45_23_16_Msk 0xFF0000UL 393 /* FLASHC_FM_CTL.RED_CTL67 */ 394 #define FLASHC_FM_CTL_RED_CTL67_VLIM_TRIM_HV_1_Pos 0UL 395 #define FLASHC_FM_CTL_RED_CTL67_VLIM_TRIM_HV_1_Msk 0x1UL 396 #define FLASHC_FM_CTL_RED_CTL67_DNU_67_1_Pos 1UL 397 #define FLASHC_FM_CTL_RED_CTL67_DNU_67_1_Msk 0x2UL 398 #define FLASHC_FM_CTL_RED_CTL67_VPROT_ACT_HV_Pos 2UL 399 #define FLASHC_FM_CTL_RED_CTL67_VPROT_ACT_HV_Msk 0x4UL 400 #define FLASHC_FM_CTL_RED_CTL67_DNU_67_3_Pos 3UL 401 #define FLASHC_FM_CTL_RED_CTL67_DNU_67_3_Msk 0x8UL 402 #define FLASHC_FM_CTL_RED_CTL67_IPREF_TC_HV_Pos 4UL 403 #define FLASHC_FM_CTL_RED_CTL67_IPREF_TC_HV_Msk 0x10UL 404 #define FLASHC_FM_CTL_RED_CTL67_DNU_67_5_Pos 5UL 405 #define FLASHC_FM_CTL_RED_CTL67_DNU_67_5_Msk 0x20UL 406 #define FLASHC_FM_CTL_RED_CTL67_IPREF_TRIMA_HI_HV_Pos 6UL 407 #define FLASHC_FM_CTL_RED_CTL67_IPREF_TRIMA_HI_HV_Msk 0x40UL 408 #define FLASHC_FM_CTL_RED_CTL67_DNU_67_7_Pos 7UL 409 #define FLASHC_FM_CTL_RED_CTL67_DNU_67_7_Msk 0x80UL 410 #define FLASHC_FM_CTL_RED_CTL67_IPREF_TRIMA_LO_HV_Pos 8UL 411 #define FLASHC_FM_CTL_RED_CTL67_IPREF_TRIMA_LO_HV_Msk 0x100UL 412 #define FLASHC_FM_CTL_RED_CTL67_DNU_67_23_16_Pos 16UL 413 #define FLASHC_FM_CTL_RED_CTL67_DNU_67_23_16_Msk 0xFF0000UL 414 /* FLASHC_FM_CTL.RED_CTL_SM01 */ 415 #define FLASHC_FM_CTL_RED_CTL_SM01_RED_ADDR_SM0_Pos 0UL 416 #define FLASHC_FM_CTL_RED_CTL_SM01_RED_ADDR_SM0_Msk 0xFFUL 417 #define FLASHC_FM_CTL_RED_CTL_SM01_RED_EN_SM0_Pos 8UL 418 #define FLASHC_FM_CTL_RED_CTL_SM01_RED_EN_SM0_Msk 0x100UL 419 #define FLASHC_FM_CTL_RED_CTL_SM01_RED_ADDR_SM1_Pos 16UL 420 #define FLASHC_FM_CTL_RED_CTL_SM01_RED_ADDR_SM1_Msk 0xFF0000UL 421 #define FLASHC_FM_CTL_RED_CTL_SM01_RED_EN_SM1_Pos 24UL 422 #define FLASHC_FM_CTL_RED_CTL_SM01_RED_EN_SM1_Msk 0x1000000UL 423 #define FLASHC_FM_CTL_RED_CTL_SM01_TRKD_Pos 30UL 424 #define FLASHC_FM_CTL_RED_CTL_SM01_TRKD_Msk 0x40000000UL 425 #define FLASHC_FM_CTL_RED_CTL_SM01_R_GRANT_EN_Pos 31UL 426 #define FLASHC_FM_CTL_RED_CTL_SM01_R_GRANT_EN_Msk 0x80000000UL 427 /* FLASHC_FM_CTL.TM_CMPR */ 428 #define FLASHC_FM_CTL_TM_CMPR_DATA_COMP_RESULT_Pos 0UL 429 #define FLASHC_FM_CTL_TM_CMPR_DATA_COMP_RESULT_Msk 0x1UL 430 /* FLASHC_FM_CTL.FM_HV_DATA */ 431 #define FLASHC_FM_CTL_FM_HV_DATA_DATA32_Pos 0UL 432 #define FLASHC_FM_CTL_FM_HV_DATA_DATA32_Msk 0xFFFFFFFFUL 433 /* FLASHC_FM_CTL.FM_MEM_DATA */ 434 #define FLASHC_FM_CTL_FM_MEM_DATA_DATA32_Pos 0UL 435 #define FLASHC_FM_CTL_FM_MEM_DATA_DATA32_Msk 0xFFFFFFFFUL 436 437 438 /* FLASHC.FLASH_CTL */ 439 #define FLASHC_FLASH_CTL_MAIN_WS_Pos 0UL 440 #define FLASHC_FLASH_CTL_MAIN_WS_Msk 0xFUL 441 #define FLASHC_FLASH_CTL_REMAP_Pos 8UL 442 #define FLASHC_FLASH_CTL_REMAP_Msk 0x100UL 443 /* FLASHC.FLASH_PWR_CTL */ 444 #define FLASHC_FLASH_PWR_CTL_ENABLE_Pos 0UL 445 #define FLASHC_FLASH_PWR_CTL_ENABLE_Msk 0x1UL 446 #define FLASHC_FLASH_PWR_CTL_ENABLE_HV_Pos 1UL 447 #define FLASHC_FLASH_PWR_CTL_ENABLE_HV_Msk 0x2UL 448 /* FLASHC.FLASH_CMD */ 449 #define FLASHC_FLASH_CMD_INV_Pos 0UL 450 #define FLASHC_FLASH_CMD_INV_Msk 0x1UL 451 /* FLASHC.BIST_CTL */ 452 #define FLASHC_BIST_CTL_OPCODE_Pos 0UL 453 #define FLASHC_BIST_CTL_OPCODE_Msk 0x3UL 454 #define FLASHC_BIST_CTL_UP_Pos 2UL 455 #define FLASHC_BIST_CTL_UP_Msk 0x4UL 456 #define FLASHC_BIST_CTL_ROW_FIRST_Pos 3UL 457 #define FLASHC_BIST_CTL_ROW_FIRST_Msk 0x8UL 458 #define FLASHC_BIST_CTL_ADDR_START_ENABLED_Pos 4UL 459 #define FLASHC_BIST_CTL_ADDR_START_ENABLED_Msk 0x10UL 460 #define FLASHC_BIST_CTL_ADDR_COMPLIMENT_ENABLED_Pos 5UL 461 #define FLASHC_BIST_CTL_ADDR_COMPLIMENT_ENABLED_Msk 0x20UL 462 #define FLASHC_BIST_CTL_INCR_DECR_BOTH_Pos 6UL 463 #define FLASHC_BIST_CTL_INCR_DECR_BOTH_Msk 0x40UL 464 #define FLASHC_BIST_CTL_STOP_ON_ERROR_Pos 7UL 465 #define FLASHC_BIST_CTL_STOP_ON_ERROR_Msk 0x80UL 466 /* FLASHC.BIST_CMD */ 467 #define FLASHC_BIST_CMD_START_Pos 0UL 468 #define FLASHC_BIST_CMD_START_Msk 0x1UL 469 /* FLASHC.BIST_ADDR_START */ 470 #define FLASHC_BIST_ADDR_START_COL_ADDR_START_Pos 0UL 471 #define FLASHC_BIST_ADDR_START_COL_ADDR_START_Msk 0xFFFFUL 472 #define FLASHC_BIST_ADDR_START_ROW_ADDR_START_Pos 16UL 473 #define FLASHC_BIST_ADDR_START_ROW_ADDR_START_Msk 0xFFFF0000UL 474 /* FLASHC.BIST_DATA */ 475 #define FLASHC_BIST_DATA_DATA_Pos 0UL 476 #define FLASHC_BIST_DATA_DATA_Msk 0xFFFFFFFFUL 477 /* FLASHC.BIST_DATA_ACT */ 478 #define FLASHC_BIST_DATA_ACT_DATA_Pos 0UL 479 #define FLASHC_BIST_DATA_ACT_DATA_Msk 0xFFFFFFFFUL 480 /* FLASHC.BIST_DATA_EXP */ 481 #define FLASHC_BIST_DATA_EXP_DATA_Pos 0UL 482 #define FLASHC_BIST_DATA_EXP_DATA_Msk 0xFFFFFFFFUL 483 /* FLASHC.BIST_ADDR */ 484 #define FLASHC_BIST_ADDR_COL_ADDR_Pos 0UL 485 #define FLASHC_BIST_ADDR_COL_ADDR_Msk 0xFFFFUL 486 #define FLASHC_BIST_ADDR_ROW_ADDR_Pos 16UL 487 #define FLASHC_BIST_ADDR_ROW_ADDR_Msk 0xFFFF0000UL 488 /* FLASHC.BIST_STATUS */ 489 #define FLASHC_BIST_STATUS_FAIL_Pos 0UL 490 #define FLASHC_BIST_STATUS_FAIL_Msk 0x1UL 491 /* FLASHC.CM0_CA_CTL0 */ 492 #define FLASHC_CM0_CA_CTL0_WAY_Pos 16UL 493 #define FLASHC_CM0_CA_CTL0_WAY_Msk 0x30000UL 494 #define FLASHC_CM0_CA_CTL0_SET_ADDR_Pos 24UL 495 #define FLASHC_CM0_CA_CTL0_SET_ADDR_Msk 0x7000000UL 496 #define FLASHC_CM0_CA_CTL0_PREF_EN_Pos 30UL 497 #define FLASHC_CM0_CA_CTL0_PREF_EN_Msk 0x40000000UL 498 #define FLASHC_CM0_CA_CTL0_ENABLED_Pos 31UL 499 #define FLASHC_CM0_CA_CTL0_ENABLED_Msk 0x80000000UL 500 /* FLASHC.CM0_CA_CTL1 */ 501 #define FLASHC_CM0_CA_CTL1_PWR_MODE_Pos 0UL 502 #define FLASHC_CM0_CA_CTL1_PWR_MODE_Msk 0x3UL 503 #define FLASHC_CM0_CA_CTL1_VECTKEYSTAT_Pos 16UL 504 #define FLASHC_CM0_CA_CTL1_VECTKEYSTAT_Msk 0xFFFF0000UL 505 /* FLASHC.CM0_CA_CTL2 */ 506 #define FLASHC_CM0_CA_CTL2_PWRUP_DELAY_Pos 0UL 507 #define FLASHC_CM0_CA_CTL2_PWRUP_DELAY_Msk 0x3FFUL 508 /* FLASHC.CM0_CA_CMD */ 509 #define FLASHC_CM0_CA_CMD_INV_Pos 0UL 510 #define FLASHC_CM0_CA_CMD_INV_Msk 0x1UL 511 /* FLASHC.CM0_CA_STATUS0 */ 512 #define FLASHC_CM0_CA_STATUS0_VALID16_Pos 0UL 513 #define FLASHC_CM0_CA_STATUS0_VALID16_Msk 0xFFFFUL 514 /* FLASHC.CM0_CA_STATUS1 */ 515 #define FLASHC_CM0_CA_STATUS1_TAG_Pos 0UL 516 #define FLASHC_CM0_CA_STATUS1_TAG_Msk 0xFFFFFFFFUL 517 /* FLASHC.CM0_CA_STATUS2 */ 518 #define FLASHC_CM0_CA_STATUS2_LRU_Pos 0UL 519 #define FLASHC_CM0_CA_STATUS2_LRU_Msk 0x3FUL 520 /* FLASHC.CM4_CA_CTL0 */ 521 #define FLASHC_CM4_CA_CTL0_WAY_Pos 16UL 522 #define FLASHC_CM4_CA_CTL0_WAY_Msk 0x30000UL 523 #define FLASHC_CM4_CA_CTL0_SET_ADDR_Pos 24UL 524 #define FLASHC_CM4_CA_CTL0_SET_ADDR_Msk 0x7000000UL 525 #define FLASHC_CM4_CA_CTL0_PREF_EN_Pos 30UL 526 #define FLASHC_CM4_CA_CTL0_PREF_EN_Msk 0x40000000UL 527 #define FLASHC_CM4_CA_CTL0_ENABLED_Pos 31UL 528 #define FLASHC_CM4_CA_CTL0_ENABLED_Msk 0x80000000UL 529 /* FLASHC.CM4_CA_CTL1 */ 530 #define FLASHC_CM4_CA_CTL1_PWR_MODE_Pos 0UL 531 #define FLASHC_CM4_CA_CTL1_PWR_MODE_Msk 0x3UL 532 #define FLASHC_CM4_CA_CTL1_VECTKEYSTAT_Pos 16UL 533 #define FLASHC_CM4_CA_CTL1_VECTKEYSTAT_Msk 0xFFFF0000UL 534 /* FLASHC.CM4_CA_CTL2 */ 535 #define FLASHC_CM4_CA_CTL2_PWRUP_DELAY_Pos 0UL 536 #define FLASHC_CM4_CA_CTL2_PWRUP_DELAY_Msk 0x3FFUL 537 /* FLASHC.CM4_CA_CMD */ 538 #define FLASHC_CM4_CA_CMD_INV_Pos 0UL 539 #define FLASHC_CM4_CA_CMD_INV_Msk 0x1UL 540 /* FLASHC.CM4_CA_STATUS0 */ 541 #define FLASHC_CM4_CA_STATUS0_VALID16_Pos 0UL 542 #define FLASHC_CM4_CA_STATUS0_VALID16_Msk 0xFFFFUL 543 /* FLASHC.CM4_CA_STATUS1 */ 544 #define FLASHC_CM4_CA_STATUS1_TAG_Pos 0UL 545 #define FLASHC_CM4_CA_STATUS1_TAG_Msk 0xFFFFFFFFUL 546 /* FLASHC.CM4_CA_STATUS2 */ 547 #define FLASHC_CM4_CA_STATUS2_LRU_Pos 0UL 548 #define FLASHC_CM4_CA_STATUS2_LRU_Msk 0x3FUL 549 /* FLASHC.CRYPTO_BUFF_CTL */ 550 #define FLASHC_CRYPTO_BUFF_CTL_PREF_EN_Pos 30UL 551 #define FLASHC_CRYPTO_BUFF_CTL_PREF_EN_Msk 0x40000000UL 552 #define FLASHC_CRYPTO_BUFF_CTL_ENABLED_Pos 31UL 553 #define FLASHC_CRYPTO_BUFF_CTL_ENABLED_Msk 0x80000000UL 554 /* FLASHC.CRYPTO_BUFF_CMD */ 555 #define FLASHC_CRYPTO_BUFF_CMD_INV_Pos 0UL 556 #define FLASHC_CRYPTO_BUFF_CMD_INV_Msk 0x1UL 557 /* FLASHC.DW0_BUFF_CTL */ 558 #define FLASHC_DW0_BUFF_CTL_PREF_EN_Pos 30UL 559 #define FLASHC_DW0_BUFF_CTL_PREF_EN_Msk 0x40000000UL 560 #define FLASHC_DW0_BUFF_CTL_ENABLED_Pos 31UL 561 #define FLASHC_DW0_BUFF_CTL_ENABLED_Msk 0x80000000UL 562 /* FLASHC.DW0_BUFF_CMD */ 563 #define FLASHC_DW0_BUFF_CMD_INV_Pos 0UL 564 #define FLASHC_DW0_BUFF_CMD_INV_Msk 0x1UL 565 /* FLASHC.DW1_BUFF_CTL */ 566 #define FLASHC_DW1_BUFF_CTL_PREF_EN_Pos 30UL 567 #define FLASHC_DW1_BUFF_CTL_PREF_EN_Msk 0x40000000UL 568 #define FLASHC_DW1_BUFF_CTL_ENABLED_Pos 31UL 569 #define FLASHC_DW1_BUFF_CTL_ENABLED_Msk 0x80000000UL 570 /* FLASHC.DW1_BUFF_CMD */ 571 #define FLASHC_DW1_BUFF_CMD_INV_Pos 0UL 572 #define FLASHC_DW1_BUFF_CMD_INV_Msk 0x1UL 573 /* FLASHC.DAP_BUFF_CTL */ 574 #define FLASHC_DAP_BUFF_CTL_PREF_EN_Pos 30UL 575 #define FLASHC_DAP_BUFF_CTL_PREF_EN_Msk 0x40000000UL 576 #define FLASHC_DAP_BUFF_CTL_ENABLED_Pos 31UL 577 #define FLASHC_DAP_BUFF_CTL_ENABLED_Msk 0x80000000UL 578 /* FLASHC.DAP_BUFF_CMD */ 579 #define FLASHC_DAP_BUFF_CMD_INV_Pos 0UL 580 #define FLASHC_DAP_BUFF_CMD_INV_Msk 0x1UL 581 /* FLASHC.EXT_MS0_BUFF_CTL */ 582 #define FLASHC_EXT_MS0_BUFF_CTL_PREF_EN_Pos 30UL 583 #define FLASHC_EXT_MS0_BUFF_CTL_PREF_EN_Msk 0x40000000UL 584 #define FLASHC_EXT_MS0_BUFF_CTL_ENABLED_Pos 31UL 585 #define FLASHC_EXT_MS0_BUFF_CTL_ENABLED_Msk 0x80000000UL 586 /* FLASHC.EXT_MS0_BUFF_CMD */ 587 #define FLASHC_EXT_MS0_BUFF_CMD_INV_Pos 0UL 588 #define FLASHC_EXT_MS0_BUFF_CMD_INV_Msk 0x1UL 589 /* FLASHC.EXT_MS1_BUFF_CTL */ 590 #define FLASHC_EXT_MS1_BUFF_CTL_PREF_EN_Pos 30UL 591 #define FLASHC_EXT_MS1_BUFF_CTL_PREF_EN_Msk 0x40000000UL 592 #define FLASHC_EXT_MS1_BUFF_CTL_ENABLED_Pos 31UL 593 #define FLASHC_EXT_MS1_BUFF_CTL_ENABLED_Msk 0x80000000UL 594 /* FLASHC.EXT_MS1_BUFF_CMD */ 595 #define FLASHC_EXT_MS1_BUFF_CMD_INV_Pos 0UL 596 #define FLASHC_EXT_MS1_BUFF_CMD_INV_Msk 0x1UL 597 598 599 #endif /* _CYIP_FLASHC_H_ */ 600 601 602 /* [] END OF FILE */ 603
