1 /* 2 * Copyright (c) 2016 Linaro Limited. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file SoC configuration macros for the ARM LTD Beetle SoC PLL. 9 * 10 */ 11 12 #ifndef _ARM_BEETLE_SOC_PLL_H_ 13 #define _ARM_BEETLE_SOC_PLL_H_ 14 15 /* 16 * This header provides the defines to configure the Beetle PLL. 17 * 18 * BEETLE PLL main register is the PLLCTRL in the System Control 19 * 20 * The PLLCTRL relevant bits are: 21 * - PLL_OUTPUTDIV [9:8] 22 * - PLL_INPUTDIV [20:16] 23 * - PLL_FEEDDIV [30:24] 24 * 25 * The formula to calculate the output frequency of the PLL is: 26 * Fout = Fin * PLL_FEEDDIV / (PLL_INPUTDIV * PLL_OUTPUTDIV) 27 * The Fin = 24Mhz on Beetle 28 * 29 * PLL_OUTPUTDIV | 0 1 2 3 30 * ----------------------- 31 * | 1 2 4 8 32 * 33 * PLL_INPUTDIV = R[20:16] + 1 34 * 35 * PLL_FEEDDIV = 2*(R[30:24] + 1) 36 * 37 * BEETLE PLL has a non bypassable divider by 2 in output 38 * 39 * BEETLE PLL derived clock is prescaled [1-16] 40 */ 41 42 /* BEETLE PLL Masks */ 43 #define PLL_MAINCLK_ENABLE_Msk 0x1 44 #define PLL_MAINCLK_DISABLE_Msk 0x1 45 #define PLL_MAINCLK_PRESCALER_Msk 0xF0 46 47 /* BEETLE PLL Configuration */ 48 #define BEETLE_PLL_CONFIGURATION 0x17000200 49 50 /* BEETLE PLL Supported Frequencies */ 51 /* BEETLE_PLL_48Mhz */ 52 #define BEETLE_PLL_FREQUENCY_48MHZ 48000000 53 #define BEETLE_PLL_PRESCALER_48MHZ 0x21 54 /* BEETLE_PLL_36Mhz */ 55 #define BEETLE_PLL_FREQUENCY_36MHZ 36000000 56 #define BEETLE_PLL_PRESCALER_36MHZ 0x31 57 /* BEETLE_PLL_24Mhz */ 58 #define BEETLE_PLL_FREQUENCY_24MHZ 24000000 59 #define BEETLE_PLL_PRESCALER_24MHZ 0x51 60 /* BEETLE_PLL_12Mhz */ 61 #define BEETLE_PLL_FREQUENCY_12MHZ 12000000 62 #define BEETLE_PLL_PRESCALER_12MHZ 0xB1 63 64 #endif /* _ARM_BEETLE_SOC_PLL_H_ */ 65
