1 /**************************************************************************//** 2 * @file hsusbd_reg.h 3 * @version V3.00 4 * @brief HSUSBD register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __HSUSBD_REG_H__ 10 #define __HSUSBD_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup HSUSBD USB 2.0 Device Controller (HSUSBD) 23 Memory Mapped Structure for HSUSBD Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 /** 30 * @var HSUSBD_EP_T::EPDAT 31 * Offset: 0x00 Endpoint n Data Register 32 * --------------------------------------------------------------------------------------------------- 33 * |Bits |Field |Descriptions 34 * | :----: | :----: | :---- | 35 * |[31:0] |EPDAT |Endpoint A~L Data Register 36 * | | |Endpoint A~L data buffer for the buffer transaction (read or write). 37 * | | |Note: Only word access is supported. 38 * @var HSUSBD_EP_T::EPDAT_BYTE 39 * Offset: 0x00 Endpoint n Data Register 40 * --------------------------------------------------------------------------------------------------- 41 * |Bits |Field |Descriptions 42 * | :----: | :----: | :---- | 43 * |[7:0] |EPDAT |Endpoint A~L Data Register 44 * | | |Endpoint A~L data buffer for the buffer transaction (read or write). 45 * | | |Note: Only byte access is supported. 46 * @var HSUSBD_EP_T::EPINTSTS 47 * Offset: 0x04 Endpoint n Interrupt Status Register 48 * --------------------------------------------------------------------------------------------------- 49 * |Bits |Field |Descriptions 50 * | :----: | :----: | :---- | 51 * |[0] |BUFFULLIF |Buffer Full 52 * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write) 53 * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading). 54 * | | |0 = The endpoint packet buffer is not full. 55 * | | |1 = The endpoint packet buffer is full. 56 * | | |Note: This bit is read-only. 57 * |[1] |BUFEMPTYIF|Buffer Empty 58 * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes. 59 * | | |0 = The endpoint buffer is not empty. 60 * | | |1 = The endpoint buffer is empty. 61 * | | |For an OUT endpoint: 62 * | | |0 = The currently selected buffer has not a count of 0. 63 * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read). 64 * | | |Note: This bit is read-only. 65 * |[2] |SHORTTXIF |Short Packet Transferred Interrupt 66 * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS). 67 * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS). 68 * | | |Note: Write 1 to clear this bit to 0. 69 * |[3] |TXPKIF |Data Packet Transmitted Interrupt 70 * | | |0 = Not a data packet is transmitted from the endpoint to the host. 71 * | | |1 = A data packet is transmitted from the endpoint to the host. 72 * | | |Note: Write 1 to clear this bit to 0. 73 * |[4] |RXPKIF |Data Packet Received Interrupt 74 * | | |0 = No data packet is received from the host by the endpoint. 75 * | | |1 = A data packet is received from the host by the endpoint. 76 * | | |Note: Write 1 to clear this bit to 0. 77 * |[5] |OUTTKIF |Data OUT Token Interrupt 78 * | | |0 = A Data OUT token has not been received from the host. 79 * | | |1 = A Data OUT token has been received from the host 80 * | | |This bit also set by PING token (in high-speed only). 81 * | | |Note: Write 1 to clear this bit to 0. 82 * |[6] |INTKIF |Data IN Token Interrupt 83 * | | |0 = Not Data IN token has been received from the host. 84 * | | |1 = A Data IN token has been received from the host. 85 * | | |Note: Write 1 to clear this bit to 0. 86 * |[7] |PINGIF |PING Token Interrupt 87 * | | |0 = A Data PING token has not been received from the host. 88 * | | |1 = A Data PING token has been received from the host. 89 * | | |Note: Write 1 to clear this bit to 0. 90 * |[8] |NAKIF |USB NAK Sent 91 * | | |0 = The last USB IN packet could be provided, and was acknowledged with an ACK. 92 * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK. 93 * | | |Note: Write 1 to clear this bit to 0. 94 * |[9] |STALLIF |USB STALL Sent 95 * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL. 96 * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL. 97 * | | |Note: Write 1 to clear this bit to 0. 98 * |[10] |NYETIF |NYET Sent 99 * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet. 100 * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet. 101 * | | |Note: Write 1 to clear this bit to 0. 102 * |[11] |ERRIF |ERR Sent 103 * | | |0 = No any error in the transaction. 104 * | | |1 = There occurs any error in the transaction. 105 * | | |Note: Write 1 to clear this bit to 0. 106 * |[12] |SHORTRXIF |Bulk Out Short Packet Received 107 * | | |0 = No bulk out short packet is received. 108 * | | |1 = Received bulk out short packet (including zero length packet). 109 * | | |Note: Write 1 to clear this bit to 0. 110 * @var HSUSBD_EP_T::EPINTEN 111 * Offset: 0x08 Endpoint n Interrupt Enable Register 112 * --------------------------------------------------------------------------------------------------- 113 * |Bits |Field |Descriptions 114 * | :----: | :----: | :---- | 115 * |[0] |BUFFULLIEN|Buffer Full Interrupt 116 * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus. 117 * | | |0 = Buffer full interrupt Disabled. 118 * | | |1 = Buffer full interrupt Enabled. 119 * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt 120 * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus. 121 * | | |0 = Buffer empty interrupt Disabled. 122 * | | |1 = Buffer empty interrupt Enabled. 123 * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Bit 124 * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host. 125 * | | |0 = Short data packet interrupt Disabled. 126 * | | |1 = Short data packet interrupt Enabled. 127 * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Bit 128 * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host. 129 * | | |0 = Data packet has been received from the host interrupt Disabled. 130 * | | |1 = Data packet has been received from the host interrupt Enabled. 131 * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Bit 132 * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host. 133 * | | |0 = Data packet has been transmitted to the host interrupt Disabled. 134 * | | |1 = Data packet has been transmitted to the host interrupt Enabled. 135 * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Bit 136 * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host. 137 * | | |0 = Data OUT token interrupt Disabled. 138 * | | |1 = Data OUT token interrupt Enabled. 139 * |[6] |INTKIEN |Data IN Token Interrupt Enable Bit 140 * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host. 141 * | | |0 = Data IN token interrupt Disabled. 142 * | | |1 = Data IN token interrupt Enabled. 143 * |[7] |PINGIEN |PING Token Interrupt Enable Bit 144 * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host. 145 * | | |0 = PING token interrupt Disabled. 146 * | | |1 = PING token interrupt Enabled. 147 * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Bit 148 * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host. 149 * | | |0 = NAK token interrupt Disabled. 150 * | | |1 = NAK token interrupt Enabled. 151 * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Bit 152 * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host. 153 * | | |0 = STALL token interrupt Disabled. 154 * | | |1 = STALL token interrupt Enabled. 155 * |[10] |NYETIEN |NYET Interrupt Enable Bit 156 * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint. 157 * | | |0 = NYET condition interrupt Disabled. 158 * | | |1 = NYET condition interrupt Enabled. 159 * |[11] |ERRIEN |ERR Interrupt Enable Bit 160 * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint. 161 * | | |0 = Error event interrupt Disabled. 162 * | | |1 = Error event interrupt Enabled. 163 * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Bit 164 * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint. 165 * | | |0 = Bulk out interrupt Disabled. 166 * | | |1 = Bulk out interrupt Enabled. 167 * @var HSUSBD_EP_T::EPDATCNT 168 * Offset: 0x0C Endpoint n Data Available Count Register 169 * --------------------------------------------------------------------------------------------------- 170 * |Bits |Field |Descriptions 171 * | :----: | :----: | :---- | 172 * |[15:0] |DATCNT |Data Count 173 * | | |For an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.), this register returns the number of valid bytes in the IN endpoint packet buffer. 174 * | | |For an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.), this register returns the number of received valid bytes in the Host OUT transfer. 175 * |[30:16] |DMALOOP |DMA Loop 176 * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer. 177 * @var HSUSBD_EP_T::EPRSPCTL 178 * Offset: 0x10 Endpoint n Response Control Register 179 * --------------------------------------------------------------------------------------------------- 180 * |Bits |Field |Descriptions 181 * | :----: | :----: | :---- | 182 * |[0] |FLUSH |Buffer Flush 183 * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared 184 * | | |This bit is self-clearing 185 * | | |This bit should always be written after an configuration event. 186 * | | |0 = The packet buffer is not flushed. 187 * | | |1 = The packet buffer is flushed by user. 188 * |[2:1] |MODE |Mode Control 189 * | | |The two bits decide the operation mode of the in-endpoint. 190 * | | |00: Auto-Validate Mode 191 * | | |01: Manual-Validate Mode 192 * | | |10: Fly Mode 193 * | | |11: Reserved 194 * | | |These bits are not valid for an out-endpoint 195 * | | |The auto validate mode will be activated when the reserved mode is selected 196 * |[3] |TOGGLE |Endpoint Toggle 197 * | | |This bit is used to clear the endpoint data toggle bit 198 * | | |Reading this bit returns the current state of the endpoint data toggle bit. 199 * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host 200 * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3]. 201 * | | |0 = Not clear the endpoint data toggle bit. 202 * | | |1 = Clear the endpoint data toggle bit. 203 * |[4] |HALT |Endpoint Halt 204 * | | |This bit is used to send a STALL handshake as response to the token from the host 205 * | | |When an Endpoint Set Feature (ep_halt) is detected by the local CPU, it must write a '1' to this bit. 206 * | | |0 = Not send a STALL handshake as response to the token from the host. 207 * | | |1 = Send a STALL handshake as response to the token from the host. 208 * |[5] |ZEROLEN |Zero Length 209 * | | |This bit is used to send a zero-length packet response to an IN-token 210 * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token 211 * | | |This bit gets cleared once the zero length data packet is sent. 212 * | | |0 = A zero packet is not sent to the host on reception of an IN-token. 213 * | | |1 = A zero packet is sent to the host on reception of an IN-token. 214 * |[6] |SHORTTXEN |Short Packet Transfer Enable 215 * | | |This bit is applicable only in case of Auto-Validate Method 216 * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer 217 * | | |This bit gets cleared once the data packet is sent. 218 * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint. 219 * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint. 220 * |[7] |DISBUF |Buffer Disable Bit 221 * | | |This bit is used to receive unknown size OUT short packet 222 * | | |The received packet size is reference USBD_EPxDATCNT register. 223 * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received. 224 * | | |1 = Buffer Disabled when Bulk-OUT short packet is received. 225 * @var HSUSBD_EP_T::EPMPS 226 * Offset: 0x14 Endpoint n Maximum Packet Size Register 227 * --------------------------------------------------------------------------------------------------- 228 * |Bits |Field |Descriptions 229 * | :----: | :----: | :---- | 230 * |[10:0] |EPMPS |Endpoint Maximum Packet Size 231 * | | |This field determines the Maximum Packet Size of the Endpoint. 232 * @var HSUSBD_EP_T::EPTXCNT 233 * Offset: 0x18 Endpoint n Transfer Count Register 234 * --------------------------------------------------------------------------------------------------- 235 * |Bits |Field |Descriptions 236 * | :----: | :----: | :---- | 237 * |[10:0] |TXCNT |Endpoint Transfer Count 238 * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method. 239 * | | |For OUT endpoints, this field has no effect. 240 * @var HSUSBD_EP_T::EPCFG 241 * Offset: 0x1C Endpoint n Configuration Register 242 * --------------------------------------------------------------------------------------------------- 243 * |Bits |Field |Descriptions 244 * | :----: | :----: | :---- | 245 * |[0] |EPEN |Endpoint Valid 246 * | | |When set, this bit enables this endpoint 247 * | | |This bit has no effect on Endpoint 0, which is always enabled. 248 * | | |0 = The endpoint Disabled. 249 * | | |1 = The endpoint Enabled. 250 * |[2:1] |EPTYPE |Endpoint Type 251 * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type. 252 * | | |00 = Reserved. 253 * | | |01 = Bulk. 254 * | | |10 = Interrupt. 255 * | | |11 = Isochronous. 256 * |[3] |EPDIR |Endpoint Direction 257 * | | |0 = out-endpoint (Host OUT to Device). 258 * | | |1 = in-endpoint (Host IN to Device). 259 * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number. 260 * |[7:4] |EPNUM |Endpoint Number 261 * | | |This field selects the number of the endpoint. Valid numbers 1 to 15. 262 * | | |Note: Do not support two endpoints have same endpoint number. 263 * @var HSUSBD_EP_T::EPBUFST 264 * Offset: 0x20 Endpoint n RAM Start Address Register 265 * --------------------------------------------------------------------------------------------------- 266 * |Bits |Field |Descriptions 267 * | :----: | :----: | :---- | 268 * |[11:0] |SADDR |Endpoint Start Address 269 * | | |This is the start-address of the RAM space allocated for the endpoint A~L. 270 * @var HSUSBD_EP_T::EPBUFEND 271 * Offset: 0x24 Endpoint n RAM End Address Register 272 * --------------------------------------------------------------------------------------------------- 273 * |Bits |Field |Descriptions 274 * | :----: | :----: | :---- | 275 * |[11:0] |EADDR |Endpoint End Address 276 * | | |This is the end-address of the RAM space allocated for the endpoint A~L. 277 */ 278 279 union 280 { 281 __IO uint32_t EPDAT; 282 __IO uint8_t EPDAT_BYTE; 283 284 }; /*!< [0x0000] Endpoint n Data Register */ 285 286 __IO uint32_t EPINTSTS; /*!< [0x0004] Endpoint n Interrupt Status Register */ 287 __IO uint32_t EPINTEN; /*!< [0x0008] Endpoint n Interrupt Enable Register */ 288 __I uint32_t EPDATCNT; /*!< [0x000c] Endpoint n Data Available Count Register */ 289 __IO uint32_t EPRSPCTL; /*!< [0x0010] Endpoint n Response Control Register */ 290 __IO uint32_t EPMPS; /*!< [0x0014] Endpoint n Maximum Packet Size Register */ 291 __IO uint32_t EPTXCNT; /*!< [0x0018] Endpoint n Transfer Count Register */ 292 __IO uint32_t EPCFG; /*!< [0x001c] Endpoint n Configuration Register */ 293 __IO uint32_t EPBUFST; /*!< [0x0020] Endpoint n RAM Start Address Register */ 294 __IO uint32_t EPBUFEND; /*!< [0x0024] Endpoint n RAM End Address Register */ 295 296 } HSUSBD_EP_T; 297 298 typedef struct 299 { 300 301 /** 302 * @var HSUSBD_T::GINTSTS 303 * Offset: 0x00 Global Interrupt Status Register 304 * --------------------------------------------------------------------------------------------------- 305 * |Bits |Field |Descriptions 306 * | :----: | :----: | :---- | 307 * |[0] |USBIF |USB Interrupt 308 * | | |This bit conveys the interrupt status for USB specific events endpoint 309 * | | |When set, USB interrupt status register should be read to determine the cause of the interrupt. 310 * | | |0 = No interrupt event occurred. 311 * | | |1 = The related interrupt event is occurred. 312 * |[1] |CEPIF |Control Endpoint Interrupt 313 * | | |This bit conveys the interrupt status for control endpoint 314 * | | |When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt. 315 * | | |0 = No interrupt event occurred. 316 * | | |1 = The related interrupt event is occurred. 317 * |[2] |EPAIF |Endpoint a Interrupt 318 * | | |When set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt. 319 * | | |0 = No interrupt event occurred. 320 * | | |1 = The related interrupt event is occurred. 321 * |[3] |EPBIF |Endpoint B Interrupt 322 * | | |When set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt. 323 * | | |0 = No interrupt event occurred. 324 * | | |1 = The related interrupt event is occurred. 325 * |[4] |EPCIF |Endpoint C Interrupt 326 * | | |When set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt. 327 * | | |0 = No interrupt event occurred. 328 * | | |1 = The related interrupt event is occurred. 329 * |[5] |EPDIF |Endpoint D Interrupt 330 * | | |When set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt. 331 * | | |0 = No interrupt event occurred. 332 * | | |1 = The related interrupt event is occurred. 333 * |[6] |EPEIF |Endpoint E Interrupt 334 * | | |When set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt. 335 * | | |0 = No interrupt event occurred. 336 * | | |1 = The related interrupt event is occurred. 337 * |[7] |EPFIF |Endpoint F Interrupt 338 * | | |When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt. 339 * | | |0 = No interrupt event occurred. 340 * | | |1 = The related interrupt event is occurred. 341 * |[8] |EPGIF |Endpoint G Interrupt 342 * | | |When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt. 343 * | | |0 = No interrupt event occurred. 344 * | | |1 = The related interrupt event is occurred. 345 * |[9] |EPHIF |Endpoint H Interrupt 346 * | | |When set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt. 347 * | | |0 = No interrupt event occurred. 348 * | | |1 = The related interrupt event is occurred. 349 * |[10] |EPIIF |Endpoint I Interrupt 350 * | | |When set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt. 351 * | | |0 = No interrupt event occurred. 352 * | | |1 = The related interrupt event is occurred. 353 * |[11] |EPJIF |Endpoint J Interrupt 354 * | | |When set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt. 355 * | | |0 = No interrupt event occurred. 356 * | | |1 = The related interrupt event is occurred. 357 * |[12] |EPKIF |Endpoint K Interrupt 358 * | | |When set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt. 359 * | | |0 = No interrupt event occurred. 360 * | | |1 = The related interrupt event is occurred. 361 * |[13] |EPLIF |Endpoint L Interrupt 362 * | | |When set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt. 363 * | | |0 = No interrupt event occurred. 364 * | | |1 = The related interrupt event is occurred. 365 * @var HSUSBD_T::GINTEN 366 * Offset: 0x08 Global Interrupt Enable Register 367 * --------------------------------------------------------------------------------------------------- 368 * |Bits |Field |Descriptions 369 * | :----: | :----: | :---- | 370 * |[0] |USBIEN |USB Interrupt Enable Bit 371 * | | |When set, this bit enables a local interrupt to be generated when a USB event occurs on the bus. 372 * | | |0 = The related interrupt Disabled. 373 * | | |1 = The related interrupt Enabled. 374 * |[1] |CEPIEN |Control Endpoint Interrupt Enable Bit 375 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the control endpoint. 376 * | | |0 = The related interrupt Disabled. 377 * | | |1 = The related interrupt Enabled. 378 * |[2] |EPAIEN |Interrupt Enable Control for Endpoint a 379 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint A. 380 * | | |0 = The related interrupt Disabled. 381 * | | |1 = The related interrupt Enabled. 382 * |[3] |EPBIEN |Interrupt Enable Control for Endpoint B 383 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint B 384 * | | |0 = The related interrupt Disabled. 385 * | | |1 = The related interrupt Enabled. 386 * |[4] |EPCIEN |Interrupt Enable Control for Endpoint C 387 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint C 388 * | | |0 = The related interrupt Disabled. 389 * | | |1 = The related interrupt Enabled. 390 * |[5] |EPDIEN |Interrupt Enable Control for Endpoint D 391 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint D 392 * | | |0 = The related interrupt Disabled. 393 * | | |1 = The related interrupt Enabled. 394 * |[6] |EPEIEN |Interrupt Enable Control for Endpoint E 395 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint E 396 * | | |0 = The related interrupt Disabled. 397 * | | |1 = The related interrupt Enabled. 398 * |[7] |EPFIEN |Interrupt Enable Control for Endpoint F 399 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint F 400 * | | |0 = The related interrupt Disabled. 401 * | | |1 = The related interrupt Enabled. 402 * |[8] |EPGIEN |Interrupt Enable Control for Endpoint G 403 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint G 404 * | | |0 = The related interrupt Disabled. 405 * | | |1 = The related interrupt Enabled. 406 * |[9] |EPHIEN |Interrupt Enable Control for Endpoint H 407 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint H 408 * | | |0 = The related interrupt Disabled. 409 * | | |1 = The related interrupt Enabled. 410 * |[10] |EPIIEN |Interrupt Enable Control for Endpoint I 411 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint I 412 * | | |0 = The related interrupt Disabled. 413 * | | |1 = The related interrupt Enabled. 414 * |[11] |EPJIEN |Interrupt Enable Control for Endpoint J 415 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint J 416 * | | |0 = The related interrupt Disabled. 417 * | | |1 = The related interrupt Enabled. 418 * |[12] |EPKIEN |Interrupt Enable Control for Endpoint K 419 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint K 420 * | | |0 = The related interrupt Disabled. 421 * | | |1 = The related interrupt Enabled. 422 * |[13] |EPLIEN |Interrupt Enable Control for Endpoint L 423 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint L 424 * | | |0 = The related interrupt Disabled. 425 * | | |1 = The related interrupt Enabled. 426 * @var HSUSBD_T::BUSINTSTS 427 * Offset: 0x10 USB Bus Interrupt Status Register 428 * --------------------------------------------------------------------------------------------------- 429 * |Bits |Field |Descriptions 430 * | :----: | :----: | :---- | 431 * |[0] |SOFIF |SOF Receive Control 432 * | | |This bit indicates when a start-of-frame packet has been received. 433 * | | |0 = No start-of-frame packet has been received. 434 * | | |1 = Start-of-frame packet has been received. 435 * | | |Note: Write 1 to clear this bit to 0. 436 * |[1] |RSTIF |Reset Status 437 * | | |When set, this bit indicates that either the USB root port reset is end. 438 * | | |0 = No USB root port reset is end. 439 * | | |1 = USB root port reset is end. 440 * | | |Note: Write 1 to clear this bit to 0. 441 * |[2] |RESUMEIF |Resume 442 * | | |When set, this bit indicates that a device resume has occurred. 443 * | | |0 = No device resume has occurred. 444 * | | |1 = Device resume has occurred. 445 * | | |Note: Write 1 to clear this bit to 0. 446 * |[3] |SUSPENDIF |Suspend Request 447 * | | |This bit is set as default and it has to be cleared by writing '1' before the USB reset 448 * | | |This bit is also set when a USB Suspend request is detected from the host. 449 * | | |0 = No USB Suspend request is detected from the host. 450 * | | |1= USB Suspend request is detected from the host. 451 * | | |Note: Write 1 to clear this bit to 0. 452 * |[4] |HISPDIF |High-speed Settle 453 * | | |0 = No valid high-speed reset protocol is detected. 454 * | | |1 = Valid high-speed reset protocol is over and the device has settled in high-speed. 455 * | | |Note: Write 1 to clear this bit to 0. 456 * |[5] |DMADONEIF |DMA Completion Interrupt 457 * | | |0 = No DMA transfer over. 458 * | | |1 = DMA transfer is over. 459 * | | |Note: Write 1 to clear this bit to 0. 460 * |[6] |PHYCLKVLDIF|Usable Clock Interrupt 461 * | | |0 = Usable clock is not available. 462 * | | |1 = Usable clock is available from the transceiver. 463 * | | |Note: Write 1 to clear this bit to 0. 464 * |[8] |VBUSDETIF |VBUS Detection Interrupt Status 465 * | | |0 = No VBUS is plug-in. 466 * | | |1 = VBUS is plug-in. 467 * | | |Note: Write 1 to clear this bit to 0. 468 * @var HSUSBD_T::BUSINTEN 469 * Offset: 0x14 USB Bus Interrupt Enable Register 470 * --------------------------------------------------------------------------------------------------- 471 * |Bits |Field |Descriptions 472 * | :----: | :----: | :---- | 473 * |[0] |SOFIEN |SOF Interrupt 474 * | | |This bit enables the SOF interrupt. 475 * | | |0 = SOF interrupt Disabled. 476 * | | |1 = SOF interrupt Enabled. 477 * |[1] |RSTIEN |Reset Status 478 * | | |This bit enables the USB-Reset interrupt. 479 * | | |0 = USB-Reset interrupt Disabled. 480 * | | |1 = USB-Reset interrupt Enabled. 481 * |[2] |RESUMEIEN |Resume 482 * | | |This bit enables the Resume interrupt. 483 * | | |0 = Resume interrupt Disabled. 484 * | | |1 = Resume interrupt Enabled. 485 * |[3] |SUSPENDIEN|Suspend Request 486 * | | |This bit enables the Suspend interrupt. 487 * | | |0 = Suspend interrupt Disabled. 488 * | | |1 = Suspend interrupt Enabled. 489 * |[4] |HISPDIEN |High-speed Settle 490 * | | |This bit enables the high-speed settle interrupt. 491 * | | |0 = High-speed settle interrupt Disabled. 492 * | | |1 = High-speed settle interrupt Enabled. 493 * |[5] |DMADONEIEN|DMA Completion Interrupt 494 * | | |This bit enables the DMA completion interrupt 495 * | | |0 = DMA completion interrupt Disabled. 496 * | | |1 = DMA completion interrupt Enabled. 497 * |[6] |PHYCLKVLDIEN|Usable Clock Interrupt 498 * | | |This bit enables the usable clock interrupt. 499 * | | |0 = Usable clock interrupt Disabled. 500 * | | |1 = Usable clock interrupt Enabled. 501 * |[8] |VBUSDETIEN|VBUS Detection Interrupt Enable Bit 502 * | | |This bit enables the VBUS floating detection interrupt. 503 * | | |0 = VBUS floating detection interrupt Disabled. 504 * | | |1 = VBUS floating detection interrupt Enabled. 505 * @var HSUSBD_T::OPER 506 * Offset: 0x18 USB Operational Register 507 * --------------------------------------------------------------------------------------------------- 508 * |Bits |Field |Descriptions 509 * | :----: | :----: | :---- | 510 * |[0] |RESUMEEN |Generate Resume 511 * | | |0 = No Resume sequence to be initiated to the host. 512 * | | |1 = A Resume sequence to be initiated to the host if device remote wakeup is enabled 513 * | | |This bit is self-clearing. 514 * |[1] |HISPDEN |USB High-speed 515 * | | |0 = The USB device controller to suppress the chirp-sequence during reset protocol, thereby allowing the USB device controller to settle in full-speed, even though it is connected to a USB2.0 Host. 516 * | | |1 = The USB device controller to initiate a chirp-sequence during reset protocol. 517 * |[2] |CURSPD |USB Current Speed 518 * | | |0 = The device has settled in Full Speed. 519 * | | |1 = The USB device controller has settled in High-speed. 520 * @var HSUSBD_T::FRAMECNT 521 * Offset: 0x1C USB Frame Count Register 522 * --------------------------------------------------------------------------------------------------- 523 * |Bits |Field |Descriptions 524 * | :----: | :----: | :---- | 525 * |[2:0] |MFRAMECNT |Micro-frame Counter 526 * | | |This field contains the micro-frame number for the frame number in the frame counter field. 527 * |[13:3] |FRAMECNT |Frame Counter 528 * | | |This field contains the frame count from the most recent start-of-frame packet. 529 * @var HSUSBD_T::FADDR 530 * Offset: 0x20 USB Function Address Register 531 * --------------------------------------------------------------------------------------------------- 532 * |Bits |Field |Descriptions 533 * | :----: | :----: | :---- | 534 * |[6:0] |FADDR |USB Function Address 535 * | | |This field contains the current USB address of the device 536 * | | |This field is cleared when a root port reset is detected 537 * @var HSUSBD_T::TEST 538 * Offset: 0x24 USB Test Mode Register 539 * --------------------------------------------------------------------------------------------------- 540 * |Bits |Field |Descriptions 541 * | :----: | :----: | :---- | 542 * |[2:0] |TESTMODE |Test Mode Selection 543 * | | |000 = Normal Operation. 544 * | | |001 = Test_J. 545 * | | |010 = Test_K. 546 * | | |011 = Test_SE0_NAK. 547 * | | |100 = Test_Packet. 548 * | | |101 = Test_Force_Enable. 549 * | | |110 = Reserved. 550 * | | |111 = Reserved. 551 * | | |Note: This field is cleared when root port reset is detected. 552 * @var HSUSBD_T::CEPDAT 553 * Offset: 0x28 Control-Endpoint Data Buffer 554 * --------------------------------------------------------------------------------------------------- 555 * |Bits |Field |Descriptions 556 * | :----: | :----: | :---- | 557 * |[31:0] |DAT |Control-endpoint Data Buffer 558 * | | |Control endpoint data buffer for the buffer transaction (read or write). 559 * | | |Note: Only word access is supported. 560 * @var HSUSBD_T::CEPDAT_BYTE 561 * Offset: 0x28 Control-Endpoint Data Buffer 562 * --------------------------------------------------------------------------------------------------- 563 * |Bits |Field |Descriptions 564 * | :----: | :----: | :---- | 565 * |[7:0] |DAT |Control-endpoint Data Buffer 566 * | | |Control endpoint data buffer for the buffer transaction (read or write). 567 * | | |Note: Only byte access is supported. 568 * @var HSUSBD_T::CEPCTL 569 * Offset: 0x2C Control-Endpoint Control Register 570 * --------------------------------------------------------------------------------------------------- 571 * |Bits |Field |Descriptions 572 * | :----: | :----: | :---- | 573 * |[0] |NAKCLR |No Acknowledge Control 574 * | | |This bit plays a crucial role in any control transfer. 575 * | | |0 = The bit is being cleared by the local CPU by writing zero, the USB device controller will be responding with NAKs for the subsequent status phase 576 * | | |This mechanism holds the host from moving to the next request, until the local CPU is also ready to process the next request. 577 * | | |1 = This bit is set to one by the USB device controller, whenever a setup token is received 578 * | | |The local CPU can take its own time to finish off any house-keeping work based on the request and then clear this bit. 579 * | | |Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated. 580 * |[1] |STALLEN |Stall Enable Bit 581 * | | |When this stall bit is set, the control endpoint sends a stall handshake in response to any in or out token thereafter 582 * | | |This is typically used for response to invalid/unsupported requests 583 * | | |When this bit is being set the NAK clear bit has to be cleared at the same time since the NAK clear bit has highest priority than STALL 584 * | | |It is automatically cleared on receipt of a next setup-token 585 * | | |So, the local CPU need not write again to clear this bit. 586 * | | |0 = No sends a stall handshake in response to any in or out token thereafter. 587 * | | |1 = The control endpoint sends a stall handshake in response to any in or out token thereafter. 588 * | | |Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated. 589 * |[2] |ZEROLEN |Zero Packet Length 590 * | | |This bit is valid for Auto Validation mode only. 591 * | | |0 = No zero length packet to the host during Data stage to an IN token. 592 * | | |1 = USB device controller can send a zero length packet to the host during Data stage to an IN token 593 * | | |This bit gets cleared once the zero length data packet is sent 594 * | | |So, the local CPU need not write again to clear this bit. 595 * |[3] |FLUSH |CEP-flush Bit 596 * | | |0 = No the packet buffer and its corresponding USBD_CEPDATCNT register to be cleared. 597 * | | |1 = The packet buffer and its corresponding USBD_CEPDATCNT register to be cleared 598 * | | |This bit is self-cleaning. 599 * @var HSUSBD_T::CEPINTEN 600 * Offset: 0x30 Control-Endpoint Interrupt Enable 601 * --------------------------------------------------------------------------------------------------- 602 * |Bits |Field |Descriptions 603 * | :----: | :----: | :---- | 604 * |[0] |SETUPTKIEN|Setup Token Interrupt Enable Bit 605 * | | |0 = The SETUP token interrupt in Control Endpoint Disabled. 606 * | | |1 = The SETUP token interrupt in Control Endpoint Enabled. 607 * |[1] |SETUPPKIEN|Setup Packet Interrupt 608 * | | |0 = The SETUP packet interrupt in Control Endpoint Disabled. 609 * | | |1 = The SETUP packet interrupt in Control Endpoint Enabled. 610 * |[2] |OUTTKIEN |Out Token Interrupt 611 * | | |0 = The OUT token interrupt in Control Endpoint Disabled. 612 * | | |1 = The OUT token interrupt in Control Endpoint Enabled. 613 * |[3] |INTKIEN |In Token Interrupt 614 * | | |0 = The IN token interrupt in Control Endpoint Disabled. 615 * | | |1 = The IN token interrupt in Control Endpoint Enabled. 616 * |[4] |PINGIEN |Ping Token Interrupt 617 * | | |0 = The ping token interrupt in Control Endpoint Disabled. 618 * | | |1 = The ping token interrupt Control Endpoint Enabled. 619 * |[5] |TXPKIEN |Data Packet Transmitted Interrupt 620 * | | |0 = The data packet transmitted interrupt in Control Endpoint Disabled. 621 * | | |1 = The data packet transmitted interrupt in Control Endpoint Enabled. 622 * |[6] |RXPKIEN |Data Packet Received Interrupt 623 * | | |0 = The data received interrupt in Control Endpoint Disabled. 624 * | | |1 = The data received interrupt in Control Endpoint Enabled. 625 * |[7] |NAKIEN |NAK Sent Interrupt 626 * | | |0 = The NAK sent interrupt in Control Endpoint Disabled. 627 * | | |1 = The NAK sent interrupt in Control Endpoint Enabled. 628 * |[8] |STALLIEN |STALL Sent Interrupt 629 * | | |0 = The STALL sent interrupt in Control Endpoint Disabled. 630 * | | |1 = The STALL sent interrupt in Control Endpoint Enabled. 631 * |[9] |ERRIEN |USB Error Interrupt 632 * | | |0 = The USB Error interrupt in Control Endpoint Disabled. 633 * | | |1 = The USB Error interrupt in Control Endpoint Enabled. 634 * |[10] |STSDONEIEN|Status Completion Interrupt 635 * | | |0 = The Status Completion interrupt in Control Endpoint Disabled. 636 * | | |1 = The Status Completion interrupt in Control Endpoint Enabled. 637 * |[11] |BUFFULLIEN|Buffer Full Interrupt 638 * | | |0 = The buffer full interrupt in Control Endpoint Disabled. 639 * | | |1 = The buffer full interrupt in Control Endpoint Enabled. 640 * |[12] |BUFEMPTYIEN|Buffer Empty Interrupt 641 * | | |0 = The buffer empty interrupt in Control Endpoint Disabled. 642 * | | |1= The buffer empty interrupt in Control Endpoint Enabled. 643 * @var HSUSBD_T::CEPINTSTS 644 * Offset: 0x34 Control-Endpoint Interrupt Status 645 * --------------------------------------------------------------------------------------------------- 646 * |Bits |Field |Descriptions 647 * | :----: | :----: | :---- | 648 * |[0] |SETUPTKIF |Setup Token Interrupt 649 * | | |0 = Not a Setup token is received. 650 * | | |1 = A Setup token is received. Writing 1 clears this status bit 651 * | | |Note: Write 1 to clear this bit to 0. 652 * |[1] |SETUPPKIF |Setup Packet Interrupt 653 * | | |This bit must be cleared (by writing 1) before the next setup packet can be received 654 * | | |If the bit is not cleared, then the successive setup packets will be overwritten in the setup packet buffer. 655 * | | |0 = Not a Setup packet has been received from the host. 656 * | | |1 = A Setup packet has been received from the host. 657 * | | |Note: Write 1 to clear this bit to 0. 658 * |[2] |OUTTKIF |Out Token Interrupt 659 * | | |0 = The control-endpoint does not received an OUT token from the host. 660 * | | |1 = The control-endpoint receives an OUT token from the host. 661 * | | |Note: Write 1 to clear this bit to 0. 662 * |[3] |INTKIF |in Token Interrupt 663 * | | |0 = The control-endpoint does not received an IN token from the host. 664 * | | |1 = The control-endpoint receives an IN token from the host. 665 * | | |Note: Write 1 to clear this bit to 0. 666 * |[4] |PINGIF |Ping Token Interrupt 667 * | | |0 = The control-endpoint does not received a ping token from the host. 668 * | | |1 = The control-endpoint receives a ping token from the host. 669 * | | |Note: Write 1 to clear this bit to 0. 670 * |[5] |TXPKIF |Data Packet Transmitted Interrupt 671 * | | |0 = Not a data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same. 672 * | | |1 = A data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same. 673 * | | |Note: Write 1 to clear this bit to 0. 674 * |[6] |RXPKIF |Data Packet Received Interrupt 675 * | | |0 = Not a data packet is successfully received from the host for an OUT-token and an ACK is sent to the host. 676 * | | |1 = A data packet is successfully received from the host for an OUT-token and an ACK is sent to the host. 677 * | | |Note: Write 1 to clear this bit to 0. 678 * |[7] |NAKIF |NAK Sent Interrupt 679 * | | |0 = Not a NAK-token is sent in response to an IN/OUT token. 680 * | | |1 = A NAK-token is sent in response to an IN/OUT token. 681 * | | |Note: Write 1 to clear this bit to 0. 682 * |[8] |STALLIF |STALL Sent Interrupt 683 * | | |0 = Not a stall-token is sent in response to an IN/OUT token. 684 * | | |1 = A stall-token is sent in response to an IN/OUT token. 685 * | | |Note: Write 1 to clear this bit to 0. 686 * |[9] |ERRIF |USB Error Interrupt 687 * | | |0 = No error had occurred during the transaction. 688 * | | |1 = An error had occurred during the transaction. 689 * | | |Note: Write 1 to clear this bit to 0. 690 * |[10] |STSDONEIF |Status Completion Interrupt 691 * | | |0 = Not a USB transaction has completed successfully. 692 * | | |1 = The status stage of a USB transaction has completed successfully. 693 * | | |Note: Write 1 to clear this bit to 0. 694 * |[11] |BUFFULLIF |Buffer Full Interrupt 695 * | | |0 = The control-endpoint buffer is not full. 696 * | | |1 = The control-endpoint buffer is full. 697 * | | |Note: Write 1 to clear this bit to 0. 698 * |[12] |BUFEMPTYIF|Buffer Empty Interrupt 699 * | | |0 = The control-endpoint buffer is not empty. 700 * | | |1 = The control-endpoint buffer is empty. 701 * | | |Note: Write 1 to clear this bit to 0. 702 * @var HSUSBD_T::CEPTXCNT 703 * Offset: 0x38 Control-Endpoint In-transfer Data Count 704 * --------------------------------------------------------------------------------------------------- 705 * |Bits |Field |Descriptions 706 * | :----: | :----: | :---- | 707 * |[7:0] |TXCNT |In-transfer Data Count 708 * | | |There is no mode selection for the control endpoint (but it operates like manual mode).The local-CPU has to fill the control-endpoint buffer with the data to be sent for an in-token and to write the count of bytes in this register 709 * | | |When zero is written into this field, a zero length packet is sent to the host 710 * | | |When the count written in the register is more than the MPS, the data sent will be of only MPS. 711 * @var HSUSBD_T::CEPRXCNT 712 * Offset: 0x3C Control-Endpoint Out-transfer Data Count 713 * --------------------------------------------------------------------------------------------------- 714 * |Bits |Field |Descriptions 715 * | :----: | :----: | :---- | 716 * |[7:0] |RXCNT |Out-transfer Data Count 717 * | | |The USB device controller maintains the count of the data received in case of an out transfer, during the control transfer. 718 * @var HSUSBD_T::CEPDATCNT 719 * Offset: 0x40 Control-Endpoint data count 720 * --------------------------------------------------------------------------------------------------- 721 * |Bits |Field |Descriptions 722 * | :----: | :----: | :---- | 723 * |[15:0] |DATCNT |Control-endpoint Data Count 724 * | | |The USB device controller maintains the count of the data of control-endpoint. 725 * @var HSUSBD_T::SETUP1_0 726 * Offset: 0x44 Setup1 & Setup0 bytes 727 * --------------------------------------------------------------------------------------------------- 728 * |Bits |Field |Descriptions 729 * | :----: | :----: | :---- | 730 * |[7:0] |SETUP0 |Setup Byte 0[7:0] 731 * | | |This register provides byte 0 of the last setup packet received 732 * | | |For a Standard Device Request, the following bmRequestType information is returned. 733 * | | |Bit 7(Direction): 734 * | | | 0: Host to device 735 * | | | 1: Device to host 736 * | | |Bit 6-5 (Type): 737 * | | | 00: Standard 738 * | | | 01: Class 739 * | | | 10: Vendor 740 * | | | 11: Reserved 741 * | | |Bit 4-0 (Recipient) 742 * | | | 00000: Device 743 * | | | 00001: Interface 744 * | | | 00010: Endpoint 745 * | | | 00011: Other 746 * | | | Others: Reserved 747 * |[15:8] |SETUP1 |Setup Byte 1[15:8] 748 * | | |This register provides byte 1 of the last setup packet received 749 * | | |For a Standard Device Request, the following bRequest Code information is returned. 750 * | | |00000000 = Get Status. 751 * | | |00000001 = Clear Feature. 752 * | | |00000010 = Reserved. 753 * | | |00000011 = Set Feature. 754 * | | |00000100 = Reserved. 755 * | | |00000101 = Set Address. 756 * | | |00000110 = Get Descriptor. 757 * | | |00000111 = Set Descriptor. 758 * | | |00001000 = Get Configuration. 759 * | | |00001001 = Set Configuration. 760 * | | |00001010 = Get Interface. 761 * | | |00001011 = Set Interface. 762 * | | |00001100 = Sync Frame. 763 * @var HSUSBD_T::SETUP3_2 764 * Offset: 0x48 Setup3 & Setup2 Bytes 765 * --------------------------------------------------------------------------------------------------- 766 * |Bits |Field |Descriptions 767 * | :----: | :----: | :---- | 768 * |[7:0] |SETUP2 |Setup Byte 2 [7:0] 769 * | | |This register provides byte 2 of the last setup packet received 770 * | | |For a Standard Device Request, the least significant byte of the wValue field is returned 771 * |[15:8] |SETUP3 |Setup Byte 3 [15:8] 772 * | | |This register provides byte 3 of the last setup packet received 773 * | | |For a Standard Device Request, the most significant byte of the wValue field is returned. 774 * @var HSUSBD_T::SETUP5_4 775 * Offset: 0x4C Setup5 & Setup4 Bytes 776 * --------------------------------------------------------------------------------------------------- 777 * |Bits |Field |Descriptions 778 * | :----: | :----: | :---- | 779 * |[7:0] |SETUP4 |Setup Byte 4[7:0] 780 * | | |This register provides byte 4 of the last setup packet received 781 * | | |For a Standard Device Request, the least significant byte of the wIndex is returned. 782 * |[15:8] |SETUP5 |Setup Byte 5[15:8] 783 * | | |This register provides byte 5 of the last setup packet received 784 * | | |For a Standard Device Request, the most significant byte of the wIndex field is returned. 785 * @var HSUSBD_T::SETUP7_6 786 * Offset: 0x50 Setup7 & Setup6 Bytes 787 * --------------------------------------------------------------------------------------------------- 788 * |Bits |Field |Descriptions 789 * | :----: | :----: | :---- | 790 * |[7:0] |SETUP6 |Setup Byte 6[7:0] 791 * | | |This register provides byte 6 of the last setup packet received 792 * | | |For a Standard Device Request, the least significant byte of the wLength field is returned. 793 * |[15:8] |SETUP7 |Setup Byte 7[15:8] 794 * | | |This register provides byte 7 of the last setup packet received 795 * | | |For a Standard Device Request, the most significant byte of the wLength field is returned. 796 * @var HSUSBD_T::CEPBUFST 797 * Offset: 0x54 Control Endpoint RAM Start Address Register 798 * --------------------------------------------------------------------------------------------------- 799 * |Bits |Field |Descriptions 800 * | :----: | :----: | :---- | 801 * |[11:0] |SADDR |Control-endpoint Start Address 802 * | | |This is the start-address of the RAM space allocated for the control-endpoint. 803 * @var HSUSBD_T::CEPBUFEND 804 * Offset: 0x58 Control Endpoint RAM End Address Register 805 * --------------------------------------------------------------------------------------------------- 806 * |Bits |Field |Descriptions 807 * | :----: | :----: | :---- | 808 * |[11:0] |EADDR |Control-endpoint End Address 809 * | | |This is the end-address of the RAM space allocated for the control-endpoint. 810 * @var HSUSBD_T::DMACTL 811 * Offset: 0x5C DMA Control Status Register 812 * --------------------------------------------------------------------------------------------------- 813 * |Bits |Field |Descriptions 814 * | :----: | :----: | :---- | 815 * |[3:0] |EPNUM |DMA Endpoint Address Bits 816 * | | |Used to define the Endpoint Address 817 * |[4] |DMARD |DMA Operation 818 * | | |0 : The operation is a DMA write (read from USB buffer) 819 * | | |DMA will check endpoint data available count (USBD_EPxDATCNT) according to EPNM setting before to perform DMA write operation. 820 * | | |1 : The operation is a DMA read (write to USB buffer). 821 * |[5] |DMAEN |DMA Enable Bit 822 * | | |0 : DMA function Disabled. 823 * | | |1 : DMA function Enabled. 824 * |[6] |SGEN |Scatter Gather Function Enable Bit 825 * | | |0 : Scatter gather function Disabled. 826 * | | |1 : Scatter gather function Enabled. 827 * |[7] |DMARST |Reset DMA State Machine 828 * | | |0 : No reset the DMA state machine. 829 * | | |1 : Reset the DMA state machine. 830 * |[8] |SVINEP |Serve IN Endpoint 831 * | | |This bit is used to specify DMA serving endpoint-IN endpoint or OUT endpoint. 832 * | | |0: DMA serves OUT endpoint 833 * | | |1: DMA serves IN endpoint 834 * @var HSUSBD_T::DMACNT 835 * Offset: 0x60 DMA Count Register 836 * --------------------------------------------------------------------------------------------------- 837 * |Bits |Field |Descriptions 838 * | :----: | :----: | :---- | 839 * |[19:0] |DMACNT |DMA Transfer Count 840 * | | |The transfer count of the DMA operation to be performed is written to this register. 841 * @var HSUSBD_T::DMAADDR 842 * Offset: 0x700 AHB DMA Address Register 843 * --------------------------------------------------------------------------------------------------- 844 * |Bits |Field |Descriptions 845 * | :----: | :----: | :---- | 846 * |[31:0] |DMAADDR |DMAADDR 847 * | | |The register specifies the address from which the DMA has to read / write 848 * | | |The address must WORD (32-bit) aligned. 849 * @var HSUSBD_T::PHYCTL 850 * Offset: 0x704 USB PHY Control Register 851 * --------------------------------------------------------------------------------------------------- 852 * |Bits |Field |Descriptions 853 * | :----: | :----: | :---- | 854 * |[8] |DPPUEN |DP Pull-up 855 * | | |0 = Pull-up resistor on D+ Disabled. 856 * | | |1 = Pull-up resistor on D+ Enabled. 857 * |[9] |PHYEN |PHY Suspend Enable Bit 858 * | | |0 = The USB PHY is suspend. 859 * | | |1 = The USB PHY is not suspend. 860 * |[24] |VBUSWKEN |Wake-up Enable Bit 861 * | | |0 = The wake-up function Disabled. 862 * | | |1 = The wake-up function Enabled. 863 * |[31] |VBUSDET |VBUS Status 864 * | | |0 = The VBUS is not detected yet. 865 * | | |1 = The VBUS is detected. 866 */ 867 868 __I uint32_t GINTSTS; /*!< [0x0000] Global Interrupt Status Register */ 869 /// @cond HIDDEN_SYMBOLS 870 __I uint32_t RESERVE0[1]; 871 /// @endcond //HIDDEN_SYMBOLS 872 __IO uint32_t GINTEN; /*!< [0x0008] Global Interrupt Enable Register */ 873 /// @cond HIDDEN_SYMBOLS 874 __I uint32_t RESERVE1[1]; 875 /// @endcond //HIDDEN_SYMBOLS 876 __IO uint32_t BUSINTSTS; /*!< [0x0010] USB Bus Interrupt Status Register */ 877 __IO uint32_t BUSINTEN; /*!< [0x0014] USB Bus Interrupt Enable Register */ 878 __IO uint32_t OPER; /*!< [0x0018] USB Operational Register */ 879 __I uint32_t FRAMECNT; /*!< [0x001c] USB Frame Count Register */ 880 __IO uint32_t FADDR; /*!< [0x0020] USB Function Address Register */ 881 __IO uint32_t TEST; /*!< [0x0024] USB Test Mode Register */ 882 883 union 884 { 885 __IO uint32_t CEPDAT; 886 __IO uint8_t CEPDAT_BYTE; 887 888 }; /*!< [0x0028] Control-Endpoint Data Buffer */ 889 890 __IO uint32_t CEPCTL; /*!< [0x002c] Control-Endpoint Control Register */ 891 __IO uint32_t CEPINTEN; /*!< [0x0030] Control-Endpoint Interrupt Enable */ 892 __IO uint32_t CEPINTSTS; /*!< [0x0034] Control-Endpoint Interrupt Status */ 893 __IO uint32_t CEPTXCNT; /*!< [0x0038] Control-Endpoint In-transfer Data Count */ 894 __I uint32_t CEPRXCNT; /*!< [0x003c] Control-Endpoint Out-transfer Data Count */ 895 __I uint32_t CEPDATCNT; /*!< [0x0040] Control-Endpoint data count */ 896 __I uint32_t SETUP1_0; /*!< [0x0044] Setup1 & Setup0 bytes */ 897 __I uint32_t SETUP3_2; /*!< [0x0048] Setup3 & Setup2 Bytes */ 898 __I uint32_t SETUP5_4; /*!< [0x004c] Setup5 & Setup4 Bytes */ 899 __I uint32_t SETUP7_6; /*!< [0x0050] Setup7 & Setup6 Bytes */ 900 __IO uint32_t CEPBUFST; /*!< [0x0054] Control Endpoint RAM Start Address Register */ 901 __IO uint32_t CEPBUFEND; /*!< [0x0058] Control Endpoint RAM End Address Register */ 902 __IO uint32_t DMACTL; /*!< [0x005c] DMA Control Status Register */ 903 __IO uint32_t DMACNT; /*!< [0x0060] DMA Count Register */ 904 905 HSUSBD_EP_T EP[12]; 906 907 /// @cond HIDDEN_SYMBOLS 908 __I uint32_t RESERVE2[301]; 909 /// @endcond //HIDDEN_SYMBOLS 910 __IO uint32_t BCDC; /*!< [0x06f8] Battery Charge Detect Control Register */ 911 __IO uint32_t LPMCSR; /*!< [0x06fc] LPM Control and Status Register */ 912 __IO uint32_t DMAADDR; /*!< [0x0700] AHB DMA Address Register */ 913 __IO uint32_t PHYCTL; /*!< [0x0704] USB PHY Control Register */ 914 915 } HSUSBD_T; 916 917 /** 918 @addtogroup HSUSBD_CONST HSUSBD Bit Field Definition 919 Constant Definitions for HSUSBD Controller 920 @{ */ 921 922 #define HSUSBD_GINTSTS_USBIF_Pos (0) /*!< HSUSBD_T::GINTSTS: USBIF Position */ 923 #define HSUSBD_GINTSTS_USBIF_Msk (0x1ul << HSUSBD_GINTSTS_USBIF_Pos) /*!< HSUSBD_T::GINTSTS: USBIF Mask */ 924 925 #define HSUSBD_GINTSTS_CEPIF_Pos (1) /*!< HSUSBD_T::GINTSTS: CEPIF Position */ 926 #define HSUSBD_GINTSTS_CEPIF_Msk (0x1ul << HSUSBD_GINTSTS_CEPIF_Pos) /*!< HSUSBD_T::GINTSTS: CEPIF Mask */ 927 928 #define HSUSBD_GINTSTS_EPAIF_Pos (2) /*!< HSUSBD_T::GINTSTS: EPAIF Position */ 929 #define HSUSBD_GINTSTS_EPAIF_Msk (0x1ul << HSUSBD_GINTSTS_EPAIF_Pos) /*!< HSUSBD_T::GINTSTS: EPAIF Mask */ 930 931 #define HSUSBD_GINTSTS_EPBIF_Pos (3) /*!< HSUSBD_T::GINTSTS: EPBIF Position */ 932 #define HSUSBD_GINTSTS_EPBIF_Msk (0x1ul << HSUSBD_GINTSTS_EPBIF_Pos) /*!< HSUSBD_T::GINTSTS: EPBIF Mask */ 933 934 #define HSUSBD_GINTSTS_EPCIF_Pos (4) /*!< HSUSBD_T::GINTSTS: EPCIF Position */ 935 #define HSUSBD_GINTSTS_EPCIF_Msk (0x1ul << HSUSBD_GINTSTS_EPCIF_Pos) /*!< HSUSBD_T::GINTSTS: EPCIF Mask */ 936 937 #define HSUSBD_GINTSTS_EPDIF_Pos (5) /*!< HSUSBD_T::GINTSTS: EPDIF Position */ 938 #define HSUSBD_GINTSTS_EPDIF_Msk (0x1ul << HSUSBD_GINTSTS_EPDIF_Pos) /*!< HSUSBD_T::GINTSTS: EPDIF Mask */ 939 940 #define HSUSBD_GINTSTS_EPEIF_Pos (6) /*!< HSUSBD_T::GINTSTS: EPEIF Position */ 941 #define HSUSBD_GINTSTS_EPEIF_Msk (0x1ul << HSUSBD_GINTSTS_EPEIF_Pos) /*!< HSUSBD_T::GINTSTS: EPEIF Mask */ 942 943 #define HSUSBD_GINTSTS_EPFIF_Pos (7) /*!< HSUSBD_T::GINTSTS: EPFIF Position */ 944 #define HSUSBD_GINTSTS_EPFIF_Msk (0x1ul << HSUSBD_GINTSTS_EPFIF_Pos) /*!< HSUSBD_T::GINTSTS: EPFIF Mask */ 945 946 #define HSUSBD_GINTSTS_EPGIF_Pos (8) /*!< HSUSBD_T::GINTSTS: EPGIF Position */ 947 #define HSUSBD_GINTSTS_EPGIF_Msk (0x1ul << HSUSBD_GINTSTS_EPGIF_Pos) /*!< HSUSBD_T::GINTSTS: EPGIF Mask */ 948 949 #define HSUSBD_GINTSTS_EPHIF_Pos (9) /*!< HSUSBD_T::GINTSTS: EPHIF Position */ 950 #define HSUSBD_GINTSTS_EPHIF_Msk (0x1ul << HSUSBD_GINTSTS_EPHIF_Pos) /*!< HSUSBD_T::GINTSTS: EPHIF Mask */ 951 952 #define HSUSBD_GINTSTS_EPIIF_Pos (10) /*!< HSUSBD_T::GINTSTS: EPIIF Position */ 953 #define HSUSBD_GINTSTS_EPIIF_Msk (0x1ul << HSUSBD_GINTSTS_EPIIF_Pos) /*!< HSUSBD_T::GINTSTS: EPIIF Mask */ 954 955 #define HSUSBD_GINTSTS_EPJIF_Pos (11) /*!< HSUSBD_T::GINTSTS: EPJIF Position */ 956 #define HSUSBD_GINTSTS_EPJIF_Msk (0x1ul << HSUSBD_GINTSTS_EPJIF_Pos) /*!< HSUSBD_T::GINTSTS: EPJIF Mask */ 957 958 #define HSUSBD_GINTSTS_EPKIF_Pos (12) /*!< HSUSBD_T::GINTSTS: EPKIF Position */ 959 #define HSUSBD_GINTSTS_EPKIF_Msk (0x1ul << HSUSBD_GINTSTS_EPKIF_Pos) /*!< HSUSBD_T::GINTSTS: EPKIF Mask */ 960 961 #define HSUSBD_GINTSTS_EPLIF_Pos (13) /*!< HSUSBD_T::GINTSTS: EPLIF Position */ 962 #define HSUSBD_GINTSTS_EPLIF_Msk (0x1ul << HSUSBD_GINTSTS_EPLIF_Pos) /*!< HSUSBD_T::GINTSTS: EPLIF Mask */ 963 964 #define HSUSBD_GINTEN_USBIEN_Pos (0) /*!< HSUSBD_T::GINTEN: USBIEN Position */ 965 #define HSUSBD_GINTEN_USBIEN_Msk (0x1ul << HSUSBD_GINTEN_USBIEN_Pos) /*!< HSUSBD_T::GINTEN: USBIEN Mask */ 966 967 #define HSUSBD_GINTEN_CEPIEN_Pos (1) /*!< HSUSBD_T::GINTEN: CEPIEN Position */ 968 #define HSUSBD_GINTEN_CEPIEN_Msk (0x1ul << HSUSBD_GINTEN_CEPIEN_Pos) /*!< HSUSBD_T::GINTEN: CEPIEN Mask */ 969 970 #define HSUSBD_GINTEN_EPAIEN_Pos (2) /*!< HSUSBD_T::GINTEN: EPAIEN Position */ 971 #define HSUSBD_GINTEN_EPAIEN_Msk (0x1ul << HSUSBD_GINTEN_EPAIEN_Pos) /*!< HSUSBD_T::GINTEN: EPAIEN Mask */ 972 973 #define HSUSBD_GINTEN_EPBIEN_Pos (3) /*!< HSUSBD_T::GINTEN: EPBIEN Position */ 974 #define HSUSBD_GINTEN_EPBIEN_Msk (0x1ul << HSUSBD_GINTEN_EPBIEN_Pos) /*!< HSUSBD_T::GINTEN: EPBIEN Mask */ 975 976 #define HSUSBD_GINTEN_EPCIEN_Pos (4) /*!< HSUSBD_T::GINTEN: EPCIEN Position */ 977 #define HSUSBD_GINTEN_EPCIEN_Msk (0x1ul << HSUSBD_GINTEN_EPCIEN_Pos) /*!< HSUSBD_T::GINTEN: EPCIEN Mask */ 978 979 #define HSUSBD_GINTEN_EPDIEN_Pos (5) /*!< HSUSBD_T::GINTEN: EPDIEN Position */ 980 #define HSUSBD_GINTEN_EPDIEN_Msk (0x1ul << HSUSBD_GINTEN_EPDIEN_Pos) /*!< HSUSBD_T::GINTEN: EPDIEN Mask */ 981 982 #define HSUSBD_GINTEN_EPEIEN_Pos (6) /*!< HSUSBD_T::GINTEN: EPEIEN Position */ 983 #define HSUSBD_GINTEN_EPEIEN_Msk (0x1ul << HSUSBD_GINTEN_EPEIEN_Pos) /*!< HSUSBD_T::GINTEN: EPEIEN Mask */ 984 985 #define HSUSBD_GINTEN_EPFIEN_Pos (7) /*!< HSUSBD_T::GINTEN: EPFIEN Position */ 986 #define HSUSBD_GINTEN_EPFIEN_Msk (0x1ul << HSUSBD_GINTEN_EPFIEN_Pos) /*!< HSUSBD_T::GINTEN: EPFIEN Mask */ 987 988 #define HSUSBD_GINTEN_EPGIEN_Pos (8) /*!< HSUSBD_T::GINTEN: EPGIEN Position */ 989 #define HSUSBD_GINTEN_EPGIEN_Msk (0x1ul << HSUSBD_GINTEN_EPGIEN_Pos) /*!< HSUSBD_T::GINTEN: EPGIEN Mask */ 990 991 #define HSUSBD_GINTEN_EPHIEN_Pos (9) /*!< HSUSBD_T::GINTEN: EPHIEN Position */ 992 #define HSUSBD_GINTEN_EPHIEN_Msk (0x1ul << HSUSBD_GINTEN_EPHIEN_Pos) /*!< HSUSBD_T::GINTEN: EPHIEN Mask */ 993 994 #define HSUSBD_GINTEN_EPIIEN_Pos (10) /*!< HSUSBD_T::GINTEN: EPIIEN Position */ 995 #define HSUSBD_GINTEN_EPIIEN_Msk (0x1ul << HSUSBD_GINTEN_EPIIEN_Pos) /*!< HSUSBD_T::GINTEN: EPIIEN Mask */ 996 997 #define HSUSBD_GINTEN_EPJIEN_Pos (11) /*!< HSUSBD_T::GINTEN: EPJIEN Position */ 998 #define HSUSBD_GINTEN_EPJIEN_Msk (0x1ul << HSUSBD_GINTEN_EPJIEN_Pos) /*!< HSUSBD_T::GINTEN: EPJIEN Mask */ 999 1000 #define HSUSBD_GINTEN_EPKIEN_Pos (12) /*!< HSUSBD_T::GINTEN: EPKIEN Position */ 1001 #define HSUSBD_GINTEN_EPKIEN_Msk (0x1ul << HSUSBD_GINTEN_EPKIEN_Pos) /*!< HSUSBD_T::GINTEN: EPKIEN Mask */ 1002 1003 #define HSUSBD_GINTEN_EPLIEN_Pos (13) /*!< HSUSBD_T::GINTEN: EPLIEN Position */ 1004 #define HSUSBD_GINTEN_EPLIEN_Msk (0x1ul << HSUSBD_GINTEN_EPLIEN_Pos) /*!< HSUSBD_T::GINTEN: EPLIEN Mask */ 1005 1006 #define HSUSBD_BUSINTSTS_SOFIF_Pos (0) /*!< HSUSBD_T::BUSINTSTS: SOFIF Position */ 1007 #define HSUSBD_BUSINTSTS_SOFIF_Msk (0x1ul << HSUSBD_BUSINTSTS_SOFIF_Pos) /*!< HSUSBD_T::BUSINTSTS: SOFIF Mask */ 1008 1009 #define HSUSBD_BUSINTSTS_RSTIF_Pos (1) /*!< HSUSBD_T::BUSINTSTS: RSTIF Position */ 1010 #define HSUSBD_BUSINTSTS_RSTIF_Msk (0x1ul << HSUSBD_BUSINTSTS_RSTIF_Pos) /*!< HSUSBD_T::BUSINTSTS: RSTIF Mask */ 1011 1012 #define HSUSBD_BUSINTSTS_RESUMEIF_Pos (2) /*!< HSUSBD_T::BUSINTSTS: RESUMEIF Position */ 1013 #define HSUSBD_BUSINTSTS_RESUMEIF_Msk (0x1ul << HSUSBD_BUSINTSTS_RESUMEIF_Pos) /*!< HSUSBD_T::BUSINTSTS: RESUMEIF Mask */ 1014 1015 #define HSUSBD_BUSINTSTS_SUSPENDIF_Pos (3) /*!< HSUSBD_T::BUSINTSTS: SUSPENDIF Position*/ 1016 #define HSUSBD_BUSINTSTS_SUSPENDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_SUSPENDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: SUSPENDIF Mask */ 1017 1018 #define HSUSBD_BUSINTSTS_HISPDIF_Pos (4) /*!< HSUSBD_T::BUSINTSTS: HISPDIF Position */ 1019 #define HSUSBD_BUSINTSTS_HISPDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_HISPDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: HISPDIF Mask */ 1020 1021 #define HSUSBD_BUSINTSTS_DMADONEIF_Pos (5) /*!< HSUSBD_T::BUSINTSTS: DMADONEIF Position*/ 1022 #define HSUSBD_BUSINTSTS_DMADONEIF_Msk (0x1ul << HSUSBD_BUSINTSTS_DMADONEIF_Pos) /*!< HSUSBD_T::BUSINTSTS: DMADONEIF Mask */ 1023 1024 #define HSUSBD_BUSINTSTS_PHYCLKVLDIF_Pos (6) /*!< HSUSBD_T::BUSINTSTS: PHYCLKVLDIF Position*/ 1025 #define HSUSBD_BUSINTSTS_PHYCLKVLDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_PHYCLKVLDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: PHYCLKVLDIF Mask */ 1026 1027 #define HSUSBD_BUSINTSTS_VBUSDETIF_Pos (8) /*!< HSUSBD_T::BUSINTSTS: VBUSDETIF Position*/ 1028 #define HSUSBD_BUSINTSTS_VBUSDETIF_Msk (0x1ul << HSUSBD_BUSINTSTS_VBUSDETIF_Pos) /*!< HSUSBD_T::BUSINTSTS: VBUSDETIF Mask */ 1029 1030 #define HSUSBD_BUSINTSTS_LPMTKNIF_Pos (9) /*!< HSUSBD_T::BUSINTSTS: LPMTKNIF Position */ 1031 #define HSUSBD_BUSINTSTS_LPMTKNIF_Msk (0x1ul << HSUSBD_BUSINTSTS_LPMTKNIF_Pos) /*!< HSUSBD_T::BUSINTSTS: LPMTKNIF Mask */ 1032 1033 #define HSUSBD_BUSINTEN_SOFIEN_Pos (0) /*!< HSUSBD_T::BUSINTEN: SOFIEN Position */ 1034 #define HSUSBD_BUSINTEN_SOFIEN_Msk (0x1ul << HSUSBD_BUSINTEN_SOFIEN_Pos) /*!< HSUSBD_T::BUSINTEN: SOFIEN Mask */ 1035 1036 #define HSUSBD_BUSINTEN_RSTIEN_Pos (1) /*!< HSUSBD_T::BUSINTEN: RSTIEN Position */ 1037 #define HSUSBD_BUSINTEN_RSTIEN_Msk (0x1ul << HSUSBD_BUSINTEN_RSTIEN_Pos) /*!< HSUSBD_T::BUSINTEN: RSTIEN Mask */ 1038 1039 #define HSUSBD_BUSINTEN_RESUMEIEN_Pos (2) /*!< HSUSBD_T::BUSINTEN: RESUMEIEN Position */ 1040 #define HSUSBD_BUSINTEN_RESUMEIEN_Msk (0x1ul << HSUSBD_BUSINTEN_RESUMEIEN_Pos) /*!< HSUSBD_T::BUSINTEN: RESUMEIEN Mask */ 1041 1042 #define HSUSBD_BUSINTEN_SUSPENDIEN_Pos (3) /*!< HSUSBD_T::BUSINTEN: SUSPENDIEN Position*/ 1043 #define HSUSBD_BUSINTEN_SUSPENDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_SUSPENDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: SUSPENDIEN Mask */ 1044 1045 #define HSUSBD_BUSINTEN_HISPDIEN_Pos (4) /*!< HSUSBD_T::BUSINTEN: HISPDIEN Position */ 1046 #define HSUSBD_BUSINTEN_HISPDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_HISPDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: HISPDIEN Mask */ 1047 1048 #define HSUSBD_BUSINTEN_DMADONEIEN_Pos (5) /*!< HSUSBD_T::BUSINTEN: DMADONEIEN Position*/ 1049 #define HSUSBD_BUSINTEN_DMADONEIEN_Msk (0x1ul << HSUSBD_BUSINTEN_DMADONEIEN_Pos) /*!< HSUSBD_T::BUSINTEN: DMADONEIEN Mask */ 1050 1051 #define HSUSBD_BUSINTEN_PHYCLKVLDIEN_Pos (6) /*!< HSUSBD_T::BUSINTEN: PHYCLKVLDIEN Position*/ 1052 #define HSUSBD_BUSINTEN_PHYCLKVLDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_PHYCLKVLDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: PHYCLKVLDIEN Mask */ 1053 1054 #define HSUSBD_BUSINTEN_VBUSDETIEN_Pos (8) /*!< HSUSBD_T::BUSINTEN: VBUSDETIEN Position*/ 1055 #define HSUSBD_BUSINTEN_VBUSDETIEN_Msk (0x1ul << HSUSBD_BUSINTEN_VBUSDETIEN_Pos) /*!< HSUSBD_T::BUSINTEN: VBUSDETIEN Mask */ 1056 1057 #define HSUSBD_BUSINTEN_LPMTKNIEN_Pos (9) /*!< HSUSBD_T::BUSINTEN: LPMTKNIEN Position */ 1058 #define HSUSBD_BUSINTEN_LPMTKNIEN_Msk (0x1ul << HSUSBD_BUSINTEN_LPMTKNIEN_Pos) /*!< HSUSBD_T::BUSINTEN: LPMTKNIEN Mask */ 1059 1060 #define HSUSBD_OPER_RESUMEEN_Pos (0) /*!< HSUSBD_T::OPER: RESUMEEN Position */ 1061 #define HSUSBD_OPER_RESUMEEN_Msk (0x1ul << HSUSBD_OPER_RESUMEEN_Pos) /*!< HSUSBD_T::OPER: RESUMEEN Mask */ 1062 1063 #define HSUSBD_OPER_HISPDEN_Pos (1) /*!< HSUSBD_T::OPER: HISPDEN Position */ 1064 #define HSUSBD_OPER_HISPDEN_Msk (0x1ul << HSUSBD_OPER_HISPDEN_Pos) /*!< HSUSBD_T::OPER: HISPDEN Mask */ 1065 1066 #define HSUSBD_OPER_CURSPD_Pos (2) /*!< HSUSBD_T::OPER: CURSPD Position */ 1067 #define HSUSBD_OPER_CURSPD_Msk (0x1ul << HSUSBD_OPER_CURSPD_Pos) /*!< HSUSBD_T::OPER: CURSPD Mask */ 1068 1069 #define HSUSBD_FRAMECNT_MFRAMECNT_Pos (0) /*!< HSUSBD_T::FRAMECNT: MFRAMECNT Position */ 1070 #define HSUSBD_FRAMECNT_MFRAMECNT_Msk (0x7ul << HSUSBD_FRAMECNT_MFRAMECNT_Pos) /*!< HSUSBD_T::FRAMECNT: MFRAMECNT Mask */ 1071 1072 #define HSUSBD_FRAMECNT_FRAMECNT_Pos (3) /*!< HSUSBD_T::FRAMECNT: FRAMECNT Position */ 1073 #define HSUSBD_FRAMECNT_FRAMECNT_Msk (0x7fful << HSUSBD_FRAMECNT_FRAMECNT_Pos) /*!< HSUSBD_T::FRAMECNT: FRAMECNT Mask */ 1074 1075 #define HSUSBD_FADDR_FADDR_Pos (0) /*!< HSUSBD_T::FADDR: FADDR Position */ 1076 #define HSUSBD_FADDR_FADDR_Msk (0x7ful << HSUSBD_FADDR_FADDR_Pos) /*!< HSUSBD_T::FADDR: FADDR Mask */ 1077 1078 #define HSUSBD_TEST_TESTMODE_Pos (0) /*!< HSUSBD_T::TEST: TESTMODE Position */ 1079 #define HSUSBD_TEST_TESTMODE_Msk (0x7ul << HSUSBD_TEST_TESTMODE_Pos) /*!< HSUSBD_T::TEST: TESTMODE Mask */ 1080 1081 #define HSUSBD_CEPDAT_DAT_Pos (0) /*!< HSUSBD_T::CEPDAT: DAT Position */ 1082 #define HSUSBD_CEPDAT_DAT_Msk (0xfffffffful << HSUSBD_CEPDAT_DAT_Pos) /*!< HSUSBD_T::CEPDAT: DAT Mask */ 1083 1084 #define HSUSBD_CEPCTL_NAKCLR_Pos (0) /*!< HSUSBD_T::CEPCTL: NAKCLR Position */ 1085 #define HSUSBD_CEPCTL_NAKCLR_Msk (0x1ul << HSUSBD_CEPCTL_NAKCLR_Pos) /*!< HSUSBD_T::CEPCTL: NAKCLR Mask */ 1086 1087 #define HSUSBD_CEPCTL_STALLEN_Pos (1) /*!< HSUSBD_T::CEPCTL: STALLEN Position */ 1088 #define HSUSBD_CEPCTL_STALLEN_Msk (0x1ul << HSUSBD_CEPCTL_STALLEN_Pos) /*!< HSUSBD_T::CEPCTL: STALLEN Mask */ 1089 1090 #define HSUSBD_CEPCTL_ZEROLEN_Pos (2) /*!< HSUSBD_T::CEPCTL: ZEROLEN Position */ 1091 #define HSUSBD_CEPCTL_ZEROLEN_Msk (0x1ul << HSUSBD_CEPCTL_ZEROLEN_Pos) /*!< HSUSBD_T::CEPCTL: ZEROLEN Mask */ 1092 1093 #define HSUSBD_CEPCTL_FLUSH_Pos (3) /*!< HSUSBD_T::CEPCTL: FLUSH Position */ 1094 #define HSUSBD_CEPCTL_FLUSH_Msk (0x1ul << HSUSBD_CEPCTL_FLUSH_Pos) /*!< HSUSBD_T::CEPCTL: FLUSH Mask */ 1095 1096 #define HSUSBD_CEPINTEN_SETUPTKIEN_Pos (0) /*!< HSUSBD_T::CEPINTEN: SETUPTKIEN Position*/ 1097 #define HSUSBD_CEPINTEN_SETUPTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_SETUPTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: SETUPTKIEN Mask */ 1098 1099 #define HSUSBD_CEPINTEN_SETUPPKIEN_Pos (1) /*!< HSUSBD_T::CEPINTEN: SETUPPKIEN Position*/ 1100 #define HSUSBD_CEPINTEN_SETUPPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_SETUPPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: SETUPPKIEN Mask */ 1101 1102 #define HSUSBD_CEPINTEN_OUTTKIEN_Pos (2) /*!< HSUSBD_T::CEPINTEN: OUTTKIEN Position */ 1103 #define HSUSBD_CEPINTEN_OUTTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_OUTTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: OUTTKIEN Mask */ 1104 1105 #define HSUSBD_CEPINTEN_INTKIEN_Pos (3) /*!< HSUSBD_T::CEPINTEN: INTKIEN Position */ 1106 #define HSUSBD_CEPINTEN_INTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_INTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: INTKIEN Mask */ 1107 1108 #define HSUSBD_CEPINTEN_PINGIEN_Pos (4) /*!< HSUSBD_T::CEPINTEN: PINGIEN Position */ 1109 #define HSUSBD_CEPINTEN_PINGIEN_Msk (0x1ul << HSUSBD_CEPINTEN_PINGIEN_Pos) /*!< HSUSBD_T::CEPINTEN: PINGIEN Mask */ 1110 1111 #define HSUSBD_CEPINTEN_TXPKIEN_Pos (5) /*!< HSUSBD_T::CEPINTEN: TXPKIEN Position */ 1112 #define HSUSBD_CEPINTEN_TXPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_TXPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: TXPKIEN Mask */ 1113 1114 #define HSUSBD_CEPINTEN_RXPKIEN_Pos (6) /*!< HSUSBD_T::CEPINTEN: RXPKIEN Position */ 1115 #define HSUSBD_CEPINTEN_RXPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_RXPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: RXPKIEN Mask */ 1116 1117 #define HSUSBD_CEPINTEN_NAKIEN_Pos (7) /*!< HSUSBD_T::CEPINTEN: NAKIEN Position */ 1118 #define HSUSBD_CEPINTEN_NAKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_NAKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: NAKIEN Mask */ 1119 1120 #define HSUSBD_CEPINTEN_STALLIEN_Pos (8) /*!< HSUSBD_T::CEPINTEN: STALLIEN Position */ 1121 #define HSUSBD_CEPINTEN_STALLIEN_Msk (0x1ul << HSUSBD_CEPINTEN_STALLIEN_Pos) /*!< HSUSBD_T::CEPINTEN: STALLIEN Mask */ 1122 1123 #define HSUSBD_CEPINTEN_ERRIEN_Pos (9) /*!< HSUSBD_T::CEPINTEN: ERRIEN Position */ 1124 #define HSUSBD_CEPINTEN_ERRIEN_Msk (0x1ul << HSUSBD_CEPINTEN_ERRIEN_Pos) /*!< HSUSBD_T::CEPINTEN: ERRIEN Mask */ 1125 1126 #define HSUSBD_CEPINTEN_STSDONEIEN_Pos (10) /*!< HSUSBD_T::CEPINTEN: STSDONEIEN Position*/ 1127 #define HSUSBD_CEPINTEN_STSDONEIEN_Msk (0x1ul << HSUSBD_CEPINTEN_STSDONEIEN_Pos) /*!< HSUSBD_T::CEPINTEN: STSDONEIEN Mask */ 1128 1129 #define HSUSBD_CEPINTEN_BUFFULLIEN_Pos (11) /*!< HSUSBD_T::CEPINTEN: BUFFULLIEN Position*/ 1130 #define HSUSBD_CEPINTEN_BUFFULLIEN_Msk (0x1ul << HSUSBD_CEPINTEN_BUFFULLIEN_Pos) /*!< HSUSBD_T::CEPINTEN: BUFFULLIEN Mask */ 1131 1132 #define HSUSBD_CEPINTEN_BUFEMPTYIEN_Pos (12) /*!< HSUSBD_T::CEPINTEN: BUFEMPTYIEN Position*/ 1133 #define HSUSBD_CEPINTEN_BUFEMPTYIEN_Msk (0x1ul << HSUSBD_CEPINTEN_BUFEMPTYIEN_Pos) /*!< HSUSBD_T::CEPINTEN: BUFEMPTYIEN Mask */ 1134 1135 #define HSUSBD_CEPINTSTS_SETUPTKIF_Pos (0) /*!< HSUSBD_T::CEPINTSTS: SETUPTKIF Position*/ 1136 #define HSUSBD_CEPINTSTS_SETUPTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_SETUPTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: SETUPTKIF Mask */ 1137 1138 #define HSUSBD_CEPINTSTS_SETUPPKIF_Pos (1) /*!< HSUSBD_T::CEPINTSTS: SETUPPKIF Position*/ 1139 #define HSUSBD_CEPINTSTS_SETUPPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_SETUPPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: SETUPPKIF Mask */ 1140 1141 #define HSUSBD_CEPINTSTS_OUTTKIF_Pos (2) /*!< HSUSBD_T::CEPINTSTS: OUTTKIF Position */ 1142 #define HSUSBD_CEPINTSTS_OUTTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_OUTTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: OUTTKIF Mask */ 1143 1144 #define HSUSBD_CEPINTSTS_INTKIF_Pos (3) /*!< HSUSBD_T::CEPINTSTS: INTKIF Position */ 1145 #define HSUSBD_CEPINTSTS_INTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_INTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: INTKIF Mask */ 1146 1147 #define HSUSBD_CEPINTSTS_PINGIF_Pos (4) /*!< HSUSBD_T::CEPINTSTS: PINGIF Position */ 1148 #define HSUSBD_CEPINTSTS_PINGIF_Msk (0x1ul << HSUSBD_CEPINTSTS_PINGIF_Pos) /*!< HSUSBD_T::CEPINTSTS: PINGIF Mask */ 1149 1150 #define HSUSBD_CEPINTSTS_TXPKIF_Pos (5) /*!< HSUSBD_T::CEPINTSTS: TXPKIF Position */ 1151 #define HSUSBD_CEPINTSTS_TXPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_TXPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: TXPKIF Mask */ 1152 1153 #define HSUSBD_CEPINTSTS_RXPKIF_Pos (6) /*!< HSUSBD_T::CEPINTSTS: RXPKIF Position */ 1154 #define HSUSBD_CEPINTSTS_RXPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_RXPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: RXPKIF Mask */ 1155 1156 #define HSUSBD_CEPINTSTS_NAKIF_Pos (7) /*!< HSUSBD_T::CEPINTSTS: NAKIF Position */ 1157 #define HSUSBD_CEPINTSTS_NAKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_NAKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: NAKIF Mask */ 1158 1159 #define HSUSBD_CEPINTSTS_STALLIF_Pos (8) /*!< HSUSBD_T::CEPINTSTS: STALLIF Position */ 1160 #define HSUSBD_CEPINTSTS_STALLIF_Msk (0x1ul << HSUSBD_CEPINTSTS_STALLIF_Pos) /*!< HSUSBD_T::CEPINTSTS: STALLIF Mask */ 1161 1162 #define HSUSBD_CEPINTSTS_ERRIF_Pos (9) /*!< HSUSBD_T::CEPINTSTS: ERRIF Position */ 1163 #define HSUSBD_CEPINTSTS_ERRIF_Msk (0x1ul << HSUSBD_CEPINTSTS_ERRIF_Pos) /*!< HSUSBD_T::CEPINTSTS: ERRIF Mask */ 1164 1165 #define HSUSBD_CEPINTSTS_STSDONEIF_Pos (10) /*!< HSUSBD_T::CEPINTSTS: STSDONEIF Position*/ 1166 #define HSUSBD_CEPINTSTS_STSDONEIF_Msk (0x1ul << HSUSBD_CEPINTSTS_STSDONEIF_Pos) /*!< HSUSBD_T::CEPINTSTS: STSDONEIF Mask */ 1167 1168 #define HSUSBD_CEPINTSTS_BUFFULLIF_Pos (11) /*!< HSUSBD_T::CEPINTSTS: BUFFULLIF Position*/ 1169 #define HSUSBD_CEPINTSTS_BUFFULLIF_Msk (0x1ul << HSUSBD_CEPINTSTS_BUFFULLIF_Pos) /*!< HSUSBD_T::CEPINTSTS: BUFFULLIF Mask */ 1170 1171 #define HSUSBD_CEPINTSTS_BUFEMPTYIF_Pos (12) /*!< HSUSBD_T::CEPINTSTS: BUFEMPTYIF Position*/ 1172 #define HSUSBD_CEPINTSTS_BUFEMPTYIF_Msk (0x1ul << HSUSBD_CEPINTSTS_BUFEMPTYIF_Pos) /*!< HSUSBD_T::CEPINTSTS: BUFEMPTYIF Mask */ 1173 1174 #define HSUSBD_CEPTXCNT_TXCNT_Pos (0) /*!< HSUSBD_T::CEPTXCNT: TXCNT Position */ 1175 #define HSUSBD_CEPTXCNT_TXCNT_Msk (0xfful << HSUSBD_CEPTXCNT_TXCNT_Pos) /*!< HSUSBD_T::CEPTXCNT: TXCNT Mask */ 1176 1177 #define HSUSBD_CEPRXCNT_RXCNT_Pos (0) /*!< HSUSBD_T::CEPRXCNT: RXCNT Position */ 1178 #define HSUSBD_CEPRXCNT_RXCNT_Msk (0xfful << HSUSBD_CEPRXCNT_RXCNT_Pos) /*!< HSUSBD_T::CEPRXCNT: RXCNT Mask */ 1179 1180 #define HSUSBD_CEPDATCNT_DATCNT_Pos (0) /*!< HSUSBD_T::CEPDATCNT: DATCNT Position */ 1181 #define HSUSBD_CEPDATCNT_DATCNT_Msk (0xfffful << HSUSBD_CEPDATCNT_DATCNT_Pos) /*!< HSUSBD_T::CEPDATCNT: DATCNT Mask */ 1182 1183 #define HSUSBD_SETUP1_0_SETUP0_Pos (0) /*!< HSUSBD_T::SETUP1_0: SETUP0 Position */ 1184 #define HSUSBD_SETUP1_0_SETUP0_Msk (0xfful << HSUSBD_SETUP1_0_SETUP0_Pos) /*!< HSUSBD_T::SETUP1_0: SETUP0 Mask */ 1185 1186 #define HSUSBD_SETUP1_0_SETUP1_Pos (8) /*!< HSUSBD_T::SETUP1_0: SETUP1 Position */ 1187 #define HSUSBD_SETUP1_0_SETUP1_Msk (0xfful << HSUSBD_SETUP1_0_SETUP1_Pos) /*!< HSUSBD_T::SETUP1_0: SETUP1 Mask */ 1188 1189 #define HSUSBD_SETUP3_2_SETUP2_Pos (0) /*!< HSUSBD_T::SETUP3_2: SETUP2 Position */ 1190 #define HSUSBD_SETUP3_2_SETUP2_Msk (0xfful << HSUSBD_SETUP3_2_SETUP2_Pos) /*!< HSUSBD_T::SETUP3_2: SETUP2 Mask */ 1191 1192 #define HSUSBD_SETUP3_2_SETUP3_Pos (8) /*!< HSUSBD_T::SETUP3_2: SETUP3 Position */ 1193 #define HSUSBD_SETUP3_2_SETUP3_Msk (0xfful << HSUSBD_SETUP3_2_SETUP3_Pos) /*!< HSUSBD_T::SETUP3_2: SETUP3 Mask */ 1194 1195 #define HSUSBD_SETUP5_4_SETUP4_Pos (0) /*!< HSUSBD_T::SETUP5_4: SETUP4 Position */ 1196 #define HSUSBD_SETUP5_4_SETUP4_Msk (0xfful << HSUSBD_SETUP5_4_SETUP4_Pos) /*!< HSUSBD_T::SETUP5_4: SETUP4 Mask */ 1197 1198 #define HSUSBD_SETUP5_4_SETUP5_Pos (8) /*!< HSUSBD_T::SETUP5_4: SETUP5 Position */ 1199 #define HSUSBD_SETUP5_4_SETUP5_Msk (0xfful << HSUSBD_SETUP5_4_SETUP5_Pos) /*!< HSUSBD_T::SETUP5_4: SETUP5 Mask */ 1200 1201 #define HSUSBD_SETUP7_6_SETUP6_Pos (0) /*!< HSUSBD_T::SETUP7_6: SETUP6 Position */ 1202 #define HSUSBD_SETUP7_6_SETUP6_Msk (0xfful << HSUSBD_SETUP7_6_SETUP6_Pos) /*!< HSUSBD_T::SETUP7_6: SETUP6 Mask */ 1203 1204 #define HSUSBD_SETUP7_6_SETUP7_Pos (8) /*!< HSUSBD_T::SETUP7_6: SETUP7 Position */ 1205 #define HSUSBD_SETUP7_6_SETUP7_Msk (0xfful << HSUSBD_SETUP7_6_SETUP7_Pos) /*!< HSUSBD_T::SETUP7_6: SETUP7 Mask */ 1206 1207 #define HSUSBD_CEPBUFST_SADDR_Pos (0) /*!< HSUSBD_T::CEPBUFST: SADDR Position */ 1208 #define HSUSBD_CEPBUFST_SADDR_Msk (0xffful << HSUSBD_CEPBUFST_SADDR_Pos) /*!< HSUSBD_T::CEPBUFST: SADDR Mask */ 1209 1210 #define HSUSBD_CEPBUFEND_EADDR_Pos (0) /*!< HSUSBD_T::CEPBUFEND: EADDR Position */ 1211 #define HSUSBD_CEPBUFEND_EADDR_Msk (0xffful << HSUSBD_CEPBUFEND_EADDR_Pos) /*!< HSUSBD_T::CEPBUFEND: EADDR Mask */ 1212 1213 #define HSUSBD_DMACTL_EPNUM_Pos (0) /*!< HSUSBD_T::DMACTL: EPNUM Position */ 1214 #define HSUSBD_DMACTL_EPNUM_Msk (0xful << HSUSBD_DMACTL_EPNUM_Pos) /*!< HSUSBD_T::DMACTL: EPNUM Mask */ 1215 1216 #define HSUSBD_DMACTL_DMARD_Pos (4) /*!< HSUSBD_T::DMACTL: DMARD Position */ 1217 #define HSUSBD_DMACTL_DMARD_Msk (0x1ul << HSUSBD_DMACTL_DMARD_Pos) /*!< HSUSBD_T::DMACTL: DMARD Mask */ 1218 1219 #define HSUSBD_DMACTL_DMAEN_Pos (5) /*!< HSUSBD_T::DMACTL: DMAEN Position */ 1220 #define HSUSBD_DMACTL_DMAEN_Msk (0x1ul << HSUSBD_DMACTL_DMAEN_Pos) /*!< HSUSBD_T::DMACTL: DMAEN Mask */ 1221 1222 #define HSUSBD_DMACTL_SGEN_Pos (6) /*!< HSUSBD_T::DMACTL: SGEN Position */ 1223 #define HSUSBD_DMACTL_SGEN_Msk (0x1ul << HSUSBD_DMACTL_SGEN_Pos) /*!< HSUSBD_T::DMACTL: SGEN Mask */ 1224 1225 #define HSUSBD_DMACTL_DMARST_Pos (7) /*!< HSUSBD_T::DMACTL: DMARST Position */ 1226 #define HSUSBD_DMACTL_DMARST_Msk (0x1ul << HSUSBD_DMACTL_DMARST_Pos) /*!< HSUSBD_T::DMACTL: DMARST Mask */ 1227 1228 #define HSUSBD_DMACTL_SVINEP_Pos (8) /*!< HSUSBD_T::DMACTL: SVINEP Position */ 1229 #define HSUSBD_DMACTL_SVINEP_Msk (0x1ul << HSUSBD_DMACTL_SVINEP_Pos) /*!< HSUSBD_T::DMACTL: SVINEP Mask */ 1230 1231 #define HSUSBD_DMACNT_DMACNT_Pos (0) /*!< HSUSBD_T::DMACNT: DMACNT Position */ 1232 #define HSUSBD_DMACNT_DMACNT_Msk (0xffffful << HSUSBD_DMACNT_DMACNT_Pos) /*!< HSUSBD_T::DMACNT: DMACNT Mask */ 1233 1234 #define HSUSBD_EPDAT_EPDAT_Pos (0) /*!< HSUSBD_T::EPDAT: EPDAT Position */ 1235 #define HSUSBD_EPDAT_EPDAT_Msk (0xfffffffful << HSUSBD_EPDAT_EPDAT_Pos) /*!< HSUSBD_T::EPDAT: EPDAT Mask */ 1236 1237 #define HSUSBD_EPINTSTS_BUFFULLIF_Pos (0) /*!< HSUSBD_T::EPINTSTS: BUFFULLIF Position */ 1238 #define HSUSBD_EPINTSTS_BUFFULLIF_Msk (0x1ul << HSUSBD_EPINTSTS_BUFFULLIF_Pos) /*!< HSUSBD_T::EPINTSTS: BUFFULLIF Mask */ 1239 1240 #define HSUSBD_EPINTSTS_BUFEMPTYIF_Pos (1) /*!< HSUSBD_T::EPINTSTS: BUFEMPTYIF Position*/ 1241 #define HSUSBD_EPINTSTS_BUFEMPTYIF_Msk (0x1ul << HSUSBD_EPINTSTS_BUFEMPTYIF_Pos) /*!< HSUSBD_T::EPINTSTS: BUFEMPTYIF Mask */ 1242 1243 #define HSUSBD_EPINTSTS_SHORTTXIF_Pos (2) /*!< HSUSBD_T::EPINTSTS: SHORTTXIF Position */ 1244 #define HSUSBD_EPINTSTS_SHORTTXIF_Msk (0x1ul << HSUSBD_EPINTSTS_SHORTTXIF_Pos) /*!< HSUSBD_T::EPINTSTS: SHORTTXIF Mask */ 1245 1246 #define HSUSBD_EPINTSTS_TXPKIF_Pos (3) /*!< HSUSBD_T::EPINTSTS: TXPKIF Position */ 1247 #define HSUSBD_EPINTSTS_TXPKIF_Msk (0x1ul << HSUSBD_EPINTSTS_TXPKIF_Pos) /*!< HSUSBD_T::EPINTSTS: TXPKIF Mask */ 1248 1249 #define HSUSBD_EPINTSTS_RXPKIF_Pos (4) /*!< HSUSBD_T::EPINTSTS: RXPKIF Position */ 1250 #define HSUSBD_EPINTSTS_RXPKIF_Msk (0x1ul << HSUSBD_EPINTSTS_RXPKIF_Pos) /*!< HSUSBD_T::EPINTSTS: RXPKIF Mask */ 1251 1252 #define HSUSBD_EPINTSTS_OUTTKIF_Pos (5) /*!< HSUSBD_T::EPINTSTS: OUTTKIF Position */ 1253 #define HSUSBD_EPINTSTS_OUTTKIF_Msk (0x1ul << HSUSBD_EPINTSTS_OUTTKIF_Pos) /*!< HSUSBD_T::EPINTSTS: OUTTKIF Mask */ 1254 1255 #define HSUSBD_EPINTSTS_INTKIF_Pos (6) /*!< HSUSBD_T::EPINTSTS: INTKIF Position */ 1256 #define HSUSBD_EPINTSTS_INTKIF_Msk (0x1ul << HSUSBD_EPINTSTS_INTKIF_Pos) /*!< HSUSBD_T::EPINTSTS: INTKIF Mask */ 1257 1258 #define HSUSBD_EPINTSTS_PINGIF_Pos (7) /*!< HSUSBD_T::EPINTSTS: PINGIF Position */ 1259 #define HSUSBD_EPINTSTS_PINGIF_Msk (0x1ul << HSUSBD_EPINTSTS_PINGIF_Pos) /*!< HSUSBD_T::EPINTSTS: PINGIF Mask */ 1260 1261 #define HSUSBD_EPINTSTS_NAKIF_Pos (8) /*!< HSUSBD_T::EPINTSTS: NAKIF Position */ 1262 #define HSUSBD_EPINTSTS_NAKIF_Msk (0x1ul << HSUSBD_EPINTSTS_NAKIF_Pos) /*!< HSUSBD_T::EPINTSTS: NAKIF Mask */ 1263 1264 #define HSUSBD_EPINTSTS_STALLIF_Pos (9) /*!< HSUSBD_T::EPINTSTS: STALLIF Position */ 1265 #define HSUSBD_EPINTSTS_STALLIF_Msk (0x1ul << HSUSBD_EPINTSTS_STALLIF_Pos) /*!< HSUSBD_T::EPINTSTS: STALLIF Mask */ 1266 1267 #define HSUSBD_EPINTSTS_NYETIF_Pos (10) /*!< HSUSBD_T::EPINTSTS: NYETIF Position */ 1268 #define HSUSBD_EPINTSTS_NYETIF_Msk (0x1ul << HSUSBD_EPINTSTS_NYETIF_Pos) /*!< HSUSBD_T::EPINTSTS: NYETIF Mask */ 1269 1270 #define HSUSBD_EPINTSTS_ERRIF_Pos (11) /*!< HSUSBD_T::EPINTSTS: ERRIF Position */ 1271 #define HSUSBD_EPINTSTS_ERRIF_Msk (0x1ul << HSUSBD_EPINTSTS_ERRIF_Pos) /*!< HSUSBD_T::EPINTSTS: ERRIF Mask */ 1272 1273 #define HSUSBD_EPINTSTS_SHORTRXIF_Pos (12) /*!< HSUSBD_T::EPINTSTS: SHORTRXIF Position */ 1274 #define HSUSBD_EPINTSTS_SHORTRXIF_Msk (0x1ul << HSUSBD_EPINTSTS_SHORTRXIF_Pos) /*!< HSUSBD_T::EPINTSTS: SHORTRXIF Mask */ 1275 1276 #define HSUSBD_EPINTEN_BUFFULLIEN_Pos (0) /*!< HSUSBD_T::EPINTEN: BUFFULLIEN Position */ 1277 #define HSUSBD_EPINTEN_BUFFULLIEN_Msk (0x1ul << HSUSBD_EPINTEN_BUFFULLIEN_Pos) /*!< HSUSBD_T::EPINTEN: BUFFULLIEN Mask */ 1278 1279 #define HSUSBD_EPINTEN_BUFEMPTYIEN_Pos (1) /*!< HSUSBD_T::EPINTEN: BUFEMPTYIEN Position*/ 1280 #define HSUSBD_EPINTEN_BUFEMPTYIEN_Msk (0x1ul << HSUSBD_EPINTEN_BUFEMPTYIEN_Pos) /*!< HSUSBD_T::EPINTEN: BUFEMPTYIEN Mask */ 1281 1282 #define HSUSBD_EPINTEN_SHORTTXIEN_Pos (2) /*!< HSUSBD_T::EPINTEN: SHORTTXIEN Position */ 1283 #define HSUSBD_EPINTEN_SHORTTXIEN_Msk (0x1ul << HSUSBD_EPINTEN_SHORTTXIEN_Pos) /*!< HSUSBD_T::EPINTEN: SHORTTXIEN Mask */ 1284 1285 #define HSUSBD_EPINTEN_TXPKIEN_Pos (3) /*!< HSUSBD_T::EPINTEN: TXPKIEN Position */ 1286 #define HSUSBD_EPINTEN_TXPKIEN_Msk (0x1ul << HSUSBD_EPINTEN_TXPKIEN_Pos) /*!< HSUSBD_T::EPINTEN: TXPKIEN Mask */ 1287 1288 #define HSUSBD_EPINTEN_RXPKIEN_Pos (4) /*!< HSUSBD_T::EPINTEN: RXPKIEN Position */ 1289 #define HSUSBD_EPINTEN_RXPKIEN_Msk (0x1ul << HSUSBD_EPINTEN_RXPKIEN_Pos) /*!< HSUSBD_T::EPINTEN: RXPKIEN Mask */ 1290 1291 #define HSUSBD_EPINTEN_OUTTKIEN_Pos (5) /*!< HSUSBD_T::EPINTEN: OUTTKIEN Position */ 1292 #define HSUSBD_EPINTEN_OUTTKIEN_Msk (0x1ul << HSUSBD_EPINTEN_OUTTKIEN_Pos) /*!< HSUSBD_T::EPINTEN: OUTTKIEN Mask */ 1293 1294 #define HSUSBD_EPINTEN_INTKIEN_Pos (6) /*!< HSUSBD_T::EPINTEN: INTKIEN Position */ 1295 #define HSUSBD_EPINTEN_INTKIEN_Msk (0x1ul << HSUSBD_EPINTEN_INTKIEN_Pos) /*!< HSUSBD_T::EPINTEN: INTKIEN Mask */ 1296 1297 #define HSUSBD_EPINTEN_PINGIEN_Pos (7) /*!< HSUSBD_T::EPINTEN: PINGIEN Position */ 1298 #define HSUSBD_EPINTEN_PINGIEN_Msk (0x1ul << HSUSBD_EPINTEN_PINGIEN_Pos) /*!< HSUSBD_T::EPINTEN: PINGIEN Mask */ 1299 1300 #define HSUSBD_EPINTEN_NAKIEN_Pos (8) /*!< HSUSBD_T::EPINTEN: NAKIEN Position */ 1301 #define HSUSBD_EPINTEN_NAKIEN_Msk (0x1ul << HSUSBD_EPINTEN_NAKIEN_Pos) /*!< HSUSBD_T::EPINTEN: NAKIEN Mask */ 1302 1303 #define HSUSBD_EPINTEN_STALLIEN_Pos (9) /*!< HSUSBD_T::EPINTEN: STALLIEN Position */ 1304 #define HSUSBD_EPINTEN_STALLIEN_Msk (0x1ul << HSUSBD_EPINTEN_STALLIEN_Pos) /*!< HSUSBD_T::EPINTEN: STALLIEN Mask */ 1305 1306 #define HSUSBD_EPINTEN_NYETIEN_Pos (10) /*!< HSUSBD_T::EPINTEN: NYETIEN Position */ 1307 #define HSUSBD_EPINTEN_NYETIEN_Msk (0x1ul << HSUSBD_EPINTEN_NYETIEN_Pos) /*!< HSUSBD_T::EPINTEN: NYETIEN Mask */ 1308 1309 #define HSUSBD_EPINTEN_ERRIEN_Pos (11) /*!< HSUSBD_T::EPINTEN: ERRIEN Position */ 1310 #define HSUSBD_EPINTEN_ERRIEN_Msk (0x1ul << HSUSBD_EPINTEN_ERRIEN_Pos) /*!< HSUSBD_T::EPINTEN: ERRIEN Mask */ 1311 1312 #define HSUSBD_EPINTEN_SHORTRXIEN_Pos (12) /*!< HSUSBD_T::EPINTEN: SHORTRXIEN Position */ 1313 #define HSUSBD_EPINTEN_SHORTRXIEN_Msk (0x1ul << HSUSBD_EPINTEN_SHORTRXIEN_Pos) /*!< HSUSBD_T::EPINTEN: SHORTRXIEN Mask */ 1314 1315 #define HSUSBD_EPDATCNT_DATCNT_Pos (0) /*!< HSUSBD_T::EPDATCNT: DATCNT Position */ 1316 #define HSUSBD_EPDATCNT_DATCNT_Msk (0xfffful << HSUSBD_EPDATCNT_DATCNT_Pos) /*!< HSUSBD_T::EPDATCNT: DATCNT Mask */ 1317 1318 #define HSUSBD_EPDATCNT_DMALOOP_Pos (16) /*!< HSUSBD_T::EPDATCNT: DMALOOP Position */ 1319 #define HSUSBD_EPDATCNT_DMALOOP_Msk (0x7ffful << HSUSBD_EPDATCNT_DMALOOP_Pos) /*!< HSUSBD_T::EPDATCNT: DMALOOP Mask */ 1320 1321 #define HSUSBD_EPRSPCTL_FLUSH_Pos (0) /*!< HSUSBD_T::EPRSPCTL: FLUSH Position */ 1322 #define HSUSBD_EPRSPCTL_FLUSH_Msk (0x1ul << HSUSBD_EPRSPCTL_FLUSH_Pos) /*!< HSUSBD_T::EPRSPCTL: FLUSH Mask */ 1323 1324 #define HSUSBD_EPRSPCTL_MODE_Pos (1) /*!< HSUSBD_T::EPRSPCTL: MODE Position */ 1325 #define HSUSBD_EPRSPCTL_MODE_Msk (0x3ul << HSUSBD_EPRSPCTL_MODE_Pos) /*!< HSUSBD_T::EPRSPCTL: MODE Mask */ 1326 1327 #define HSUSBD_EPRSPCTL_TOGGLE_Pos (3) /*!< HSUSBD_T::EPRSPCTL: TOGGLE Position */ 1328 #define HSUSBD_EPRSPCTL_TOGGLE_Msk (0x1ul << HSUSBD_EPRSPCTL_TOGGLE_Pos) /*!< HSUSBD_T::EPRSPCTL: TOGGLE Mask */ 1329 1330 #define HSUSBD_EPRSPCTL_HALT_Pos (4) /*!< HSUSBD_T::EPRSPCTL: HALT Position */ 1331 #define HSUSBD_EPRSPCTL_HALT_Msk (0x1ul << HSUSBD_EPRSPCTL_HALT_Pos) /*!< HSUSBD_T::EPRSPCTL: HALT Mask */ 1332 1333 #define HSUSBD_EPRSPCTL_ZEROLEN_Pos (5) /*!< HSUSBD_T::EPRSPCTL: ZEROLEN Position */ 1334 #define HSUSBD_EPRSPCTL_ZEROLEN_Msk (0x1ul << HSUSBD_EPRSPCTL_ZEROLEN_Pos) /*!< HSUSBD_T::EPRSPCTL: ZEROLEN Mask */ 1335 1336 #define HSUSBD_EPRSPCTL_SHORTTXEN_Pos (6) /*!< HSUSBD_T::EPRSPCTL: SHORTTXEN Position */ 1337 #define HSUSBD_EPRSPCTL_SHORTTXEN_Msk (0x1ul << HSUSBD_EPRSPCTL_SHORTTXEN_Pos) /*!< HSUSBD_T::EPRSPCTL: SHORTTXEN Mask */ 1338 1339 #define HSUSBD_EPRSPCTL_DISBUF_Pos (7) /*!< HSUSBD_T::EPRSPCTL: DISBUF Position */ 1340 #define HSUSBD_EPRSPCTL_DISBUF_Msk (0x1ul << HSUSBD_EPRSPCTL_DISBUF_Pos) /*!< HSUSBD_T::EPRSPCTL: DISBUF Mask */ 1341 1342 #define HSUSBD_EPMPS_EPMPS_Pos (0) /*!< HSUSBD_T::EPMPS: EPMPS Position */ 1343 #define HSUSBD_EPMPS_EPMPS_Msk (0x7fful << HSUSBD_EPMPS_EPMPS_Pos) /*!< HSUSBD_T::EPMPS: EPMPS Mask */ 1344 1345 #define HSUSBD_EPTXCNT_TXCNT_Pos (0) /*!< HSUSBD_T::EPTXCNT: TXCNT Position */ 1346 #define HSUSBD_EPTXCNT_TXCNT_Msk (0x7fful << HSUSBD_EPTXCNT_TXCNT_Pos) /*!< HSUSBD_T::EPTXCNT: TXCNT Mask */ 1347 1348 #define HSUSBD_EPCFG_EPEN_Pos (0) /*!< HSUSBD_T::EPCFG: EPEN Position */ 1349 #define HSUSBD_EPCFG_EPEN_Msk (0x1ul << HSUSBD_EPCFG_EPEN_Pos) /*!< HSUSBD_T::EPCFG: EPEN Mask */ 1350 1351 #define HSUSBD_EPCFG_EPTYPE_Pos (1) /*!< HSUSBD_T::EPCFG: EPTYPE Position */ 1352 #define HSUSBD_EPCFG_EPTYPE_Msk (0x3ul << HSUSBD_EPCFG_EPTYPE_Pos) /*!< HSUSBD_T::EPCFG: EPTYPE Mask */ 1353 1354 #define HSUSBD_EPCFG_EPDIR_Pos (3) /*!< HSUSBD_T::EPCFG: EPDIR Position */ 1355 #define HSUSBD_EPCFG_EPDIR_Msk (0x1ul << HSUSBD_EPCFG_EPDIR_Pos) /*!< HSUSBD_T::EPCFG: EPDIR Mask */ 1356 1357 #define HSUSBD_EPCFG_EPNUM_Pos (4) /*!< HSUSBD_T::EPCFG: EPNUM Position */ 1358 #define HSUSBD_EPCFG_EPNUM_Msk (0xful << HSUSBD_EPCFG_EPNUM_Pos) /*!< HSUSBD_T::EPCFG: EPNUM Mask */ 1359 1360 #define HSUSBD_EPBUFST_SADDR_Pos (0) /*!< HSUSBD_T::EPBUFST: SADDR Position */ 1361 #define HSUSBD_EPBUFST_SADDR_Msk (0xffful << HSUSBD_EPBUFST_SADDR_Pos) /*!< HSUSBD_T::EPBUFST: SADDR Mask */ 1362 1363 #define HSUSBD_EPBUFEND_EADDR_Pos (0) /*!< HSUSBD_T::EPBUFEND: EADDR Position */ 1364 #define HSUSBD_EPBUFEND_EADDR_Msk (0xffful << HSUSBD_EPBUFEND_EADDR_Pos) /*!< HSUSBD_T::EPBUFEND: EADDR Mask */ 1365 1366 #define HSUSBD_BCDC_BCDEN_Pos (0) /*!< HSUSBD_T::BCDC: BCDEN Position */ 1367 #define HSUSBD_BCDC_BCDEN_Msk (0x1ul << HSUSBD_BCDC_BCDEN_Pos) /*!< HSUSBD_T::BCDC: BCDEN Mask */ 1368 1369 #define HSUSBD_BCDC_DETMOD_Pos (1) /*!< HSUSBD_T::BCDC: DETMOD Position */ 1370 #define HSUSBD_BCDC_DETMOD_Msk (0x7ul << HSUSBD_BCDC_DETMOD_Pos) /*!< HSUSBD_T::BCDC: DETMOD Mask */ 1371 1372 #define HSUSBD_BCDC_DETSTS_Pos (4) /*!< HSUSBD_T::BCDC: DETSTS Position */ 1373 #define HSUSBD_BCDC_DETSTS_Msk (0x1ul << HSUSBD_BCDC_DETSTS_Pos) /*!< HSUSBD_T::BCDC: DETSTS Mask */ 1374 1375 #define HSUSBD_BCDC_USP_Pos (5) /*!< HSUSBD_T::BCDC: USP Position */ 1376 #define HSUSBD_BCDC_USP_Msk (0x1ul << HSUSBD_BCDC_USP_Pos) /*!< HSUSBD_T::BCDC: USP Mask */ 1377 1378 #define HSUSBD_BCDC_BCDIEN_Pos (30) /*!< HSUSBD_T::BCDC: BCDIEN Position */ 1379 #define HSUSBD_BCDC_BCDIEN_Msk (0x1ul << HSUSBD_BCDC_BCDIEN_Pos) /*!< HSUSBD_T::BCDC: BCDIEN Mask */ 1380 1381 #define HSUSBD_BCDC_BCDIF_Pos (31) /*!< HSUSBD_T::BCDC: BCDIF Position */ 1382 #define HSUSBD_BCDC_BCDIF_Msk (0x1ul << HSUSBD_BCDC_BCDIF_Pos) /*!< HSUSBD_T::BCDC: BCDIF Mask */ 1383 1384 #define HSUSBD_LPMCSR_LPMEN_Pos (12) /*!< HSUSBD_T::LPMCSR: LPMEN Position */ 1385 #define HSUSBD_LPMCSR_LPMEN_Msk (0x1ul << HSUSBD_LPMCSR_LPMEN_Pos) /*!< HSUSBD_T::LPMCSR: LPMEN Mask */ 1386 1387 #define HSUSBD_LPMCSR_LPMSLEEPEN_Pos (13) /*!< HSUSBD_T::LPMCSR: LPMSLEEPEN Position */ 1388 #define HSUSBD_LPMCSR_LPMSLEEPEN_Msk (0x1ul << HSUSBD_LPMCSR_LPMSLEEPEN_Pos) /*!< HSUSBD_T::LPMCSR: LPMSLEEPEN Mask */ 1389 1390 #define HSUSBD_LPMCSR_LPMSENDNYET_Pos (14) /*!< HSUSBD_T::LPMCSR: LPMSENDNYET Position */ 1391 #define HSUSBD_LPMCSR_LPMSENDNYET_Msk (0x1ul << HSUSBD_LPMCSR_LPMSENDNYET_Pos) /*!< HSUSBD_T::LPMCSR: LPMSENDNYET Mask */ 1392 1393 #define HSUSBD_DMAADDR_DMAADDR_Pos (0) /*!< HSUSBD_T::DMAADDR: DMAADDR Position */ 1394 #define HSUSBD_DMAADDR_DMAADDR_Msk (0xfffffffful << HSUSBD_DMAADDR_DMAADDR_Pos) /*!< HSUSBD_T::DMAADDR: DMAADDR Mask */ 1395 1396 #define HSUSBD_PHYCTL_DPPUEN_Pos (8) /*!< HSUSBD_T::PHYCTL: DPPUEN Position */ 1397 #define HSUSBD_PHYCTL_DPPUEN_Msk (0x1ul << HSUSBD_PHYCTL_DPPUEN_Pos) /*!< HSUSBD_T::PHYCTL: DPPUEN Mask */ 1398 1399 #define HSUSBD_PHYCTL_PHYEN_Pos (9) /*!< HSUSBD_T::PHYCTL: PHYEN Position */ 1400 #define HSUSBD_PHYCTL_PHYEN_Msk (0x1ul << HSUSBD_PHYCTL_PHYEN_Pos) /*!< HSUSBD_T::PHYCTL: PHYEN Mask */ 1401 1402 #define HSUSBD_PHYCTL_VBUSWKEN_Pos (24) /*!< HSUSBD_T::PHYCTL: VBUSWKEN Position */ 1403 #define HSUSBD_PHYCTL_VBUSWKEN_Msk (0x1ul << HSUSBD_PHYCTL_VBUSWKEN_Pos) /*!< HSUSBD_T::PHYCTL: VBUSWKEN Mask */ 1404 1405 #define HSUSBD_PHYCTL_LINESTATEWKEN_Pos (25) /*!< HSUSBD_T::PHYCTL: LINESTATEWKEN Position*/ 1406 #define HSUSBD_PHYCTL_LINESTATEWKEN_Msk (0x1ul << HSUSBD_PHYCTL_LINESTATEWKEN_Pos) /*!< HSUSBD_T::PHYCTL: LINESTATEWKEN Mask */ 1407 1408 #define HSUSBD_PHYCTL_STALLREVERT_Pos (26) /*!< HSUSBD_T::PHYCTL: STALLREVERT Position */ 1409 #define HSUSBD_PHYCTL_STALLREVERT_Msk (0x1ul << HSUSBD_PHYCTL_STALLREVERT_Pos) /*!< HSUSBD_T::PHYCTL: STALLREVERT Mask */ 1410 1411 #define HSUSBD_PHYCTL_PHYCLKSTB_Pos (27) /*!< HSUSBD_T::PHYCTL: PHYCLKSTB Position */ 1412 #define HSUSBD_PHYCTL_PHYCLKSTB_Msk (0x1ul << HSUSBD_PHYCTL_PHYCLKSTB_Pos) /*!< HSUSBD_T::PHYCTL: PHYCLKSTB Mask */ 1413 1414 #define HSUSBD_PHYCTL_VBUSDET_Pos (31) /*!< HSUSBD_T::PHYCTL: VBUSDET Position */ 1415 #define HSUSBD_PHYCTL_VBUSDET_Msk (0x1ul << HSUSBD_PHYCTL_VBUSDET_Pos) /*!< HSUSBD_T::PHYCTL: VBUSDET Mask */ 1416 1417 /**@}*/ /* HSUSBD_CONST */ 1418 /**@}*/ /* end of HSUSBD register group */ 1419 /**@}*/ /* end of REGISTER group */ 1420 1421 #if defined ( __CC_ARM ) 1422 #pragma no_anon_unions 1423 #endif 1424 1425 #endif /* __HSUSBD_REG_H__ */ 1426
