1 /*
2 * Copyright 2020-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file
9 *
10 * @addtogroup adc_sar_ip Adc Sar IPL
11 * @{
12 */
13
14 #ifdef __cplusplus
15 extern "C"{
16 #endif
17
18 /*==================================================================================================
19 * INCLUDE FILES
20 * 1) system and project includes
21 * 2) needed interfaces from external units
22 * 3) internal and external interfaces from this unit
23 ==================================================================================================*/
24 #include "Adc_Sar_Ip.h"
25 #include "Adc_Sar_Ip_Irq.h"
26 #include "Adc_Sar_Ip_HwAccess.h"
27 #include "Adc_Sar_Ip_TrustedFunctions.h"
28 #include "Reg_eSys.h"
29 #include "SchM_Adc.h"
30
31 #if defined(ADC_SAR_IP_DEV_ERROR_DETECT)
32 #include "OsIf.h"
33
34 /* local definitions on the limits of the clock frequency */
35 #define ADC_CLOCK_FREQ_MAX_RUNTIME (80000000U)
36 #define ADC_CLOCK_FREQ_MAX_CALIBRATION (40000000U)
37
38 #endif /* defined(ADC_SAR_IP_DEV_ERROR_DETECT) */
39
40 #if (STD_ON == ADC_SAR_IP_ENABLE_USER_MODE_SUPPORT)
41 /* USER_MODE_REG_PROT_ENABLED is defined for Base sanity check in RegLockMacros.h */
42 #define USER_MODE_REG_PROT_ENABLED (ADC_SAR_IP_ENABLE_USER_MODE_SUPPORT)
43 #include "RegLockMacros.h"
44 #endif /* (STD_ON == ADC_SAR_IP_ENABLE_USER_MODE_SUPPORT) */
45
46 /*==================================================================================================
47 * SOURCE FILE VERSION INFORMATION
48 ==================================================================================================*/
49 #define ADC_SAR_IP_VENDOR_ID_C 43
50 #define ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_C 4
51 #define ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_C 7
52 #define ADC_SAR_IP_AR_RELEASE_REVISION_VERSION_C 0
53 #define ADC_SAR_IP_SW_MAJOR_VERSION_C 3
54 #define ADC_SAR_IP_SW_MINOR_VERSION_C 0
55 #define ADC_SAR_IP_SW_PATCH_VERSION_C 0
56
57 /*==================================================================================================
58 * FILE VERSION CHECKS
59 ==================================================================================================*/
60 /* Check if Adc_Sar_Ip.c file and Adc_Sar_Ip.h file are of the same vendor */
61 #if (ADC_SAR_IP_VENDOR_ID_C != ADC_SAR_IP_VENDOR_ID)
62 #error "Adc_Sar_Ip.c and Adc_Sar_Ip.h have different vendor ids"
63 #endif
64
65 /* Check if Adc_Sar_Ip.c file and Adc_Sar_Ip.h file are of the same Autosar version */
66 #if ((ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_C != ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION) || \
67 (ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_C != ADC_SAR_IP_AR_RELEASE_MINOR_VERSION) || \
68 (ADC_SAR_IP_AR_RELEASE_REVISION_VERSION_C != ADC_SAR_IP_AR_RELEASE_REVISION_VERSION) \
69 )
70 #error "AutoSar Version Numbers of Adc_Sar_Ip.c and Adc_Sar_Ip.h are different"
71 #endif
72
73 /* Check if Adc_Sar_Ip.c file and Adc_Sar_Ip.h file are of the same Software version */
74 #if ((ADC_SAR_IP_SW_MAJOR_VERSION_C != ADC_SAR_IP_SW_MAJOR_VERSION) || \
75 (ADC_SAR_IP_SW_MINOR_VERSION_C != ADC_SAR_IP_SW_MINOR_VERSION) || \
76 (ADC_SAR_IP_SW_PATCH_VERSION_C != ADC_SAR_IP_SW_PATCH_VERSION) \
77 )
78 #error "Software Version Numbers of Adc_Sar_Ip.c and Adc_Sar_Ip.h are different"
79 #endif
80
81 /* Check if Adc_Sar_Ip.c file and Adc_Sar_Ip_Irq.h file are of the same vendor */
82 #if (ADC_SAR_IP_VENDOR_ID_C != ADC_SAR_IP_VENDOR_ID_IRQ)
83 #error "Adc_Sar_Ip.c and Adc_Sar_Ip_Irq.h have different vendor ids"
84 #endif
85
86 /* Check if Adc_Sar_Ip.c file and Adc_Sar_Ip_Irq.h file are of the same Autosar version */
87 #if ((ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_C != ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_IRQ) || \
88 (ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_C != ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_IRQ) || \
89 (ADC_SAR_IP_AR_RELEASE_REVISION_VERSION_C != ADC_SAR_IP_AR_RELEASE_REVISION_VERSION_IRQ) \
90 )
91 #error "AutoSar Version Numbers of Adc_Sar_Ip.c and Adc_Sar_Ip_Irq.h are different"
92 #endif
93
94 /* Check if Adc_Sar_Ip.c file and Adc_Sar_Ip_Irq.h file are of the same Software version */
95 #if ((ADC_SAR_IP_SW_MAJOR_VERSION_C != ADC_SAR_IP_SW_MAJOR_VERSION_IRQ) || \
96 (ADC_SAR_IP_SW_MINOR_VERSION_C != ADC_SAR_IP_SW_MINOR_VERSION_IRQ) || \
97 (ADC_SAR_IP_SW_PATCH_VERSION_C != ADC_SAR_IP_SW_PATCH_VERSION_IRQ) \
98 )
99 #error "Software Version Numbers of Adc_Sar_Ip.c and Adc_Sar_Ip_Irq.h are different"
100 #endif
101
102 /* Check if Adc_Sar_Ip.c file and Adc_Sar_Ip_HwAccess.h file are of the same vendor */
103 #if (ADC_SAR_IP_VENDOR_ID_C != ADC_SAR_IP_VENDOR_ID_HWACCESS)
104 #error "Adc_Sar_Ip.c and Adc_Sar_Ip_HwAccess.h have different vendor ids"
105 #endif
106
107 /* Check if Adc_Sar_Ip.c file and Adc_Sar_Ip_HwAccess.h file are of the same Autosar version */
108 #if ((ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_C != ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_HWACCESS) || \
109 (ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_C != ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_HWACCESS) || \
110 (ADC_SAR_IP_AR_RELEASE_REVISION_VERSION_C != ADC_SAR_IP_AR_RELEASE_REVISION_VERSION_HWACCESS) \
111 )
112 #error "AutoSar Version Numbers of Adc_Sar_Ip.c and Adc_Sar_Ip_HwAccess.h are different"
113 #endif
114
115 /* Check if Adc_Sar_Ip.c file and Adc_Sar_Ip_HwAccess.h file are of the same Software version */
116 #if ((ADC_SAR_IP_SW_MAJOR_VERSION_C != ADC_SAR_IP_SW_MAJOR_VERSION_HWACCESS) || \
117 (ADC_SAR_IP_SW_MINOR_VERSION_C != ADC_SAR_IP_SW_MINOR_VERSION_HWACCESS) || \
118 (ADC_SAR_IP_SW_PATCH_VERSION_C != ADC_SAR_IP_SW_PATCH_VERSION_HWACCESS) \
119 )
120 #error "Software Version Numbers of Adc_Sar_Ip.c and Adc_Sar_Ip_HwAccess.h are different"
121 #endif
122
123 /* Check if Adc_Sar_Ip.c file and Adc_Sar_Ip_TrustedFunctions.h file are of the same vendor */
124 #if (ADC_SAR_IP_VENDOR_ID_C != ADC_SAR_IP_VENDOR_ID_TRUSTEDFUNCTIONS)
125 #error "Adc_Sar_Ip.c and Adc_Sar_Ip_TrustedFunctions.h have different vendor ids"
126 #endif
127
128 /* Check if Adc_Sar_Ip.c file and Adc_Sar_Ip_TrustedFunctions.h file are of the same Autosar version */
129 #if ((ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_C != ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_TRUSTEDFUNCTIONS) || \
130 (ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_C != ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_TRUSTEDFUNCTIONS) || \
131 (ADC_SAR_IP_AR_RELEASE_REVISION_VERSION_C != ADC_SAR_IP_AR_RELEASE_REVISION_VERSION_TRUSTEDFUNCTIONS) \
132 )
133 #error "AutoSar Version Numbers of Adc_Sar_Ip.c and Adc_Sar_Ip_TrustedFunctions.h are different"
134 #endif
135
136 /* Check if Adc_Sar_Ip.c file and Adc_Sar_Ip_TrustedFunctions.h file are of the same Software version */
137 #if ((ADC_SAR_IP_SW_MAJOR_VERSION_C != ADC_SAR_IP_SW_MAJOR_VERSION_TRUSTEDFUNCTIONS) || \
138 (ADC_SAR_IP_SW_MINOR_VERSION_C != ADC_SAR_IP_SW_MINOR_VERSION_TRUSTEDFUNCTIONS) || \
139 (ADC_SAR_IP_SW_PATCH_VERSION_C != ADC_SAR_IP_SW_PATCH_VERSION_TRUSTEDFUNCTIONS) \
140 )
141 #error "Software Version Numbers of Adc_Sar_Ip.c and Adc_Sar_Ip_TrustedFunctions.h are different"
142 #endif
143
144 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
145 /* Check if Adc_Sar_Ip.c file and Reg_eSys.h file are of the same Autosar version */
146 #if ((ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_C != REG_ESYS_AR_RELEASE_MAJOR_VERSION) || \
147 (ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_C != REG_ESYS_AR_RELEASE_MINOR_VERSION) \
148 )
149 #error "AutoSar Version Numbers of Adc_Sar_Ip.c and Reg_eSys.h are different"
150 #endif
151
152 #if defined(ADC_SAR_IP_DEV_ERROR_DETECT)
153 /* Check if Adc_Sar_Ip.c file and OsIf.h file are of the same Autosar version */
154 #if ((ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_C != OSIF_AR_RELEASE_MAJOR_VERSION) || \
155 (ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_C != OSIF_AR_RELEASE_MINOR_VERSION) \
156 )
157 #error "AutoSar Version Numbers of Adc_Sar_Ip.c and OsIf.h are different"
158 #endif
159 #endif /* defined(ADC_SAR_IP_DEV_ERROR_DETECT) */
160
161 #if (STD_ON == ADC_SAR_IP_ENABLE_USER_MODE_SUPPORT)
162 /* Checks against RegLockMacros.h */
163 #if ((ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MAJOR_VERSION) || \
164 (ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MINOR_VERSION))
165 #error "AUTOSAR Version Numbers of Adc_Sar_Ip.c and RegLockMacros.h are different"
166 #endif
167 #endif /* (STD_ON == ADC_SAR_IP_ENABLE_USER_MODE_SUPPORT) */
168
169 /* Check if Adc_Sar_Ip.c file and SchM_Adc.h file are of the same version */
170 #if ((ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_C != SCHM_ADC_AR_RELEASE_MAJOR_VERSION) || \
171 (ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_C != SCHM_ADC_AR_RELEASE_MINOR_VERSION) \
172 )
173 #error "AutoSar Version Numbers of Adc_Sar_Ip.c and SchM_Adc.h are different"
174 #endif
175 #endif /* DISABLE_MCAL_INTERMODULE_ASR_CHECK */
176
177 /*******************************************************************************
178 * Pre-check
179 ******************************************************************************/
180 #ifndef MCAL_ENABLE_USER_MODE_SUPPORT
181 #if (STD_ON == ADC_SAR_IP_ENABLE_USER_MODE_SUPPORT)
182 #error MCAL_ENABLE_USER_MODE_SUPPORT is not enabled. For running ADC in user mode the MCAL_ENABLE_USER_MODE_SUPPORT needs to be defined
183 #endif /* (STD_ON == ADC_ENABLE_USER_MODE_SUPPORT) */
184 #endif /* ifndef MCAL_ENABLE_USER_MODE_SUPPORT*/
185
186 /*==================================================================================================
187 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
188 ==================================================================================================*/
189
190 /*==================================================================================================
191 * LOCAL MACROS
192 ==================================================================================================*/
193 #if FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL
194 /* ADC_SAR_IP_INST_HAS_REG_<bitwidth> macros. Checks the availability of a
195 register index based on the availability of the ADC channels
196 for the particular u32Instance on the platform.
197 <bitwidth> represents the width of the bitfield associated with each
198 ADC channel in the register series.
199 */
200 #define ADC_SAR_IP_INST_HAS_REG_4(inst,regIdx) ((Adc_Sar_Ip_au32AdcChanBitmap[inst][(regIdx) / 4u] & (0xFFUL << (((regIdx) % 4u) * 8u))) != 0u)
201 #define ADC_SAR_IP_INST_HAS_REG_32(inst,regIdx) ((Adc_Sar_Ip_au32AdcChanBitmap[inst][(regIdx) / 32u] & (0x01UL << ((regIdx) % 32u))) != 0u)
202
203 /* <bitwidth> = 4. Four bits in the register correspond to one ADC channel */
204 #define ADC_SAR_IP_INST_HAS_CWSELRn(inst,x) (ADC_SAR_IP_INST_HAS_REG_4(inst,x))
205
206 /* <bitwidth> = 32. The entire 4 byte register is associated with one ADC channel */
207 #define ADC_SAR_IP_INST_HAS_CDRn(inst,n) (ADC_SAR_IP_INST_HAS_REG_32(inst,n))
208 #define ADC_SAR_IP_INST_HAS_CHANn(inst,n) (ADC_SAR_IP_INST_HAS_REG_32(inst,n))
209
210 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL */
211
212 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
213
214 #ifdef ADC_DSDR_DSD
215 #define ADC_SAR_IP_INST_HAS_DSDR(inst) ((Adc_Sar_Ip_au32AdcFeatureBitmap[inst] & (1UL << 0u)) != 0u)
216 #endif /* ADC_DSDR_DSD */
217 #define ADC_SAR_IP_INST_HAS_PSCR(inst) ((Adc_Sar_Ip_au32AdcFeatureBitmap[inst] & (1UL << 1u)) != 0u)
218 #define ADC_SAR_IP_INST_HAS_CTU(inst) ((Adc_Sar_Ip_au32AdcFeatureBitmap[inst] & (1UL << 2u)) != 0u)
219 #define ADC_SAR_IP_INST_HAS_CTU_TRIGGER_MODE(inst) ((Adc_Sar_Ip_au32AdcFeatureBitmap[inst] & (1UL << 3u)) != 0u)
220 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_FEATURE */
221
222 /* Macros for watchdog registers to help decode and compose bit mask for the functionality */
223 #define ADC_SAR_IP_WDG_REG_MASK_HIGH(registerIdx) ((uint32)((uint32)1UL << (((registerIdx) * 2u) + 1u)))
224 #define ADC_SAR_IP_WDG_REG_MASK_LOW(registerIdx) ((uint32)((uint32)1UL << ((registerIdx) * 2u)))
225 /*==================================================================================================
226 * LOCAL CONSTANTS
227 ==================================================================================================*/
228
229 /*==================================================================================================
230 * LOCAL VARIABLES
231 ==================================================================================================*/
232 #define ADC_START_SEC_CONST_UNSPECIFIED
233 #include "Adc_MemMap.h"
234
235 /* Table of pBase addresses for ADC instances. */
236 ADC_Type * const Adc_Sar_Ip_apxAdcBase[ADC_INSTANCE_COUNT] = IP_ADC_BASE_PTRS;
237 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
238 SAR_ADC_AE_Type * const Adc_Sar_AE_Ip_apxAdcBase[SAR_ADC_AE_INSTANCE_COUNT] = IP_SAR_ADC_AE_BASE_PTRS;
239 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
240 #if FEATURE_ADC_HAS_TEMPSENSE_CHN
241 #if (ADC_SAR_IP_TEMPSENSE_ENABLED == STD_ON)
242 static TEMPSENSE_Type * const Adc_Sar_Ip_apxTempsenseBase[TEMPSENSE_INSTANCE_COUNT] = IP_TEMPSENSE_BASE_PTRS;
243 #endif /* (ADC_SAR_IP_TEMPSENSE_ENABLED == STD_ON) */
244 #endif
245
246 #define ADC_STOP_SEC_CONST_UNSPECIFIED
247 #include "Adc_MemMap.h"
248
249 #define ADC_START_SEC_VAR_CLEARED_UNSPECIFIED
250 #include "Adc_MemMap.h"
251 /* Global state structure */
252 static Adc_Sar_Ip_StateStructType Adc_Sar_Ip_axAdcSarState[ADC_SAR_IP_INSTANCE_COUNT];
253
254 #define ADC_STOP_SEC_VAR_CLEARED_UNSPECIFIED
255 #include "Adc_MemMap.h"
256
257 #define ADC_START_SEC_CONST_32
258 #include "Adc_MemMap.h"
259
260 static const uint8 Adc_Sar_Ip_au8AdcGroupCount[ADC_SAR_IP_INSTANCE_COUNT] = FEATURE_ADC_MAX_GROUP_COUNT;
261
262 #if FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL
263 static const uint32 Adc_Sar_Ip_au32AdcChanBitmap[ADC_SAR_IP_INSTANCE_COUNT][ADC_SAR_IP_NUM_GROUP_CHAN] = FEATURE_ADC_CHN_AVAIL_BITMAP;
264 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL */
265
266 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
267 static const uint32 Adc_Sar_Ip_au32AdcFeatureBitmap[ADC_SAR_IP_INSTANCE_COUNT] = FEATURE_ADC_FEAT_AVAIL_BITMAP;
268 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_FEATURE */
269
270 #define ADC_STOP_SEC_CONST_32
271 #include "Adc_MemMap.h"
272
273 /*==================================================================================================
274 * GLOBAL CONSTANTS
275 ==================================================================================================*/
276
277 /*==================================================================================================
278 * GLOBAL VARIABLES
279 ==================================================================================================*/
280
281 /*==================================================================================================
282 * GLOBAL FUNCTION PROTOTYPES
283 ==================================================================================================*/
284
285 /*==================================================================================================
286 * LOCAL FUNCTION PROTOTYPES
287 ==================================================================================================*/
288 #define ADC_START_SEC_CODE
289 #include "Adc_MemMap.h"
290
291 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
292 static inline uint8 Adc_Sar_GetResolution(const uint32 Instance);
293 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
294
295 static inline uint16 Adc_Sar_GetMaskedResult(const uint32 Instance,
296 const uint32 Cdr);
297 static inline uint32 Adc_Sar_GetMsrFlags(const uint32 Instance);
298 static inline uint32 Adc_Sar_GetIsrFlags(const uint32 Instance);
299 #if ADC_SAR_IP_HAS_ADCLKSEL
300 static inline uint32 Adc_Sar_GetADCLKSELValue(Adc_Sar_Ip_ClockSelType ClockSel);
301 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
302 static inline uint32 Adc_Sar_CollectMcrMasks(const uint32 Instance,
303 const Adc_Sar_Ip_ConfigType * const Config,
304 uint32 InitialMcr);
305 static inline void Adc_Sar_ConfigChannels(const uint32 Instance,
306 const Adc_Sar_Ip_ChanConfigType * ChannelConfigsPtr,
307 uint8 NumChannels);
308 #if (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED)
309 static inline Adc_Sar_Ip_StatusType Adc_Sar_CheckSelfTestProgress(const uint32 Instance);
310 static inline void Adc_Sar_ConfigSelftestThreshold(const uint32 Instance,
311 const Adc_Sar_Ip_SelfTestThresholdType * SelfTestThresholdConfig);
312 static inline void Adc_Sar_EnableSelftestThreshold(const uint32 Instance);
313 static inline void Adc_Sar_DisableSelftestThreshold(const uint32 Instance);
314 #endif /* (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED) */
315 static uint32 Adc_Sar_GetConvResults(const uint32 Instance,
316 const Adc_Sar_Ip_ConvChainType ChainType,
317 uint16 * const ResultsRaw,
318 Adc_Sar_Ip_ChanResultType * const ResultsStruct,
319 const uint32 Length);
320
321 static void Adc_Sar_ResetWdog(const uint32 Instance);
322
323 #if FEATURE_ADC_HAS_CLOCK_DIVIDER
324 static inline void Adc_Sar_EnableClkDiv(const uint32 Instance,
325 const boolean ClkDivEnable);
326 #endif /* FEATURE_ADC_HAS_CLOCK_DIVIDER */
327
328 #if ( \
329 (STD_ON == ADC_SAR_IP_ECH_ENABLED) || (STD_ON == ADC_SAR_IP_JECH_ENABLED) || \
330 ((FEATURE_ADC_HAS_CTU == 1U) && (STD_ON == ADC_SAR_IP_EOCTU_ENABLED)) \
331 )
332 static inline void Adc_Sar_CheckAndCallNotification(void (*Callback)(void));
333 #endif /* (STD_ON == ADC_SAR_IP_ECH_ENABLED) .. */
334
335 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
336 static inline void Adc_Sar_CheckAndCallEocNotification(uint32 Instance,
337 uint16 ChanIdx,
338 uint16 VectAdr,
339 uint32 EocFlag,
340 boolean * CeocfrFlag);
341 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
342
343 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
344 static inline uint32 Adc_Sar_CheckAndCallWorrNotification(uint32 Instance,
345 uint16 ChanIdx,
346 uint16 VectAdr);
347 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
348
349 #if ((STD_ON == ADC_SAR_IP_WDG_ENABLED) || (STD_ON == ADC_SAR_IP_EOC_ENABLED))
350 static inline void Adc_CheckAndCallAllChannelNotification(const uint32 Instance);
351 #endif /* ((STD_ON == ADC_SAR_IP_WDG_ENABLED) || (STD_ON == ADC_SAR_IP_EOC_ENABLED)) */
352
353 #if (ADC_SAR_IP_EXTERNAL_TRIGGER_ENABLE)
354 #if (FEATURE_ADC_HAS_INJ_EXT_TRIGGER || FEATURE_ADC_HAS_EXT_TRIGGER)
355 static inline void Adc_Sar_ConfigExternalTrigger(const uint32 Instance,
356 const Adc_Sar_Ip_ExtTriggerEdgeType TriggerEdge,
357 const uint32 TrgEdgeSetMask,
358 const uint32 TrgEdgeClrMask,
359 const uint32 TrigSrcMask);
360 #endif /* (FEATURE_ADC_HAS_INJ_EXT_TRIGGER || FEATURE_ADC_HAS_EXT_TRIGGER) */
361 #endif /* (ADC_SAR_IP_EXTERNAL_TRIGGER_ENABLE) */
362
363 #if FEATURE_ADC_HAS_TEMPSENSE_CHN
364 #if (ADC_SAR_IP_TEMPSENSE_ENABLED == STD_ON)
365 static inline uint32 Adc_Sar_TempsenseConvFp2Int(const uint32 FloatingPoint);
366 static inline uint16 Adc_Sar_TempsenseConvInt2Fp(const sint32 SignedInteger);
367 #endif /* (ADC_SAR_IP_TEMPSENSE_ENABLED == STD_ON) */
368 #endif /* FEATURE_ADC_HAS_TEMPSENSE_CHN */
369
370 static inline void Adc_Sar_SetNormalChain(const uint32 Instance,
371 const uint32 * const Mask);
372 static inline void Adc_Sar_SetInjectedChain(const uint32 Instance,
373 const uint32 * const Mask);
374
375 /* The function is used to reduce complexity for parent function */
376 static inline uint32 Adc_Sar_GetValueFromBool(const boolean bVal,
377 const uint32 TrueVal,
378 const uint32 FalseVal);
379
380 /*==================================================================================================
381 * LOCAL FUNCTIONS
382 ==================================================================================================*/
383 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
384 /*FUNCTION*********************************************************************
385 *
386 * Function Name : Adc_Sar_GetResolution
387 * Description : Returns Adc Sar resolution for conversion data
388 *
389 *END*************************************************************************/
Adc_Sar_GetResolution(const uint32 Instance)390 static inline uint8 Adc_Sar_GetResolution(const uint32 Instance)
391 {
392 uint8 Resolution;
393 static const uint8 ResolutionArray[] = {14U, 12U, 10U, 8U}; /* maps each register bit value to resolution bit number */
394 const ADC_Type * const AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
395 uint32 Calbistreg = AdcBasePtr->CALBISTREG;
396 /* ResolutionArray can be used only for 2 bits resolutions. On S32K3 platforms only 2 bits are used so "& 3U" operation is needed */
397 uint8 ResolutionBits = (uint8)(((Calbistreg & ADC_CALBISTREG_RESN_MASK) >> ADC_CALBISTREG_RESN_SHIFT) & 3U);
398
399 Resolution = ResolutionArray[ResolutionBits];
400
401 return Resolution;
402 }
403 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
404
405 #if (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED)
406 /*FUNCTION*********************************************************************
407 *
408 * Function Name : Adc_Sar_ConfigSelftestThreshold
409 * Description : Configure self-test threshold value
410 *
411 *END*************************************************************************/
Adc_Sar_ConfigSelftestThreshold(const uint32 Instance,const Adc_Sar_Ip_SelfTestThresholdType * SelfTestThresholdConfig)412 static inline void Adc_Sar_ConfigSelftestThreshold(const uint32 Instance,
413 const Adc_Sar_Ip_SelfTestThresholdType * SelfTestThresholdConfig)
414 {
415 ADC_Type * AdcBasePtr = NULL_PTR;
416 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
417 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
418 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
419 #ifdef ADC_STAW0R_AWDE
420 volatile uint32 * STAW0RAddr = NULL_PTR;
421 #endif /* ADC_STAW0R_AWDE */
422 #ifdef ADC_STAW1R_AWDE
423 volatile uint32 * STAW1RAddr = NULL_PTR;
424 #endif /* ADC_STAW1R_AWDE */
425 #ifdef ADC_STAW1AR_AWDE
426 volatile uint32 * STAW1ARAddr = NULL_PTR;
427 volatile uint32 * STAW1BRAddr = NULL_PTR;
428 #endif /* ADC_STAW1AR_AWDE */
429 #ifdef ADC_STAW2R_AWDE
430 volatile uint32 * STAW2RAddr = NULL_PTR;
431 #endif /* ADC_STAW2R_AWDE */
432 #ifdef ADC_STAW4R_AWDE
433 volatile uint32 * STAW4RAddr = NULL_PTR;
434 volatile uint32 * STAW5RAddr = NULL_PTR;
435 #endif /* ADC_STAW4R_AWDE */
436
437 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
438 if (Instance >= ADC_INSTANCE_COUNT)
439 {
440 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
441 #ifdef ADC_STAW0R_AWDE
442 STAW0RAddr = &(AdcAEBasePtr->STAW0R);
443 #endif /* ADC_STAW0R_AWDE */
444 #ifdef ADC_STAW1R_AWDE
445 STAW1RAddr = &(AdcAEBasePtr->STAW1R);
446 #endif /* ADC_STAW1R_AWDE */
447 #ifdef ADC_STAW1AR_AWDE
448 STAW1ARAddr = &(AdcAEBasePtr->STAW1AR);
449 STAW1BRAddr = &(AdcAEBasePtr->STAW1BR);
450 #endif /* ADC_STAW1AR_AWDE */
451 #ifdef ADC_STAW2R_AWDE
452 STAW2RAddr = &(AdcAEBasePtr->STAW2R);
453 #endif /* ADC_STAW2R_AWDE */
454 #ifdef ADC_STAW4R_AWDE
455 STAW4RAddr = &(AdcAEBasePtr->STAW4R);
456 STAW5RAddr = &(AdcAEBasePtr->STAW5R);
457 #endif /* ADC_STAW4R_AWDE */
458 }
459 else
460 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
461 {
462 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
463 #ifdef ADC_STAW0R_AWDE
464 STAW0RAddr = &(AdcBasePtr->STAW0R);
465 #endif /* ADC_STAW0R_AWDE */
466 #ifdef ADC_STAW1R_AWDE
467 STAW1RAddr = &(AdcBasePtr->STAW1R);
468 #endif /* ADC_STAW1R_AWDE */
469 #ifdef ADC_STAW1AR_AWDE
470 STAW1ARAddr = &(AdcBasePtr->STAW1AR);
471 STAW1BRAddr = &(AdcBasePtr->STAW1BR);
472 #endif /* ADC_STAW1AR_AWDE */
473 #ifdef ADC_STAW2R_AWDE
474 STAW2RAddr = &(AdcBasePtr->STAW2R);
475 #endif /* ADC_STAW2R_AWDE */
476 #ifdef ADC_STAW4R_AWDE
477 STAW4RAddr = &(AdcBasePtr->STAW4R);
478 STAW5RAddr = &(AdcBasePtr->STAW5R);
479 #endif /* ADC_STAW4R_AWDE */
480 }
481
482 #ifdef ADC_STAW0R_AWDE
483 /* Configure the self-test watchdog threshold for S0 algorithm */
484 *STAW0RAddr &= ~(ADC_STAW0R_THRH_MASK | ADC_STAW0R_THRL_MASK);
485 *STAW0RAddr |= ADC_STAW0R_THRH(SelfTestThresholdConfig->AdcSTAW0RHighVal) | ADC_STAW0R_THRL(SelfTestThresholdConfig->AdcSTAW0RLowVal);
486 #endif /* ADC_STAW0R_AWDE */
487
488 #ifdef ADC_STAW1R_AWDE
489 /* Configure the self-test watchdog threshold for S1 algorithm */
490 *STAW1RAddr &= ~(ADC_STAW1R_THRL_MASK);
491 *STAW1RAddr |= ADC_STAW1R_THRL(SelfTestThresholdConfig->AdcSTAW1RLowVal);
492 #endif /* ADC_STAW1R_AWDE */
493 #ifdef ADC_STAW1AR_AWDE
494 /* Configure the self-test watchdog threshold for S1 algorithm */
495 *STAW1ARAddr &= ~(ADC_STAW1AR_THRH_MASK | ADC_STAW1AR_THRL_MASK);
496 *STAW1ARAddr |= ADC_STAW1AR_THRH(SelfTestThresholdConfig->AdcSTAW1ARHighVal) | ADC_STAW1AR_THRL(SelfTestThresholdConfig->AdcSTAW1ARLowVal);
497 *STAW1BRAddr &= ~(ADC_STAW1BR_THRH_MASK | ADC_STAW1BR_THRL_MASK);
498 *STAW1BRAddr |= ADC_STAW1BR_THRH(SelfTestThresholdConfig->AdcSTAW1BRHighVal) | ADC_STAW1BR_THRL(SelfTestThresholdConfig->AdcSTAW1BRLowVal);
499 #endif /* ADC_STAW1AR_AWDE */
500
501 #ifdef ADC_STAW2R_AWDE
502 /* Configure the self-test watchdog threshold for S2 algorithm */
503 *STAW2RAddr &= ~(ADC_STAW2R_THRL_MASK);
504 *STAW2RAddr |= ADC_STAW2R_THRL(SelfTestThresholdConfig->AdcSTAW2RLowVal);
505 #endif /* ADC_STAW2R_AWDE */
506
507 #ifdef ADC_STAW4R_AWDE
508 /* Configure the self-test watchdog threshold for C algorithm */
509 *STAW4RAddr &= ~(ADC_STAW4R_THRH_MASK | ADC_STAW4R_THRL_MASK);
510 *STAW4RAddr |= ADC_STAW4R_THRH(SelfTestThresholdConfig->AdcSTAW4RHighVal) | ADC_STAW4R_THRL(SelfTestThresholdConfig->AdcSTAW4RLowVal);
511 *STAW5RAddr &= ~(ADC_STAW5R_THRH_MASK | ADC_STAW5R_THRL_MASK);
512 *STAW5RAddr |= ADC_STAW5R_THRH(SelfTestThresholdConfig->AdcSTAW5RHighVal) | ADC_STAW5R_THRL(SelfTestThresholdConfig->AdcSTAW5RLowVal);
513 #endif /* ADC_STAW4R_AWDE */
514 }
515
516 /*FUNCTION*********************************************************************
517 *
518 * Function Name : Adc_Sar_EnableSelftestThreshold
519 * Description : Enable self-test threshold
520 *
521 *END*************************************************************************/
Adc_Sar_EnableSelftestThreshold(const uint32 Instance)522 static inline void Adc_Sar_EnableSelftestThreshold(const uint32 Instance)
523 {
524 ADC_Type * AdcBasePtr = NULL_PTR;
525 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
526 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
527 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
528 #ifdef ADC_STAW0R_AWDE
529 volatile uint32 * STAW0RAddr = NULL_PTR;
530 #endif /* ADC_STAW0R_AWDE */
531 #ifdef ADC_STAW1R_AWDE
532 volatile uint32 * STAW1RAddr = NULL_PTR;
533 #endif /* ADC_STAW1R_AWDE */
534 #ifdef ADC_STAW1AR_AWDE
535 volatile uint32 * STAW1ARAddr = NULL_PTR;
536 #endif /* ADC_STAW1AR_AWDE */
537 #ifdef ADC_STAW2R_AWDE
538 volatile uint32 * STAW2RAddr = NULL_PTR;
539 #endif /* ADC_STAW2R_AWDE */
540 #ifdef ADC_STAW4R_AWDE
541 volatile uint32 * STAW4RAddr = NULL_PTR;
542 #endif /* ADC_STAW4R_AWDE */
543
544 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
545 if (Instance >= ADC_INSTANCE_COUNT)
546 {
547 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
548 #ifdef ADC_STAW0R_AWDE
549 STAW0RAddr = &(AdcAEBasePtr->STAW0R);
550 #endif /* ADC_STAW0R_AWDE */
551 #ifdef ADC_STAW1R_AWDE
552 STAW1RAddr = &(AdcAEBasePtr->STAW1R);
553 #endif /* ADC_STAW1R_AWDE */
554 #ifdef ADC_STAW1AR_AWDE
555 STAW1ARAddr = &(AdcAEBasePtr->STAW1AR);
556 #endif /* ADC_STAW1AR_AWDE */
557 #ifdef ADC_STAW2R_AWDE
558 STAW2RAddr = &(AdcAEBasePtr->STAW2R);
559 #endif /* ADC_STAW2R_AWDE */
560 #ifdef ADC_STAW4R_AWDE
561 STAW4RAddr = &(AdcAEBasePtr->STAW4R);
562 #endif /* ADC_STAW4R_AWDE */
563 }
564 else
565 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
566 {
567 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
568 #ifdef ADC_STAW0R_AWDE
569 STAW0RAddr = &(AdcBasePtr->STAW0R);
570 #endif /* ADC_STAW0R_AWDE */
571 #ifdef ADC_STAW1R_AWDE
572 STAW1RAddr = &(AdcBasePtr->STAW1R);
573 #endif /* ADC_STAW1R_AWDE */
574 #ifdef ADC_STAW1AR_AWDE
575 STAW1ARAddr = &(AdcBasePtr->STAW1AR);
576 #endif /* ADC_STAW1AR_AWDE */
577 #ifdef ADC_STAW2R_AWDE
578 STAW2RAddr = &(AdcBasePtr->STAW2R);
579 #endif /* ADC_STAW2R_AWDE */
580 #ifdef ADC_STAW4R_AWDE
581 STAW4RAddr = &(AdcBasePtr->STAW4R);
582 #endif /* ADC_STAW4R_AWDE */
583 }
584
585 #ifdef ADC_STAW0R_AWDE
586 /* Enable the self-test watchdog threshold for S0 algorithm */
587 *STAW0RAddr |= ADC_STAW0R_AWDE(0x1UL);
588 #endif /* ADC_STAW0R_AWDE */
589
590 #ifdef ADC_STAW1R_AWDE
591 /* Enable the self-test watchdog threshold for S1 algorithm */
592 *STAW1RAddr |= ADC_STAW1R_AWDE(0x1UL);
593 #endif /* ADC_STAW1R_AWDE */
594 #ifdef ADC_STAW1AR_AWDE
595 /* Enable the self-test watchdog threshold for S1 algorithm */
596 *STAW1ARAddr |= ADC_STAW1AR_AWDE(0x1UL);
597 #endif /* ADC_STAW1AR_AWDE */
598
599 #ifdef ADC_STAW2R_AWDE
600 /* Enable the self-test watchdog threshold for S2 algorithm */
601 *STAW2RAddr |= ADC_STAW2R_AWDE(0x1UL);
602 #endif /* ADC_STAW2R_AWDE */
603
604 #ifdef ADC_STAW4R_AWDE
605 /* Enable the self-test watchdog threshold for C algorithm */
606 *STAW4RAddr |= ADC_STAW4R_AWDE(0x1UL);
607 #endif /* ADC_STAW4R_AWDE */
608 }
609
610 /*FUNCTION*********************************************************************
611 *
612 * Function Name : Adc_Sar_DisableSelftestThreshold
613 * Description : Disable self-test threshold
614 *
615 *END*************************************************************************/
Adc_Sar_DisableSelftestThreshold(const uint32 Instance)616 static inline void Adc_Sar_DisableSelftestThreshold(const uint32 Instance)
617 {
618 ADC_Type * AdcBasePtr = NULL_PTR;
619 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
620 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
621 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
622 #ifdef ADC_STAW0R_AWDE
623 volatile uint32 * STAW0RAddr = NULL_PTR;
624 #endif /* ADC_STAW0R_AWDE */
625 #ifdef ADC_STAW1R_AWDE
626 volatile uint32 * STAW1RAddr = NULL_PTR;
627 #endif /* ADC_STAW1R_AWDE */
628 #ifdef ADC_STAW1AR_AWDE
629 volatile uint32 * STAW1ARAddr = NULL_PTR;
630 #endif /* ADC_STAW1AR_AWDE */
631 #ifdef ADC_STAW2R_AWDE
632 volatile uint32 * STAW2RAddr = NULL_PTR;
633 #endif /* ADC_STAW2R_AWDE */
634 #ifdef ADC_STAW4R_AWDE
635 volatile uint32 * STAW4RAddr = NULL_PTR;
636 #endif /* ADC_STAW4R_AWDE */
637
638 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
639 if (Instance >= ADC_INSTANCE_COUNT)
640 {
641 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
642 #ifdef ADC_STAW0R_AWDE
643 STAW0RAddr = &(AdcAEBasePtr->STAW0R);
644 #endif /* ADC_STAW0R_AWDE */
645 #ifdef ADC_STAW1R_AWDE
646 STAW1RAddr = &(AdcAEBasePtr->STAW1R);
647 #endif /* ADC_STAW1R_AWDE */
648 #ifdef ADC_STAW1AR_AWDE
649 STAW1ARAddr = &(AdcAEBasePtr->STAW1AR);
650 #endif /* ADC_STAW1AR_AWDE */
651 #ifdef ADC_STAW2R_AWDE
652 STAW2RAddr = &(AdcAEBasePtr->STAW2R);
653 #endif /* ADC_STAW2R_AWDE */
654 #ifdef ADC_STAW4R_AWDE
655 STAW4RAddr = &(AdcAEBasePtr->STAW4R);
656 #endif /* ADC_STAW4R_AWDE */
657 }
658 else
659 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
660 {
661 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
662 #ifdef ADC_STAW0R_AWDE
663 STAW0RAddr = &(AdcBasePtr->STAW0R);
664 #endif /* ADC_STAW0R_AWDE */
665 #ifdef ADC_STAW1R_AWDE
666 STAW1RAddr = &(AdcBasePtr->STAW1R);
667 #endif /* ADC_STAW1R_AWDE */
668 #ifdef ADC_STAW1AR_AWDE
669 STAW1ARAddr = &(AdcBasePtr->STAW1AR);
670 #endif /* ADC_STAW1AR_AWDE */
671 #ifdef ADC_STAW2R_AWDE
672 STAW2RAddr = &(AdcBasePtr->STAW2R);
673 #endif /* ADC_STAW2R_AWDE */
674 #ifdef ADC_STAW4R_AWDE
675 STAW4RAddr = &(AdcBasePtr->STAW4R);
676 #endif /* ADC_STAW4R_AWDE */
677 }
678
679 #ifdef ADC_STAW0R_AWDE
680 /* Disable the self-test watchdog threshold for S0 algorithm */
681 *STAW0RAddr &= ~(ADC_STAW0R_AWDE_MASK);
682 #endif /* ADC_STAW0R_AWDE */
683 #ifdef ADC_STAW1R_AWDE
684 /* Disable the self-test watchdog threshold for S1 algorithm */
685 *STAW1RAddr &= ~(ADC_STAW1R_AWDE_MASK);
686 #endif /* ADC_STAW1R_AWDE */
687 #ifdef ADC_STAW1AR_AWDE
688 /* Enable the self-test watchdog threshold for S1 algorithm */
689 *STAW1ARAddr &= ~(ADC_STAW1AR_AWDE_MASK);
690 #endif /* ADC_STAW1AR_AWDE */
691 #ifdef ADC_STAW2R_AWDE
692 /* Disable the self-test watchdog threshold for S2 algorithm */
693 *STAW2RAddr &= ~(ADC_STAW2R_AWDE_MASK);
694 #endif /* ADC_STAW2R_AWDE */
695 #ifdef ADC_STAW4R_AWDE
696 /* Disable the self-test watchdog threshold for C algorithm */
697 *STAW4RAddr &= ~(ADC_STAW4R_AWDE_MASK);
698 #endif /* ADC_STAW4R_AWDE */
699 }
700 #endif /* (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED) */
701
702 /*FUNCTION*********************************************************************
703 *
704 * Function Name : Adc_Sar_GetMaskedResult
705 * Description : Returns result masked accordingly with alignment
706 *
707 *END*************************************************************************/
Adc_Sar_GetMaskedResult(const uint32 Instance,const uint32 Cdr)708 static inline uint16 Adc_Sar_GetMaskedResult(const uint32 Instance,
709 const uint32 Cdr)
710 {
711 uint32 CdrMask;
712 uint16 Result;
713 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
714 uint8 Resolution;
715 #else
716 uint8 Resolution = ADC_SAR_IP_MAX_RESOLUTION;
717 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
718
719 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
720 if (FALSE == Adc_Sar_Ip_axAdcSarState[Instance].BypassResolution)
721 {
722 Resolution = Adc_Sar_GetResolution(Instance);
723 }
724 else
725 {
726 Resolution = ADC_SAR_IP_RESULT_RESOLUTION;
727 }
728 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
729
730 /* If the result is left aligned, adjust register mask accordingly */
731 if (Adc_Sar_Ip_axAdcSarState[Instance].DataAlign == ADC_SAR_IP_DATA_ALIGNED_LEFT)
732 {
733 /* Assumption: the width of the register is less than 16 */
734 CdrMask = (uint32)ADC_CDR_CDATA_MASK << (16u - Resolution);
735 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
736 Result = ((uint16)(Cdr & CdrMask)) >> ADC_CDR_CDATA_SHIFT;
737 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
738 }
739 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
740 else
741 {
742 CdrMask = ((uint32)ADC_CDR_CDATA_MASK >> 1u) & ((uint32)ADC_CDR_CDATA_MASK << (ADC_SAR_IP_RESULT_RESOLUTION - Resolution));
743 Result = ((uint16)(Cdr & CdrMask)) >> (ADC_SAR_IP_RESULT_RESOLUTION - Resolution + ADC_CDR_CDATA_SHIFT);
744 }
745 #else
746 Result = ((uint16)(Cdr & CdrMask)) >> ADC_CDR_CDATA_SHIFT;
747 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
748 return Result;
749 }
750
751
752 /*FUNCTION*********************************************************************
753 *
754 * Function Name : Adc_Sar_GetMsrFlags
755 * Description : Returns the flag status from MSR register
756 *
757 *END*************************************************************************/
Adc_Sar_GetMsrFlags(const uint32 Instance)758 static inline uint32 Adc_Sar_GetMsrFlags(const uint32 Instance)
759 {
760 uint32 Msr = 0U;
761 uint32 Flags = 0U;
762 const ADC_Type * AdcBasePtr = NULL_PTR;
763 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
764 const SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
765 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
766
767 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
768 if (Instance >= ADC_INSTANCE_COUNT)
769 {
770 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
771 Msr = AdcAEBasePtr->MSR;
772 }
773 else
774 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
775 {
776 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
777 Msr = AdcBasePtr->MSR;
778 }
779
780 #if FEATURE_ADC_HAS_CALIBRATION
781 Flags |= ((Msr & ADC_MSR_CALIBRTD_MASK) != 0U) ? ADC_SAR_IP_STATUS_FLAG_CALIBRATED : 0U;
782 #endif /* FEATURE_ADC_HAS_CALIBRATION */
783 Flags |= ((Msr & ADC_MSR_NSTART_MASK) != 0U) ? ADC_SAR_IP_STATUS_FLAG_NORMAL_STARTED : 0U;
784 Flags |= ((Msr & ADC_MSR_JABORT_MASK) != 0U) ? ADC_SAR_IP_STATUS_FLAG_INJECTED_ABORTED : 0U;
785 Flags |= ((Msr & ADC_MSR_JSTART_MASK) != 0U) ? ADC_SAR_IP_STATUS_FLAG_INJECTED_STARTED : 0U;
786 #if FEATURE_ADC_HAS_CTU
787 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
788 if (ADC_SAR_IP_INST_HAS_CTU(Instance))
789 {
790 #endif /*FEATURE_ADC_BAD_ACCESS_PROT_FEATURE*/
791 Flags |= ((Msr & ADC_MSR_CTUSTART_MASK) != 0U) ? ADC_SAR_IP_STATUS_FLAG_CTU_STARTED : 0U;
792 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
793 }
794 #endif /*FEATURE_ADC_BAD_ACCESS_PROT_FEATURE*/
795 #endif /* FEATURE_ADC_HAS_CTU */
796 Flags |= ((Msr & ADC_MSR_ACKO_MASK) != 0U) ? ADC_SAR_IP_STATUS_FLAG_AUTOCLOCKOFF : 0U;
797
798 return Flags;
799 }
800
801 /*FUNCTION*********************************************************************
802 *
803 * Function Name : Adc_Sar_GetIsrFlags
804 * Description : Returns the flag status from ISR register
805 *
806 *END*************************************************************************/
Adc_Sar_GetIsrFlags(const uint32 Instance)807 static inline uint32 Adc_Sar_GetIsrFlags(const uint32 Instance)
808 {
809 uint32 Flags = 0U;
810 uint32 Isr = 0U;
811 const ADC_Type * AdcBasePtr = NULL_PTR;
812 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
813 const SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
814 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
815
816 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
817 if (Instance >= ADC_INSTANCE_COUNT)
818 {
819 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
820 Isr = AdcAEBasePtr->ISR;
821 }
822 else
823 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
824 {
825 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
826 Isr = AdcBasePtr->ISR;
827 }
828 Flags |= ((Isr & ADC_ISR_EOC_MASK) != 0U) ? ADC_SAR_IP_NOTIF_FLAG_NORMAL_EOC : 0U;
829 Flags |= ((Isr & ADC_ISR_ECH_MASK) != 0U) ? ADC_SAR_IP_NOTIF_FLAG_NORMAL_ENDCHAIN : 0U;
830 Flags |= ((Isr & ADC_ISR_JEOC_MASK) != 0U) ? ADC_SAR_IP_NOTIF_FLAG_INJECTED_EOC : 0U;
831 Flags |= ((Isr & ADC_ISR_JECH_MASK) != 0U) ? ADC_SAR_IP_NOTIF_FLAG_INJECTED_ENDCHAIN : 0U;
832 #if FEATURE_ADC_HAS_CTU
833 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
834 if (ADC_SAR_IP_INST_HAS_CTU(Instance))
835 {
836 #endif /*FEATURE_ADC_BAD_ACCESS_PROT_FEATURE*/
837 Flags |= ((Isr & ADC_ISR_EOCTU_MASK) != 0U) ? ADC_SAR_IP_NOTIF_FLAG_CTU_EOC : 0U;
838 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
839 }
840 #endif /*FEATURE_ADC_BAD_ACCESS_PROT_FEATURE*/
841 #endif /* FEATURE_ADC_HAS_CTU */
842
843 return Flags;
844 }
845
846 #if ADC_SAR_IP_HAS_ADCLKSEL
847 /*FUNCTION*********************************************************************
848 *
849 * Function Name : Adc_Sar_GetADCLKSELValue
850 * Description : This function returns the value that ADCLKSEL field should
851 * have based on the input parameter.
852 *
853 *END*************************************************************************/
Adc_Sar_GetADCLKSELValue(Adc_Sar_Ip_ClockSelType ClockSel)854 static inline uint32 Adc_Sar_GetADCLKSELValue(Adc_Sar_Ip_ClockSelType ClockSel)
855 {
856 #if FEATURE_ADC_HAS_CLKSEL_EXTENDED
857 return ADC_MCR_ADCLKSEL(ClockSel);
858 #else
859 uint32 Temp = 0u;
860 switch (ClockSel)
861 {
862 case ADC_SAR_IP_CLK_FULL_BUS:
863 /* Full bus clock when MCR[ADCLKSEL] = 1 */
864 Temp = ADC_MCR_ADCLKSEL(1U);
865 break;
866 case ADC_SAR_IP_CLK_HALF_BUS:
867 /* Half bus clock when MCR[ADCLKSEL] = 0 */
868 break;
869 default:
870 /* no-op */
871 break;
872 }
873 return Temp;
874 #endif /* FEATURE_ADC_HAS_CLKSEL_EXTENDED */
875 }
876 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
877
878 /*FUNCTION*********************************************************************
879 *
880 * Function Name : Adc_Sar_CollectMcrMasks
881 * Description : The function collects the mask for MCR register from provided
882 * structure. The funcion is used to reduce the complexity of Adc_Sar_Ip_Init()
883 *
884 *END*************************************************************************/
Adc_Sar_CollectMcrMasks(const uint32 Instance,const Adc_Sar_Ip_ConfigType * const Config,uint32 InitialMcr)885 static inline uint32 Adc_Sar_CollectMcrMasks(const uint32 Instance,
886 const Adc_Sar_Ip_ConfigType * const Config,
887 uint32 InitialMcr)
888 {
889 uint32 Mcr = InitialMcr;
890
891 Mcr &= ~(ADC_MCR_MODE_MASK);
892 Mcr |= ADC_MCR_MODE(Config->ConvMode);
893 #if ADC_SAR_IP_HAS_ADCLKSEL
894 Mcr &= ~(ADC_MCR_ADCLKSEL_MASK);
895 Mcr |= Adc_Sar_GetADCLKSELValue(Config->ClkSelect);
896 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
897 Mcr &= ~(ADC_MCR_ACKO_MASK);
898 Mcr |= Adc_Sar_GetValueFromBool(Config->AutoClockOff, ADC_MCR_ACKO_MASK, 0U);
899 Mcr &= ~(ADC_MCR_OWREN_MASK);
900 Mcr |= Adc_Sar_GetValueFromBool(Config->OverwriteEnable, ADC_MCR_OWREN_MASK, 0U);
901 Mcr &= ~(ADC_MCR_WLSIDE_MASK);
902 Mcr |= ADC_MCR_WLSIDE(Config->DataAlign);
903
904 #if FEATURE_ADC_HAS_CTU
905 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
906 if (ADC_SAR_IP_INST_HAS_CTU(Instance))
907 {
908 #endif /*FEATURE_ADC_BAD_ACCESS_PROT_FEATURE*/
909 Mcr &= ~(ADC_MCR_CTUEN_MASK | ADC_MCR_CTU_MODE_MASK); /* Clear CTU_MODE bit of MCR*/
910
911 switch (Config->CtuMode)
912 {
913 case ADC_SAR_IP_CTU_MODE_CONTROL:
914 Mcr |= ADC_MCR_CTUEN(1U); /* Enable CTU */
915 break;
916 #if FEATURE_ADC_HAS_CTU_TRIGGER_MODE
917 case ADC_SAR_IP_CTU_MODE_TRIGGER:
918 Mcr |= ADC_MCR_CTU_MODE(1U); /* Set CTU to Trigger Mode CTU_MODE = 1 */
919 Mcr |= ADC_MCR_CTUEN(1U); /* Enable CTU */
920 break;
921 #endif /* FEATURE_ADC_HAS_CTU_TRIGGER_MODE */
922 case ADC_SAR_IP_CTU_MODE_DISABLED:
923 /* CTU is disabled (CTUEN = 0 and CTU_MODE = 0) */
924 /* Pass through */
925 default:
926 ; /* no-op */
927 break;
928 }
929 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
930 }
931 #endif /*FEATURE_ADC_BAD_ACCESS_PROT_FEATURE*/
932 #endif /* FEATURE_ADC_HAS_CTU */
933 #if (ADC_SAR_IP_EXTERNAL_TRIGGER_ENABLE)
934 #if FEATURE_ADC_HAS_INJ_EXT_TRIGGER
935 switch (Config->InjectedEdge)
936 {
937 case ADC_SAR_IP_EXT_TRIG_EDGE_FALLING:
938 /* Already on falling edge JEDGE = 0 */
939 Mcr &= ~(ADC_MCR_JTRGEN_MASK);
940 Mcr |= ADC_MCR_JTRGEN_MASK; /* enable Injected trigger */
941 break;
942 case ADC_SAR_IP_EXT_TRIG_EDGE_RISING:
943 /* Enable Injected trigger and set to rising edge JEDGE = 1 */
944 Mcr &= ~(ADC_MCR_JEDGE_MASK | ADC_MCR_JTRGEN_MASK);
945 Mcr |= (ADC_MCR_JEDGE_MASK | ADC_MCR_JTRGEN_MASK);
946 break;
947 case ADC_SAR_IP_EXT_TRIG_EDGE_DISABLED:
948 /* Already set to injected trigger disabled (JTRGEN = 0 and JEDGE = 0) */
949 default:
950 ; /* no-op */
951 break;
952 }
953 #endif /* FEATURE_ADC_HAS_INJ_EXT_TRIGGER */
954 #endif /* (ADC_SAR_IP_EXTERNAL_TRIGGER_ENABLE) */
955
956 #if (ADC_SAR_IP_EXTERNAL_TRIGGER_ENABLE)
957 #if FEATURE_ADC_HAS_EXT_TRIGGER
958 /* Get normal trigger masks */
959 Mcr &= ~(ADC_MCR_EDGE_MASK);
960 Mcr |= (Config->ExtTrigger == ADC_SAR_IP_EXT_TRIG_EDGE_RISING) ? (ADC_MCR_EDGE(1U)) : 0U;
961 if (Config->ExtTrigger != ADC_SAR_IP_EXT_TRIG_EDGE_DISABLED)
962 {
963 Mcr &= ~(ADC_MCR_TRGEN_MASK);
964 Mcr |= Adc_Sar_GetValueFromBool(Config->NormalExtTrgEn, ADC_MCR_TRGEN_MASK, 0U);
965 #if FEATURE_ADC_HAS_AUX_EXT_TRIGGER
966 Mcr &= ~(ADC_MCR_XSTRTEN_MASK);
967 Mcr |= Adc_Sar_GetValueFromBool(Config->NormalAuxExtTrgEn, ADC_MCR_XSTRTEN_MASK, 0U);
968 #endif /* FEATURE_ADC_HAS_AUX_EXT_TRIGGER */
969 }
970 #endif /* FEATURE_ADC_HAS_EXT_TRIGGER */
971 #endif /* (ADC_SAR_IP_EXTERNAL_TRIGGER_ENABLE) */
972
973 #if FEATURE_ADC_HAS_AVERAGING
974 Mcr &= ~(ADC_MCR_AVGEN_MASK);
975 Mcr |= Adc_Sar_GetValueFromBool(Config->AvgEn, ADC_MCR_AVGEN_MASK, 0U);
976 Mcr &= ~(ADC_MCR_AVGS_MASK);
977 Mcr |= ADC_MCR_AVGS(Config->AvgSel);
978 #else
979 #if FEATURE_ADC_HAS_CALIBRATION
980 /* On platforms that use AVGEN only for calibration, reset to default value */
981 Mcr |= ADC_MCR_AVGEN_MASK;
982 #endif /* FEATURE_ADC_HAS_CALIBRATION */
983 #endif /* FEATURE_ADC_HAS_AVERAGING */
984
985 #if FEATURE_ADC_HAS_CALIBRATION
986 #if ADC_SAR_IP_CALIBRATION_USES_MCR
987 /* Reset NRSMPL to default value */
988 Mcr &= ~(ADC_MCR_NRSMPL_MASK);
989 Mcr |= ADC_MCR_NRSMPL_MASK;
990 #endif /* ADC_SAR_IP_CALIBRATION_USES_MCR */
991 #endif /* FEATURE_ADC_HAS_CALIBRATION */
992
993 return Mcr;
994 }
995
996 /*FUNCTION*********************************************************************
997 *
998 * Function Name : Adc_Sar_ConfigChannels
999 * Description : Configure a list of channels by enabling channel notifications
1000 * and setting presampling.
1001 *END*************************************************************************/
Adc_Sar_ConfigChannels(const uint32 Instance,const Adc_Sar_Ip_ChanConfigType * ChannelConfigsPtr,uint8 NumChannels)1002 static inline void Adc_Sar_ConfigChannels(const uint32 Instance,
1003 const Adc_Sar_Ip_ChanConfigType * ChannelConfigsPtr,
1004 uint8 NumChannels)
1005 {
1006 uint8 Index;
1007 uint32 VectAdr;
1008 uint32 VectBit;
1009 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
1010 uint32 CimrMask[ADC_SAR_IP_NUM_GROUP_CHAN] = ADC_SAR_IP_NUM_GROUP_CHAN_INIT_VAL;
1011 #else
1012 const uint32 CimrMask[ADC_SAR_IP_NUM_GROUP_CHAN] = ADC_SAR_IP_NUM_GROUP_CHAN_INIT_VAL;
1013 #endif
1014 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
1015 uint32 CwenrMask[ADC_SAR_IP_NUM_GROUP_CHAN] = ADC_SAR_IP_NUM_GROUP_CHAN_INIT_VAL;
1016 #else
1017 const uint32 CwenrMask[ADC_SAR_IP_NUM_GROUP_CHAN] = ADC_SAR_IP_NUM_GROUP_CHAN_INIT_VAL;
1018 #endif
1019 uint32 DmarMask[ADC_SAR_IP_NUM_GROUP_CHAN] = ADC_SAR_IP_NUM_GROUP_CHAN_INIT_VAL;
1020 #if FEATURE_ADC_HAS_PRESAMPLING
1021 uint32 PsrMask[ADC_SAR_IP_NUM_GROUP_CHAN] = ADC_SAR_IP_NUM_GROUP_CHAN_INIT_VAL;
1022 #endif /* FEATURE_ADC_HAS_PRESAMPLING */
1023 const Adc_Sar_Ip_ChanConfigType * ChnConfig;
1024
1025 ADC_Type * AdcBasePtr = NULL_PTR;
1026 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1027 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
1028 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1029
1030 for (Index = 0U; Index < NumChannels; Index++)
1031 {
1032 ChnConfig = &(ChannelConfigsPtr[Index]);
1033 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
1034 /* Each CWSELR register contains 8 watchdog selections according to 8 channels
1035 Each watchdog selection possibly needs maximum 4 bits for setting
1036 This is to calculate the CWSELR register index and position of channel on that register */
1037 VectAdr = (uint32)ChnConfig->ChanIndex / 8U;
1038 VectBit = (uint32)ChnConfig->ChanIndex % 8U;
1039 #if FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL
1040 if (ADC_SAR_IP_INST_HAS_CWSELRn(Instance, VectAdr))
1041 {
1042 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL */
1043 Adc_Sar_WriteChannelMapping(Instance, VectAdr, VectBit, ChnConfig->WdgThreshRegIndex);
1044 /* Store threshold register index for configured channel */
1045 Adc_Sar_Ip_axAdcSarState[Instance].ChanWdgThresholdIndex[ChnConfig->ChanIndex] = ChnConfig->WdgThreshRegIndex;
1046 #if FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL
1047 }
1048 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL */
1049 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
1050
1051 VectAdr = ADC_SAR_IP_CHAN_2_VECT((uint32)ChnConfig->ChanIndex);
1052 VectBit = ADC_SAR_IP_CHAN_2_BIT((uint32)ChnConfig->ChanIndex);
1053 /* Collect bit-mask for WDG, EOC, DMA and Presample */
1054 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
1055 CimrMask[VectAdr] |= Adc_Sar_GetValueFromBool(ChnConfig->EndOfConvNotification, (1UL << VectBit), 0UL);
1056 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
1057 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
1058 CwenrMask[VectAdr] |= Adc_Sar_GetValueFromBool(ChnConfig->WdgNotificationEn, (1UL << VectBit), 0UL);
1059 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
1060 DmarMask[VectAdr] |= Adc_Sar_GetValueFromBool(ChnConfig->EndOfConvDmaEnable, (1UL << VectBit), 0UL);
1061 #if FEATURE_ADC_HAS_PRESAMPLING
1062 PsrMask[VectAdr] |= Adc_Sar_GetValueFromBool(ChnConfig->PresamplingEnable, (1UL << VectBit), 0UL);
1063 #endif /* FEATURE_ADC_HAS_PRESAMPLING */
1064 }
1065
1066 /* Enable WDG, EOC, DMA and Presample */
1067 for (Index = 0U; Index < Adc_Sar_Ip_au8AdcGroupCount[Instance]; Index++)
1068 {
1069 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1070 if (Instance >= ADC_INSTANCE_COUNT)
1071 {
1072 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
1073 CIMR(AdcAEBasePtr, Index) = CimrMask[Index];
1074 CWENR(AdcAEBasePtr, Index) = CwenrMask[Index];
1075 DMAR(AdcAEBasePtr, Index) = DmarMask[Index];
1076 #if FEATURE_ADC_HAS_PRESAMPLING
1077 PSR(AdcAEBasePtr, Index) = PsrMask[Index];
1078 #endif /* FEATURE_ADC_HAS_PRESAMPLING */
1079 }
1080 else
1081 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1082 {
1083 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
1084 CIMR(AdcBasePtr, Index) = CimrMask[Index];
1085 CWENR(AdcBasePtr, Index) = CwenrMask[Index];
1086 DMAR(AdcBasePtr, Index) = DmarMask[Index];
1087 #if FEATURE_ADC_HAS_PRESAMPLING
1088 PSR(AdcBasePtr, Index) = PsrMask[Index];
1089 #endif /* FEATURE_ADC_HAS_PRESAMPLING */
1090 }
1091 }
1092 }
1093
1094 #if (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED)
1095 /*FUNCTION*********************************************************************
1096 *
1097 * Function Name : Adc_Sar_CheckSelfTestProgress
1098 * Description : Configures watchdog threshold with provided array of configuration
1099 *
1100 *END*************************************************************************/
Adc_Sar_CheckSelfTestProgress(const uint32 Instance)1101 static inline Adc_Sar_Ip_StatusType Adc_Sar_CheckSelfTestProgress(const uint32 Instance)
1102 {
1103 Adc_Sar_Ip_StatusType Status = ADC_SAR_IP_STATUS_SUCCESS;
1104 uint32 Reg = 0U;
1105 uint32 TimeoutTicks = OsIf_MicrosToTicks(ADC_SAR_IP_TIMEOUT_VAL, ADC_SAR_IP_TIMEOUT_TYPE);
1106 uint32 CurrentTicks = OsIf_GetCounter(ADC_SAR_IP_TIMEOUT_TYPE);
1107 uint32 ElapsedTicks;
1108 volatile const uint32 * MSRAddr = NULL_PTR;
1109 volatile const uint32 * STSR1Addr = NULL_PTR;
1110 uint8 Index;
1111
1112 const ADC_Type * AdcBasePtr = NULL_PTR;
1113 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1114 const SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
1115 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1116
1117 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1118 if (Instance >= ADC_INSTANCE_COUNT)
1119 {
1120 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
1121 MSRAddr = &(AdcAEBasePtr->MSR);
1122 STSR1Addr = &(AdcAEBasePtr->STSR1);
1123 }
1124 else
1125 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1126 {
1127 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
1128 MSRAddr = &(AdcBasePtr->MSR);
1129 STSR1Addr = &(AdcBasePtr->STSR1);
1130 }
1131
1132 /* Each for loop checks the conversion of all steps in self-test S algorithm
1133 * ForLoop(0): while (AlgS-start-1) ->S0 -> S1 -> S2 -> while (Alg-end-1) -> C0 to C11 ->
1134 * ForLoop(1): while (AlgS-start-2) ->S0 -> S1 -> S2 -> while (Alg-end-2)
1135 */
1136 for (Index = 0U; Index < 2U; Index++)
1137 {
1138 /* Wait until Alg S has started*/
1139 ElapsedTicks = 0U;
1140 while ((((*MSRAddr) & ADC_MSR_SELF_TEST_S_MASK) != ADC_MSR_SELF_TEST_S_MASK) && (ElapsedTicks < TimeoutTicks))
1141 {
1142 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
1143 }
1144 if (ElapsedTicks >= TimeoutTicks)
1145 {
1146 Status = ADC_SAR_IP_STATUS_TIMEOUT;
1147 }
1148 if (Status == ADC_SAR_IP_STATUS_SUCCESS)
1149 {
1150 /* Wait until Alg S has finished*/
1151 ElapsedTicks = 0U;
1152 while ((((*MSRAddr) & ADC_MSR_SELF_TEST_S_MASK) == ADC_MSR_SELF_TEST_S_MASK) && (ElapsedTicks < TimeoutTicks))
1153 {
1154 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
1155 }
1156 if (ElapsedTicks >= TimeoutTicks)
1157 {
1158 Status = ADC_SAR_IP_STATUS_TIMEOUT;
1159 }
1160 }
1161 if (Status == ADC_SAR_IP_STATUS_TIMEOUT)
1162 {
1163 /* Break the loop if timeout occured in order to increase performance */
1164 break;
1165 }
1166 }
1167
1168 if (Status != ADC_SAR_IP_STATUS_TIMEOUT)
1169 {
1170 Reg |= ADC_STSR1_ERR_S0_MASK;
1171 #if (defined(ADC_STSR1_ERR_S1_MASK) || defined(ADC_STSR1_ERR_S2_MASK) || defined(ADC_STSR1_ERR_C_MASK))
1172 Reg |= ADC_STSR1_ERR_S1_MASK | ADC_STSR1_ERR_S2_MASK | ADC_STSR1_ERR_C_MASK;
1173 #endif
1174 if (((*STSR1Addr) & Reg) != 0UL)
1175 {
1176 Status = ADC_SAR_IP_STATUS_ERROR;
1177 }
1178 }
1179
1180 return Status;
1181 }
1182 #endif /* (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED) */
1183 /*FUNCTION*********************************************************************
1184 *
1185 * Function Name : Adc_Sar_GetConvResults
1186 * Description : Reads the conversion results to output arrays
1187 * Params:
1188 * - Instance : the ADC Instance to read
1189 * - ChainType : the conversion chain (Normal, Injected or CTU)
1190 * - ResultsRaw : an uint16 array to write only conversion data
1191 * - ResultsStruct : an Adc_Sar_Ip_ChanResultType array to write detailed information
1192 about each conversion result
1193 * - length : the maximum size of ResultsRaw and ResultsStruct
1194 *
1195 * ResultsRaw or ResultsStruct can be NULL, but not both, as the function will
1196 * have nowhere to write the results.
1197 *
1198 *END*************************************************************************/
Adc_Sar_GetConvResults(const uint32 Instance,const Adc_Sar_Ip_ConvChainType ChainType,uint16 * const ResultsRaw,Adc_Sar_Ip_ChanResultType * const ResultsStruct,const uint32 Length)1199 static uint32 Adc_Sar_GetConvResults(const uint32 Instance,
1200 const Adc_Sar_Ip_ConvChainType ChainType,
1201 uint16 * const ResultsRaw,
1202 Adc_Sar_Ip_ChanResultType * const ResultsStruct,
1203 const uint32 Length)
1204 {
1205 uint32 Index = 0u;
1206 boolean LengthExceeded = FALSE;
1207 ADC_Type * AdcBasePtr = NULL_PTR;
1208 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1209 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
1210 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1211 uint32 VectAdr;
1212 uint32 VectBit;
1213 uint8 ChnIdx;
1214 uint32 Cdr;
1215 volatile uint32 * CEOCFRAddr = NULL_PTR;
1216 const uint16 AdcChanCount[ADC_SAR_IP_INSTANCE_COUNT][ADC_SAR_IP_NUM_GROUP_CHAN] = FEATURE_ADC_MAX_CHN_COUNT;
1217
1218 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1219 if (Instance >= ADC_INSTANCE_COUNT)
1220 {
1221 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
1222 }
1223 else
1224 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1225 {
1226 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
1227 }
1228 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
1229 /* ResultsRaw and ResultsStruct cannot be both NULL */
1230 DevAssert((ResultsRaw != NULL_PTR) || (ResultsStruct != NULL_PTR));
1231 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
1232
1233 /* Go through each channel group */
1234 for (VectAdr = 0u; VectAdr < Adc_Sar_Ip_au8AdcGroupCount[Instance]; VectAdr++)
1235 {
1236 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1237 if (Instance >= ADC_INSTANCE_COUNT)
1238 {
1239 CEOCFRAddr = &(CEOCFR(AdcAEBasePtr, VectAdr));
1240 }
1241 else
1242 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1243 {
1244 CEOCFRAddr = &(CEOCFR(AdcBasePtr, VectAdr));
1245 }
1246 /* go through each bit in the group, check if there is a completed conversion */
1247 for (VectBit = 0u; VectBit < AdcChanCount[Instance][VectAdr]; VectBit++)
1248 {
1249 ChnIdx = (uint8)((VectAdr * 32u) + VectBit);
1250 #if FEATURE_ADC_SAF8544_CHANNEL_WORKAROUND
1251 if ((0u == ChnIdx) && ((ADC_SAR_IP_CONV_CHAIN_INJECTED == ChainType) || (ADC_SAR_IP_CONV_CHAIN_CTU == ChainType)))
1252 {
1253 continue;
1254 }
1255 #endif /* FEATURE_ADC_SAF8544_CHANNEL_WORKAROUND */
1256 #if FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL
1257 if (!(ADC_SAR_IP_INST_HAS_CDRn(Instance, ChnIdx)))
1258 {
1259 continue; /* skip if the CDR register is not available */
1260 }
1261 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL */
1262 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1263 if (Instance >= ADC_INSTANCE_COUNT)
1264 {
1265 Cdr = CDR_AE(AdcAEBasePtr, ChnIdx);
1266 }
1267 else
1268 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1269 {
1270 Cdr = CDR(AdcBasePtr, ChnIdx);
1271 }
1272
1273 if ((ADC_CDR_RESULT((uint32)ChainType) | ADC_CDR_VALID_MASK) == (Cdr & (ADC_CDR_RESULT_MASK | ADC_CDR_VALID_MASK)))
1274 {
1275 /* if the result type matches the one request by ChainType
1276 and the data is valid, write to the output array(s)
1277 */
1278 if (ResultsRaw != NULL_PTR)
1279 {
1280 ResultsRaw[Index] = Adc_Sar_GetMaskedResult(Instance, Cdr);
1281 }
1282 if (ResultsStruct != NULL_PTR)
1283 {
1284 ResultsStruct[Index].ConvData = Adc_Sar_GetMaskedResult(Instance, Cdr);
1285 ResultsStruct[Index].AdcChnIdx = ChnIdx;
1286 ResultsStruct[Index].ValidFlag = ((Cdr & ADC_CDR_VALID_MASK) != 0U) ? TRUE : FALSE;
1287 ResultsStruct[Index].OverWrittenFlag = ((Cdr & ADC_CDR_OVERW_MASK) != 0U) ? TRUE : FALSE;
1288 }
1289 /* Increment the current Index and reset the CEOCFR flag */
1290 *CEOCFRAddr = ((uint32)1UL << VectBit); /* w1c bit */
1291 Index++;
1292 if (Index >= Length)
1293 {
1294 /* We have filled the output buffer, exit the loop.
1295 * Data may still exist in the result registers, which won't be reached.
1296 */
1297 LengthExceeded = TRUE;
1298 break;
1299 }
1300 }
1301 }
1302 if (LengthExceeded)
1303 {
1304 break;
1305 }
1306 }
1307 return Index;
1308 }
1309
1310 /*FUNCTION*********************************************************************
1311 *
1312 * Function Name : Adc_Sar_ResetWdog
1313 * Description : Reset and disable the Analog Watchdog feature
1314 *
1315 *END*************************************************************************/
Adc_Sar_ResetWdog(const uint32 Instance)1316 static void Adc_Sar_ResetWdog(const uint32 Instance)
1317 {
1318 uint8 Index;
1319 uint8 MaxThresholdRegs = 0U;
1320
1321 ADC_Type * AdcBasePtr = NULL_PTR;
1322 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1323 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
1324 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1325
1326 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1327 if (Instance >= ADC_INSTANCE_COUNT)
1328 {
1329 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
1330 MaxThresholdRegs = ADC_SAR_AE_IP_THRHLR_COUNT;
1331 }
1332 else
1333 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1334 {
1335 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
1336 MaxThresholdRegs = ADC_SAR_IP_THRHLR_COUNT;
1337 }
1338
1339 for (Index = 0u; Index < Adc_Sar_Ip_au8AdcGroupCount[Instance]; Index++)
1340 {
1341 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1342 if (Instance >= ADC_INSTANCE_COUNT)
1343 {
1344 CWENR(AdcAEBasePtr, Index) = 0u;
1345 AWORR(AdcAEBasePtr, Index) = 0xFFFFFFFFu; /* w1c bits */
1346 }
1347 else
1348 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1349 {
1350 CWENR(AdcBasePtr, Index) = 0u;
1351 AWORR(AdcBasePtr, Index) = 0xFFFFFFFFu; /* w1c bits */
1352 }
1353
1354 }
1355
1356 for (Index = 0u; Index < MaxThresholdRegs; Index++)
1357 {
1358 Adc_Sar_WriteThresholds(Instance, Index, 0xFFFFu, 0u);
1359 }
1360
1361 for (Index = 0u; Index < ADC_SAR_IP_CWSELR_COUNT; Index++)
1362 {
1363 #if FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL
1364 if (!(ADC_SAR_IP_INST_HAS_CWSELRn(Instance, Index)))
1365 {
1366 continue; /* skip register if it's not available */
1367 }
1368 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL */
1369 Adc_Sar_ResetWdogCWSELR(Instance, Index);
1370 }
1371 }
1372
1373 #if FEATURE_ADC_HAS_CLOCK_DIVIDER
1374 /*FUNCTION*********************************************************************
1375 *
1376 * Function Name : Adc_Sar_EnableClkDiv
1377 * Description : Configure clock divider
1378 *
1379 *END*************************************************************************/
Adc_Sar_EnableClkDiv(const uint32 Instance,const boolean ClkDivEnable)1380 static inline void Adc_Sar_EnableClkDiv(const uint32 Instance,
1381 const boolean ClkDivEnable)
1382 {
1383 ADC_Type * const AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
1384
1385 /* Enable clock divider */
1386 if (ClkDivEnable)
1387 {
1388 AdcBasePtr->CLKDIV_CTRL |= ADC_CLKDIV_CTRL_CLKDIV_ENABLE(1U);
1389 }
1390 else
1391 {
1392 AdcBasePtr->CLKDIV_CTRL &= ~(ADC_CLKDIV_CTRL_CLKDIV_ENABLE_MASK);
1393 }
1394 }
1395 #endif /* FEATURE_ADC_HAS_CLOCK_DIVIDER */
1396
1397 #if ( \
1398 (STD_ON == ADC_SAR_IP_ECH_ENABLED) || (STD_ON == ADC_SAR_IP_JECH_ENABLED) || \
1399 ((FEATURE_ADC_HAS_CTU == 1U) && (STD_ON == ADC_SAR_IP_EOCTU_ENABLED)) \
1400 )
1401 /*FUNCTION*********************************************************************
1402 *
1403 * Function Name : Adc_Sar_CheckAndCallNotification
1404 * Description : Checks if the given callback is not NULL then calls it
1405 *
1406 *END*************************************************************************/
Adc_Sar_CheckAndCallNotification(void (* Callback)(void))1407 static inline void Adc_Sar_CheckAndCallNotification(void (*Callback)(void))
1408 {
1409 if (Callback != NULL_PTR)
1410 {
1411 Callback();
1412 }
1413 }
1414 #endif /* (STD_ON == ADC_SAR_IP_ECH_ENABLED) .. */
1415
1416 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
1417 /*FUNCTION*********************************************************************
1418 *
1419 * Function Name : Adc_Sar_CheckAndCallEocNotification
1420 * Description : Checks if the given channel interrupt was triggered, clears
1421 * the interrupt, check if it is not spurious, checks that the
1422 * callback is not null.
1423 *
1424 *END*************************************************************************/
Adc_Sar_CheckAndCallEocNotification(uint32 Instance,uint16 ChanIdx,uint16 VectAdr,uint32 EocFlag,boolean * CeocfrFlag)1425 static inline void Adc_Sar_CheckAndCallEocNotification(uint32 Instance,
1426 uint16 ChanIdx,
1427 uint16 VectAdr,
1428 uint32 EocFlag,
1429 boolean * CeocfrFlag)
1430 {
1431 ADC_Type * AdcBasePtr = NULL_PTR;
1432 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1433 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
1434 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1435 const uint32 Mask = (uint32)1UL << ADC_SAR_IP_CHAN_2_BIT(ChanIdx);
1436 uint32 Ceocfr = 0U;
1437 uint32 Cimr = 0U;
1438 volatile uint32 * CEOCFRAddr = NULL_PTR;
1439
1440 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1441 if (Instance >= ADC_INSTANCE_COUNT)
1442 {
1443 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
1444 CEOCFRAddr = &(CEOCFR(AdcAEBasePtr, VectAdr));
1445 Cimr = (CIMR(AdcAEBasePtr, VectAdr) & Mask);
1446 }
1447 else
1448 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1449 {
1450 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
1451 CEOCFRAddr = &(CEOCFR(AdcBasePtr, VectAdr));
1452 Cimr = (CIMR(AdcBasePtr, VectAdr) & Mask);
1453 }
1454
1455 Ceocfr = ((*CEOCFRAddr) & Mask);
1456 /* Check if the interrupt was not spurious */
1457 if ((Ceocfr != 0U) && (Cimr != 0U) && (EocFlag != 0U))
1458 {
1459 /* Clears flag by w1c */
1460 *CEOCFRAddr = Mask;
1461 *CeocfrFlag = TRUE;
1462
1463 /* Check if the callback is not null */
1464 if (Adc_Sar_Ip_axAdcSarState[Instance].EndOfConvNotification != NULL_PTR)
1465 {
1466 Adc_Sar_Ip_axAdcSarState[Instance].EndOfConvNotification(ChanIdx);
1467 }
1468 }
1469 }
1470 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
1471
1472 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
1473 /*FUNCTION*********************************************************************
1474 *
1475 * Function Name : Adc_Sar_CheckAndCallWorrNotification
1476 * Description : Checks if the given channel interrupt was triggered, clears
1477 * the interrupt, check if it is not spurious, checks that the
1478 * callback is not null and return WTISR flag
1479 * in order to be cleared outside of this function when loop of all channels is completed.
1480 *
1481 *END*************************************************************************/
Adc_Sar_CheckAndCallWorrNotification(uint32 Instance,uint16 ChanIdx,uint16 VectAdr)1482 static inline uint32 Adc_Sar_CheckAndCallWorrNotification(uint32 Instance,
1483 uint16 ChanIdx,
1484 uint16 VectAdr)
1485 {
1486 ADC_Type * AdcBasePtr = NULL_PTR;
1487 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1488 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
1489 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1490 const uint32 Mask = (uint32)1UL << ADC_SAR_IP_CHAN_2_BIT(ChanIdx);
1491 uint32 Aworr = 0U;
1492 uint32 Cwenr = 0U;
1493 uint32 Wtisr = 0U;
1494 uint32 Wtimr = 0U;
1495 uint32 WdgFlags = 0U;
1496 uint32 ThresholdIndex;
1497 volatile uint32 * AWORRAddr;
1498
1499 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1500 if (Instance >= ADC_INSTANCE_COUNT)
1501 {
1502 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
1503 AWORRAddr = &(AWORR(AdcAEBasePtr, VectAdr));
1504 Cwenr = (CWENR(AdcAEBasePtr, VectAdr) & Mask);
1505 Wtisr = AdcAEBasePtr->WTISR;
1506 Wtimr = AdcAEBasePtr->WTIMR;
1507 }
1508 else
1509 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1510 {
1511 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
1512 AWORRAddr = &(AWORR(AdcBasePtr, VectAdr));
1513 Cwenr = (CWENR(AdcBasePtr, VectAdr) & Mask);
1514 Wtisr = AdcBasePtr->WTISR;
1515 Wtimr = AdcBasePtr->WTIMR;
1516 }
1517 Aworr = ((*AWORRAddr) & Mask);
1518
1519 /* Check if wdg channel enabled associated to the wdg out of range flag */
1520 if ((Aworr != 0U) && (Cwenr != 0U))
1521 {
1522 /* Get the mapping threshold register index corresponding to the configured channel */
1523 ThresholdIndex = Adc_Sar_Ip_axAdcSarState[Instance].ChanWdgThresholdIndex[ChanIdx];
1524
1525 /* Check if the high/low flags were not set spuriously. */
1526 if ((Wtimr & (ADC_SAR_IP_WDG_REG_MASK_LOW(ThresholdIndex))) != 0u)
1527 {
1528 WdgFlags |= ((Wtisr & ADC_SAR_IP_WDG_REG_MASK_LOW(ThresholdIndex)) != 0u) ? ADC_SAR_IP_WDG_LOW_FLAG : 0u;
1529 }
1530 if ((Wtimr & (ADC_SAR_IP_WDG_REG_MASK_HIGH(ThresholdIndex))) != 0u)
1531 {
1532 WdgFlags |= ((Wtisr & ADC_SAR_IP_WDG_REG_MASK_HIGH(ThresholdIndex)) != 0u) ? ADC_SAR_IP_WDG_HIGH_FLAG : 0u;
1533 }
1534 if (WdgFlags != 0u)
1535 {
1536 /* Only clear relevant flags if interrupt is not spurious (i.e: satisfy combination of AWORR-CWENR and WTISR-WTIMR) */
1537 *AWORRAddr = Mask;
1538 /* Multiple ADC channels can use same THRHLRx so return the associated WTISR flag value of that threshold
1539 which will be used for clearing all WTISR flags outside of this function, when completing the loop for ADC channels */
1540 WdgFlags = WdgFlags << (ThresholdIndex << 1);
1541 /* Check if the callback is not null */
1542 if (Adc_Sar_Ip_axAdcSarState[Instance].WdgOutOfRangeNotification != NULL_PTR)
1543 {
1544 Adc_Sar_Ip_axAdcSarState[Instance].WdgOutOfRangeNotification(ChanIdx, WdgFlags);
1545 }
1546 }
1547 }
1548
1549 return WdgFlags;
1550 }
1551 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
1552
1553 #if ((STD_ON == ADC_SAR_IP_WDG_ENABLED) || (STD_ON == ADC_SAR_IP_EOC_ENABLED))
1554 /*LOCAL FUNCTION*********************************************************************
1555 *
1556 * Function Name : Adc_CheckAndCallAllChannelNotification
1557 * Description : Check for all watchdog interrupts and for all individual channel interrupts
1558 * if it was detected. And then call the appropriate notification
1559 *
1560 *END*********************************************************************************/
Adc_CheckAndCallAllChannelNotification(const uint32 Instance)1561 static inline void Adc_CheckAndCallAllChannelNotification(const uint32 Instance)
1562 {
1563 ADC_Type * AdcBasePtr = NULL_PTR;
1564 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1565 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
1566 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1567 uint16 VectAdr;
1568 uint16 PhyChan;
1569 uint16 ChanCnt;
1570 const uint16 AdcChanCount[ADC_SAR_IP_INSTANCE_COUNT][ADC_SAR_IP_NUM_GROUP_CHAN] = FEATURE_ADC_MAX_CHN_COUNT;
1571 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
1572 uint32 WtisrMask = 0U;
1573 volatile uint32 * WTISRAddr = NULL_PTR;
1574 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
1575 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
1576 volatile const uint32 * IMRAddr = NULL_PTR;
1577 volatile uint32 * ISRAddr = NULL_PTR;
1578 uint32 EocFlag = 0U;
1579 boolean CeocfrFlag = FALSE;
1580 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
1581
1582 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1583 if (Instance >= ADC_INSTANCE_COUNT)
1584 {
1585 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
1586 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
1587 IMRAddr = &(AdcAEBasePtr->IMR);
1588 ISRAddr = &(AdcAEBasePtr->ISR);
1589 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
1590 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
1591 WTISRAddr = &(AdcAEBasePtr->WTISR);
1592 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
1593 }
1594 else
1595 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1596 {
1597 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
1598 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
1599 IMRAddr = &(AdcBasePtr->IMR);
1600 ISRAddr = &(AdcBasePtr->ISR);
1601 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
1602 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
1603 WTISRAddr = &(AdcBasePtr->WTISR);
1604 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
1605 }
1606 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
1607 /* EocFlag = 0 if all EOC flags are spurious interrupts */
1608 /* Avoid Compiler Warning about accessing two volatile variables simultaneously */
1609 EocFlag = (*IMRAddr);
1610 EocFlag &= (*ISRAddr);
1611 EocFlag &= (ADC_ISR_EOC_MASK | ADC_ISR_JEOC_MASK);
1612
1613 /* Clear EOC Flag */
1614 if (EocFlag != 0)
1615 {
1616 *ISRAddr = EocFlag;
1617 }
1618 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
1619
1620 for (VectAdr = 0U; VectAdr < Adc_Sar_Ip_au8AdcGroupCount[Instance]; VectAdr++)
1621 {
1622 for (ChanCnt = 0U; ChanCnt < AdcChanCount[Instance][VectAdr]; ChanCnt++)
1623 {
1624 PhyChan = (ChanCnt + (uint16)(ADC_SAR_IP_HW_REG_SIZE * VectAdr));
1625
1626 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
1627 /* Check end of conversion interrupt */
1628 Adc_Sar_CheckAndCallEocNotification(Instance, PhyChan, VectAdr, EocFlag, &CeocfrFlag);
1629 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
1630
1631 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
1632 /* Check watchdog out of range interrupt */
1633 WtisrMask |= Adc_Sar_CheckAndCallWorrNotification(Instance, PhyChan, VectAdr);
1634 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
1635 }
1636 }
1637
1638 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
1639 if (WtisrMask != 0U)
1640 {
1641 *WTISRAddr = WtisrMask;
1642 }
1643 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
1644 }
1645 #endif /* ((STD_ON == ADC_SAR_IP_WDG_ENABLED) || (STD_ON == ADC_SAR_IP_EOC_ENABLED)) */
1646
1647 #if (ADC_SAR_IP_EXTERNAL_TRIGGER_ENABLE)
1648 #if (FEATURE_ADC_HAS_INJ_EXT_TRIGGER || FEATURE_ADC_HAS_EXT_TRIGGER)
1649 /*FUNCTION**********************************************************************
1650 *
1651 * Function Name : Adc_Sar_ConfigExternalTrigger
1652 * Description : This function configures the external trigger.
1653 *
1654 * END**************************************************************************/
Adc_Sar_ConfigExternalTrigger(const uint32 Instance,const Adc_Sar_Ip_ExtTriggerEdgeType TriggerEdge,const uint32 TrgEdgeSetMask,const uint32 TrgEdgeClrMask,const uint32 TrigSrcMask)1655 static inline void Adc_Sar_ConfigExternalTrigger(const uint32 Instance,
1656 const Adc_Sar_Ip_ExtTriggerEdgeType TriggerEdge,
1657 const uint32 TrgEdgeSetMask,
1658 const uint32 TrgEdgeClrMask,
1659 const uint32 TrigSrcMask)
1660 {
1661 ADC_Type * AdcBasePtr = NULL_PTR;
1662 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1663 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
1664 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1665 volatile uint32 * MCRAddr = NULL_PTR;
1666
1667 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1668 if (Instance >= ADC_INSTANCE_COUNT)
1669 {
1670 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
1671 MCRAddr = &(AdcAEBasePtr->MCR);
1672 }
1673 else
1674 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1675 {
1676 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
1677 MCRAddr = &(AdcBasePtr->MCR);
1678 }
1679 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_21();
1680
1681 switch (TriggerEdge)
1682 {
1683 case ADC_SAR_IP_EXT_TRIG_EDGE_FALLING:
1684 *MCRAddr &= ~TrgEdgeSetMask; /* set to falling edge 0 */
1685 *MCRAddr |= TrigSrcMask; /* enable external trigger */
1686 break;
1687 case ADC_SAR_IP_EXT_TRIG_EDGE_RISING:
1688 /* enable external trigger and set to rising edge EDGE = 1 */
1689 *MCRAddr |= (TrgEdgeSetMask | TrigSrcMask);
1690 break;
1691 case ADC_SAR_IP_EXT_TRIG_EDGE_DISABLED:
1692 /* disable external trigger and reset edge field */
1693 *MCRAddr &= ~(TrgEdgeClrMask | TrigSrcMask);
1694 break;
1695 default:
1696 ; /* no-op */
1697 break;
1698 }
1699
1700 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_21();
1701 }
1702 #endif /* (FEATURE_ADC_HAS_INJ_EXT_TRIGGER || FEATURE_ADC_HAS_EXT_TRIGGER) */
1703 #endif /* (ADC_SAR_IP_EXTERNAL_TRIGGER_ENABLE) */
1704
1705 #if FEATURE_ADC_HAS_TEMPSENSE_CHN
1706 #if (ADC_SAR_IP_TEMPSENSE_ENABLED == STD_ON)
1707 /*FUNCTION**********************************************************************
1708 *
1709 * Function Name : Adc_Sar_TempsenseConvFp2Int
1710 * Description : The function converts the number in signed fixed point format
1711 * (1,11,4) to the integer number multipled with ADC_SAR_IP_TEMPSENSE_MULTIPLIER to avoid
1712 * rounding the decimal part.
1713 *
1714 *END**************************************************************************/
Adc_Sar_TempsenseConvFp2Int(const uint32 FloatingPoint)1715 static inline uint32 Adc_Sar_TempsenseConvFp2Int(const uint32 FloatingPoint)
1716 {
1717 uint32 RetVal;
1718
1719 /* The integer and decimal part multiple with ADC_SAR_IP_TEMPSENSE_MULTIPLIER to avoid rounding the decimal part */
1720 RetVal = ((FloatingPoint & ADC_SAR_IP_TEMPSENSE_INTEGER_MASK) >> ADC_SAR_IP_TEMPSENSE_INTEGER_SHIFT) * ADC_SAR_IP_TEMPSENSE_MULTIPLIER;
1721 RetVal += ((FloatingPoint & ADC_SAR_IP_TEMPSENSE_DECIMAL_MASK) * ADC_SAR_IP_TEMPSENSE_MULTIPLIER) / (ADC_SAR_IP_TEMPSENSE_DECIMAL_MASK + 1U);
1722
1723 return RetVal;
1724 }
1725
1726 /*FUNCTION**********************************************************************
1727 *
1728 * Function Name : Adc_Sar_TempsenseConvInt2Fp
1729 * Description : The function converts the number in integer number to signed fixed
1730 * point format (1,11,4). The integer number parameter is multipled with ADC_SAR_IP_TEMPSENSE_MULTIPLIER
1731 *
1732 *END**************************************************************************/
Adc_Sar_TempsenseConvInt2Fp(const sint32 SignedInteger)1733 static inline uint16 Adc_Sar_TempsenseConvInt2Fp(const sint32 SignedInteger)
1734 {
1735 uint16 RetVal;
1736 uint32 Temp;
1737
1738 if (SignedInteger < 0)
1739 {
1740 RetVal = ADC_SAR_IP_TEMPSENSE_SIGN_MASK;
1741 Temp = (uint32)(- SignedInteger);
1742 }
1743 else
1744 {
1745 RetVal = 0U;
1746 Temp = (uint32)SignedInteger;
1747 }
1748
1749 /* Calculates the integer part */
1750 RetVal |= (uint16)(((Temp / ADC_SAR_IP_TEMPSENSE_MULTIPLIER) << ADC_SAR_IP_TEMPSENSE_INTEGER_SHIFT) & ADC_SAR_IP_TEMPSENSE_INTEGER_MASK);
1751 /* Calculates the decimal part */
1752 RetVal |= (uint16)(((Temp % ADC_SAR_IP_TEMPSENSE_MULTIPLIER) * (ADC_SAR_IP_TEMPSENSE_DECIMAL_MASK + 1U)) / ADC_SAR_IP_TEMPSENSE_MULTIPLIER);
1753
1754 return RetVal;
1755 }
1756 #endif /* (ADC_SAR_IP_TEMPSENSE_ENABLED == STD_ON) */
1757 #endif /* FEATURE_ADC_HAS_TEMPSENSE_CHN */
1758
1759 /*FUNCTION*********************************************************************
1760 *
1761 * Function Name : Adc_Sar_Ip_IRQHandler
1762 * Description : Handles Adc Sar interrupts
1763 *
1764 * @implements Adc_Sar_Ip_IRQHandler_Activity
1765 *END*************************************************************************/
Adc_Sar_Ip_IRQHandler(const uint32 Instance)1766 void Adc_Sar_Ip_IRQHandler(const uint32 Instance)
1767 {
1768 ADC_Type * AdcBasePtr = NULL_PTR;
1769 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1770 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
1771 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1772 volatile uint32 * ISRAddr = NULL_PTR;
1773 volatile uint32 * WTISRAddr = NULL_PTR;
1774 uint32 Isr = 0u;
1775 uint32 Wtisr = 0u;
1776 #if ((FEATURE_ADC_HAS_CTU && (STD_ON == ADC_SAR_IP_EOCTU_ENABLED)) || \
1777 (STD_ON == ADC_SAR_IP_ECH_ENABLED) || \
1778 (STD_ON == ADC_SAR_IP_JECH_ENABLED))
1779 uint32 Imr = 0u;
1780 #endif /* (FEATURE_ADC_HAS_CTU && (STD_ON == ADC_SAR_IP_EOCTU_ENABLED)) || ... */
1781
1782 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
1783 DevAssert(Instance < ADC_SAR_IP_INSTANCE_COUNT);
1784 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
1785
1786 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1787 if (Instance >= ADC_INSTANCE_COUNT)
1788 {
1789 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
1790 ISRAddr = &(AdcAEBasePtr->ISR);
1791 WTISRAddr = &(AdcAEBasePtr->WTISR);
1792 #if ((FEATURE_ADC_HAS_CTU && (STD_ON == ADC_SAR_IP_EOCTU_ENABLED)) || \
1793 (STD_ON == ADC_SAR_IP_ECH_ENABLED) || \
1794 (STD_ON == ADC_SAR_IP_JECH_ENABLED))
1795 Imr = AdcAEBasePtr->IMR;
1796 #endif /* (FEATURE_ADC_HAS_CTU && (STD_ON == ADC_SAR_IP_EOCTU_ENABLED)) || ... */
1797 }
1798 else
1799 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1800 {
1801 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
1802 ISRAddr = &(AdcBasePtr->ISR);
1803 WTISRAddr = &(AdcBasePtr->WTISR);
1804 #if ((FEATURE_ADC_HAS_CTU && (STD_ON == ADC_SAR_IP_EOCTU_ENABLED)) || \
1805 (STD_ON == ADC_SAR_IP_ECH_ENABLED) || \
1806 (STD_ON == ADC_SAR_IP_JECH_ENABLED))
1807 Imr = AdcBasePtr->IMR;
1808 #endif /* (FEATURE_ADC_HAS_CTU && (STD_ON == ADC_SAR_IP_EOCTU_ENABLED)) || ... */
1809 }
1810
1811 /* CPR_RTD_00011 */
1812 if (Adc_Sar_Ip_axAdcSarState[Instance].InitStatus)
1813 {
1814 /* Check which interrupt was triggered and not spurious, clear it and call the associated callback */
1815 #if (FEATURE_ADC_HAS_CTU && (STD_ON == ADC_SAR_IP_EOCTU_ENABLED))
1816 if ((((*ISRAddr) & ADC_ISR_EOCTU_MASK) != 0U) && ((Imr & ADC_IMR_MSKEOCTU_MASK) != 0U))
1817 {
1818 /* CPR_RTD_00644 */
1819 *ISRAddr = ADC_ISR_EOCTU_MASK;
1820 Adc_Sar_CheckAndCallNotification(Adc_Sar_Ip_axAdcSarState[Instance].EndOfCtuConversionNotification);
1821 }
1822 #endif /* (FEATURE_ADC_HAS_CTU && (STD_ON == ADC_SAR_IP_EOCTU_ENABLED)) */
1823 #if (STD_ON == ADC_SAR_IP_ECH_ENABLED)
1824 if ((((*ISRAddr) & ADC_ISR_ECH_MASK) != 0U) && ((Imr & ADC_IMR_MSKECH_MASK) != 0U))
1825 {
1826 /* CPR_RTD_00644 */
1827 *ISRAddr = ADC_ISR_ECH_MASK;
1828 Adc_Sar_CheckAndCallNotification(Adc_Sar_Ip_axAdcSarState[Instance].EndOfNormalChainNotification);
1829 }
1830 #endif /* (STD_ON == ADC_SAR_IP_ECH_ENABLED) */
1831 #if (STD_ON == ADC_SAR_IP_JECH_ENABLED)
1832 if ((((*ISRAddr) & ADC_ISR_JECH_MASK) != 0U) && ((Imr & ADC_IMR_MSKJECH_MASK)!= 0U))
1833 {
1834 /* CPR_RTD_00644 */
1835 *ISRAddr = ADC_ISR_JECH_MASK;
1836 Adc_Sar_CheckAndCallNotification(Adc_Sar_Ip_axAdcSarState[Instance].EndOfInjectedChainNotification);
1837 }
1838 #endif /* (STD_ON == ADC_SAR_IP_JECH_ENABLED) */
1839
1840 #if ((STD_ON == ADC_SAR_IP_WDG_ENABLED) || (STD_ON == ADC_SAR_IP_EOC_ENABLED))
1841 Adc_CheckAndCallAllChannelNotification(Instance);
1842 #endif /* ((STD_ON == ADC_SAR_IP_WDG_ENABLED) || (STD_ON == ADC_SAR_IP_EOC_ENABLED)) */
1843 }
1844 else
1845 {
1846 /* CPR_RTD_00011 */
1847 Isr = *ISRAddr;
1848 *ISRAddr = Isr;
1849
1850 Wtisr = *WTISRAddr;
1851 *WTISRAddr = Wtisr;
1852 }
1853 }
1854
1855 /*FUNCTION**********************************************************************
1856 *
1857 * Function Name : Adc_Sar_SetNormalChain
1858 * Description : This function configures the ADC Normal Chain.
1859 *
1860 *END**************************************************************************/
Adc_Sar_SetNormalChain(const uint32 Instance,const uint32 * const Mask)1861 static inline void Adc_Sar_SetNormalChain(const uint32 Instance,
1862 const uint32 * const Mask)
1863 {
1864 uint8 Index;
1865
1866 ADC_Type * AdcBasePtr = NULL_PTR;
1867 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1868 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
1869 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1870
1871 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1872 if (Instance >= ADC_INSTANCE_COUNT)
1873 {
1874 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
1875 for (Index = 0U; Index < Adc_Sar_Ip_au8AdcGroupCount[Instance]; Index++)
1876 {
1877 NCMR(AdcAEBasePtr, Index) = Mask[Index];
1878 }
1879 }
1880 else
1881 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1882 {
1883 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
1884 for (Index = 0U; Index < Adc_Sar_Ip_au8AdcGroupCount[Instance]; Index++)
1885 {
1886 NCMR(AdcBasePtr, Index) = Mask[Index];
1887 }
1888 }
1889 }
1890
1891 /*FUNCTION**********************************************************************
1892 *
1893 * Function Name : Adc_Sar_SetInjectedChain
1894 * Description : This function configures the ADC Injected Chain.
1895 *
1896 *END**************************************************************************/
Adc_Sar_SetInjectedChain(const uint32 Instance,const uint32 * const Mask)1897 static inline void Adc_Sar_SetInjectedChain(const uint32 Instance,
1898 const uint32 * const Mask)
1899 {
1900 uint8 Index;
1901
1902 ADC_Type * AdcBasePtr = NULL_PTR;
1903 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1904 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
1905 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1906
1907 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1908 if (Instance >= ADC_INSTANCE_COUNT)
1909 {
1910 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
1911 for (Index = 0U; Index < Adc_Sar_Ip_au8AdcGroupCount[Instance]; Index++)
1912 {
1913 JCMR(AdcAEBasePtr, Index) = Mask[Index];
1914 }
1915 }
1916 else
1917 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1918 {
1919 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
1920 for (Index = 0U; Index < Adc_Sar_Ip_au8AdcGroupCount[Instance]; Index++)
1921 {
1922 JCMR(AdcBasePtr, Index) = Mask[Index];
1923 }
1924 }
1925 #if FEATURE_ADC_SAF8544_CHANNEL_WORKAROUND
1926 JCMR(AdcBasePtr, 0) |= ADC_JCMR0_CH0_MASK;
1927 #endif /* FEATURE_ADC_SAF8544_CHANNEL_WORKAROUND */
1928 }
1929
1930 /*FUNCTION**********************************************************************
1931 *
1932 * Function Name : Adc_Sar_GetValueFromBool
1933 * Description : The function is used to reduce complexity for parent function
1934 *
1935 *END**************************************************************************/
Adc_Sar_GetValueFromBool(const boolean bVal,const uint32 TrueVal,const uint32 FalseVal)1936 static inline uint32 Adc_Sar_GetValueFromBool(const boolean bVal,
1937 const uint32 TrueVal,
1938 const uint32 FalseVal)
1939 {
1940 return ((TRUE == bVal) ? TrueVal : FalseVal);
1941 }
1942 /*==================================================================================================
1943 * GLOBAL FUNCTIONS
1944 ==================================================================================================*/
1945 /*FUNCTION**********************************************************************
1946 *
1947 * Function Name : Adc_Sar_Ip_Init
1948 * Description : This function initializes the ADC_SAR module by configuring all
1949 * available features.
1950 *
1951 * @implements Adc_Sar_Ip_Init_Activity
1952 * END**************************************************************************/
Adc_Sar_Ip_Init(const uint32 u32Instance,const Adc_Sar_Ip_ConfigType * const pConfig)1953 Adc_Sar_Ip_StatusType Adc_Sar_Ip_Init(const uint32 u32Instance,
1954 const Adc_Sar_Ip_ConfigType * const pConfig)
1955 {
1956 Adc_Sar_Ip_StatusType Status = ADC_SAR_IP_STATUS_SUCCESS;
1957 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
1958 uint8 Index = 0u;
1959 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
1960 volatile uint32 * MCRAddr = NULL_PTR;
1961 volatile uint32 * PDEDRAddr = NULL_PTR;
1962 volatile uint32 * DMAEAddr = NULL_PTR;
1963 #if FEATURE_ADC_SAR_DECODE_DELAY
1964 volatile uint32 * DSDRAddr = NULL_PTR;
1965 #endif /* FEATURE_ADC_SAR_DECODE_DELAY */
1966 #if FEATURE_ADC_HAS_PRESAMPLING
1967 volatile uint32 * PSCRAddr = NULL_PTR;
1968 #endif /* FEATURE_ADC_HAS_PRESAMPLING */
1969
1970 ADC_Type * AdcBasePtr = NULL_PTR;
1971 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1972 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
1973 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1974
1975 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
1976 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
1977 DevAssert(pConfig != NULL_PTR);
1978 #if FEATURE_ADC_HAS_CTU
1979 #if (FEATURE_ADC_HAS_CTU_TRIGGER_MODE == 0u)
1980 /* test that the feature is enabled only on platforms that have it */
1981 DevAssert(pConfig->CtuMode != ADC_SAR_IP_CTU_MODE_TRIGGER);
1982 #endif /* FEATURE_ADC_HAS_CTU */
1983 #endif /* (FEATURE_ADC_HAS_CTU_TRIGGER_MODE == 0u) */
1984 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
1985
1986 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1987 if (u32Instance >= ADC_INSTANCE_COUNT)
1988 {
1989 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
1990 MCRAddr = &(AdcAEBasePtr->MCR);
1991 PDEDRAddr = &(AdcAEBasePtr->PDEDR);
1992 DMAEAddr = &(AdcAEBasePtr->DMAE);
1993 #if FEATURE_ADC_SAR_DECODE_DELAY
1994 DSDRAddr = &(AdcAEBasePtr->DSDR);
1995 #endif /* FEATURE_ADC_SAR_DECODE_DELAY */
1996 #if FEATURE_ADC_HAS_PRESAMPLING
1997 PSCRAddr = &(AdcAEBasePtr->PSCR);
1998 #endif /* FEATURE_ADC_HAS_PRESAMPLING */
1999 }
2000 else
2001 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2002 {
2003 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
2004 MCRAddr = &(AdcBasePtr->MCR);
2005 PDEDRAddr = &(AdcBasePtr->PDEDR);
2006 DMAEAddr = &(AdcBasePtr->DMAE);
2007 #if FEATURE_ADC_SAR_DECODE_DELAY
2008 DSDRAddr = &(AdcBasePtr->DSDR);
2009 #endif /* FEATURE_ADC_SAR_DECODE_DELAY */
2010 #if FEATURE_ADC_HAS_PRESAMPLING
2011 PSCRAddr = &(AdcBasePtr->PSCR);
2012 #endif /* FEATURE_ADC_HAS_PRESAMPLING */
2013 }
2014
2015 #if (STD_ON == ADC_SAR_IP_ENABLE_USER_MODE_SUPPORT)
2016 /* Set the UAA bit in REG_PROT to make the instance accessible in user mode */
2017 OsIf_Trusted_Call1param(Adc_Sar_Ip_SetUserAccessAllowed, u32Instance);
2018 #endif
2019
2020 /* Stop any conversions, if any */
2021 (void)Adc_Sar_Ip_AbortChain(u32Instance, TRUE, FALSE);
2022
2023 /* Clear CTUEN to allow Powerdown operation to succeed. */
2024 #if defined(ADC_MCR_CTUEN_MASK)
2025 *MCRAddr &= ~ADC_MCR_CTUEN_MASK;
2026 #endif /* ADC_MCR_CTUEN_MASK */
2027
2028 Status = Adc_Sar_Ip_Powerdown(u32Instance);
2029 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
2030 {
2031 /* Collects the mask and writes MCR mask */
2032 *MCRAddr = Adc_Sar_CollectMcrMasks(u32Instance, pConfig, *MCRAddr);
2033
2034 Adc_Sar_Ip_axAdcSarState[u32Instance].DataAlign = pConfig->DataAlign;
2035
2036 Status = Adc_Sar_Ip_Powerup(u32Instance);
2037 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
2038 {
2039 if (ADC_SAR_IP_CTU_MODE_TRIGGER == pConfig->CtuMode)
2040 {
2041 /* Workaround to enable CTU_MODE because it cannot be written in power-down mode in SAF85 */
2042 *MCRAddr |= ADC_MCR_CTU_MODE(1U);
2043 }
2044 #if FEATURE_ADC_HAS_HIGH_SPEED_ENABLE
2045 /* Enables high speed conversion or calibration */
2046 Adc_Sar_EnableHighSpeed(AdcBasePtr, pConfig->HighSpeedConvEn);
2047 #endif /* FEATURE_ADC_HAS_HIGH_SPEED_ENABLE */
2048
2049 #if FEATURE_ADC_HAS_CONVERSION_TIMING
2050 /* Set the sample times for each channnel group */
2051 Adc_Sar_Ip_SetSampleTimes(u32Instance, pConfig->SampleTimeArr);
2052 #endif /* FEATURE_ADC_HAS_CONVERSION_TIMING */
2053
2054 *PDEDRAddr = ADC_PDEDR_PDED(pConfig->PowerDownDelay);
2055
2056 #if FEATURE_ADC_HAS_CLOCK_DIVIDER
2057 /* Configure clock divider */
2058 Adc_Sar_EnableClkDiv(u32Instance, pConfig->ClkDivEnable);
2059 #endif /* FEATURE_ADC_HAS_CLOCK_DIVIDER */
2060
2061 #ifdef ADC_DSDR_DSD
2062 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
2063 if (ADC_SAR_IP_INST_HAS_DSDR(u32Instance))
2064 {
2065 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_FEATURE */
2066 #if FEATURE_ADC_SAR_DECODE_DELAY
2067 *DSDRAddr = ADC_DSDR_DSD(pConfig->DecodeDelay);
2068 #endif /* FEATURE_ADC_SAR_DECODE_DELAY */
2069 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
2070 }
2071 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_FEATURE */
2072 #endif /* ADC_DSDR_DSD */
2073
2074 /* Configure chain conversions */
2075 Adc_Sar_SetNormalChain(u32Instance, pConfig->ChanMaskNormal);
2076 Adc_Sar_SetInjectedChain(u32Instance, pConfig->ChanMaskInjected);
2077
2078 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
2079 /* Configure resolution */
2080 Adc_Sar_Ip_SetResolution(u32Instance, pConfig->AdcResolution);
2081 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
2082
2083 /* Configure WDG */
2084 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
2085 if ((pConfig->WdgThresholds != NULL_PTR) && (pConfig->NumWdgThresholds > 0u))
2086 {
2087 for (Index = 0U; Index < pConfig->NumWdgThresholds; Index++)
2088 {
2089 Adc_Sar_Ip_SetWdgThreshold(u32Instance, pConfig->WdgThresholds[Index].WdgIndex, &pConfig->WdgThresholds[Index]);
2090 }
2091 }
2092 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
2093
2094 #if (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED)
2095 if (pConfig->SelfTestThresholdConfig != NULL_PTR)
2096 {
2097 /* Configure self-test threshold value */
2098 Adc_Sar_ConfigSelftestThreshold(u32Instance, pConfig->SelfTestThresholdConfig);
2099 }
2100 #endif /* (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED) */
2101
2102 /* Configure DMA for channels */
2103 *DMAEAddr &= ~(ADC_DMAE_DMAEN_MASK | ADC_DMAE_DCLR_MASK);
2104 if (pConfig->DmaEnable)
2105 {
2106 *DMAEAddr |= (ADC_DMAE_DMAEN(1U) | ADC_DMAE_DCLR((uint32)pConfig->DmaClearSource));
2107 }
2108
2109 /* Configure per channel notifications and presampling */
2110 if ((pConfig->ChannelConfigsPtr != NULL_PTR) && (pConfig->NumChannels > 0u))
2111 {
2112 Adc_Sar_ConfigChannels(u32Instance, pConfig->ChannelConfigsPtr, pConfig->NumChannels);
2113 }
2114
2115 #if FEATURE_ADC_HAS_PRESAMPLING
2116 /* Configure presampling sources */
2117 *PSCRAddr &= ~(ADC_PSCR_PRECONV_MASK);
2118 *PSCRAddr |= ADC_PSCR_PRECONV(pConfig->BypassSampling ? 1u : 0u);
2119
2120 Adc_Sar_Ip_SetPresamplingSource(u32Instance, ADC_SAR_IP_CHAN_GROUP_0, pConfig->PresamplingSourceArr[0u]);
2121 Adc_Sar_Ip_SetPresamplingSource(u32Instance, ADC_SAR_IP_CHAN_GROUP_1, pConfig->PresamplingSourceArr[1u]);
2122 #if ADC_SAR_IP_NUM_GROUP_CHAN > 2u
2123 Adc_Sar_Ip_SetPresamplingSource(u32Instance, ADC_SAR_IP_CHAN_GROUP_2, pConfig->PresamplingSourceArr[2u]);
2124 #endif /* ADC_SAR_IP_NUM_GROUP_CHAN > 2u */
2125 #endif /* FEATURE_ADC_HAS_PRESAMPLING */
2126
2127 /* Add notification callbacks to the state structure */
2128 #if (STD_ON == ADC_SAR_IP_ECH_ENABLED)
2129 Adc_Sar_Ip_axAdcSarState[u32Instance].EndOfNormalChainNotification = pConfig->EndOfNormalChainNotification;
2130 #endif /* (STD_ON == ADC_SAR_IP_ECH_ENABLED) */
2131 #if (STD_ON == ADC_SAR_IP_JECH_ENABLED)
2132 Adc_Sar_Ip_axAdcSarState[u32Instance].EndOfInjectedChainNotification = pConfig->EndOfInjectedChainNotification;
2133 #endif /* (STD_ON == ADC_SAR_IP_JECH_ENABLED) */
2134 #if FEATURE_ADC_HAS_CTU
2135 #if (STD_ON == ADC_SAR_IP_EOCTU_ENABLED)
2136 Adc_Sar_Ip_axAdcSarState[u32Instance].EndOfCtuConversionNotification = pConfig->EndOfCtuConversionNotification;
2137 #endif /* (STD_ON == ADC_SAR_IP_EOCTU_ENABLED) */
2138 #endif /* FEATURE_ADC_HAS_CTU */
2139 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
2140 Adc_Sar_Ip_axAdcSarState[u32Instance].EndOfConvNotification = pConfig->EndOfConvNotification;
2141 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
2142 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
2143 Adc_Sar_Ip_axAdcSarState[u32Instance].WdgOutOfRangeNotification = pConfig->WdgOutOfRangeNotification;
2144 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
2145 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
2146 Adc_Sar_Ip_axAdcSarState[u32Instance].BypassResolution = pConfig->BypassResolution;
2147 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
2148 Adc_Sar_Ip_axAdcSarState[u32Instance].CalibrationClkSelect = pConfig->CalibrationClkSelect;
2149
2150 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2151 if (u32Instance >= ADC_INSTANCE_COUNT)
2152 {
2153 /* Configure user gain and offset */
2154 AdcAEBasePtr->ADC_AE_USER_OFFSET_GAIN_REG = ADC_AE_USER_OFFSET(pConfig->UsrOffset) | ADC_AE_USER_GAIN(pConfig->UsrGain);
2155 }
2156 else
2157 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2158 {
2159 /* Configure user gain and offset */
2160 AdcBasePtr->ADC_USER_OFFSET_GAIN_REG = ADC_USER_OFFSET(pConfig->UsrOffset) | ADC_USER_GAIN(pConfig->UsrGain);
2161 }
2162
2163 /* Mark that the driver was initialized */
2164 Adc_Sar_Ip_axAdcSarState[u32Instance].InitStatus = TRUE;
2165 }
2166 }
2167
2168 return Status;
2169 }
2170
2171 /*FUNCTION**********************************************************************
2172 *
2173 * Function Name : Adc_Sar_Ip_Deinit
2174 * Description : This function writes all the internal ADC registers with
2175 * their Reference Manual reset values.
2176 *
2177 * @implements Adc_Sar_Ip_DeInit_Activity
2178 * END**************************************************************************/
Adc_Sar_Ip_Deinit(const uint32 u32Instance)2179 Adc_Sar_Ip_StatusType Adc_Sar_Ip_Deinit(const uint32 u32Instance)
2180 {
2181 ADC_Type * AdcBasePtr = NULL_PTR;
2182 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2183 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
2184 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2185 uint32 Index;
2186 Adc_Sar_Ip_ConfigType DefaultConfig;
2187 Adc_Sar_Ip_StatusType Status;
2188
2189 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2190 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
2191 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2192
2193 DefaultConfig.ConvMode = ADC_SAR_IP_CONV_MODE_ONESHOT;
2194 DefaultConfig.ClkSelect = ADC_SAR_IP_CLK_FULL_BUS;
2195 DefaultConfig.CalibrationClkSelect = ADC_SAR_IP_CLK_HALF_BUS;
2196 #if FEATURE_ADC_HAS_HIGH_SPEED_ENABLE
2197 DefaultConfig.HighSpeedConvEn = FALSE;
2198 #endif /* FEATURE_ADC_HAS_HIGH_SPEED_ENABLE */
2199 #if FEATURE_ADC_HAS_CTU
2200 DefaultConfig.CtuMode = ADC_SAR_IP_CTU_MODE_DISABLED;
2201 #endif /* FEATURE_ADC_HAS_CTU */
2202 #if (ADC_SAR_IP_EXTERNAL_TRIGGER_ENABLE)
2203 #if FEATURE_ADC_HAS_INJ_EXT_TRIGGER
2204 DefaultConfig.InjectedEdge = ADC_SAR_IP_EXT_TRIG_EDGE_DISABLED;
2205 #endif /* FEATURE_ADC_HAS_INJ_EXT_TRIGGER */
2206 #if FEATURE_ADC_HAS_EXT_TRIGGER
2207 DefaultConfig.ExtTrigger = ADC_SAR_IP_EXT_TRIG_EDGE_DISABLED;
2208 DefaultConfig.NormalExtTrgEn = FALSE;
2209 #if FEATURE_ADC_HAS_AUX_EXT_TRIGGER
2210 DefaultConfig.NormalAuxExtTrgEn = FALSE;
2211 #endif /* FEATURE_ADC_HAS_AUX_EXT_TRIGGER */
2212 #endif /* FEATURE_ADC_HAS_EXT_TRIGGER */
2213 #endif /* (ADC_SAR_IP_EXTERNAL_TRIGGER_ENABLE) */
2214 #if (FEATURE_ADC_HAS_CONVERSION_TIMING || FEATURE_ADC_HAS_PRESAMPLING)
2215 for (Index = 0u; Index < Adc_Sar_Ip_au8AdcGroupCount[u32Instance]; Index++)
2216 {
2217 #if FEATURE_ADC_HAS_CONVERSION_TIMING
2218 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2219 if (u32Instance >= ADC_INSTANCE_COUNT)
2220 {
2221 DefaultConfig.SampleTimeArr[Index] = ADC_SAR_AE_IP_DEF_SAMPLE_TIME;
2222 }
2223 else
2224 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2225 {
2226 DefaultConfig.SampleTimeArr[Index] = ADC_SAR_IP_DEF_SAMPLE_TIME;
2227 }
2228 #endif /* FEATURE_ADC_HAS_CONVERSION_TIMING */
2229 #if FEATURE_ADC_HAS_PRESAMPLING
2230 #if (ADC_PSCR_PREVAL0_WIDTH > 1u)
2231 DefaultConfig.PresamplingSourceArr[Index] = ADC_SAR_IP_PRESAMPLE_DVDD;
2232 #else
2233 DefaultConfig.PresamplingSourceArr[Index] = ADC_SAR_IP_PRESAMPLE_VREFL;
2234 #endif /* (ADC_PSCR_PREVAL0_WIDTH > 1u) */
2235 #endif /* FEATURE_ADC_HAS_PRESAMPLING */
2236 }
2237 #endif /* (FEATURE_ADC_HAS_CONVERSION_TIMING || FEATURE_ADC_HAS_PRESAMPLING) */
2238 #if FEATURE_ADC_HAS_PRESAMPLING
2239 DefaultConfig.BypassSampling = FALSE;
2240 #endif /* FEATURE_ADC_HAS_PRESAMPLING */
2241 DefaultConfig.AutoClockOff = FALSE;
2242 DefaultConfig.OverwriteEnable = FALSE;
2243 DefaultConfig.DataAlign = ADC_SAR_IP_DATA_ALIGNED_RIGHT;
2244 #if FEATURE_ADC_SAR_DECODE_DELAY
2245 DefaultConfig.DecodeDelay = 0u;
2246 #endif /* FEATURE_ADC_SAR_DECODE_DELAY */
2247 DefaultConfig.PowerDownDelay = 0u;
2248 #if (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED)
2249 DefaultConfig.SelfTestThresholdConfig = NULL_PTR;
2250 #endif /* (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED) */
2251 #if FEATURE_ADC_HAS_CLOCK_DIVIDER
2252 DefaultConfig.ClkDivEnable = FALSE;
2253 #endif /* FEATURE_ADC_HAS_CLOCK_DIVIDER */
2254 #if FEATURE_ADC_HAS_AVERAGING
2255 DefaultConfig.AvgEn = FALSE;
2256 DefaultConfig.AvgSel = ADC_SAR_IP_AVG_4_CONV;
2257 #endif /* FEATURE_ADC_HAS_AVERAGING */
2258 DefaultConfig.UsrOffset = 0u;
2259 DefaultConfig.UsrGain = 0u;
2260 DefaultConfig.DmaEnable = FALSE;
2261 DefaultConfig.DmaClearSource = ADC_SAR_IP_DMA_REQ_CLEAR_ON_ACK;
2262 DefaultConfig.NumChannels = 0u;
2263 DefaultConfig.ChannelConfigsPtr = NULL_PTR;
2264 #if (STD_ON == ADC_SAR_IP_ECH_ENABLED)
2265 DefaultConfig.EndOfNormalChainNotification = NULL_PTR;
2266 #endif /* (STD_ON == ADC_SAR_IP_ECH_ENABLED) */
2267 #if (STD_ON == ADC_SAR_IP_JECH_ENABLED)
2268 DefaultConfig.EndOfInjectedChainNotification = NULL_PTR;
2269 #endif /* (STD_ON == ADC_SAR_IP_JECH_ENABLED) */
2270 #if FEATURE_ADC_HAS_CTU
2271 #if (STD_ON == ADC_SAR_IP_EOCTU_ENABLED)
2272 DefaultConfig.EndOfCtuConversionNotification = NULL_PTR;
2273 #endif /* (STD_ON == ADC_SAR_IP_EOCTU_ENABLED) */
2274 #endif /* FEATURE_ADC_HAS_CTU */
2275
2276 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
2277 DefaultConfig.EndOfConvNotification = NULL_PTR;
2278 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
2279 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
2280 DefaultConfig.NumWdgThresholds = 0u;
2281 DefaultConfig.WdgThresholds = NULL_PTR;
2282 DefaultConfig.WdgOutOfRangeNotification = NULL_PTR;
2283 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
2284
2285 Status = Adc_Sar_Ip_Init(u32Instance, &DefaultConfig);
2286 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
2287 {
2288 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2289 if ((u32Instance >= ADC_INSTANCE_COUNT))
2290 {
2291 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
2292 for (Index = 0u; Index < Adc_Sar_Ip_au8AdcGroupCount[u32Instance]; Index++)
2293 {
2294 CIMR(AdcAEBasePtr, Index) = 0u;
2295 CEOCFR(AdcAEBasePtr, Index) = 0xFFFFFFFFu; /* w1c bits */
2296 DMAR(AdcAEBasePtr, Index) = 0u;
2297 #if FEATURE_ADC_HAS_PRESAMPLING
2298 PSR(AdcAEBasePtr, Index) = 0u;
2299 #endif /* FEATURE_ADC_HAS_PRESAMPLING */
2300 }
2301
2302 /* Deinit watchdog interrupts */
2303 Adc_Sar_ResetWdog(u32Instance);
2304 AdcAEBasePtr->WTIMR = 0u;
2305 }
2306 else
2307 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2308 {
2309 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
2310 for (Index = 0u; Index < Adc_Sar_Ip_au8AdcGroupCount[u32Instance]; Index++)
2311 {
2312 CIMR(AdcBasePtr, Index) = 0u;
2313 CEOCFR(AdcBasePtr, Index) = 0xFFFFFFFFu; /* w1c bits */
2314 DMAR(AdcBasePtr, Index) = 0u;
2315 #if FEATURE_ADC_HAS_PRESAMPLING
2316 PSR(AdcBasePtr, Index) = 0u;
2317 #endif /* FEATURE_ADC_HAS_PRESAMPLING */
2318 }
2319
2320 /* Deinit watchdog interrupts */
2321 Adc_Sar_ResetWdog(u32Instance);
2322 AdcBasePtr->WTIMR = 0u;
2323 }
2324 /* Deinit channel configuration */
2325
2326 Adc_Sar_Ip_ClearStatusFlags(u32Instance, ADC_SAR_IP_NOTIF_FLAG_ALL);
2327 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
2328 /* Set default resolution */
2329 Adc_Sar_Ip_SetResolution(u32Instance, ADC_SAR_IP_RESOLUTION_12);
2330 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
2331
2332 /* Mark that the driver was deinitialized */
2333 Adc_Sar_Ip_axAdcSarState[u32Instance].InitStatus = FALSE;
2334
2335 Status = Adc_Sar_Ip_Powerdown(u32Instance);
2336
2337 #if (STD_ON == ADC_SAR_IP_ENABLE_USER_MODE_SUPPORT)
2338 /* Clear the UAA bit in REG_PROT to reset the elevation requirement */
2339 OsIf_Trusted_Call1param(Adc_Sar_Ip_ClrUserAccessAllowed, u32Instance);
2340 #endif
2341 }
2342
2343 return Status;
2344 }
2345
2346 /*FUNCTION**********************************************************************
2347 *
2348 * Function Name : Adc_Sar_Ip_ChainConfig
2349 * Description : This function configures the ADC Normal and Injected Chains
2350 * with the options provided in the structure.
2351 *
2352 * @implements Adc_Sar_Ip_ChainConfig_Activity
2353 * END**************************************************************************/
Adc_Sar_Ip_ChainConfig(const uint32 u32Instance,const Adc_Sar_Ip_ChansIdxMaskType * const pChansIdxMask,const Adc_Sar_Ip_ConvChainType pChainType)2354 void Adc_Sar_Ip_ChainConfig(const uint32 u32Instance,
2355 const Adc_Sar_Ip_ChansIdxMaskType * const pChansIdxMask,
2356 const Adc_Sar_Ip_ConvChainType pChainType)
2357 {
2358 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2359 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
2360 DevAssert(pChansIdxMask != NULL_PTR);
2361 #if FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL
2362 uint8 i;
2363 /* Enabling unavailable channels is forbidden */
2364 for (i = 0U; i < ADC_SAR_IP_NUM_GROUP_CHAN; i++)
2365 {
2366 DevAssert((pChansIdxMask->ChanMaskArr[i] & (~Adc_Sar_Ip_au32AdcChanBitmap[u32Instance][i])) == 0u);
2367 }
2368 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL */
2369 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2370
2371 switch (pChainType)
2372 {
2373 case ADC_SAR_IP_CONV_CHAIN_NORMAL:
2374 Adc_Sar_SetNormalChain(u32Instance, pChansIdxMask->ChanMaskArr);
2375 break;
2376 case ADC_SAR_IP_CONV_CHAIN_INJECTED:
2377 Adc_Sar_SetInjectedChain(u32Instance, pChansIdxMask->ChanMaskArr);
2378 break;
2379 default:
2380 ; /* no-op */
2381 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2382 DevAssert(FALSE);
2383 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2384 break;
2385 }
2386 }
2387
2388 /*FUNCTION**********************************************************************
2389 *
2390 * Function Name : Adc_Sar_Ip_EnableChannel
2391 * Description : This function enables a channel in a conversion chain (
2392 * ADC_SAR_IP_CONV_CHAIN_NORMAL or ADC_SAR_IP_CONV_CHAIN_INJECTED).
2393 *
2394 * @implements Adc_Sar_Ip_EnableChannel_Activity
2395 * END**************************************************************************/
Adc_Sar_Ip_EnableChannel(const uint32 u32Instance,const Adc_Sar_Ip_ConvChainType pChainType,const uint32 u32ChnIdx)2396 void Adc_Sar_Ip_EnableChannel(const uint32 u32Instance,
2397 const Adc_Sar_Ip_ConvChainType pChainType,
2398 const uint32 u32ChnIdx)
2399 {
2400 uint32 VectAdr;
2401 uint32 VectBit;
2402 ADC_Type * AdcBasePtr = NULL_PTR;
2403 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2404 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
2405 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2406 volatile uint32 * NCMRAddr = NULL_PTR;
2407 volatile uint32 * JCMRAddr = NULL_PTR;
2408
2409 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2410 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
2411 DevAssert(u32ChnIdx < ADC_SAR_IP_CDR_COUNT);
2412 #if FEATURE_ADC_SAF8544_CHANNEL_WORKAROUND
2413 DevAssert(!((0U == u32ChnIdx) && ((ADC_SAR_IP_CONV_CHAIN_INJECTED == pChainType) || (ADC_SAR_IP_CONV_CHAIN_CTU == pChainType))));
2414 #endif
2415 #if FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL
2416 DevAssert(ADC_SAR_IP_INST_HAS_CHANn(u32Instance, u32ChnIdx));
2417 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL */
2418 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2419
2420 VectAdr = ADC_SAR_IP_CHAN_2_VECT(u32ChnIdx);
2421 VectBit = ADC_SAR_IP_CHAN_2_BIT(u32ChnIdx);
2422
2423 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2424 if (u32Instance >= ADC_INSTANCE_COUNT)
2425 {
2426 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
2427 NCMRAddr = &(NCMR(AdcAEBasePtr, VectAdr));
2428 JCMRAddr = &(JCMR(AdcAEBasePtr, VectAdr));
2429 }
2430 else
2431 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2432 {
2433 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
2434 NCMRAddr = &(NCMR(AdcBasePtr, VectAdr));
2435 JCMRAddr = &(JCMR(AdcBasePtr, VectAdr));
2436 }
2437
2438 switch (pChainType)
2439 {
2440 case ADC_SAR_IP_CONV_CHAIN_NORMAL:
2441 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_23();
2442 *NCMRAddr |= (1UL << VectBit);
2443 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_23();
2444 break;
2445 case ADC_SAR_IP_CONV_CHAIN_INJECTED:
2446 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_26();
2447 *JCMRAddr |= (1UL << VectBit);
2448 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_26();
2449 break;
2450 default:
2451 ; /* no-op */
2452 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2453 DevAssert(FALSE);
2454 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2455 break;
2456 }
2457 }
2458
2459 /*FUNCTION**********************************************************************
2460 *
2461 * Function Name : Adc_Sar_Ip_DisableChannel
2462 * Description : This function disables a channel from a conversion chain (ADC_SAR_IP_CONV_CHAIN_NORMAL
2463 * or ADC_SAR_IP_CONV_CHAIN_INJECTED).
2464 *
2465 * @implements Adc_Sar_Ip_DisableChannel_Activity
2466 * END**************************************************************************/
Adc_Sar_Ip_DisableChannel(const uint32 u32Instance,const Adc_Sar_Ip_ConvChainType pChainType,const uint32 u32ChnIdx)2467 void Adc_Sar_Ip_DisableChannel(const uint32 u32Instance,
2468 const Adc_Sar_Ip_ConvChainType pChainType,
2469 const uint32 u32ChnIdx)
2470 {
2471 uint32 VectAdr;
2472 uint32 VectBit;
2473 ADC_Type * AdcBasePtr = NULL_PTR;
2474 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2475 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
2476 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2477 volatile uint32 * NCMRAddr = NULL_PTR;
2478 volatile uint32 * JCMRAddr = NULL_PTR;
2479
2480 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2481 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
2482 DevAssert(u32ChnIdx < ADC_SAR_IP_CDR_COUNT);
2483 #if FEATURE_ADC_SAF8544_CHANNEL_WORKAROUND
2484 DevAssert((0U == u32ChnIdx) && (ADC_SAR_IP_CONV_CHAIN_INJECTED == pChainType));
2485 #endif
2486 #if FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL
2487 DevAssert(ADC_SAR_IP_INST_HAS_CHANn(u32Instance, u32ChnIdx));
2488 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL */
2489 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2490
2491 VectAdr = ADC_SAR_IP_CHAN_2_VECT(u32ChnIdx);
2492 VectBit = ADC_SAR_IP_CHAN_2_BIT(u32ChnIdx);
2493
2494 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2495 if (u32Instance >= ADC_INSTANCE_COUNT)
2496 {
2497 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
2498 NCMRAddr = &(NCMR(AdcAEBasePtr, VectAdr));
2499 JCMRAddr = &(JCMR(AdcAEBasePtr, VectAdr));
2500 }
2501 else
2502 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2503 {
2504 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
2505 NCMRAddr = &(NCMR(AdcBasePtr, VectAdr));
2506 JCMRAddr = &(JCMR(AdcBasePtr, VectAdr));
2507 }
2508
2509 switch (pChainType)
2510 {
2511 case ADC_SAR_IP_CONV_CHAIN_NORMAL:
2512 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_24();
2513 *NCMRAddr &= ~(1UL << VectBit);
2514 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_24();
2515 break;
2516 case ADC_SAR_IP_CONV_CHAIN_INJECTED:
2517 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_27();
2518 *JCMRAddr &= ~(1UL << VectBit);
2519 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_27();
2520 break;
2521 default:
2522 ; /* no-op */
2523 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2524 DevAssert(FALSE);
2525 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2526 break;
2527 }
2528 }
2529
2530 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
2531 /*FUNCTION**********************************************************************
2532 *
2533 * Function Name : Adc_Sar_Ip_SetResolution
2534 * Description : This function sets the conversion resolution (number of bits per conversion data)
2535 *
2536 * @implements Adc_Sar_Ip_SetResolution_Activity
2537 * END**************************************************************************/
Adc_Sar_Ip_SetResolution(const uint32 u32Instance,const Adc_Sar_Ip_Resolution eResolution)2538 void Adc_Sar_Ip_SetResolution(const uint32 u32Instance,
2539 const Adc_Sar_Ip_Resolution eResolution)
2540 {
2541 uint32 Calbistreg;
2542 ADC_Type * AdcBasePtr = NULL_PTR;
2543 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2544 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
2545 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2546 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2547 uint32 Msr;
2548 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
2549 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2550 volatile uint32 * CALBISTREGAddr = NULL_PTR;
2551
2552
2553 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2554 if (u32Instance >= ADC_INSTANCE_COUNT)
2555 {
2556 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
2557 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2558 Msr = AdcAEBasePtr->MSR;
2559 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2560 CALBISTREGAddr = &(AdcAEBasePtr->CALBISTREG);
2561 }
2562 else
2563 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2564 {
2565 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
2566 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2567 Msr = AdcBasePtr->MSR;
2568 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2569 CALBISTREGAddr = &(AdcBasePtr->CALBISTREG);
2570 }
2571
2572 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2573 /* The selected ADC should be in IDLE state */
2574 DevAssert((Msr & ADC_MSR_ADCSTATUS_MASK) == ADC_MSR_ADCSTATUS(ADC_SAR_IP_MSR_ADCSTATUS_IDLE));
2575 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2576 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_37();
2577 Calbistreg = *CALBISTREGAddr;
2578 /* Clear the bits and set resolution value */
2579 Calbistreg &= ~(ADC_CALBISTREG_RESN_MASK);
2580 Calbistreg |= ADC_CALBISTREG_RESN(eResolution);
2581 *CALBISTREGAddr = Calbistreg;
2582 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_37();
2583
2584 }
2585 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
2586
2587 /*FUNCTION**********************************************************************
2588 *
2589 * Function Name : Adc_Sar_Ip_StartConversion
2590 * Description : This function starts a conversion chain (ADC_SAR_IP_CONV_CHAIN_NORMAL
2591 * or ADC_SAR_IP_CONV_CHAIN_INJECTED).
2592 *
2593 * @implements Adc_Sar_Ip_StartConversion_Activity
2594 * END**************************************************************************/
Adc_Sar_Ip_StartConversion(const uint32 u32Instance,const Adc_Sar_Ip_ConvChainType pChainType)2595 void Adc_Sar_Ip_StartConversion(const uint32 u32Instance,
2596 const Adc_Sar_Ip_ConvChainType pChainType)
2597 {
2598 ADC_Type * AdcBasePtr = NULL_PTR;
2599 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2600 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
2601 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2602 volatile uint32 * MCRAddr = NULL_PTR;
2603
2604 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2605 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
2606 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2607
2608 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2609 if (u32Instance >= ADC_INSTANCE_COUNT)
2610 {
2611 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
2612 MCRAddr = &(AdcAEBasePtr->MCR);
2613 }
2614 else
2615 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2616 {
2617 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
2618 MCRAddr = &(AdcBasePtr->MCR);
2619 }
2620
2621 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_10();
2622 switch (pChainType)
2623 {
2624 case ADC_SAR_IP_CONV_CHAIN_NORMAL:
2625 *MCRAddr |= ADC_MCR_NSTART(1U);
2626 break;
2627 case ADC_SAR_IP_CONV_CHAIN_INJECTED:
2628 *MCRAddr |= ADC_MCR_JSTART(1U);
2629 break;
2630 default:
2631 ; /* no-op */
2632 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2633 DevAssert(FALSE);
2634 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2635 break;
2636 }
2637 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_10();
2638 }
2639
2640 /*FUNCTION**********************************************************************
2641 *
2642 * Function Name : Adc_Sar_Ip_GetStatusFlags
2643 * Description : This function returns the status flags of the ADC.
2644 *
2645 * @implements Adc_Sar_Ip_GetStatusFlags_Activity
2646 * END**************************************************************************/
Adc_Sar_Ip_GetStatusFlags(const uint32 u32Instance)2647 uint32 Adc_Sar_Ip_GetStatusFlags(const uint32 u32Instance)
2648 {
2649 uint32 Flags = 0U;
2650
2651 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2652 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
2653 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2654
2655 /* Returns the flag status from MSR register */
2656 Flags |= Adc_Sar_GetMsrFlags(u32Instance);
2657 /* Returns the flag status from ISR register */
2658 Flags |= Adc_Sar_GetIsrFlags(u32Instance);
2659
2660 return Flags;
2661 }
2662
2663 /*FUNCTION**********************************************************************
2664 *
2665 * Function Name : Adc_Sar_Ip_ClearStatusFlags
2666 * Description : This function clears the status flags that are set to '1' in
2667 * the mask.
2668 *
2669 * @implements Adc_Sar_Ip_ClearStatusFlags_Activity
2670 * END**************************************************************************/
Adc_Sar_Ip_ClearStatusFlags(const uint32 u32Instance,const uint32 u32Mask)2671 void Adc_Sar_Ip_ClearStatusFlags(const uint32 u32Instance,
2672 const uint32 u32Mask)
2673 {
2674 uint32 IsrFlags = 0U;
2675 volatile uint32 * ISRAddr = NULL_PTR;
2676
2677 ADC_Type * AdcBasePtr = NULL_PTR;
2678 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2679 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
2680 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2681
2682 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2683 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
2684 DevAssert((u32Mask & (~ADC_SAR_IP_NOTIF_FLAG_ALL)) == 0UL);
2685 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2686
2687 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2688 if (u32Instance >= ADC_INSTANCE_COUNT)
2689 {
2690 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
2691 ISRAddr = &(AdcAEBasePtr->ISR);
2692 }
2693 else
2694 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2695 {
2696 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
2697 ISRAddr = &(AdcBasePtr->ISR);
2698 }
2699
2700 IsrFlags |= ((u32Mask & ADC_SAR_IP_NOTIF_FLAG_NORMAL_EOC) != 0U) ? ADC_ISR_EOC(1U) : 0U;
2701 IsrFlags |= ((u32Mask & ADC_SAR_IP_NOTIF_FLAG_NORMAL_ENDCHAIN) != 0U) ? ADC_ISR_ECH(1U) : 0U;
2702 IsrFlags |= ((u32Mask & ADC_SAR_IP_NOTIF_FLAG_INJECTED_EOC) != 0U) ? ADC_ISR_JEOC(1U) : 0U;
2703 IsrFlags |= ((u32Mask & ADC_SAR_IP_NOTIF_FLAG_INJECTED_ENDCHAIN) != 0U) ? ADC_ISR_JECH(1U) : 0U;
2704 #if FEATURE_ADC_HAS_CTU
2705 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
2706 if (ADC_SAR_IP_INST_HAS_CTU(u32Instance))
2707 {
2708 #endif /*FEATURE_ADC_BAD_ACCESS_PROT_FEATURE*/
2709 IsrFlags |= ((u32Mask & ADC_SAR_IP_NOTIF_FLAG_CTU_EOC) != 0U) ? ADC_ISR_EOCTU(1U) : 0U;
2710 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
2711 }
2712 #endif /*FEATURE_ADC_BAD_ACCESS_PROT_FEATURE*/
2713 #endif /* FEATURE_ADC_HAS_CTU */
2714
2715 /* Write-1-to-clear bits in ISR register */
2716 *ISRAddr = IsrFlags;
2717 #ifdef FEATURE_CPU_HAS_WRITE_BUFFER
2718 (void) *ISRAddr;
2719 #endif /* FEATURE_CPU_HAS_WRITE_BUFFER */
2720 }
2721
2722 #if (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED)
2723 /*FUNCTION**********************************************************************
2724 *
2725 * Function Name : Adc_Sar_Ip_SelfTest
2726 * Description : This function executes a self test on the ADC instance.
2727 *
2728 * @implements Adc_Sar_Ip_SelfTest_Activity
2729 * END**************************************************************************/
Adc_Sar_Ip_SelfTest(const uint32 u32Instance)2730 Adc_Sar_Ip_StatusType Adc_Sar_Ip_SelfTest(const uint32 u32Instance)
2731 {
2732 ADC_Type * AdcBasePtr = NULL_PTR;
2733 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2734 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
2735 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2736 Adc_Sar_Ip_StatusType Status = ADC_SAR_IP_STATUS_SUCCESS;
2737 #if FEATURE_ADC_HAS_SELFTEST_STCR1
2738 uint32 Reg;
2739 #endif /* FEATURE_ADC_HAS_SELFTEST_STCR1 */
2740 uint32 MsrStatus;
2741 uint32 TimeoutTicks = OsIf_MicrosToTicks(ADC_SAR_IP_TIMEOUT_VAL, ADC_SAR_IP_TIMEOUT_TYPE);
2742 uint32 CurrentTicks = OsIf_GetCounter(ADC_SAR_IP_TIMEOUT_TYPE);
2743 uint32 ElapsedTicks = 0U;
2744 #if (FEATURE_ADC_SELFTEST_FULL_CLK && ADC_SAR_IP_HAS_ADCLKSEL)
2745 uint32 AdcClkSel = 0u;
2746 #endif /* (FEATURE_ADC_SELFTEST_FULL_CLK && ADC_SAR_IP_HAS_ADCLKSEL) */
2747 volatile uint32 * MCRAddr = NULL_PTR;
2748 volatile const uint32 * MSRAddr = NULL_PTR;
2749 #if !FEATURE_ADC_HAS_SELFTEST_USE_CH32
2750 volatile uint32 * NCMR0Addr = NULL_PTR;
2751 #else
2752 volatile uint32 * NCMR1Addr = NULL_PTR;
2753 #endif /* FEATURE_ADC_HAS_SELFTEST_USE_CH32 */
2754 #if FEATURE_ADC_HAS_SELFTEST_STCR1
2755 volatile uint32 * STCR1Addr = NULL_PTR;
2756 #endif /* FEATURE_ADC_HAS_SELFTEST_STCR1 */
2757 volatile uint32 * STCR2Addr = NULL_PTR;
2758 #if FEATURE_ADC_HAS_SELFTEST_STCR3
2759 volatile uint32 * STCR3Addr = NULL_PTR;
2760 #endif /* FEATURE_ADC_HAS_SELFTEST_STCR3 */
2761
2762 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2763 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
2764 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2765
2766 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2767 if (u32Instance >= ADC_INSTANCE_COUNT)
2768 {
2769 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
2770 MCRAddr = &(AdcAEBasePtr->MCR);
2771 MSRAddr = &(AdcAEBasePtr->MSR);
2772 #if !FEATURE_ADC_HAS_SELFTEST_USE_CH32
2773 NCMR0Addr = &(NCMR(AdcAEBasePtr, 0u));
2774 #else
2775 NCMR1Addr = &(NCMR(AdcAEBasePtr, 1u));
2776 #endif /* FEATURE_ADC_HAS_SELFTEST_USE_CH32 */
2777 #if FEATURE_ADC_HAS_SELFTEST_STCR1
2778 STCR1Addr = &(AdcAEBasePtr->STCR1);
2779 #endif /* FEATURE_ADC_HAS_SELFTEST_STCR1 */
2780 STCR2Addr = &(AdcAEBasePtr->STCR2);
2781 #if FEATURE_ADC_HAS_SELFTEST_STCR3
2782 STCR3Addr = &(AdcAEBasePtr->STCR3);
2783 #endif /* FEATURE_ADC_HAS_SELFTEST_STCR3 */
2784 }
2785 else
2786 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2787 {
2788 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
2789 MCRAddr = &(AdcBasePtr->MCR);
2790 MSRAddr = &(AdcBasePtr->MSR);
2791 #if !FEATURE_ADC_HAS_SELFTEST_USE_CH32
2792 NCMR0Addr = &(NCMR(AdcBasePtr, 0u));
2793 #else
2794 NCMR1Addr = &(NCMR(AdcBasePtr, 1u));
2795 #endif /* FEATURE_ADC_HAS_SELFTEST_USE_CH32 */
2796 #if FEATURE_ADC_HAS_SELFTEST_STCR1
2797 STCR1Addr = &(AdcBasePtr->STCR1);
2798 #endif /* FEATURE_ADC_HAS_SELFTEST_STCR1 */
2799 STCR2Addr = &(AdcBasePtr->STCR2);
2800 #if FEATURE_ADC_HAS_SELFTEST_STCR3
2801 STCR3Addr = &(AdcBasePtr->STCR3);
2802 #endif /* FEATURE_ADC_HAS_SELFTEST_STCR3 */
2803 }
2804
2805 #if FEATURE_ADC_SELFTEST_FULL_CLK
2806 /* Enter into power-down Mode */
2807 Status = Adc_Sar_Ip_Powerdown(u32Instance);
2808 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
2809 {
2810 #if ADC_SAR_IP_HAS_ADCLKSEL
2811 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_11();
2812 /* Save the current state of ADCLKSEL in order to restore it */
2813 AdcClkSel = ((*MCRAddr) & ADC_MCR_ADCLKSEL_MASK);
2814 /* ADC self-test should be run with MCR[ADCLKSE] bit set to 1 */
2815 *MCRAddr &= ~(ADC_MCR_ADCLKSEL_MASK);
2816 *MCRAddr |= ADC_MCR_ADCLKSEL(1U);
2817 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_11();
2818 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
2819
2820 /* Exit into power-down Mode */
2821 Status = Adc_Sar_Ip_Powerup(u32Instance);
2822 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
2823 {
2824 #endif /* FEATURE_ADC_SELFTEST_FULL_CLK */
2825 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_25();
2826 #if !FEATURE_ADC_HAS_SELFTEST_USE_CH32
2827 /* 1. Program NCMR0 to select channels to be converted for normal conversion.*/
2828 *NCMR0Addr |= ADC_NCMR_CH0(0x1UL);
2829 #else
2830 /* Workaround for SAF8544 since self-test result register is written twice with the last channel of chain and self-test channel 32
2831 Enabling channel 32 at last of chain to have register field having only result of selftest channel 32 */
2832 *NCMR1Addr |= ADC_NCMR1_CH32(0x1UL);
2833 #endif /* FEATURE_ADC_HAS_SELFTEST_USE_CH32 */
2834 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_25();
2835
2836 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_11();
2837 /* Self-test will only run with CPU mode so clear CTU enable */
2838 #if defined(ADC_MCR_CTUEN_MASK)
2839 *MCRAddr &= ~(ADC_MCR_CTUEN_MASK);
2840 #endif /* ADC_MCR_CTUEN_MASK */
2841
2842 /* 2. Program MCR[MODE] = 1 to select Scan mode. ADC_ONE_SHOT_MODE_U32 ADCDIG_CONTINUOUS_MODE_U32*/
2843 *MCRAddr |= ADC_MCR_MODE(0x1UL);
2844 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_11();
2845 #if FEATURE_ADC_HAS_SELFTEST_STCR1
2846 /* 3. Program sampling duration values in STCR1[INPSAMPx].*/
2847 Reg = 0u;
2848 Reg |= ADC_STCR1_INPSAMP_S(0x10UL) | ADC_STCR1_INPSAMP_C(0x10UL);
2849 *STCR1Addr = Reg;
2850 #endif /* FEATURE_ADC_HAS_SELFTEST_STCR1 */
2851
2852 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_35();
2853 #if FEATURE_ADC_HAS_SELFTEST_STCR3
2854 /* 4. Select the self-testing algorithm in STCR3[ALG]. */
2855 *STCR3Addr |= ADC_STCR3_ALG(0x3UL);
2856 #endif /* FEATURE_ADC_HAS_SELFTEST_STCR3 */
2857 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_35();
2858
2859 Adc_Sar_EnableSelftestThreshold(u32Instance);
2860 #ifdef ADC_GPADC_ANA_TEST0_VDAC
2861 AdcBasePtr->GPADC_ANA_TEST0 &= ~(ADC_GPADC_ANA_TEST0_VDAC_MASK);
2862 AdcBasePtr->GPADC_ANA_TEST0 |= ADC_GPADC_ANA_TEST0_VDAC(8U);
2863 #endif /* ADC_GPADC_ANA_TEST0_VDAC */
2864 #ifdef ADC_GPADC_CALCFG0_SET_VREF_OUT_BUF
2865 if (ADC_GPADC_CALCFG0_SET_VREF_OUT_BUF_1V6 == ((REG_ACCESS_BY_ADDR(ADC_GPADC_CALCFG0_ADDR) & ADC_GPADC_CALCFG0_SET_VREF_OUT_BUF_MASK) >> ADC_GPADC_CALCFG0_SET_VREF_OUT_BUF_SHIFT))
2866 {
2867 #ifdef ADC_GPADC_ANA_CONF_VIN_SE_REF
2868 /* GPADC_ANA_CONF[VIN_SE_REF] = 1 (enable self-test channel div2 mode) to be aligned with CALCFG0[SET_VREF_OUT_BUF] = 4 (1.6v) (only shown in DDTS) */
2869 AdcBasePtr->GPADC_ANA_CONF |= ADC_GPADC_ANA_CONF_VIN_SE_REF(1U);
2870 #endif /* ADC_GPADC_ANA_CONF_VIN_SE_REF */
2871 }
2872 else if (ADC_GPADC_CALCFG0_SET_VREF_OUT_BUF_0V8 == ((REG_ACCESS_BY_ADDR(ADC_GPADC_CALCFG0_ADDR) & ADC_GPADC_CALCFG0_SET_VREF_OUT_BUF_MASK) >> ADC_GPADC_CALCFG0_SET_VREF_OUT_BUF_SHIFT))
2873 {
2874 #ifdef ADC_GPADC_ANA_CONF_VIN_SE_REF
2875 /* GPADC_ANA_CONF[VIN_SE_REF] = 0 (disable self-test channel div2 mode) to be aligned with CALCFG0[SET_VREF_OUT_BUF] = 2 (0.8v) (only shown in DDTS) */
2876 AdcBasePtr->GPADC_ANA_CONF |= ADC_GPADC_ANA_CONF_VIN_SE_REF(0U);
2877 #endif /* ADC_GPADC_ANA_CONF_VIN_SE_REF */
2878 }
2879 else
2880 {
2881 /* Overwrite to 4 (1.6v vref) */
2882 REG_ACCESS_BY_ADDR(ADC_GPADC_CALCFG0_ADDR) &= ~(ADC_GPADC_CALCFG0_SET_VREF_OUT_BUF_MASK);
2883 REG_ACCESS_BY_ADDR(ADC_GPADC_CALCFG0_ADDR) |= ADC_GPADC_CALCFG0_SET_VREF_OUT_BUF(ADC_GPADC_CALCFG0_SET_VREF_OUT_BUF_1V6);
2884 #ifdef ADC_GPADC_ANA_CONF_VIN_SE_REF
2885 /* GPADC_ANA_CONF[VIN_SE_REF] = 1 (enable self-test channel div2 mode) to be aligned with CALCFG0[SET_VREF_OUT_BUF] = 4 (1.6v) (only shown in DDTS) */
2886 AdcBasePtr->GPADC_ANA_CONF |= ADC_GPADC_ANA_CONF_VIN_SE_REF(1U);
2887 #endif /* ADC_GPADC_ANA_CONF_VIN_SE_REF */
2888 /* Wait after changing SET_VREF_OUT_BUF to avoid unstable result */
2889 TimeoutTicks = OsIf_MicrosToTicks(ADC_SAR_IP_BANDGAP_TIMEOUT_VAL, ADC_SAR_IP_TIMEOUT_TYPE);
2890 CurrentTicks = OsIf_GetCounter(ADC_SAR_IP_TIMEOUT_TYPE);
2891 ElapsedTicks = 0u;
2892 while (ElapsedTicks < TimeoutTicks)
2893 {
2894 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
2895 }
2896 }
2897 #endif /* ADC_GPADC_CALCFG0_SET_VREF_OUT_BUF */
2898
2899 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_35();
2900 /* 5. Enable the self-testing channel by setting STCR2[EN]. */
2901 *STCR2Addr |= ADC_STCR2_EN(0x1UL);
2902 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_35();
2903
2904 /* 6. Start the normal conversion by setting MCR[NSTART]. */
2905 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_11();
2906 *MCRAddr |= ADC_MCR_NSTART(0x1UL);
2907 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_11();
2908
2909 /* Check that all algorithms have executed at least once. */
2910 Status = Adc_Sar_CheckSelfTestProgress(u32Instance);
2911
2912 /* Stop the conversion */
2913 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_11();
2914 *MCRAddr &= ~(ADC_MCR_NSTART(0x1UL));
2915 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_11();
2916
2917 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
2918 {
2919 /* Read ADC status */
2920 MsrStatus = ((*MSRAddr) & ADC_MSR_ADCSTATUS_MASK) >> ADC_MSR_ADCSTATUS_SHIFT;
2921 /* Wait for ADC changes to the expected Idle mode, The bitfield MSR[ADCSTATUS] should be checked to Idle state when MCR[NSTART] is written to 0 */
2922 TimeoutTicks = OsIf_MicrosToTicks(ADC_SAR_IP_TIMEOUT_VAL, ADC_SAR_IP_TIMEOUT_TYPE);
2923 ElapsedTicks = 0U;
2924 while ((MsrStatus != ADC_MSR_ADCSTATUS(ADC_SAR_IP_MSR_ADCSTATUS_IDLE)) && (ElapsedTicks < TimeoutTicks))
2925 {
2926 MsrStatus = ((*MSRAddr) & ADC_MSR_ADCSTATUS_MASK) >> ADC_MSR_ADCSTATUS_SHIFT;
2927 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
2928 }
2929 }
2930
2931 Adc_Sar_DisableSelftestThreshold(u32Instance);
2932
2933 #ifdef ADC_GPADC_ANA_TEST0_VDAC
2934 AdcBasePtr->GPADC_ANA_TEST0 &= ~(ADC_GPADC_ANA_TEST0_VDAC_MASK);
2935 #endif /* ADC_GPADC_ANA_TEST0_VDAC */
2936 #ifdef ADC_GPADC_ANA_CONF_VIN_SE_REF
2937 AdcBasePtr->GPADC_ANA_CONF &= ~(ADC_GPADC_ANA_CONF_VIN_SE_REF_MASK);
2938 #endif /* ADC_GPADC_ANA_CONF_VIN_SE_REF */
2939
2940 /* Disable Self-test */
2941 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_35();
2942 *STCR2Addr &= ~(ADC_STCR2_EN(0x1UL));
2943 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_35();
2944
2945 #if FEATURE_ADC_SELFTEST_FULL_CLK
2946 }
2947 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
2948 {
2949 /* Enter into power-down Mode */
2950 Status = Adc_Sar_Ip_Powerdown(u32Instance);
2951 #if ADC_SAR_IP_HAS_ADCLKSEL
2952 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_11();
2953 /* Restore the state of ADCLKSEL */
2954 *MCRAddr &= ~(ADC_MCR_ADCLKSEL_MASK);
2955 *MCRAddr |= AdcClkSel;
2956 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_11();
2957 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
2958
2959 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
2960 {
2961 /* Exit into power-down Mode */
2962 Status = Adc_Sar_Ip_Powerup(u32Instance);
2963 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
2964 #endif /* FEATURE_ADC_SELFTEST_FULL_CLK */
2965 {
2966 if (ElapsedTicks >= TimeoutTicks)
2967 {
2968 Status = ADC_SAR_IP_STATUS_TIMEOUT;
2969 }
2970 }
2971 #if FEATURE_ADC_SELFTEST_FULL_CLK
2972 }
2973 }
2974 }
2975 #endif /* FEATURE_ADC_SELFTEST_FULL_CLK */
2976
2977 return Status;
2978 }
2979 #endif /* (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED) */
2980
2981 /*FUNCTION**********************************************************************
2982 *
2983 * Function Name : Adc_Sar_Ip_GetConvDataToArray
2984 * Description : This function reads the conversion result values for a conversion chain
2985 * (ADC_SAR_IP_CONV_CHAIN_NORMAL, ADC_SAR_IP_CONV_CHAIN_INJECTED or ADC_SAR_IP_CONV_CHAIN_CTU).
2986 *
2987 * @implements Adc_Sar_Ip_GetConvDataToArray_Activity
2988 * END**************************************************************************/
Adc_Sar_Ip_GetConvDataToArray(const uint32 u32Instance,const Adc_Sar_Ip_ConvChainType pChainType,const uint32 u32Length,uint16 * const pResults)2989 uint32 Adc_Sar_Ip_GetConvDataToArray(const uint32 u32Instance,
2990 const Adc_Sar_Ip_ConvChainType pChainType,
2991 const uint32 u32Length,
2992 uint16 * const pResults)
2993 {
2994 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2995 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
2996 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2997 return Adc_Sar_GetConvResults(u32Instance, pChainType, pResults, NULL_PTR, u32Length);
2998 }
2999
3000 /*FUNCTION**********************************************************************
3001 *
3002 * Function Name : Adc_Sar_Ip_GetConvResultsToArray
3003 * Description : This function gets the conversion results for the selected
3004 * Conversion Chain. It follows the same algorithm as Adc_Sar_Ip_GetConvDataToArray,
3005 * but will copy some extra information to the output.
3006 *
3007 * @implements Adc_Sar_Ip_GetConvResultsToArray_Activity
3008 * END**************************************************************************/
Adc_Sar_Ip_GetConvResultsToArray(const uint32 u32Instance,const Adc_Sar_Ip_ConvChainType pChainType,const uint32 u32Length,Adc_Sar_Ip_ChanResultType * const pResults)3009 uint32 Adc_Sar_Ip_GetConvResultsToArray(const uint32 u32Instance,
3010 const Adc_Sar_Ip_ConvChainType pChainType,
3011 const uint32 u32Length,
3012 Adc_Sar_Ip_ChanResultType* const pResults)
3013 {
3014 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
3015 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
3016 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
3017 return Adc_Sar_GetConvResults(u32Instance, pChainType, NULL_PTR, pResults, u32Length);
3018 }
3019
3020 /*FUNCTION**********************************************************************
3021 *
3022 * Function Name : Adc_Sar_Ip_GetConvData
3023 * Description : This function returns the result of the conversion for
3024 * a single channel
3025 *
3026 * @implements Adc_Sar_Ip_GetConvData_Activity
3027 * END**************************************************************************/
Adc_Sar_Ip_GetConvData(const uint32 u32Instance,const uint32 u32ChnIdx)3028 uint16 Adc_Sar_Ip_GetConvData(const uint32 u32Instance,
3029 const uint32 u32ChnIdx)
3030 {
3031 uint16 Result = 0U;
3032 uint32 VectAdr;
3033 uint32 VectBit;
3034 uint32 Cdr;
3035 ADC_Type * AdcBasePtr = NULL_PTR;
3036 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3037 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
3038 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3039
3040 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
3041 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
3042 DevAssert(u32ChnIdx < ADC_SAR_IP_CDR_COUNT);
3043 #if FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL
3044 DevAssert(ADC_SAR_IP_INST_HAS_CHANn(u32Instance, u32ChnIdx));
3045 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL */
3046 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
3047
3048 VectAdr = ADC_SAR_IP_CHAN_2_VECT(u32ChnIdx);
3049 VectBit = ADC_SAR_IP_CHAN_2_BIT(u32ChnIdx);
3050 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3051 if (u32Instance >= ADC_INSTANCE_COUNT)
3052 {
3053 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
3054 Cdr = CDR_AE(AdcAEBasePtr, u32ChnIdx);
3055 /* check if the conversion data is valid */
3056 if (((Cdr & ADC_CDR_VALID_MASK) != 0U))
3057 {
3058 /* the data is correct, store the result in and clear the flag */
3059 Result = Adc_Sar_GetMaskedResult(u32Instance, Cdr);
3060 CEOCFR(AdcAEBasePtr, VectAdr) = ((uint32)1UL << VectBit); /* w1c bit */
3061 }
3062 }
3063 else
3064 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3065 {
3066 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
3067 Cdr = CDR(AdcBasePtr, u32ChnIdx);
3068 /* check if the conversion data is valid */
3069 if (((Cdr & ADC_CDR_VALID_MASK) != 0U))
3070 {
3071 #if FEATURE_ADC_SAF8544_CHANNEL_WORKAROUND
3072 if (!(((ADC_CDR_RESULT((uint32)ADC_SAR_IP_CONV_CHAIN_INJECTED) == (Cdr & (ADC_CDR_RESULT_MASK))) \
3073 || (ADC_CDR_RESULT((uint32)ADC_SAR_IP_CONV_CHAIN_CTU) == (Cdr & (ADC_CDR_RESULT_MASK)))) \
3074 && (0u == u32ChnIdx) \
3075 ) \
3076 )
3077 #endif
3078 {
3079 /* the data is correct, store the result in and clear the flag */
3080 Result = Adc_Sar_GetMaskedResult(u32Instance, Cdr);
3081 CEOCFR(AdcBasePtr, VectAdr) = ((uint32)1UL << VectBit); /* w1c bit */
3082 }
3083 }
3084 }
3085
3086 return Result;
3087 }
3088
3089 /*FUNCTION**********************************************************************
3090 *
3091 * Function Name : Adc_Sar_Ip_GetConvResult
3092 * Description : This function returns the result and the status of
3093 * the conversion for a single channel
3094 *
3095 * @implements Adc_Sar_Ip_GetConvResult_Activity
3096 * END**************************************************************************/
Adc_Sar_Ip_GetConvResult(const uint32 u32Instance,const uint32 u32ChnIdx,const Adc_Sar_Ip_ConvChainType pChainType,Adc_Sar_Ip_ChanResultType * const pResult)3097 void Adc_Sar_Ip_GetConvResult(const uint32 u32Instance,
3098 const uint32 u32ChnIdx,
3099 const Adc_Sar_Ip_ConvChainType pChainType,
3100 Adc_Sar_Ip_ChanResultType * const pResult)
3101 {
3102 uint32 VectAdr;
3103 uint32 VectBit;
3104 uint32 Cdr;
3105 volatile uint32 * CEOCFRAddr = NULL_PTR;
3106 ADC_Type * AdcBasePtr = NULL_PTR;
3107 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3108 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
3109 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3110
3111 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
3112 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
3113 DevAssert(u32ChnIdx < ADC_SAR_IP_CDR_COUNT);
3114 DevAssert(pResult != NULL_PTR);
3115 #if FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL
3116 DevAssert(ADC_SAR_IP_INST_HAS_CHANn(u32Instance, u32ChnIdx));
3117 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL */
3118 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
3119
3120 VectAdr = ADC_SAR_IP_CHAN_2_VECT(u32ChnIdx);
3121 VectBit = ADC_SAR_IP_CHAN_2_BIT(u32ChnIdx);
3122
3123 pResult->ConvData = 0u;
3124 pResult->AdcChnIdx = (uint8)u32ChnIdx;
3125 pResult->ValidFlag = FALSE;
3126 pResult->OverWrittenFlag = FALSE;
3127
3128 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3129 if (u32Instance >= ADC_INSTANCE_COUNT)
3130 {
3131 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
3132 Cdr = CDR_AE(AdcAEBasePtr, u32ChnIdx);
3133 CEOCFRAddr = &(CEOCFR(AdcAEBasePtr, VectAdr));
3134 }
3135 else
3136 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3137 {
3138 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
3139 Cdr = CDR(AdcBasePtr, u32ChnIdx);
3140 CEOCFRAddr = &(CEOCFR(AdcBasePtr, VectAdr));
3141 }
3142
3143 /* check if the result type matches the one request by pChainType */
3144 if (ADC_CDR_RESULT((uint32)pChainType) == (Cdr & ADC_CDR_RESULT_MASK))
3145 {
3146 #if FEATURE_ADC_SAF8544_CHANNEL_WORKAROUND
3147 if (!((0U == u32ChnIdx) && ((ADC_SAR_IP_CONV_CHAIN_INJECTED == pChainType) || (ADC_SAR_IP_CONV_CHAIN_CTU == pChainType))))
3148 #endif /* FEATURE_ADC_SAF8544_CHANNEL_WORKAROUND */
3149 {
3150 pResult->ValidFlag = ((Cdr & ADC_CDR_VALID_MASK) != 0U) ? TRUE : FALSE;
3151 pResult->OverWrittenFlag = (1U == ((Cdr & ADC_CDR_OVERW_MASK) >> ADC_CDR_OVERW_SHIFT));
3152 pResult->ConvData = Adc_Sar_GetMaskedResult(u32Instance, Cdr);
3153 }
3154 }
3155
3156 *CEOCFRAddr = ((uint32)1UL << VectBit); /* w1c bit */
3157 }
3158
3159 #if FEATURE_ADC_HAS_CALIBRATION
3160 /*FUNCTION**********************************************************************
3161 *
3162 * Function Name : Adc_Sar_Ip_DoCalibration
3163 * Description : This functions executes a calibration sequence. It is recommended
3164 * to run this sequence before using the ADC converter. The maximum clock frequency
3165 * for the calibration is 40 MHz, this function sets the ADCLKSEL bit resulting in
3166 * a maximum input clock frequency of 80 MHz.
3167 *
3168 * @implements Adc_Sar_Ip_DoCalibration_Activity
3169 * END**************************************************************************/
Adc_Sar_Ip_DoCalibration(const uint32 u32Instance)3170 Adc_Sar_Ip_StatusType Adc_Sar_Ip_DoCalibration(const uint32 u32Instance)
3171 {
3172 ADC_Type * AdcBasePtr = NULL_PTR;
3173 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3174 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
3175 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3176 Adc_Sar_Ip_StatusType Status = ADC_SAR_IP_STATUS_SUCCESS;
3177 Adc_Sar_Ip_StatusType CalStatus = ADC_SAR_IP_STATUS_SUCCESS;
3178 uint32 TimeoutTicks = OsIf_MicrosToTicks(ADC_SAR_IP_TIMEOUT_VAL, ADC_SAR_IP_TIMEOUT_TYPE);
3179 uint32 CurrentTicks = OsIf_GetCounter(ADC_SAR_IP_TIMEOUT_TYPE);
3180 uint32 ElapsedTicks = 0u;
3181 uint32 AdcClkSel = 0u;
3182 uint32 Mcr;
3183 #if ADC_SAR_IP_HAS_ADCLKSEL
3184 volatile uint32 * MCRAddr = NULL_PTR;
3185 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
3186 #if (!ADC_SAR_IP_CALIBRATION_USES_MCR || FEATURE_ADC_HAS_APPLICATION_EXTENSION)
3187 uint32 Calbistreg;
3188 volatile uint32 * CALBISTREGAddr = NULL_PTR;
3189 #if defined(ADC_CAL2_ENX_MASK)
3190 volatile uint32 * CAL2Addr = NULL_PTR;
3191 #endif /* defined(ADC_CAL2_ENX_MASK) */
3192 #endif /* (!ADC_SAR_IP_CALIBRATION_USES_MCR || FEATURE_ADC_HAS_APPLICATION_EXTENSION) */
3193
3194 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
3195 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
3196 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
3197
3198 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3199 if (u32Instance >= ADC_INSTANCE_COUNT)
3200 {
3201 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
3202 #if ADC_SAR_IP_HAS_ADCLKSEL
3203 MCRAddr = &(AdcAEBasePtr->MCR);
3204 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
3205 CALBISTREGAddr = &(AdcAEBasePtr->CALBISTREG);
3206 #if defined(ADC_CAL2_ENX_MASK)
3207 CAL2Addr = &(AdcAEBasePtr->CAL2);
3208 #endif /* defined(ADC_CAL2_ENX_MASK) */
3209 }
3210 else
3211 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3212 {
3213 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
3214 #if ADC_SAR_IP_HAS_ADCLKSEL
3215 MCRAddr = &(AdcBasePtr->MCR);
3216 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
3217 #if !ADC_SAR_IP_CALIBRATION_USES_MCR
3218 CALBISTREGAddr = &(AdcBasePtr->CALBISTREG);
3219 #if defined(ADC_CAL2_ENX_MASK)
3220 CAL2Addr = &(AdcBasePtr->CAL2);
3221 #endif /* defined(ADC_CAL2_ENX_MASK) */
3222 #endif /* !ADC_SAR_IP_CALIBRATION_USES_MCR */
3223 }
3224
3225 /* Set CLKSEL to CalibrationClkSelect value */
3226 Status = Adc_Sar_Ip_Powerdown(u32Instance);
3227 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
3228 {
3229 #if ADC_SAR_IP_HAS_ADCLKSEL
3230 /* Save the current state of ADCLKSEL in order to restore it */
3231 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_12();
3232 Mcr = *MCRAddr;
3233 AdcClkSel = (Mcr & ADC_MCR_ADCLKSEL_MASK);
3234 Mcr &= ~(ADC_MCR_ADCLKSEL_MASK);
3235 Mcr |= Adc_Sar_GetADCLKSELValue(Adc_Sar_Ip_axAdcSarState[u32Instance].CalibrationClkSelect);
3236 *MCRAddr = Mcr;
3237 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_12();
3238 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
3239
3240 Status = Adc_Sar_Ip_Powerup(u32Instance);
3241 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
3242 {
3243 #if (!ADC_SAR_IP_CALIBRATION_USES_MCR || FEATURE_ADC_HAS_APPLICATION_EXTENSION)
3244 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3245 if (u32Instance >= ADC_INSTANCE_COUNT)
3246 {
3247 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3248 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_36();
3249 Calbistreg = *CALBISTREGAddr;
3250 /* clear the bits and set to calibration values */
3251 Calbistreg &= ~(ADC_SAR_IP_CALBISTREG_TSAMP_MASK | ADC_SAR_IP_CALBISTREG_NR_SMPL_MASK | ADC_SAR_IP_CALBISTREG_AVG_EN_MASK | ADC_SAR_IP_CALBISTREG_TEST_EN_MASK);
3252 Calbistreg |= ADC_SAR_IP_CALBISTREG_NR_SMPL(0x03u) | ADC_SAR_IP_CALBISTREG_AVG_EN(1U);
3253 *CALBISTREGAddr = Calbistreg;
3254 /* clear the calibration failed before a new calibration */
3255 *CALBISTREGAddr |= ADC_SAR_IP_CALBISTREG_TEST_FAIL_MASK;
3256 /* Disable the error correction for the smaller capacitances in the CDAC of the ADC */
3257 #if defined(ADC_CAL2_ENX_MASK)
3258 *CAL2Addr &= ~(ADC_CAL2_ENX_MASK);
3259 #endif /* defined(ADC_CAL2_ENX_MASK) */
3260 /* Start calibration */
3261 *CALBISTREGAddr |= ADC_SAR_IP_CALBISTREG_TEST_EN(1U);
3262 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_36();
3263
3264 /* Wait for calibration to finish */
3265 ElapsedTicks = 0U;
3266 while (((*CALBISTREGAddr & ADC_SAR_IP_CALBISTREG_C_T_BUSY_MASK) != 0U) && (ElapsedTicks < TimeoutTicks))
3267 {
3268 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
3269 }
3270 if (ElapsedTicks >= TimeoutTicks)
3271 {
3272 CalStatus = ADC_SAR_IP_STATUS_TIMEOUT;
3273 }
3274 else if ((*CALBISTREGAddr & ADC_SAR_IP_CALBISTREG_TEST_FAIL_MASK) != 0U)
3275 {
3276 /* If the calibration failed, return error */
3277 CalStatus = ADC_SAR_IP_STATUS_ERROR;
3278 }
3279 else
3280 {
3281 ; /* Empty else branch to avoid MISRA */
3282 }
3283 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3284 }
3285 else
3286 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3287 #endif /* (!ADC_SAR_IP_CALIBRATION_USES_MCR || FEATURE_ADC_HAS_APPLICATION_EXTENSION) */
3288 {
3289 #if ADC_SAR_IP_CALIBRATION_USES_MCR
3290 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_12();
3291 /* Clear the bits and set to calibration values */
3292 Mcr = AdcBasePtr->MCR;
3293 Mcr &= ~(ADC_MCR_TSAMP_MASK | ADC_MCR_NRSMPL_MASK | ADC_MCR_AVGEN_MASK);
3294 Mcr |= ADC_MCR_NRSMPL(0x03u) | ADC_MCR_AVGEN(1U);
3295 AdcBasePtr->MCR = Mcr;
3296
3297 /* Start calibration */
3298 AdcBasePtr->MCR |= ADC_MCR_CALSTART(1U);
3299 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_12();
3300
3301 /* Wait for calibration to finish */
3302 while (((AdcBasePtr->MSR & ADC_MSR_CALBUSY_MASK) != 0U) && (ElapsedTicks < TimeoutTicks))
3303 {
3304 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
3305 }
3306
3307 if (ElapsedTicks >= TimeoutTicks)
3308 {
3309 CalStatus = ADC_SAR_IP_STATUS_TIMEOUT;
3310 }
3311 else if ((AdcBasePtr->MSR & ADC_MSR_CALFAIL_MASK) != 0U)
3312 {
3313 /* If the calibration failed, return error */
3314 CalStatus = ADC_SAR_IP_STATUS_ERROR;
3315 }
3316 else
3317 {
3318 ; /* Empty else branch to avoid MISRA */
3319 }
3320 #endif /* ADC_SAR_IP_CALIBRATION_USES_MCR */
3321 }
3322
3323 /* Restore the state of ADCLKSEL */
3324 Status = Adc_Sar_Ip_Powerdown(u32Instance);
3325 }
3326
3327 #if ADC_SAR_IP_HAS_ADCLKSEL
3328 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_12();
3329 Mcr = *MCRAddr;
3330 Mcr &= ~(ADC_MCR_ADCLKSEL_MASK);
3331 Mcr |= AdcClkSel;
3332 *MCRAddr = Mcr;
3333 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_12();
3334 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
3335
3336 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
3337 {
3338 Status = Adc_Sar_Ip_Powerup(u32Instance);
3339
3340 if (ADC_SAR_IP_STATUS_SUCCESS != CalStatus)
3341 {
3342 Status = CalStatus;
3343 }
3344 }
3345 }
3346
3347 return Status;
3348 }
3349 #endif /* FEATURE_ADC_HAS_CALIBRATION */
3350
3351 /*FUNCTION**********************************************************************
3352 *
3353 * Function Name : Adc_Sar_Ip_Powerup
3354 * Description : This function enables the ADC module (by clearing the Powerdown
3355 * bit).
3356 *
3357 * @implements Adc_Sar_Ip_Powerup_Activity
3358 * END**************************************************************************/
Adc_Sar_Ip_Powerup(const uint32 u32Instance)3359 Adc_Sar_Ip_StatusType Adc_Sar_Ip_Powerup(const uint32 u32Instance)
3360 {
3361 Adc_Sar_Ip_StatusType ReturnStatus = ADC_SAR_IP_STATUS_SUCCESS;
3362
3363 const ADC_Type * AdcBasePtr = NULL_PTR;
3364 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3365 const SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
3366 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3367 #if FEATURE_ADC_HAS_BANDGAP_STATUS
3368 uint32 BandGapStatus = 0u;
3369 #else
3370 uint32 ExpectedStatus = ADC_MSR_ADCSTATUS(ADC_SAR_IP_MSR_ADCSTATUS_IDLE); /* expected status is IDLE */
3371 uint32 MsrStatus;
3372 volatile const uint32 * MSRAddr = NULL_PTR;
3373 #endif /* FEATURE_ADC_HAS_BANDGAP_STATUS */
3374 uint32 TimeoutTicks = OsIf_MicrosToTicks(ADC_SAR_IP_TIMEOUT_VAL, ADC_SAR_IP_TIMEOUT_TYPE);
3375 uint32 CurrentTicks = OsIf_GetCounter(ADC_SAR_IP_TIMEOUT_TYPE);
3376 uint32 ElapsedTicks = 0u;
3377
3378 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
3379 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
3380 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
3381
3382 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3383 if (u32Instance >= ADC_INSTANCE_COUNT)
3384 {
3385 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
3386 #if !FEATURE_ADC_HAS_BANDGAP_STATUS
3387 MSRAddr = &(AdcAEBasePtr->MSR);
3388 #endif /* !FEATURE_ADC_HAS_BANDGAP_STATUS */
3389 }
3390 else
3391 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3392 {
3393 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
3394 #if !FEATURE_ADC_HAS_BANDGAP_STATUS
3395 MSRAddr = &(AdcBasePtr->MSR);
3396 #endif /* !FEATURE_ADC_HAS_BANDGAP_STATUS */
3397 }
3398
3399 #if FEATURE_ADC_HAS_BANDGAP_STATUS
3400 BandGapStatus = AdcBasePtr->GPADC_READOUT & ADC_GPADC_READOUT_BG_OK_MASK;
3401 #else
3402 MsrStatus = (*MSRAddr) & ADC_MSR_ADCSTATUS_MASK;
3403 #endif /* FEATURE_ADC_HAS_BANDGAP_STATUS */
3404
3405 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_13();
3406 Adc_Sar_Powerup(u32Instance);
3407 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_13();
3408
3409 /* Wait for the device to power up */
3410 #if FEATURE_ADC_HAS_BANDGAP_STATUS
3411 while ((0U == BandGapStatus) && (ElapsedTicks < TimeoutTicks))
3412 {
3413 BandGapStatus = AdcBasePtr->GPADC_READOUT & ADC_GPADC_READOUT_BG_OK_MASK;
3414 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
3415 }
3416 #else
3417 while ((MsrStatus != ExpectedStatus) && (ElapsedTicks < TimeoutTicks))
3418 {
3419 MsrStatus = (*MSRAddr) & ADC_MSR_ADCSTATUS_MASK;
3420 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
3421 }
3422 #endif /* FEATURE_ADC_HAS_BANDGAP_STATUS */
3423
3424 if (ElapsedTicks >= TimeoutTicks)
3425 {
3426 ReturnStatus = ADC_SAR_IP_STATUS_TIMEOUT;
3427 }
3428 #if FEATURE_ADC_HAS_BANDGAP_STATUS
3429 else
3430 {
3431 /* Wait for 20us after BandGap is OK */
3432 TimeoutTicks = OsIf_MicrosToTicks(ADC_SAR_IP_BANDGAP_TIMEOUT_VAL, ADC_SAR_IP_TIMEOUT_TYPE);
3433 CurrentTicks = OsIf_GetCounter(ADC_SAR_IP_TIMEOUT_TYPE);
3434 ElapsedTicks = 0u;
3435 while (ElapsedTicks < TimeoutTicks)
3436 {
3437 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
3438 }
3439 }
3440 #endif /* FEATURE_ADC_HAS_BANDGAP_STATUS */
3441
3442 return ReturnStatus;
3443 }
3444
3445 /*FUNCTION**********************************************************************
3446 *
3447 * Function Name : Adc_Sar_Ip_Powerdown
3448 * Description : This function disables the ADC module (by setting the Powerdown
3449 * bit).
3450 *
3451 * @implements Adc_Sar_Ip_Powerdown_Activity
3452 * END**************************************************************************/
Adc_Sar_Ip_Powerdown(const uint32 u32Instance)3453 Adc_Sar_Ip_StatusType Adc_Sar_Ip_Powerdown(const uint32 u32Instance)
3454 {
3455 const ADC_Type * AdcBasePtr = NULL_PTR;
3456 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3457 const SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
3458 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3459 Adc_Sar_Ip_StatusType ReturnStatus = ADC_SAR_IP_STATUS_SUCCESS;
3460
3461 #if FEATURE_ADC_HAS_BANDGAP_STATUS
3462 uint32 BandGapStatus = 0u;
3463 #else
3464 uint32 ExpectedStatus = ADC_MSR_ADCSTATUS(ADC_SAR_IP_MSR_ADCSTATUS_POWER_DOWN); /* expected status is powered down */
3465 uint32 MsrStatus;
3466 volatile const uint32 * MSRAddr = NULL_PTR;
3467 #endif /* FEATURE_ADC_HAS_BANDGAP_STATUS */
3468 uint32 TimeoutTicks = OsIf_MicrosToTicks(ADC_SAR_IP_TIMEOUT_VAL, ADC_SAR_IP_TIMEOUT_TYPE);
3469 uint32 CurrentTicks = OsIf_GetCounter(ADC_SAR_IP_TIMEOUT_TYPE);
3470 uint32 ElapsedTicks = 0u;
3471
3472 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
3473 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
3474 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
3475
3476 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3477 if (u32Instance >= ADC_INSTANCE_COUNT)
3478 {
3479 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
3480 #if !FEATURE_ADC_HAS_BANDGAP_STATUS
3481 MSRAddr = &(AdcAEBasePtr->MSR);
3482 #endif /* !FEATURE_ADC_HAS_BANDGAP_STATUS */
3483 }
3484 else
3485 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3486 {
3487 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
3488 #if !FEATURE_ADC_HAS_BANDGAP_STATUS
3489 MSRAddr = &(AdcBasePtr->MSR);
3490 #endif /* !FEATURE_ADC_HAS_BANDGAP_STATUS */
3491 }
3492
3493 #if FEATURE_ADC_HAS_BANDGAP_STATUS
3494 BandGapStatus = AdcBasePtr->GPADC_READOUT & ADC_GPADC_READOUT_BG_OK_MASK;
3495 #else
3496 MsrStatus = (*MSRAddr) & ADC_MSR_ADCSTATUS_MASK;
3497 #endif /* FEATURE_ADC_HAS_BANDGAP_STATUS */
3498
3499 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_14();
3500 Adc_Sar_Powerdown(u32Instance);
3501 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_14();
3502
3503 /* Wait for the device to power down */
3504 #if FEATURE_ADC_HAS_BANDGAP_STATUS
3505 while ((1U == BandGapStatus) && (ElapsedTicks < TimeoutTicks))
3506 {
3507 BandGapStatus = AdcBasePtr->GPADC_READOUT & ADC_GPADC_READOUT_BG_OK_MASK;
3508 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
3509 }
3510 #else
3511 while ((MsrStatus != ExpectedStatus) && (ElapsedTicks < TimeoutTicks))
3512 {
3513 MsrStatus = (*MSRAddr) & ADC_MSR_ADCSTATUS_MASK;
3514 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
3515 }
3516 #endif /* FEATURE_ADC_HAS_BANDGAP_STATUS */
3517
3518 if (ElapsedTicks >= TimeoutTicks)
3519 {
3520 ReturnStatus = ADC_SAR_IP_STATUS_TIMEOUT;
3521 }
3522
3523 return ReturnStatus;
3524 }
3525
3526 #if ( \
3527 (STD_ON == ADC_SAR_IP_ECH_ENABLED) || (STD_ON == ADC_SAR_IP_JECH_ENABLED) || \
3528 (STD_ON == ADC_SAR_IP_EOC_ENABLED) || \
3529 ((FEATURE_ADC_HAS_CTU == 1U) && (STD_ON == ADC_SAR_IP_EOCTU_ENABLED)) \
3530 )
3531 /*FUNCTION**********************************************************************
3532 *
3533 * Function Name : Adc_Sar_Ip_EnableNotifications
3534 * Description : This function enables the ADC notifications set to '1' in the
3535 * mask parameter.
3536 *
3537 * @implements Adc_Sar_Ip_EnableNotifications_Activity
3538 * END**************************************************************************/
Adc_Sar_Ip_EnableNotifications(const uint32 u32Instance,const uint32 u32NotificationMask)3539 void Adc_Sar_Ip_EnableNotifications(const uint32 u32Instance,
3540 const uint32 u32NotificationMask)
3541 {
3542 ADC_Type * AdcBasePtr = NULL_PTR;
3543 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3544 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
3545 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3546 uint32 ImrFlags = 0U;
3547
3548 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
3549 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
3550 DevAssert((u32NotificationMask & (~ADC_SAR_IP_NOTIF_FLAG_ALL)) == 0UL);
3551 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
3552
3553 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
3554 ImrFlags |= ((u32NotificationMask & ADC_SAR_IP_NOTIF_FLAG_NORMAL_EOC) != 0U) ? ADC_IMR_MSKEOC(1U) : 0U;
3555 ImrFlags |= ((u32NotificationMask & ADC_SAR_IP_NOTIF_FLAG_INJECTED_EOC) != 0U) ? ADC_IMR_MSKJEOC(1U) : 0U;
3556 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
3557 #if (STD_ON == ADC_SAR_IP_ECH_ENABLED)
3558 ImrFlags |= ((u32NotificationMask & ADC_SAR_IP_NOTIF_FLAG_NORMAL_ENDCHAIN) != 0U) ? ADC_IMR_MSKECH(1U) : 0U;
3559 #endif /* (STD_ON == ADC_SAR_IP_ECH_ENABLED) */
3560 #if (STD_ON == ADC_SAR_IP_JECH_ENABLED)
3561 ImrFlags |= ((u32NotificationMask & ADC_SAR_IP_NOTIF_FLAG_INJECTED_ENDCHAIN) != 0U) ? ADC_IMR_MSKJECH(1U) : 0U;
3562 #endif /* (STD_ON == ADC_SAR_IP_JECH_ENABLED) */
3563 #if FEATURE_ADC_HAS_CTU
3564 #if (STD_ON == ADC_SAR_IP_EOCTU_ENABLED)
3565 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
3566 if (ADC_SAR_IP_INST_HAS_CTU(u32Instance))
3567 {
3568 #endif /*FEATURE_ADC_BAD_ACCESS_PROT_FEATURE*/
3569 ImrFlags |= ((u32NotificationMask & ADC_SAR_IP_NOTIF_FLAG_CTU_EOC) != 0U) ? ADC_IMR_MSKEOCTU(1U) : 0U;
3570 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
3571 }
3572 #endif /*FEATURE_ADC_BAD_ACCESS_PROT_FEATURE*/
3573 #endif /* (STD_ON == ADC_SAR_IP_EOCTU_ENABLED) */
3574 #endif /* FEATURE_ADC_HAS_CTU */
3575 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3576 if (u32Instance >= ADC_INSTANCE_COUNT)
3577 {
3578 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
3579 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_33();
3580 AdcAEBasePtr->IMR |= ImrFlags;
3581 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_33();
3582 }
3583 else
3584 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3585 {
3586 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
3587 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_33();
3588 AdcBasePtr->IMR |= ImrFlags;
3589 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_33();
3590 }
3591 }
3592
3593 /*FUNCTION**********************************************************************
3594 *
3595 * Function Name : Adc_Sar_Ip_DisableNotifications
3596 * Description : This function disables the ADC notifications set to '1' in the
3597 * mask parameter.
3598 *
3599 * @implements Adc_Sar_Ip_DisableNotifications_Activity
3600 * END**************************************************************************/
Adc_Sar_Ip_DisableNotifications(const uint32 u32Instance,const uint32 u32NotificationMask)3601 void Adc_Sar_Ip_DisableNotifications(const uint32 u32Instance,
3602 const uint32 u32NotificationMask)
3603 {
3604 ADC_Type * AdcBasePtr = NULL_PTR;
3605 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3606 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
3607 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3608 uint32 ImrFlags = 0U;
3609
3610 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
3611 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
3612 DevAssert((u32NotificationMask & (~ADC_SAR_IP_NOTIF_FLAG_ALL)) == 0UL);
3613 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
3614
3615 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
3616 ImrFlags |= ((u32NotificationMask & ADC_SAR_IP_NOTIF_FLAG_NORMAL_EOC) != 0U) ? ADC_IMR_MSKEOC(1U) : 0U;
3617 ImrFlags |= ((u32NotificationMask & ADC_SAR_IP_NOTIF_FLAG_INJECTED_EOC) != 0U) ? ADC_IMR_MSKJEOC(1U) : 0U;
3618 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
3619 #if (STD_ON == ADC_SAR_IP_ECH_ENABLED)
3620 ImrFlags |= ((u32NotificationMask & ADC_SAR_IP_NOTIF_FLAG_NORMAL_ENDCHAIN) != 0U) ? ADC_IMR_MSKECH(1U) : 0U;
3621 #endif /* (STD_ON == ADC_SAR_IP_ECH_ENABLED) */
3622 #if (STD_ON == ADC_SAR_IP_JECH_ENABLED)
3623 ImrFlags |= ((u32NotificationMask & ADC_SAR_IP_NOTIF_FLAG_INJECTED_ENDCHAIN) != 0U) ? ADC_IMR_MSKJECH(1U) : 0U;
3624 #endif /* (STD_ON == ADC_SAR_IP_JECH_ENABLED) */
3625 #if FEATURE_ADC_HAS_CTU
3626 #if (STD_ON == ADC_SAR_IP_EOCTU_ENABLED)
3627 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
3628 if (ADC_SAR_IP_INST_HAS_CTU(u32Instance))
3629 {
3630 #endif /*FEATURE_ADC_BAD_ACCESS_PROT_FEATURE*/
3631 ImrFlags |= ((u32NotificationMask & ADC_SAR_IP_NOTIF_FLAG_CTU_EOC) != 0U) ? ADC_IMR_MSKEOCTU(1U) : 0U;
3632 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
3633 }
3634 #endif /*FEATURE_ADC_BAD_ACCESS_PROT_FEATURE*/
3635 #endif /* (STD_ON == ADC_SAR_IP_EOCTU_ENABLED) */
3636 #endif /* FEATURE_ADC_HAS_CTU */
3637 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3638 if (u32Instance >= ADC_INSTANCE_COUNT)
3639 {
3640 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
3641 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_34();
3642 AdcAEBasePtr->IMR &= ~(ImrFlags);
3643 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_34();
3644 }
3645 else
3646 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3647 {
3648 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
3649 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_34();
3650 AdcBasePtr->IMR &= ~(ImrFlags);
3651 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_34();
3652 }
3653 }
3654 #endif /* (STD_ON == ADC_SAR_IP_ECH_ENABLED) .. */
3655
3656 #if ((STD_ON == ADC_SAR_IP_WDG_ENABLED) || (STD_ON == ADC_SAR_IP_EOC_ENABLED))
3657 /*FUNCTION**********************************************************************
3658 *
3659 * Function Name : Adc_Sar_Ip_EnableChannelNotifications
3660 * Description : This function enables End-of-Conversion and watchdog
3661 * interrupts generation for a single channel.
3662 *
3663 * @implements Adc_Sar_Ip_EnableChannelNotifications_Activity
3664 * END**************************************************************************/
Adc_Sar_Ip_EnableChannelNotifications(const uint32 u32Instance,const uint32 u32ChnIdx,const uint32 u32Mask)3665 void Adc_Sar_Ip_EnableChannelNotifications(const uint32 u32Instance,
3666 const uint32 u32ChnIdx,
3667 const uint32 u32Mask)
3668 {
3669 ADC_Type * AdcBasePtr = NULL_PTR;
3670 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3671 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
3672 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3673 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
3674 volatile uint32 * CIMRAddr = NULL_PTR;
3675 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
3676 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
3677 volatile uint32 * CWENRAddr = NULL_PTR;
3678 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
3679 uint32 VectAdr;
3680 uint32 VectBit;
3681
3682 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
3683 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
3684 DevAssert(u32ChnIdx < ADC_SAR_IP_CDR_COUNT);
3685 DevAssert((u32Mask & ~(ADC_SAR_IP_CHAN_NOTIF_FLAG_ALL)) == 0UL);
3686 #if FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL
3687 DevAssert(ADC_SAR_IP_INST_HAS_CHANn(u32Instance, u32ChnIdx));
3688 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL */
3689 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
3690
3691 VectAdr = ADC_SAR_IP_CHAN_2_VECT(u32ChnIdx);
3692 VectBit = ADC_SAR_IP_CHAN_2_BIT(u32ChnIdx);
3693
3694 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3695 if (u32Instance >= ADC_INSTANCE_COUNT)
3696 {
3697 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
3698 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
3699 CIMRAddr = &(CIMR(AdcAEBasePtr, VectAdr));
3700 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
3701 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
3702 CWENRAddr = &(CWENR(AdcAEBasePtr, VectAdr));
3703 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
3704 }
3705 else
3706 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3707 {
3708 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
3709 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
3710 CIMRAddr = &(CIMR(AdcBasePtr, VectAdr));
3711 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
3712 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
3713 CWENRAddr = &(CWENR(AdcBasePtr, VectAdr));
3714 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
3715 }
3716
3717 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
3718 if ((u32Mask & ADC_SAR_IP_CHAN_NOTIF_EOC) != 0u)
3719 {
3720 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_30();
3721 *CIMRAddr |= 1UL << VectBit;
3722 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_30();
3723 }
3724 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
3725
3726 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
3727 if ((u32Mask & ADC_SAR_IP_CHAN_NOTIF_WDG) != 0u)
3728 {
3729 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_28();
3730 *CWENRAddr |= 1UL << VectBit;
3731 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_28();
3732 }
3733 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
3734 }
3735
3736 /*FUNCTION**********************************************************************
3737 *
3738 * Function Name : Adc_Sar_Ip_DisableChannelNotifications
3739 * Description : This function disables End-of-Conversion and watchdog
3740 * interrupts generation for a single channel.
3741 *
3742 * @implements Adc_Sar_Ip_DisableChannelNotifications_Activity
3743 * END**************************************************************************/
Adc_Sar_Ip_DisableChannelNotifications(const uint32 u32Instance,const uint32 u32ChnIdx,const uint32 u32Mask)3744 void Adc_Sar_Ip_DisableChannelNotifications(const uint32 u32Instance,
3745 const uint32 u32ChnIdx,
3746 const uint32 u32Mask)
3747 {
3748 ADC_Type * AdcBasePtr = NULL_PTR;
3749 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3750 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
3751 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3752 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
3753 volatile uint32 * CIMRAddr = NULL_PTR;
3754 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
3755 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
3756 volatile uint32 * CWENRAddr = NULL_PTR;
3757 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
3758 uint32 VectAdr;
3759 uint32 VectBit;
3760
3761 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
3762 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
3763 DevAssert(u32ChnIdx < ADC_SAR_IP_CDR_COUNT);
3764 DevAssert((u32Mask & ~(ADC_SAR_IP_CHAN_NOTIF_FLAG_ALL)) == 0UL);
3765 #if FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL
3766 DevAssert(ADC_SAR_IP_INST_HAS_CHANn(u32Instance, u32ChnIdx));
3767 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL */
3768 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
3769
3770 VectAdr = ADC_SAR_IP_CHAN_2_VECT(u32ChnIdx);
3771 VectBit = ADC_SAR_IP_CHAN_2_BIT(u32ChnIdx);
3772
3773 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3774 if (u32Instance >= ADC_INSTANCE_COUNT)
3775 {
3776 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
3777 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
3778 CIMRAddr = &(CIMR(AdcAEBasePtr, VectAdr));
3779 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
3780 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
3781 CWENRAddr = &(CWENR(AdcAEBasePtr, VectAdr));
3782 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
3783 }
3784 else
3785 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3786 {
3787 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
3788 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
3789 CIMRAddr = &(CIMR(AdcBasePtr, VectAdr));
3790 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
3791 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
3792 CWENRAddr = &(CWENR(AdcBasePtr, VectAdr));
3793 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
3794 }
3795
3796 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
3797 if ((u32Mask & ADC_SAR_IP_CHAN_NOTIF_EOC) != 0u)
3798 {
3799 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_31();
3800 *CIMRAddr &= ~(1UL << VectBit);
3801 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_31();
3802 }
3803 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
3804
3805 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
3806 if ((u32Mask & ADC_SAR_IP_CHAN_NOTIF_WDG) != 0u)
3807 {
3808 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_29();
3809 *CWENRAddr &= ~(1UL << VectBit);
3810 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_29();
3811 }
3812 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
3813 }
3814 #endif /* ((STD_ON == ADC_SAR_IP_WDG_ENABLED) || (STD_ON == ADC_SAR_IP_EOC_ENABLED)) */
3815
3816 /*FUNCTION**********************************************************************
3817 *
3818 * Function Name : Adc_Sar_Ip_SetClockMode
3819 * Description : This function initializes the ADC clock configuration.
3820 *
3821 * @implements Adc_Sar_Ip_SetClockMode_Activity
3822 * END**************************************************************************/
Adc_Sar_Ip_SetClockMode(const uint32 u32Instance,const Adc_Sar_Ip_ClockConfigType * const pConfig)3823 Adc_Sar_Ip_StatusType Adc_Sar_Ip_SetClockMode(const uint32 u32Instance,
3824 const Adc_Sar_Ip_ClockConfigType * const pConfig)
3825 {
3826 Adc_Sar_Ip_StatusType Status = ADC_SAR_IP_STATUS_SUCCESS;
3827 #if ADC_SAR_IP_HAS_ADCLKSEL
3828 uint32 Mcr = 0u;
3829 volatile uint32 * MCRAddr = NULL_PTR;
3830 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
3831 volatile uint32 * PDEDRAddr = NULL_PTR;
3832 ADC_Type * AdcBasePtr = NULL_PTR;
3833 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3834 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
3835 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3836
3837 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
3838 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
3839 DevAssert(pConfig != NULL_PTR);
3840 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
3841
3842 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3843 if (u32Instance >= ADC_INSTANCE_COUNT)
3844 {
3845 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
3846 #if ADC_SAR_IP_HAS_ADCLKSEL
3847 MCRAddr = &(AdcAEBasePtr->MCR);
3848 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
3849 PDEDRAddr = &(AdcAEBasePtr->PDEDR);
3850 }
3851 else
3852 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3853 {
3854 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
3855 #if ADC_SAR_IP_HAS_ADCLKSEL
3856 MCRAddr = &(AdcBasePtr->MCR);
3857 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
3858 PDEDRAddr = &(AdcBasePtr->PDEDR);
3859 }
3860
3861 #if ADC_SAR_IP_HAS_ADCLKSEL
3862 /* Read MCR value and clear values that will be replaced */
3863 Mcr |= Adc_Sar_GetADCLKSELValue(pConfig->ClkSelect);
3864 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
3865 Status = Adc_Sar_Ip_Powerdown(u32Instance);
3866 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
3867 {
3868 #if ADC_SAR_IP_HAS_ADCLKSEL
3869 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_15();
3870 *MCRAddr = ((*MCRAddr) & ~(ADC_MCR_ADCLKSEL_MASK)) | Mcr;
3871 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_15();
3872 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
3873
3874 Status = Adc_Sar_Ip_Powerup(u32Instance);
3875 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
3876 {
3877 #if FEATURE_ADC_HAS_HIGH_SPEED_ENABLE
3878 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_51();
3879 /* Enables high speed conversion or calibration */
3880 Adc_Sar_EnableHighSpeed(AdcBasePtr, pConfig->HighSpeedConvEn);
3881 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_51();
3882 #endif /* FEATURE_ADC_HAS_HIGH_SPEED_ENABLE */
3883
3884 #if FEATURE_ADC_HAS_AVERAGING
3885 Adc_Sar_Ip_SetAveraging(u32Instance, pConfig->AvgEn, pConfig->AvgSel);
3886 #endif /* FEATURE_ADC_HAS_AVERAGING */
3887
3888 /* Set powerdown delay */
3889 *PDEDRAddr = ADC_PDEDR_PDED(pConfig->PowerDownDelay);
3890
3891 #if FEATURE_ADC_HAS_CONVERSION_TIMING
3892 /* Set sample times */
3893 Adc_Sar_Ip_SetSampleTimes(u32Instance, pConfig->SampleTimeArr);
3894 #endif /* FEATURE_ADC_HAS_CONVERSION_TIMING */
3895 }
3896 }
3897
3898 return Status;
3899 }
3900
3901 #if FEATURE_ADC_HAS_CONVERSION_TIMING
3902 /*FUNCTION**********************************************************************
3903 *
3904 * Function Name : Adc_Sar_Ip_SetSampleTimes
3905 * Description : This function sets the sample times for each channnel group.
3906 *
3907 * @implements Adc_Sar_Ip_SetSampleTimes_Activity
3908 * END**************************************************************************/
Adc_Sar_Ip_SetSampleTimes(const uint32 u32Instance,const uint8 * const aSampleTimes)3909 void Adc_Sar_Ip_SetSampleTimes(const uint32 u32Instance,
3910 const uint8 * const aSampleTimes)
3911 {
3912 ADC_Type * AdcBasePtr = NULL_PTR;
3913 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3914 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
3915 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3916 uint8 Index;
3917
3918 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
3919 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
3920 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
3921
3922 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3923 if (u32Instance >= ADC_INSTANCE_COUNT)
3924 {
3925 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
3926 for (Index = 0u; Index < Adc_Sar_Ip_au8AdcGroupCount[u32Instance]; Index++)
3927 {
3928 /* Set sample times */
3929 CTR(AdcAEBasePtr, Index) = ADC_CTR_INPSAMP(aSampleTimes[Index]);
3930 }
3931 }
3932 else
3933 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3934 {
3935 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
3936 for (Index = 0u; Index < Adc_Sar_Ip_au8AdcGroupCount[u32Instance]; Index++)
3937 {
3938 /* Set sample times */
3939 CTR(AdcBasePtr, Index) = ADC_CTR_INPSAMP(aSampleTimes[Index]);
3940 }
3941 }
3942 }
3943 #endif /* FEATURE_ADC_HAS_CONVERSION_TIMING */
3944
3945 #if FEATURE_ADC_HAS_AVERAGING
3946 /*FUNCTION**********************************************************************
3947 *
3948 * Function Name : Adc_Sar_Ip_SetAveraging
3949 * Description : This function sets the sample times for each channnel group.
3950 *
3951 * @implements Adc_Sar_Ip_SetAveraging_Activity
3952 * END**************************************************************************/
Adc_Sar_Ip_SetAveraging(const uint32 u32Instance,const boolean bAvgEn,const Adc_Sar_Ip_AvgSelectType eAvgSel)3953 void Adc_Sar_Ip_SetAveraging(const uint32 u32Instance,
3954 const boolean bAvgEn,
3955 const Adc_Sar_Ip_AvgSelectType eAvgSel)
3956 {
3957 ADC_Type * AdcBasePtr = NULL_PTR;
3958 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3959 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
3960 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3961 volatile uint32 * MCRAddr = NULL_PTR;
3962
3963 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
3964 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
3965 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
3966
3967 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3968 if (u32Instance >= ADC_INSTANCE_COUNT)
3969 {
3970 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
3971 MCRAddr = &(AdcAEBasePtr->MCR);
3972
3973 }
3974 else
3975 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3976 {
3977 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
3978 MCRAddr = &(AdcBasePtr->MCR);
3979 }
3980
3981 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_16();
3982 /* Clear old values */
3983 *MCRAddr &= ~(ADC_MCR_AVGEN_MASK | ADC_MCR_AVGS_MASK);
3984
3985 /* Write new values */
3986 *MCRAddr |= ADC_MCR_AVGEN(bAvgEn ? 1U : 0U) | ADC_MCR_AVGS(eAvgSel);
3987 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_16();
3988 }
3989 #endif /* FEATURE_ADC_HAS_AVERAGING */
3990
3991 /*FUNCTION**********************************************************************
3992 *
3993 * Function Name : Adc_Sar_Ip_AbortConversion
3994 * Description : This function aborts an ongoing conversion.
3995 *
3996 * @implements Adc_Sar_Ip_AbortConversion_Activity
3997 * END**************************************************************************/
Adc_Sar_Ip_AbortConversion(const uint32 u32Instance)3998 void Adc_Sar_Ip_AbortConversion(const uint32 u32Instance)
3999 {
4000 ADC_Type * AdcBasePtr = NULL_PTR;
4001 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4002 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4003 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4004
4005 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4006 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4007 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4008
4009 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4010 if (u32Instance >= ADC_INSTANCE_COUNT)
4011 {
4012 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4013 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_17();
4014 AdcAEBasePtr->MCR |= ADC_MCR_ABORT(1U);
4015 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_17();
4016 }
4017 else
4018 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4019 {
4020 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4021 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_17();
4022 AdcBasePtr->MCR |= ADC_MCR_ABORT(1U);
4023 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_17();
4024 }
4025 }
4026
4027 /*FUNCTION**********************************************************************
4028 *
4029 * Function Name : Adc_Sar_Ip_AbortChain
4030 * Description : This function aborts an ongoing chain of conversions.
4031 *
4032 * @implements Adc_Sar_Ip_AbortChain_Activity
4033 * END**************************************************************************/
Adc_Sar_Ip_AbortChain(const uint32 u32Instance,const boolean bBlocking,const boolean bAllowRestart)4034 Adc_Sar_Ip_StatusType Adc_Sar_Ip_AbortChain(const uint32 u32Instance,
4035 const boolean bBlocking,
4036 const boolean bAllowRestart)
4037 {
4038 ADC_Type * AdcBasePtr = NULL_PTR;
4039 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4040 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4041 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4042 volatile uint32 * MCRAddr = NULL_PTR;
4043 volatile const uint32 * MSRAddr = NULL_PTR;
4044 uint32 MsrStatus;
4045 uint32 TimeoutTicks = OsIf_MicrosToTicks(ADC_SAR_IP_TIMEOUT_VAL, ADC_SAR_IP_TIMEOUT_TYPE);
4046 uint32 CurrentTicks = OsIf_GetCounter(ADC_SAR_IP_TIMEOUT_TYPE);
4047 uint32 ElapsedTicks = 0u;
4048 Adc_Sar_Ip_StatusType ReturnStatus = ADC_SAR_IP_STATUS_SUCCESS;
4049
4050 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4051 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4052 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4053
4054 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4055 if (u32Instance >= ADC_INSTANCE_COUNT)
4056 {
4057 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4058 MCRAddr = &(AdcAEBasePtr->MCR);
4059 MSRAddr = &(AdcAEBasePtr->MSR);
4060 }
4061 else
4062 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4063 {
4064 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4065 MCRAddr = &(AdcBasePtr->MCR);
4066 MSRAddr = &(AdcBasePtr->MSR);
4067 }
4068
4069 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_18();
4070 /* The behavior of the ADC depends on MCR[MODE] (One-Shot/Scan Operation modes).
4071 If Scan Operation mode is disabled, MSR[NSTART] is automatically reset together with MCR[ABORTCHAIN].
4072 Otherwise, in Scan Operation mode, a new chain is started. Therefore MCR[NSTART] should be cleared
4073 before abort the current chain of conversions. */
4074 if (!bAllowRestart)
4075 {
4076 *MCRAddr &= ~(ADC_MCR_NSTART(1U));
4077 #if FEATURE_ADC_ABORTCHAIN_WORKAROUND
4078 /* Workaround to fix abort chain cannot clear MSR[NSTART] bit in scan mode */
4079 while (ElapsedTicks < TimeoutTicks)
4080 {
4081 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
4082 }
4083 #endif /* FEATURE_ADC_ABORTCHAIN_WORKAROUND */
4084 }
4085 *MCRAddr |= ADC_MCR_ABORTCHAIN(1U);
4086 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_18();
4087
4088 if (bBlocking)
4089 {
4090 #if FEATURE_ADC_ABORTCHAIN_WORKAROUND
4091 CurrentTicks = OsIf_GetCounter(ADC_SAR_IP_TIMEOUT_TYPE);
4092 ElapsedTicks = 0u;
4093 #endif /* FEATURE_ADC_ABORTCHAIN_WORKAROUND */
4094 /* Wait for the ongoing conversion to stop */
4095 MsrStatus = *MSRAddr & ADC_MSR_NSTART_MASK;
4096 while ((MsrStatus == ADC_MSR_NSTART_MASK) && (ElapsedTicks < TimeoutTicks))
4097 {
4098 MsrStatus = *MSRAddr & ADC_MSR_NSTART_MASK;
4099 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
4100 }
4101 if (ElapsedTicks >= TimeoutTicks)
4102 {
4103 ReturnStatus = ADC_SAR_IP_STATUS_TIMEOUT;
4104 }
4105 #if !FEATURE_ADC_SAR_W1C_ABORT
4106 else
4107 {
4108 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_18();
4109 /* Clear the ABORT_CHAIN bit if set, otherwise the next chain will be ABORTED without any End of Chain Interrupt */
4110 if (((*MCRAddr) & ADC_MCR_ABORTCHAIN_MASK) != 0u)
4111 {
4112 *MCRAddr &= ~(ADC_MCR_ABORTCHAIN(1U));
4113 }
4114 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_18();
4115 }
4116 #endif /* FEATURE_ADC_SAR_W1C_ABORT */
4117 }
4118
4119 return ReturnStatus;
4120 }
4121
4122 #if FEATURE_ADC_HAS_PRESAMPLING
4123 /*FUNCTION**********************************************************************
4124 *
4125 * Function Name : Adc_Sar_Ip_SetPresamplingSource
4126 * Description : This function configures the Presampling Source for a channel group (0-31, 32-63, 64 -95)
4127 *
4128 * @implements Adc_Sar_Ip_SetPresamplingSource_Activity
4129 * END**************************************************************************/
Adc_Sar_Ip_SetPresamplingSource(const uint32 u32Instance,const Adc_Sar_Ip_ChanGroupType pChanGroup,const Adc_Sar_Ip_PresamplingSourceType pPresampleSource)4130 void Adc_Sar_Ip_SetPresamplingSource(const uint32 u32Instance,
4131 const Adc_Sar_Ip_ChanGroupType pChanGroup,
4132 const Adc_Sar_Ip_PresamplingSourceType pPresampleSource)
4133 {
4134 uint32 Pscr;
4135 ADC_Type * AdcBasePtr = NULL_PTR;
4136 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4137 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4138 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4139 volatile uint32 * PSCRAddr = NULL_PTR;
4140
4141 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4142 if (u32Instance >= ADC_INSTANCE_COUNT)
4143 {
4144 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4145 PSCRAddr = &(AdcAEBasePtr->PSCR);
4146 }
4147 else
4148 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4149 {
4150 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4151 PSCRAddr = &(AdcBasePtr->PSCR);
4152 }
4153
4154 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4155 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4156 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4157
4158 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
4159 if (ADC_SAR_IP_INST_HAS_PSCR(u32Instance))
4160 {
4161 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_FEATURE */
4162
4163 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_38();
4164
4165 Pscr = *PSCRAddr;
4166
4167 switch (pChanGroup)
4168 {
4169 #ifdef ADC_PSCR_PREVAL0
4170 case ADC_SAR_IP_CHAN_GROUP_0:
4171 Pscr &= ~(ADC_PSCR_PREVAL0_MASK);
4172 Pscr |= ADC_PSCR_PREVAL0((uint32)pPresampleSource);
4173 break;
4174 #endif /* ADC_PSCR_PREVAL0 */
4175 #ifdef ADC_PSCR_PREVAL1
4176 case ADC_SAR_IP_CHAN_GROUP_1:
4177 Pscr &= ~(ADC_PSCR_PREVAL1_MASK);
4178 Pscr |= ADC_PSCR_PREVAL1((uint32)pPresampleSource);
4179 break;
4180 #endif /* ADC_PSCR_PREVAL1 */
4181 #ifdef ADC_PSCR_PREVAL2
4182 case ADC_SAR_IP_CHAN_GROUP_2:
4183 Pscr &= ~(ADC_PSCR_PREVAL2_MASK);
4184 Pscr |= ADC_PSCR_PREVAL2((uint32)pPresampleSource);
4185 break;
4186 #endif /* ADC_PSCR_PREVAL2 */
4187 default:
4188 ; /* no-op */
4189 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4190 /* Not supported */
4191 DevAssert(FALSE);
4192 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4193 break;
4194 }
4195
4196 *PSCRAddr = Pscr;
4197
4198 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_38();
4199 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
4200 }
4201 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_FEATURE */
4202 }
4203
4204 /*FUNCTION**********************************************************************
4205 *
4206 * Function Name : Adc_Sar_Ip_EnableChannelPresampling
4207 * Description : This function enables the Presampling on one channel of the ADC.
4208 *
4209 * @implements Adc_Sar_Ip_EnableChannelPresampling_Activity
4210 * END**************************************************************************/
Adc_Sar_Ip_EnableChannelPresampling(const uint32 u32Instance,const uint32 u32ChnIdx)4211 void Adc_Sar_Ip_EnableChannelPresampling(const uint32 u32Instance,
4212 const uint32 u32ChnIdx)
4213 {
4214 uint32 VectAdr;
4215 uint32 VectBit;
4216 ADC_Type * AdcBasePtr = NULL_PTR;
4217 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4218 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4219 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4220 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4221 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4222 DevAssert(u32ChnIdx < ADC_SAR_IP_CDR_COUNT);
4223 #if FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL
4224 DevAssert(ADC_SAR_IP_INST_HAS_CHANn(u32Instance, u32ChnIdx));
4225 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL */
4226 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4227
4228 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
4229 if (ADC_SAR_IP_INST_HAS_PSCR(u32Instance))
4230 {
4231 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_FEATURE */
4232 VectAdr = ADC_SAR_IP_CHAN_2_VECT(u32ChnIdx);
4233 VectBit = ADC_SAR_IP_CHAN_2_BIT(u32ChnIdx);
4234 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4235 if (u32Instance >= ADC_INSTANCE_COUNT)
4236 {
4237 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4238 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_41();
4239 PSR(AdcAEBasePtr, VectAdr) |= 1UL << VectBit;
4240 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_41();
4241 }
4242 else
4243 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4244 {
4245 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4246 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_41();
4247 PSR(AdcBasePtr, VectAdr) |= 1UL << VectBit;
4248 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_41();
4249 }
4250 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
4251 }
4252 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_FEATURE */
4253 }
4254
4255 /*FUNCTION**********************************************************************
4256 *
4257 * Function Name : Adc_Sar_Ip_DisableChannelPresampling
4258 * Description : This function disables the Presampling on one channel of the ADC.
4259 *
4260 * @implements Adc_Sar_Ip_DisableChannelPresampling_Activity
4261 * END**************************************************************************/
Adc_Sar_Ip_DisableChannelPresampling(const uint32 u32Instance,const uint32 u32ChnIdx)4262 void Adc_Sar_Ip_DisableChannelPresampling(const uint32 u32Instance,
4263 const uint32 u32ChnIdx)
4264 {
4265 uint32 VectAdr;
4266 uint32 VectBit;
4267 ADC_Type * AdcBasePtr = NULL_PTR;
4268 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4269 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4270 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4271
4272 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4273 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4274 DevAssert(u32ChnIdx < ADC_SAR_IP_CDR_COUNT);
4275 #if FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL
4276 DevAssert(ADC_SAR_IP_INST_HAS_CHANn(u32Instance, u32ChnIdx));
4277 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL */
4278 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4279
4280 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
4281 if (ADC_SAR_IP_INST_HAS_PSCR(u32Instance))
4282 {
4283 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_FEATURE */
4284 VectAdr = ADC_SAR_IP_CHAN_2_VECT(u32ChnIdx);
4285 VectBit = ADC_SAR_IP_CHAN_2_BIT(u32ChnIdx);
4286 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4287 if (u32Instance >= ADC_INSTANCE_COUNT)
4288 {
4289 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4290 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_42();
4291 PSR(AdcAEBasePtr, VectAdr) &= ~(1UL << VectBit);
4292 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_42();
4293 }
4294 else
4295 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4296 {
4297 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4298 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_42();
4299 PSR(AdcBasePtr, VectAdr) &= ~(1UL << VectBit);
4300 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_42();
4301 }
4302 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
4303 }
4304 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_FEATURE */
4305 }
4306
4307 /*FUNCTION**********************************************************************
4308 *
4309 * Function Name : Adc_Sar_Ip_EnablePresampleConversion
4310 * Description : This function enables bypass of the Sampling Phase, resulting in a conversion
4311 * of the presampled data. This is available only for channels that have presampling
4312 * enabled.
4313 *
4314 * @implements Adc_Sar_Ip_EnablePresampleConversion_Activity
4315 * END**************************************************************************/
Adc_Sar_Ip_EnablePresampleConversion(const uint32 u32Instance)4316 void Adc_Sar_Ip_EnablePresampleConversion(const uint32 u32Instance)
4317 {
4318 ADC_Type * AdcBasePtr = NULL_PTR;
4319 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4320 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4321 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4322
4323 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4324 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4325 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4326
4327 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
4328 if (ADC_SAR_IP_INST_HAS_PSCR(u32Instance))
4329 {
4330 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_FEATURE */
4331
4332 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4333 if (u32Instance >= ADC_INSTANCE_COUNT)
4334 {
4335 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4336 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_39();
4337 AdcAEBasePtr->PSCR |= ADC_PSCR_PRECONV(1U);
4338 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_39();
4339 }
4340 else
4341 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4342 {
4343 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4344 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_39();
4345 AdcBasePtr->PSCR |= ADC_PSCR_PRECONV(1U);
4346 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_39();
4347 }
4348 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
4349 }
4350 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_FEATURE */
4351 }
4352
4353 /*FUNCTION**********************************************************************
4354 *
4355 * Function Name : Adc_Sar_Ip_DisablePresampleConversion
4356 * Description : This function disables Sampling Phase bypass.
4357 *
4358 * @implements Adc_Sar_Ip_DisablePresampleConversion_Activity
4359 * END**************************************************************************/
Adc_Sar_Ip_DisablePresampleConversion(const uint32 u32Instance)4360 void Adc_Sar_Ip_DisablePresampleConversion(const uint32 u32Instance)
4361 {
4362 ADC_Type * AdcBasePtr = NULL_PTR;
4363 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4364 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4365 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4366
4367 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4368 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4369 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4370 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
4371 if (ADC_SAR_IP_INST_HAS_PSCR(u32Instance))
4372 {
4373 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_FEATURE */
4374
4375 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4376 if (u32Instance >= ADC_INSTANCE_COUNT)
4377 {
4378 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4379 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_40();
4380 AdcAEBasePtr->PSCR &= ~(ADC_PSCR_PRECONV(1U));
4381 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_40();
4382 }
4383 else
4384 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4385 {
4386 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4387 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_40();
4388 AdcBasePtr->PSCR &= ~(ADC_PSCR_PRECONV(1U));
4389 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_40();
4390 }
4391
4392 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
4393 }
4394 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_FEATURE */
4395 }
4396 #endif /* FEATURE_ADC_HAS_PRESAMPLING */
4397
4398 /*FUNCTION**********************************************************************
4399 *
4400 * Function Name : Adc_Sar_Ip_EnableDma
4401 * Description : This function enables requests to DMA from ADC
4402 *
4403 * @implements Adc_Sar_Ip_EnableDma_Activity
4404 * END**************************************************************************/
Adc_Sar_Ip_EnableDma(const uint32 u32Instance)4405 void Adc_Sar_Ip_EnableDma(const uint32 u32Instance)
4406 {
4407 ADC_Type * AdcBasePtr = NULL_PTR;
4408 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4409 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4410 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4411
4412 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4413 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4414 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4415
4416 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4417 if (u32Instance >= ADC_INSTANCE_COUNT)
4418 {
4419 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4420 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_43();
4421 AdcAEBasePtr->DMAE |= ADC_DMAE_DMAEN(1U);
4422 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_43();
4423 }
4424 else
4425 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4426 {
4427 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4428 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_43();
4429 AdcBasePtr->DMAE |= ADC_DMAE_DMAEN(1U);
4430 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_43();
4431 }
4432 }
4433
4434 /*FUNCTION**********************************************************************
4435 *
4436 * Function Name : Adc_Sar_Ip_DisableDma
4437 * Description : This function disables requests to DMA from ADC
4438 *
4439 * @implements Adc_Sar_Ip_DisableDma_Activity
4440 * END**************************************************************************/
Adc_Sar_Ip_DisableDma(const uint32 u32Instance)4441 void Adc_Sar_Ip_DisableDma(const uint32 u32Instance)
4442 {
4443 ADC_Type * AdcBasePtr = NULL_PTR;
4444 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4445 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4446 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4447
4448 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4449 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4450 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4451
4452 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4453 if (u32Instance >= ADC_INSTANCE_COUNT)
4454 {
4455 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4456 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_44();
4457 AdcAEBasePtr->DMAE &= ~(ADC_DMAE_DMAEN(1U));
4458 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_44();
4459 }
4460 else
4461 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4462 {
4463 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4464 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_44();
4465 AdcBasePtr->DMAE &= ~(ADC_DMAE_DMAEN(1U));
4466 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_44();
4467 }
4468 }
4469
4470 /*FUNCTION**********************************************************************
4471 *
4472 * Function Name : Adc_Sar_Ip_EnableChannelDma
4473 * Description : This function enables DMA requests triggered by End of Conversion event from
4474 * a selected channel.
4475 *
4476 * @implements Adc_Sar_Ip_EnableChannelDma_Activity
4477 * END**************************************************************************/
Adc_Sar_Ip_EnableChannelDma(const uint32 u32Instance,const uint32 u32ChnIdx)4478 void Adc_Sar_Ip_EnableChannelDma(const uint32 u32Instance,
4479 const uint32 u32ChnIdx)
4480 {
4481 ADC_Type * AdcBasePtr = NULL_PTR;
4482 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4483 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4484 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4485 uint32 VectAdr;
4486 uint32 VectBit;
4487
4488 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4489 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4490 DevAssert(u32ChnIdx < ADC_SAR_IP_CDR_COUNT);
4491 #if FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL
4492 DevAssert(ADC_SAR_IP_INST_HAS_CHANn(u32Instance, u32ChnIdx));
4493 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL */
4494 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4495
4496 VectAdr = ADC_SAR_IP_CHAN_2_VECT(u32ChnIdx);
4497 VectBit = ADC_SAR_IP_CHAN_2_BIT(u32ChnIdx);
4498
4499 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4500 if (u32Instance >= ADC_INSTANCE_COUNT)
4501 {
4502 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4503 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_46();
4504 DMAR(AdcAEBasePtr, VectAdr) |= 1UL << VectBit;
4505 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_46();
4506 }
4507 else
4508 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4509 {
4510 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4511 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_46();
4512 DMAR(AdcBasePtr, VectAdr) |= 1UL << VectBit;
4513 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_46();
4514 }
4515 }
4516
4517 /*FUNCTION**********************************************************************
4518 *
4519 * Function Name : Adc_Sar_Ip_DisableChannelDma
4520 * Description : This function disables DMA requests triggered by End of Conversion event from
4521 * a selected channel.
4522 *
4523 * @implements Adc_Sar_Ip_DisableChannelDma_Activity
4524 * END**************************************************************************/
Adc_Sar_Ip_DisableChannelDma(const uint32 u32Instance,const uint32 u32ChnIdx)4525 void Adc_Sar_Ip_DisableChannelDma(const uint32 u32Instance,
4526 const uint32 u32ChnIdx)
4527 {
4528 ADC_Type * AdcBasePtr = NULL_PTR;
4529 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4530 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4531 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4532 uint32 VectAdr;
4533 uint32 VectBit;
4534
4535 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4536 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4537 DevAssert(u32ChnIdx < ADC_SAR_IP_CDR_COUNT);
4538 #if FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL
4539 DevAssert(ADC_SAR_IP_INST_HAS_CHANn(u32Instance, u32ChnIdx));
4540 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL */
4541 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4542
4543 VectAdr = ADC_SAR_IP_CHAN_2_VECT(u32ChnIdx);
4544 VectBit = ADC_SAR_IP_CHAN_2_BIT(u32ChnIdx);
4545
4546 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4547 if (u32Instance >= ADC_INSTANCE_COUNT)
4548 {
4549 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4550 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_47();
4551 DMAR(AdcAEBasePtr, VectAdr) &= ~(1UL << VectBit);
4552 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_47();
4553 }
4554 else
4555 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4556 {
4557 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4558 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_47();
4559 DMAR(AdcBasePtr, VectAdr) &= ~(1UL << VectBit);
4560 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_47();
4561 }
4562 }
4563
4564 /*FUNCTION**********************************************************************
4565 *
4566 * Function Name : Adc_Sar_Ip_DisableChannelDmaAll
4567 * Description : This function disables DMA requests triggered by End of Conversion event from
4568 * all channels.
4569 *
4570 * @implements Adc_Sar_Ip_DisableChannelDmaAll_Activity
4571 * END**************************************************************************/
Adc_Sar_Ip_DisableChannelDmaAll(const uint32 u32Instance)4572 void Adc_Sar_Ip_DisableChannelDmaAll(const uint32 u32Instance)
4573 {
4574 ADC_Type * AdcBasePtr = NULL_PTR;
4575 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4576 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4577 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4578 uint8 Index;
4579
4580 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4581 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4582 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4583
4584 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4585 if (u32Instance >= ADC_INSTANCE_COUNT)
4586 {
4587 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4588 for (Index = 0U; Index < Adc_Sar_Ip_au8AdcGroupCount[u32Instance]; Index++)
4589 {
4590 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_48();
4591 DMAR(AdcAEBasePtr, Index) &= ~(Adc_Sar_Ip_au32AdcChanBitmap[u32Instance][Index]);
4592 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_48();
4593 }
4594 }
4595 else
4596 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4597 {
4598 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4599 for (Index = 0U; Index < Adc_Sar_Ip_au8AdcGroupCount[u32Instance]; Index++)
4600 {
4601 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_48();
4602 DMAR(AdcBasePtr, Index) &= ~(Adc_Sar_Ip_au32AdcChanBitmap[u32Instance][Index]);
4603 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_48();
4604 }
4605 }
4606 }
4607
4608 /*FUNCTION**********************************************************************
4609 *
4610 * Function Name : Adc_Sar_Ip_SetDmaClearSource
4611 * Description : This function selects the DMA Request Flag Clear Source.
4612 *
4613 * @implements Adc_Sar_Ip_SetDmaClearSource_Activity
4614 * END**************************************************************************/
Adc_Sar_Ip_SetDmaClearSource(const uint32 u32Instance,const Adc_Sar_Ip_ClearSourceType pDmaClear)4615 void Adc_Sar_Ip_SetDmaClearSource(const uint32 u32Instance,
4616 const Adc_Sar_Ip_ClearSourceType pDmaClear)
4617 {
4618 ADC_Type * AdcBasePtr = NULL_PTR;
4619 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4620 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4621 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4622
4623 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4624 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4625 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4626
4627 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4628 if (u32Instance >= ADC_INSTANCE_COUNT)
4629 {
4630 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4631 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_45();
4632 AdcAEBasePtr->DMAE &= ~(ADC_DMAE_DCLR_MASK);
4633 AdcAEBasePtr->DMAE |= ADC_DMAE_DCLR((uint32)pDmaClear);
4634 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_45();
4635 }
4636 else
4637 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4638 {
4639 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4640 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_45();
4641 AdcBasePtr->DMAE &= ~(ADC_DMAE_DCLR_MASK);
4642 AdcBasePtr->DMAE |= ADC_DMAE_DCLR((uint32)pDmaClear);
4643 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_45();
4644 }
4645 }
4646
4647 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
4648 /*FUNCTION**********************************************************************
4649 *
4650 * Function Name : Adc_Sar_Ip_SetWdgThreshold
4651 * Description : This function sets the watchdog thresholds for a certain register.
4652 *
4653 * @implements Adc_Sar_Ip_SetWdgThreshold_Activity
4654 * END**************************************************************************/
Adc_Sar_Ip_SetWdgThreshold(const uint32 u32Instance,const uint8 u8RegisterIdx,const Adc_Sar_Ip_WdgThresholdType * const pThresholdValues)4655 void Adc_Sar_Ip_SetWdgThreshold(const uint32 u32Instance,
4656 const uint8 u8RegisterIdx,
4657 const Adc_Sar_Ip_WdgThresholdType * const pThresholdValues)
4658 {
4659 ADC_Type * AdcBasePtr = NULL_PTR;
4660 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4661 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4662 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4663 volatile uint32 * WTIMRAddr = NULL_PTR;
4664 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
4665 uint8 Shift;
4666 uint16 HighThreshold;
4667 uint16 LowThreshold;
4668 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
4669 uint32 Wtimr;
4670
4671 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4672 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4673 DevAssert(pThresholdValues != NULL_PTR);
4674 DevAssert(u8RegisterIdx < ADC_SAR_IP_THRHLR_COUNT);
4675 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4676
4677 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4678 if (u32Instance >= ADC_INSTANCE_COUNT)
4679 {
4680 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4681 WTIMRAddr = &(AdcAEBasePtr->WTIMR);
4682 }
4683 else
4684 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4685 {
4686 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4687 WTIMRAddr = &(AdcBasePtr->WTIMR);
4688 }
4689
4690 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
4691 if (FALSE == Adc_Sar_Ip_axAdcSarState[u32Instance].BypassResolution)
4692 {
4693 /* Calculate the shift of the threshold value to get the number of bits
4694 * needed by the hardware unit. */
4695 Shift = ADC_SAR_IP_RESULT_RESOLUTION - Adc_Sar_GetResolution(u32Instance);
4696 /* Shift the threshold to obtain the value to be written in the threshold register. */
4697 HighThreshold = (pThresholdValues->HighThreshold) << Shift;
4698 LowThreshold = (pThresholdValues->LowThreshold) << Shift;
4699
4700 /* If the bits of the high threshold value that are ignored due to
4701 * resolution remain 0, this will trigger interrupts when the conversion
4702 * value is equal to the high threshold value because the ignored bits
4703 * of the conversion result will be more than 0, so the high threshold
4704 * value will need to have the ignored bits set to 1. */
4705 HighThreshold |= (((uint16)1U << Shift) - 1U);
4706
4707 Adc_Sar_WriteThresholds(u32Instance, u8RegisterIdx, HighThreshold, LowThreshold);
4708 }
4709 else
4710 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
4711 {
4712 Adc_Sar_WriteThresholds(u32Instance, u8RegisterIdx, pThresholdValues->HighThreshold, pThresholdValues->LowThreshold);
4713 }
4714
4715 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_32();
4716
4717 Wtimr = *WTIMRAddr;
4718
4719 if (pThresholdValues->HighThresholdIntEn)
4720 {
4721 Wtimr |= (ADC_SAR_IP_WDG_REG_MASK_HIGH(u8RegisterIdx));
4722 }
4723 else
4724 {
4725 Wtimr &= (~ADC_SAR_IP_WDG_REG_MASK_HIGH(u8RegisterIdx));
4726 }
4727 if (pThresholdValues->LowThresholdIntEn)
4728 {
4729 Wtimr |= (ADC_SAR_IP_WDG_REG_MASK_LOW(u8RegisterIdx));
4730 }
4731 else
4732 {
4733 Wtimr &= (~ADC_SAR_IP_WDG_REG_MASK_LOW(u8RegisterIdx));
4734 }
4735
4736 *WTIMRAddr = Wtimr;
4737
4738 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_32();
4739 }
4740 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
4741
4742 /*FUNCTION**********************************************************************
4743 *
4744 * Function Name : Adc_Sar_Ip_SetConversionMode
4745 * Description : This function configures the used conversion mode.
4746 * Note: The ADC instance must be in IDLE state in order to change this.
4747 *
4748 * @implements Adc_Sar_Ip_SetConversionMode_Activity
4749 * END**************************************************************************/
Adc_Sar_Ip_SetConversionMode(const uint32 u32Instance,const Adc_Sar_Ip_ConvModeType eConvMode)4750 void Adc_Sar_Ip_SetConversionMode(const uint32 u32Instance,
4751 const Adc_Sar_Ip_ConvModeType eConvMode)
4752 {
4753 ADC_Type * AdcBasePtr = NULL_PTR;
4754 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4755 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4756 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4757 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4758 volatile const uint32 * MSRAddr = NULL_PTR;
4759 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4760 volatile uint32 * MCRAddr = NULL_PTR;
4761
4762 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4763 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4764 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4765
4766 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4767 if (u32Instance >= ADC_INSTANCE_COUNT)
4768 {
4769 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4770 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4771 MSRAddr = &(AdcAEBasePtr->MSR);
4772 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4773 MCRAddr = &(AdcAEBasePtr->MCR);
4774 }
4775 else
4776 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4777 {
4778 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4779 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4780 MSRAddr = &(AdcBasePtr->MSR);
4781 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4782 MCRAddr = &(AdcBasePtr->MCR);
4783 }
4784
4785 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4786 /* The selected ADC should be in IDLE state */
4787 DevAssert(((*MSRAddr) & ADC_MSR_ADCSTATUS_MASK) == ADC_MSR_ADCSTATUS(ADC_SAR_IP_MSR_ADCSTATUS_IDLE));
4788 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4789
4790 /* Edit MODE */
4791 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_19();
4792 switch (eConvMode)
4793 {
4794 case ADC_SAR_IP_CONV_MODE_ONESHOT:
4795 *MCRAddr &= ~(ADC_MCR_MODE(1u)); /* MODE = 0 */
4796 break;
4797 case ADC_SAR_IP_CONV_MODE_SCAN:
4798 *MCRAddr |= ADC_MCR_MODE(1u); /* MODE = 1 */
4799 break;
4800 default:
4801 ; /* no-op */
4802 break;
4803 }
4804 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_19();
4805 }
4806
4807 #if FEATURE_ADC_HAS_CTU
4808 /*FUNCTION**********************************************************************
4809 *
4810 * Function Name : Adc_Sar_Ip_SetCtuMode
4811 * Description : This function configures the CTU mode and enable.
4812 *
4813 * @implements Adc_Sar_Ip_SetCtuMode_Activity
4814 * END**************************************************************************/
Adc_Sar_Ip_SetCtuMode(const uint32 u32Instance,const Adc_Sar_Ip_CtuModeType eCtuMode)4815 Adc_Sar_Ip_StatusType Adc_Sar_Ip_SetCtuMode(const uint32 u32Instance,
4816 const Adc_Sar_Ip_CtuModeType eCtuMode)
4817 {
4818 ADC_Type * AdcBasePtr = NULL_PTR;
4819 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4820 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4821 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4822 Adc_Sar_Ip_StatusType Status = ADC_SAR_IP_STATUS_SUCCESS;
4823 volatile uint32 * MCRAddr = NULL_PTR;
4824
4825 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4826 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4827 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
4828 DevAssert(!((FALSE == ADC_SAR_IP_INST_HAS_CTU_TRIGGER_MODE(u32Instance)) && (ADC_SAR_IP_CTU_MODE_TRIGGER == eCtuMode)));
4829 #endif /*FEATURE_ADC_BAD_ACCESS_PROT_FEATURE*/
4830 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4831
4832 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4833 if (u32Instance >= ADC_INSTANCE_COUNT)
4834 {
4835 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4836 MCRAddr = &(AdcAEBasePtr->MCR);
4837 }
4838 else
4839 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4840 {
4841 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4842 MCRAddr = &(AdcBasePtr->MCR);
4843 }
4844
4845 /* Clear CTUEN to allow Powerdown operation to succeed. */
4846 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_20();
4847 *MCRAddr &= ~ADC_MCR_CTUEN_MASK;
4848 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_20();
4849
4850 /* Power down */
4851 Status = Adc_Sar_Ip_Powerdown(u32Instance);
4852 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
4853 {
4854 /* Configure CTU */
4855 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
4856 if (ADC_SAR_IP_INST_HAS_CTU(u32Instance))
4857 {
4858 #endif /*FEATURE_ADC_BAD_ACCESS_PROT_FEATURE*/
4859 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_20();
4860 switch (eCtuMode)
4861 {
4862 case ADC_SAR_IP_CTU_MODE_CONTROL:
4863 *MCRAddr &= ~(ADC_MCR_CTU_MODE(1U)); /* CTU_MODE = 0 */
4864 *MCRAddr |= ADC_MCR_CTUEN(1U); /* CTUEN = 1 */
4865 break;
4866 #if FEATURE_ADC_HAS_CTU_TRIGGER_MODE
4867 case ADC_SAR_IP_CTU_MODE_TRIGGER:
4868 /* Set CTU_MODE = 1 and CTUEN = 1 */
4869 *MCRAddr |= (ADC_MCR_CTU_MODE(1U) | ADC_MCR_CTUEN(1U));
4870 break;
4871 #endif /* FEATURE_ADC_HAS_CTU_TRIGGER_MODE */
4872 /* Set CTU_MODE = 0 and CTUEN = 0 */
4873 case ADC_SAR_IP_CTU_MODE_DISABLED:
4874 *MCRAddr &= ~(ADC_MCR_CTU_MODE(1U) | ADC_MCR_CTUEN(1U));
4875 break;
4876 default:
4877 ; /* no-op */
4878 break;
4879 }
4880 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_20();
4881 #if FEATURE_ADC_BAD_ACCESS_PROT_FEATURE
4882 }
4883 #endif /*FEATURE_ADC_BAD_ACCESS_PROT_FEATURE*/
4884
4885 /* Power up */
4886 Status = Adc_Sar_Ip_Powerup(u32Instance);
4887 }
4888
4889 return Status;
4890 }
4891 #endif /* FEATURE_ADC_HAS_CTU */
4892
4893 #if (ADC_SAR_IP_EXTERNAL_TRIGGER_ENABLE)
4894 #if (FEATURE_ADC_HAS_INJ_EXT_TRIGGER || FEATURE_ADC_HAS_EXT_TRIGGER)
4895 /*FUNCTION**********************************************************************
4896 *
4897 * Function Name : Adc_Sar_Ip_SetExternalTrigger
4898 * Description : This function configures the external trigger.
4899 *
4900 * @implements Adc_Sar_Ip_SetExternalTrigger_Activity
4901 * END**************************************************************************/
Adc_Sar_Ip_SetExternalTrigger(const uint32 u32Instance,const Adc_Sar_Ip_ExtTriggerEdgeType eTriggerEdge,const Adc_Sar_Ip_ExtTriggerSourceType eTrggerSrc)4902 void Adc_Sar_Ip_SetExternalTrigger(const uint32 u32Instance,
4903 const Adc_Sar_Ip_ExtTriggerEdgeType eTriggerEdge,
4904 const Adc_Sar_Ip_ExtTriggerSourceType eTrggerSrc)
4905 {
4906 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4907 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4908 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4909
4910 /* Switch between injected and normal external trigger */
4911 switch (eTrggerSrc)
4912 {
4913 #if FEATURE_ADC_HAS_EXT_TRIGGER
4914 case ADC_SAR_IP_NORMAL_EXT_TRIG:
4915 Adc_Sar_ConfigExternalTrigger(u32Instance, eTriggerEdge, ADC_MCR_EDGE_MASK, 0U, ADC_MCR_TRGEN_MASK);
4916 break;
4917 #if FEATURE_ADC_HAS_AUX_EXT_TRIGGER
4918 case ADC_SAR_IP_AUX_NORMAL_EXT_TRIG:
4919 Adc_Sar_ConfigExternalTrigger(u32Instance, eTriggerEdge, ADC_MCR_EDGE_MASK, 0U, ADC_MCR_XSTRTEN_MASK);
4920 break;
4921 case ADC_SAR_IP_ALL_NORMAL_EXT_TRIG:
4922 Adc_Sar_ConfigExternalTrigger(u32Instance, eTriggerEdge, ADC_MCR_EDGE_MASK, ADC_MCR_EDGE_MASK, (ADC_MCR_TRGEN_MASK | ADC_MCR_XSTRTEN_MASK));
4923 break;
4924 #endif /* FEATURE_ADC_HAS_AUX_EXT_TRIGGER */
4925 #endif /* FEATURE_ADC_HAS_EXT_TRIGGER */
4926 #if FEATURE_ADC_HAS_INJ_EXT_TRIGGER
4927 case ADC_SAR_IP_INJECTED_EXT_TRIG:
4928 Adc_Sar_ConfigExternalTrigger(u32Instance, eTriggerEdge, ADC_MCR_JEDGE_MASK, ADC_MCR_JEDGE_MASK, ADC_MCR_JTRGEN_MASK);
4929 break;
4930 #endif /* FEATURE_ADC_HAS_INJ_EXT_TRIGGER */
4931 default:
4932 ; /* no-op */
4933 break;
4934 }
4935 }
4936 #endif /* (FEATURE_ADC_HAS_INJ_EXT_TRIGGER || FEATURE_ADC_HAS_EXT_TRIGGER) */
4937 #endif /* (ADC_SAR_IP_EXTERNAL_TRIGGER_ENABLE) */
4938
4939 #if FEATURE_ADC_HAS_TEMPSENSE_CHN
4940 #if (ADC_SAR_IP_TEMPSENSE_ENABLED == STD_ON)
4941 /*FUNCTION**********************************************************************
4942 *
4943 * Function Name : Adc_Sar_Ip_TempSenseCalculateTemp
4944 * Description : This function calculates the temperature on chip from the provided
4945 * parameter.
4946 *
4947 * @implements Adc_Sar_Ip_TempSenseCalculateTemp_Activity
4948 * END**************************************************************************/
Adc_Sar_Ip_TempSenseCalculateTemp(const uint32 u32AdcInstance,const uint32 u32TempInstance,const uint16 u16TempSenseAdcConvData)4949 uint16 Adc_Sar_Ip_TempSenseCalculateTemp(const uint32 u32AdcInstance,
4950 const uint32 u32TempInstance,
4951 const uint16 u16TempSenseAdcConvData)
4952 {
4953 uint32 Vets;
4954 uint32 Vref;
4955 uint32 TempValue;
4956 sint32 Tets;
4957 uint16 Result;
4958 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
4959 uint8 Resolution;
4960 #else
4961 uint8 Resolution = ADC_SAR_IP_MAX_RESOLUTION;
4962 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
4963
4964 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
4965 if (FALSE == Adc_Sar_Ip_axAdcSarState[u32AdcInstance].BypassResolution)
4966 {
4967 Resolution = Adc_Sar_GetResolution(u32AdcInstance);
4968 }
4969 else
4970 {
4971 Resolution = ADC_SAR_IP_RESULT_RESOLUTION;
4972 }
4973 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
4974
4975 Result = (Resolution > ADC_SAR_IP_TEMPSENSE_RESOLUTION) ? \
4976 (u16TempSenseAdcConvData >> (Resolution - ADC_SAR_IP_TEMPSENSE_RESOLUTION)) : \
4977 (u16TempSenseAdcConvData << (ADC_SAR_IP_TEMPSENSE_RESOLUTION - Resolution));
4978
4979 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4980 DevAssert(u32TempInstance < TEMPSENSE_INSTANCE_COUNT);
4981 DevAssert(AdcVoltageRefs[u32AdcInstance] <= 0x58U); /* Vref should be less than 5.5V */
4982 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4983
4984 const TEMPSENSE_Type * const TempSenseBasePtr = Adc_Sar_Ip_apxTempsenseBase[u32TempInstance];
4985 uint32 Tca0 = TempSenseBasePtr->TCA0;
4986 uint32 Tca1 = TempSenseBasePtr->TCA1;
4987 uint32 Tca2 = TempSenseBasePtr->TCA2;
4988
4989 if (AdcVoltageRefs[u32AdcInstance] > ADC_SAR_IP_TEMPSENSE_VOLTAGE_SUPPLY)
4990 {
4991 Vref = Adc_Sar_TempsenseConvFp2Int(ADC_SAR_IP_TEMPSENSE_VOLTAGE_SUPPLY);
4992 }
4993 else
4994 {
4995 Vref = Adc_Sar_TempsenseConvFp2Int(AdcVoltageRefs[u32AdcInstance]);
4996 }
4997
4998 if ((Tca0 & ADC_SAR_IP_TEMPSENSE_SIGN_MASK) != 0U)
4999 {
5000 Tets = - (sint32)(Adc_Sar_TempsenseConvFp2Int(Tca0));
5001 }
5002 else
5003 {
5004 Tets = (sint32)(Adc_Sar_TempsenseConvFp2Int(Tca0));
5005 }
5006
5007 Vets = (uint32)((Vref * Result) / ADC_SAR_IP_TEMPSENSE_RESOLUTION_12B);
5008 TempValue = (Adc_Sar_TempsenseConvFp2Int(Tca1) * Vets) / ADC_SAR_IP_TEMPSENSE_MULTIPLIER;
5009
5010 if ((Tca1 & ADC_SAR_IP_TEMPSENSE_SIGN_MASK) != 0U)
5011 {
5012 Tets -= (sint32)(TempValue);
5013 }
5014 else
5015 {
5016 Tets += (sint32)(TempValue);
5017 }
5018
5019 Vets = (Vets * Vets) / ADC_SAR_IP_TEMPSENSE_MULTIPLIER;
5020 TempValue = (Adc_Sar_TempsenseConvFp2Int(Tca2) * Vets) / ADC_SAR_IP_TEMPSENSE_MULTIPLIER;
5021
5022 if ((Tca2 & ADC_SAR_IP_TEMPSENSE_SIGN_MASK) != 0U)
5023 {
5024 Tets -= (sint32)(TempValue);
5025 }
5026 else
5027 {
5028 Tets += (sint32)(TempValue);
5029 }
5030
5031 return Adc_Sar_TempsenseConvInt2Fp(Tets);
5032 }
5033
5034
5035 /*FUNCTION**********************************************************************
5036 *
5037 * Function Name : Adc_Sar_Ip_TempSenseGetTemp
5038 * Description : This function starts a normal software conversion on tempsense
5039 * channel and calculates the temperature on chip from the data conversion
5040 * parameter. Tempsense calculations are done using 12bits operators, so it is
5041 * recommended for Adc to run on minimum resolution of 12-bit.
5042 *
5043 * @implements Adc_Sar_Ip_TempSenseGetTemp_Activity
5044 * END**************************************************************************/
Adc_Sar_Ip_TempSenseGetTemp(const uint32 u32AdcInstance,const uint32 u32TempInstance,uint16 * const pTempSenseVal)5045 Adc_Sar_Ip_StatusType Adc_Sar_Ip_TempSenseGetTemp(const uint32 u32AdcInstance,
5046 const uint32 u32TempInstance,
5047 uint16 * const pTempSenseVal)
5048 {
5049 Adc_Sar_Ip_StatusType ReturnStatus = ADC_SAR_IP_STATUS_SUCCESS;
5050 uint32 TimeoutTicks = OsIf_MicrosToTicks(ADC_SAR_IP_TIMEOUT_VAL, ADC_SAR_IP_TIMEOUT_TYPE);
5051 uint32 CurrentTicks = OsIf_GetCounter(ADC_SAR_IP_TIMEOUT_TYPE);
5052 uint32 ElapsedTicks = 0u;
5053 uint32 ExpectedStatus;
5054 uint32 ConvFlagStatus;
5055 uint32 Cdr;
5056 uint16 Result;
5057 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
5058 uint8 Resolution;
5059 #else
5060 uint8 Resolution = ADC_SAR_IP_MAX_RESOLUTION;
5061 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
5062 uint32 VectAdr;
5063 uint32 VectBit;
5064 ADC_Type * const AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32AdcInstance];
5065 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
5066 uint32 Cimr[ADC_SAR_IP_NUM_GROUP_CHAN];
5067 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
5068 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
5069 uint32 Cwenr[ADC_SAR_IP_NUM_GROUP_CHAN];
5070 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
5071 const uint32 Imr = AdcBasePtr->IMR;
5072 const uint32 Wtimr = AdcBasePtr->WTIMR;
5073
5074 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
5075 DevAssert(u32AdcInstance < ADC_SAR_IP_INSTANCE_COUNT);
5076 DevAssert(u32TempInstance < TEMPSENSE_INSTANCE_COUNT);
5077 DevAssert(AdcVoltageRefs[u32AdcInstance] <= 0x58U); /* Vref should be less than 5.5V */
5078 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
5079
5080 /* Store the state of control interrupt registers and disable them,
5081 * Since this function cannt work when any ISR enabled */
5082 AdcBasePtr->IMR = 0UL;
5083 AdcBasePtr->WTIMR = 0UL;
5084 #if ((STD_ON == ADC_SAR_IP_WDG_ENABLED) || (STD_ON == ADC_SAR_IP_EOC_ENABLED))
5085 for (VectAdr = 0U; VectAdr < Adc_Sar_Ip_au8AdcGroupCount[u32AdcInstance]; VectAdr++)
5086 {
5087 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
5088 Cimr[VectAdr] = CIMR(AdcBasePtr, VectAdr);
5089 CIMR(AdcBasePtr, VectAdr) = 0UL;
5090 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
5091
5092 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
5093 Cwenr[VectAdr] = CWENR(AdcBasePtr, VectAdr);
5094 CWENR(AdcBasePtr, VectAdr) = 0UL;
5095 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
5096 }
5097 #endif /* ((STD_ON == ADC_SAR_IP_WDG_ENABLED) || (STD_ON == ADC_SAR_IP_EOC_ENABLED)) */
5098
5099 VectAdr = ADC_SAR_IP_CHAN_2_VECT(ADC_SAR_IP_TEMPSENSE_CHANNEL);
5100 VectBit = ADC_SAR_IP_CHAN_2_BIT(ADC_SAR_IP_TEMPSENSE_CHANNEL);
5101 /* Enable tempsense channel */
5102 NCMR(AdcBasePtr, VectAdr) |= (1UL << VectBit);
5103 /* One-shot mode */
5104 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_22();
5105 AdcBasePtr->MCR &= ~(ADC_MCR_MODE(1U));
5106 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_22();
5107
5108 /* Start normal software conversion */
5109 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_22();
5110 AdcBasePtr->MCR |= ADC_MCR_NSTART(1U);
5111 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_22();
5112
5113 /* Wait for the conversion to be finished */
5114 ExpectedStatus = (1UL << VectBit);
5115 ConvFlagStatus = CEOCFR(AdcBasePtr, VectAdr) & (1UL << VectBit);
5116 while ((ConvFlagStatus != ExpectedStatus) && (ElapsedTicks < TimeoutTicks))
5117 {
5118 ConvFlagStatus = CEOCFR(AdcBasePtr, VectAdr) & (1UL << VectBit);
5119 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
5120 }
5121 if (ElapsedTicks >= TimeoutTicks)
5122 {
5123 ReturnStatus = ADC_SAR_IP_STATUS_TIMEOUT;
5124 }
5125
5126 if (ReturnStatus == ADC_SAR_IP_STATUS_SUCCESS)
5127 {
5128 Cdr = CDR(AdcBasePtr, (uint32)ADC_SAR_IP_TEMPSENSE_CHANNEL);
5129 if (((Cdr & ADC_CDR_VALID_MASK) != 0U))
5130 {
5131 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
5132 if (FALSE == Adc_Sar_Ip_axAdcSarState[u32AdcInstance].BypassResolution)
5133 {
5134 Resolution = Adc_Sar_GetResolution(u32AdcInstance);
5135 }
5136 else
5137 {
5138 Resolution = ADC_SAR_IP_RESULT_RESOLUTION;
5139 }
5140 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
5141 Result = Adc_Sar_GetMaskedResult(u32AdcInstance, Cdr);
5142 /* the data is correct, store the result in 12bit resolution and clear the flag */
5143 if (Adc_Sar_Ip_axAdcSarState[u32AdcInstance].DataAlign == ADC_SAR_IP_DATA_ALIGNED_LEFT)
5144 {
5145 /* Assumption: the width of the register is less than 16 */
5146 Result = Result >> (16u - Resolution);
5147 }
5148
5149 CEOCFR(AdcBasePtr, VectAdr) = ((uint32)1UL << VectBit); /* w1c bit */
5150 *pTempSenseVal = Adc_Sar_Ip_TempSenseCalculateTemp(u32AdcInstance, u32TempInstance, Result);
5151 }
5152 }
5153
5154 /* Disable tempsense channel */
5155 NCMR(AdcBasePtr, VectAdr) &= ~(1UL << VectBit);
5156
5157 /* Re-store control interrupt registers */
5158 AdcBasePtr->IMR = Imr;
5159 AdcBasePtr->WTIMR = Wtimr;
5160 #if ((STD_ON == ADC_SAR_IP_WDG_ENABLED) || (STD_ON == ADC_SAR_IP_EOC_ENABLED))
5161 for (VectAdr = 0U; VectAdr < Adc_Sar_Ip_au8AdcGroupCount[u32AdcInstance]; VectAdr++)
5162 {
5163 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
5164 CIMR(AdcBasePtr, VectAdr) = Cimr[VectAdr];
5165 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
5166
5167 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
5168 CWENR(AdcBasePtr, VectAdr) = Cwenr[VectAdr];
5169 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
5170 }
5171 #endif /* ((STD_ON == ADC_SAR_IP_WDG_ENABLED) || (STD_ON == ADC_SAR_IP_EOC_ENABLED)) */
5172
5173 return ReturnStatus;
5174 }
5175
5176
5177 /*FUNCTION**********************************************************************
5178 *
5179 * Function Name : Adc_Sar_Ip_TempSenseEnable
5180 * Description : This function enables the temperature sensor.
5181 *
5182 * @implements Adc_Sar_Ip_TempSenseEnable_Activity
5183 * END**************************************************************************/
Adc_Sar_Ip_TempSenseEnable(const uint32 u32Instance)5184 void Adc_Sar_Ip_TempSenseEnable(const uint32 u32Instance)
5185 {
5186 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
5187 DevAssert(u32Instance < TEMPSENSE_INSTANCE_COUNT);
5188 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
5189 TEMPSENSE_Type * const TempSenseBasePtr = Adc_Sar_Ip_apxTempsenseBase[u32Instance];
5190
5191 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_49();
5192 TempSenseBasePtr->ETSCTL |= TEMPSENSE_ETSCTL_ETS_EN_MASK;
5193 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_49();
5194 }
5195
5196 /*FUNCTION**********************************************************************
5197 *
5198 * Function Name : Adc_Sar_Ip_TempSenseDisable
5199 * Description : This function disables the temperature sensor.
5200 *
5201 * @implements Adc_Sar_Ip_TempSenseDisable_Activity
5202 * END**************************************************************************/
Adc_Sar_Ip_TempSenseDisable(const uint32 u32Instance)5203 void Adc_Sar_Ip_TempSenseDisable(const uint32 u32Instance)
5204 {
5205 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
5206 DevAssert(u32Instance < TEMPSENSE_INSTANCE_COUNT);
5207 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
5208 TEMPSENSE_Type * const TempSenseBasePtr = Adc_Sar_Ip_apxTempsenseBase[u32Instance];
5209
5210 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_50();
5211 TempSenseBasePtr->ETSCTL &= (~TEMPSENSE_ETSCTL_ETS_EN_MASK);
5212 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_50();
5213 }
5214 #endif /* (ADC_SAR_IP_TEMPSENSE_ENABLED == STD_ON) */
5215 #endif /* FEATURE_ADC_HAS_TEMPSENSE_CHN */
5216
5217 /*FUNCTION*********************************************************************
5218 *
5219 * Function Name : Adc_Sar_Ip_GetDataAddress
5220 * Description : Returns the address of the specified CDR register
5221 * @implements Adc_Sar_Ip_GetDataAddress_Activity
5222 *END*************************************************************************/
Adc_Sar_Ip_GetDataAddress(uint32 u32Instance,uint32 u32ChannelIndex)5223 uint32 Adc_Sar_Ip_GetDataAddress(uint32 u32Instance,
5224 uint32 u32ChannelIndex)
5225 {
5226 uint32 returnAddr = 0U;
5227
5228 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
5229 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
5230 DevAssert(u32ChannelIndex < ADC_SAR_IP_CDR_COUNT);
5231 #if FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL
5232 DevAssert(ADC_SAR_IP_INST_HAS_CHANn(u32Instance, u32ChannelIndex));
5233 #endif /* FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL */
5234 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
5235
5236 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
5237 if (u32Instance >= ADC_INSTANCE_COUNT)
5238 {
5239 returnAddr = (uint32)&(CDR_AE(Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT], u32ChannelIndex));
5240 }
5241 else
5242 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
5243 {
5244 returnAddr = (uint32)&(CDR(Adc_Sar_Ip_apxAdcBase[u32Instance], u32ChannelIndex));
5245 }
5246 return returnAddr;
5247 }
5248
5249 #if (STD_ON == ADC_SAR_IP_ENABLE_USER_MODE_SUPPORT)
5250 /*FUNCTION**********************************************************************
5251 *
5252 * Function Name : Adc_Sar_Ip_SetUserAccessAllowed
5253 * Description : Sets the UAA bit in REG_PROT to make the instance accessible in user mode.
5254 *
5255 *END**************************************************************************/
Adc_Sar_Ip_SetUserAccessAllowed(const uint32 Instance)5256 void Adc_Sar_Ip_SetUserAccessAllowed(const uint32 Instance)
5257 {
5258 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
5259 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
5260 #else
5261 #ifdef SAR_ADC_PROT_MEM_U32
5262 ADC_Type * AdcBasePtr = NULL_PTR;
5263 #endif /* SAR_ADC_PROT_MEM_U32 */
5264 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
5265
5266 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
5267 DevAssert(Instance < ADC_SAR_IP_INSTANCE_COUNT);
5268 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
5269
5270 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
5271 if (Instance >= ADC_INSTANCE_COUNT)
5272 {
5273 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
5274 SET_USER_ACCESS_ALLOWED((uint32)AdcAEBasePtr, SAR_ADC_AE_PROT_MEM_U32);
5275 }
5276 #else
5277 #ifdef SAR_ADC_PROT_MEM_U32
5278 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
5279 SET_USER_ACCESS_ALLOWED((uint32)AdcBasePtr, SAR_ADC_PROT_MEM_U32);
5280 #else
5281 (void)Instance;
5282 #endif /* SAR_ADC_PROT_MEM_U32 */
5283 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
5284 }
5285
5286 /*FUNCTION**********************************************************************
5287 *
5288 * Function Name : Adc_Sar_Ip_ClrUserAccessAllowed
5289 * Description : Clears the UAA bit in REG_PROT to make the instance inaccessible in user mode.
5290 *
5291 *END**************************************************************************/
Adc_Sar_Ip_ClrUserAccessAllowed(const uint32 Instance)5292 void Adc_Sar_Ip_ClrUserAccessAllowed(const uint32 Instance)
5293 {
5294 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
5295 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
5296 #else
5297 #ifdef SAR_ADC_PROT_MEM_U32
5298 ADC_Type * AdcBasePtr = NULL_PTR;
5299 #endif /* SAR_ADC_PROT_MEM_U32 */
5300 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
5301
5302 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
5303 DevAssert(Instance < ADC_SAR_IP_INSTANCE_COUNT);
5304 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
5305
5306 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
5307 if (Instance >= ADC_INSTANCE_COUNT)
5308 {
5309 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
5310 CLR_USER_ACCESS_ALLOWED((uint32)AdcAEBasePtr, SAR_ADC_AE_PROT_MEM_U32);
5311 }
5312 #else
5313 #ifdef SAR_ADC_PROT_MEM_U32
5314 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
5315 CLR_USER_ACCESS_ALLOWED((uint32)AdcBasePtr, SAR_ADC_PROT_MEM_U32);
5316 #else
5317 (void)Instance;
5318 #endif /* SAR_ADC_PROT_MEM_U32 */
5319 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
5320 }
5321 #endif /* (STD_ON == ADC_SAR_IP_ENABLE_USER_MODE_SUPPORT) */
5322
5323 #define ADC_STOP_SEC_CODE
5324 #include "Adc_MemMap.h"
5325
5326 #ifdef __cplusplus
5327 }
5328 #endif
5329
5330 /** @} */
5331