1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef __STM32L4xx_HAL_RCC_EX_H 38 #define __STM32L4xx_HAL_RCC_EX_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* Includes ------------------------------------------------------------------*/ 45 #include "stm32l4xx_hal_def.h" 46 47 /** @addtogroup STM32L4xx_HAL_Driver 48 * @{ 49 */ 50 51 /** @addtogroup RCCEx 52 * @{ 53 */ 54 55 /* Exported types ------------------------------------------------------------*/ 56 57 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 58 * @{ 59 */ 60 61 #if defined(RCC_PLLSAI1_SUPPORT) 62 /** 63 * @brief PLLSAI1 Clock structure definition 64 */ 65 typedef struct 66 { 67 68 uint32_t PLLSAI1Source; /*!< PLLSAI1Source: PLLSAI1 entry clock source. 69 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 70 71 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 72 uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock. 73 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ 74 #else 75 uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock. 76 This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ 77 #endif 78 79 uint32_t PLLSAI1N; /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock. 80 This parameter must be a number between 8 and 86 or 127 depending on devices. */ 81 82 uint32_t PLLSAI1P; /*!< PLLSAI1P: specifies the division factor for SAI clock. 83 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 84 85 uint32_t PLLSAI1Q; /*!< PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock. 86 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ 87 88 uint32_t PLLSAI1R; /*!< PLLSAI1R: specifies the division factor for ADC clock. 89 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ 90 91 uint32_t PLLSAI1ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled. 92 This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */ 93 }RCC_PLLSAI1InitTypeDef; 94 #endif /* RCC_PLLSAI1_SUPPORT */ 95 96 #if defined(RCC_PLLSAI2_SUPPORT) 97 /** 98 * @brief PLLSAI2 Clock structure definition 99 */ 100 typedef struct 101 { 102 103 uint32_t PLLSAI2Source; /*!< PLLSAI2Source: PLLSAI2 entry clock source. 104 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 105 106 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 107 uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock. 108 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ 109 #else 110 uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock. 111 This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ 112 #endif 113 114 uint32_t PLLSAI2N; /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock. 115 This parameter must be a number between 8 and 86 or 127 depending on devices. */ 116 117 uint32_t PLLSAI2P; /*!< PLLSAI2P: specifies the division factor for SAI clock. 118 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 119 120 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 121 uint32_t PLLSAI2Q; /*!< PLLSAI2Q: specifies the division factor for DSI clock. 122 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ 123 #endif 124 125 uint32_t PLLSAI2R; /*!< PLLSAI2R: specifies the division factor for ADC clock. 126 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ 127 128 uint32_t PLLSAI2ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled. 129 This parameter must be a value of @ref RCC_PLLSAI2_Clock_Output */ 130 }RCC_PLLSAI2InitTypeDef; 131 132 #endif /* RCC_PLLSAI2_SUPPORT */ 133 134 /** 135 * @brief RCC extended clocks structure definition 136 */ 137 typedef struct 138 { 139 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 140 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 141 #if defined(RCC_PLLSAI1_SUPPORT) 142 143 RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters. 144 This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */ 145 #endif /* RCC_PLLSAI1_SUPPORT */ 146 #if defined(RCC_PLLSAI2_SUPPORT) 147 148 RCC_PLLSAI2InitTypeDef PLLSAI2; /*!< PLLSAI2 structure parameters. 149 This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC */ 150 151 #endif /* RCC_PLLSAI2_SUPPORT */ 152 153 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. 154 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 155 156 uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. 157 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ 158 159 #if defined(USART3) 160 161 uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. 162 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ 163 164 #endif /* USART3 */ 165 166 #if defined(UART4) 167 168 uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. 169 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ 170 171 #endif /* UART4 */ 172 173 #if defined(UART5) 174 175 uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source. 176 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ 177 178 #endif /* UART5 */ 179 180 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. 181 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 182 183 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. 184 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ 185 186 #if defined(I2C2) 187 188 uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. 189 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 190 191 #endif /* I2C2 */ 192 193 uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. 194 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 195 196 #if defined(I2C4) 197 198 uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. 199 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ 200 201 #endif /* I2C4 */ 202 203 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. 204 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 205 206 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. 207 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ 208 #if defined(SAI1) 209 210 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. 211 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 212 #endif /* SAI1 */ 213 214 #if defined(SAI2) 215 216 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source. 217 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ 218 219 #endif /* SAI2 */ 220 221 #if defined(USB_OTG_FS) || defined(USB) 222 223 uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for SDMMC1 and RNG). 224 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 225 226 #endif /* USB_OTG_FS || USB */ 227 228 #if defined(SDMMC1) 229 230 uint32_t Sdmmc1ClockSelection; /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG). 231 This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ 232 233 #endif /* SDMMC1 */ 234 235 uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1). 236 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ 237 238 #if !defined(STM32L412xx) && !defined(STM32L422xx) 239 uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source. 240 This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ 241 #endif /* !STM32L412xx && !STM32L422xx */ 242 243 #if defined(SWPMI1) 244 245 uint32_t Swpmi1ClockSelection; /*!< Specifies SWPMI1 clock source. 246 This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */ 247 248 #endif /* SWPMI1 */ 249 250 #if defined(DFSDM1_Filter0) 251 252 uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 clock source. 253 This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */ 254 255 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 256 uint32_t Dfsdm1AudioClockSelection; /*!< Specifies DFSDM1 audio clock source. 257 This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */ 258 259 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 260 261 #endif /* DFSDM1_Filter0 */ 262 263 #if defined(LTDC) 264 265 uint32_t LtdcClockSelection; /*!< Specifies LTDC clock source. 266 This parameter can be a value of @ref RCCEx_LTDC_Clock_Source */ 267 268 #endif /* LTDC */ 269 270 #if defined(DSI) 271 272 uint32_t DsiClockSelection; /*!< Specifies DSI clock source. 273 This parameter can be a value of @ref RCCEx_DSI_Clock_Source */ 274 275 #endif /* DSI */ 276 277 #if defined(OCTOSPI1) || defined(OCTOSPI2) 278 279 uint32_t OspiClockSelection; /*!< Specifies OctoSPI clock source. 280 This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */ 281 282 #endif 283 284 uint32_t RTCClockSelection; /*!< Specifies RTC clock source. 285 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 286 }RCC_PeriphCLKInitTypeDef; 287 288 #if defined(CRS) 289 290 /** 291 * @brief RCC_CRS Init structure definition 292 */ 293 typedef struct 294 { 295 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 296 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 297 298 uint32_t Source; /*!< Specifies the SYNC signal source. 299 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 300 301 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 302 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 303 304 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. 305 It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 306 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ 307 308 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 309 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ 310 311 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 312 This parameter must be a number between 0 and 0x7F for STM32L412xx/L422xx, between 0 and 0x3F otherwise, 313 or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ 314 315 }RCC_CRSInitTypeDef; 316 317 /** 318 * @brief RCC_CRS Synchronization structure definition 319 */ 320 typedef struct 321 { 322 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 323 This parameter must be a number between 0 and 0xFFFF */ 324 325 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. 326 This parameter must be a number between 0 and 0x7F for STM32L412xx/L422xx, between 0 and 0x3F otherwise */ 327 328 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 329 value latched in the time of the last SYNC event. 330 This parameter must be a number between 0 and 0xFFFF */ 331 332 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 333 frequency error counter latched in the time of the last SYNC event. 334 It shows whether the actual frequency is below or above the target. 335 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ 336 337 }RCC_CRSSynchroInfoTypeDef; 338 339 #endif /* CRS */ 340 /** 341 * @} 342 */ 343 344 /* Exported constants --------------------------------------------------------*/ 345 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 346 * @{ 347 */ 348 349 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source 350 * @{ 351 */ 352 #define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ 353 #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ 354 /** 355 * @} 356 */ 357 358 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection 359 * @{ 360 */ 361 #define RCC_PERIPHCLK_USART1 0x00000001U 362 #define RCC_PERIPHCLK_USART2 0x00000002U 363 #if defined(USART3) 364 #define RCC_PERIPHCLK_USART3 0x00000004U 365 #endif 366 #if defined(UART4) 367 #define RCC_PERIPHCLK_UART4 0x00000008U 368 #endif 369 #if defined(UART5) 370 #define RCC_PERIPHCLK_UART5 0x00000010U 371 #endif 372 #define RCC_PERIPHCLK_LPUART1 0x00000020U 373 #define RCC_PERIPHCLK_I2C1 0x00000040U 374 #if defined(I2C2) 375 #define RCC_PERIPHCLK_I2C2 0x00000080U 376 #endif 377 #define RCC_PERIPHCLK_I2C3 0x00000100U 378 #define RCC_PERIPHCLK_LPTIM1 0x00000200U 379 #define RCC_PERIPHCLK_LPTIM2 0x00000400U 380 #if defined(SAI1) 381 #define RCC_PERIPHCLK_SAI1 0x00000800U 382 #endif 383 #if defined(SAI2) 384 #define RCC_PERIPHCLK_SAI2 0x00001000U 385 #endif 386 #if defined(USB_OTG_FS) || defined(USB) 387 #define RCC_PERIPHCLK_USB 0x00002000U 388 #endif 389 #define RCC_PERIPHCLK_ADC 0x00004000U 390 #if defined(SWPMI1) 391 #define RCC_PERIPHCLK_SWPMI1 0x00008000U 392 #endif 393 #if defined(DFSDM1_Filter0) 394 #define RCC_PERIPHCLK_DFSDM1 0x00010000U 395 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 396 #define RCC_PERIPHCLK_DFSDM1AUDIO 0x00200000U 397 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 398 #endif 399 #define RCC_PERIPHCLK_RTC 0x00020000U 400 #define RCC_PERIPHCLK_RNG 0x00040000U 401 #if defined(SDMMC1) 402 #define RCC_PERIPHCLK_SDMMC1 0x00080000U 403 #endif 404 #if defined(I2C4) 405 #define RCC_PERIPHCLK_I2C4 0x00100000U 406 #endif 407 #if defined(LTDC) 408 #define RCC_PERIPHCLK_LTDC 0x00400000U 409 #endif 410 #if defined(DSI) 411 #define RCC_PERIPHCLK_DSI 0x00800000U 412 #endif 413 #if defined(OCTOSPI1) || defined(OCTOSPI2) 414 #define RCC_PERIPHCLK_OSPI 0x01000000U 415 #endif 416 /** 417 * @} 418 */ 419 420 421 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source 422 * @{ 423 */ 424 #define RCC_USART1CLKSOURCE_PCLK2 0x00000000U 425 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 426 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 427 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) 428 /** 429 * @} 430 */ 431 432 /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source 433 * @{ 434 */ 435 #define RCC_USART2CLKSOURCE_PCLK1 0x00000000U 436 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 437 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 438 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) 439 /** 440 * @} 441 */ 442 443 #if defined(USART3) 444 /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source 445 * @{ 446 */ 447 #define RCC_USART3CLKSOURCE_PCLK1 0x00000000U 448 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0 449 #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1 450 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1) 451 /** 452 * @} 453 */ 454 #endif /* USART3 */ 455 456 #if defined(UART4) 457 /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source 458 * @{ 459 */ 460 #define RCC_UART4CLKSOURCE_PCLK1 0x00000000U 461 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0 462 #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1 463 #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1) 464 /** 465 * @} 466 */ 467 #endif /* UART4 */ 468 469 #if defined(UART5) 470 /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source 471 * @{ 472 */ 473 #define RCC_UART5CLKSOURCE_PCLK1 0x00000000U 474 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0 475 #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1 476 #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1) 477 /** 478 * @} 479 */ 480 #endif /* UART5 */ 481 482 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source 483 * @{ 484 */ 485 #define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U 486 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 487 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 488 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) 489 /** 490 * @} 491 */ 492 493 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source 494 * @{ 495 */ 496 #define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U 497 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 498 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 499 /** 500 * @} 501 */ 502 503 #if defined(I2C2) 504 /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source 505 * @{ 506 */ 507 #define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U 508 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0 509 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1 510 /** 511 * @} 512 */ 513 #endif /* I2C2 */ 514 515 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source 516 * @{ 517 */ 518 #define RCC_I2C3CLKSOURCE_PCLK1 0x00000000U 519 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0 520 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1 521 /** 522 * @} 523 */ 524 525 #if defined(I2C4) 526 /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source 527 * @{ 528 */ 529 #define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U 530 #define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0 531 #define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1 532 /** 533 * @} 534 */ 535 #endif /* I2C4 */ 536 537 #if defined(SAI1) 538 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source 539 * @{ 540 */ 541 #define RCC_SAI1CLKSOURCE_PLLSAI1 0x00000000U 542 #if defined(RCC_PLLSAI2_SUPPORT) 543 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 544 #define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI1SEL_0 545 #else 546 #define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI1SEL_0 547 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 548 #endif /* RCC_PLLSAI2_SUPPORT */ 549 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 550 #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR2_SAI1SEL_1 551 #define RCC_SAI1CLKSOURCE_PIN (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0) 552 #define RCC_SAI1CLKSOURCE_HSI RCC_CCIPR2_SAI1SEL_2 553 #else 554 #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_1 555 #define RCC_SAI1CLKSOURCE_PIN RCC_CCIPR_SAI1SEL 556 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 557 /** 558 * @} 559 */ 560 #endif /* SAI1 */ 561 562 #if defined(SAI2) 563 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source 564 * @{ 565 */ 566 #define RCC_SAI2CLKSOURCE_PLLSAI1 0x00000000U 567 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 568 #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI2SEL_0 569 #define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR2_SAI2SEL_1 570 #define RCC_SAI2CLKSOURCE_PIN (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0) 571 #define RCC_SAI2CLKSOURCE_HSI RCC_CCIPR2_SAI2SEL_2 572 #else 573 #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI2SEL_0 574 #define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR_SAI2SEL_1 575 #define RCC_SAI2CLKSOURCE_PIN RCC_CCIPR_SAI2SEL 576 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 577 /** 578 * @} 579 */ 580 #endif /* SAI2 */ 581 582 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source 583 * @{ 584 */ 585 #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U 586 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 587 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 588 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL 589 /** 590 * @} 591 */ 592 593 /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source 594 * @{ 595 */ 596 #define RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U 597 #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0 598 #define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1 599 #define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL 600 /** 601 * @} 602 */ 603 604 #if defined(SDMMC1) 605 /** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source 606 * @{ 607 */ 608 #if defined(RCC_HSI48_SUPPORT) 609 #define RCC_SDMMC1CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock selected as SDMMC1 clock */ 610 #else 611 #define RCC_SDMMC1CLKSOURCE_NONE 0x00000000U /*!< No clock selected as SDMMC1 clock */ 612 #endif /* RCC_HSI48_SUPPORT */ 613 #define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 "Q" clock selected as SDMMC1 clock */ 614 #define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL "Q" clock selected as SDMMC1 clock */ 615 #define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock selected as SDMMC1 clock */ 616 #if defined(RCC_CCIPR2_SDMMCSEL) 617 #define RCC_SDMMC1CLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /*!< PLL "P" clock selected as SDMMC1 kernel clock */ 618 #endif /* RCC_CCIPR2_SDMMCSEL */ 619 /** 620 * @} 621 */ 622 #endif /* SDMMC1 */ 623 624 /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source 625 * @{ 626 */ 627 #if defined(RCC_HSI48_SUPPORT) 628 #define RCC_RNGCLKSOURCE_HSI48 0x00000000U 629 #else 630 #define RCC_RNGCLKSOURCE_NONE 0x00000000U 631 #endif /* RCC_HSI48_SUPPORT */ 632 #if defined(RCC_PLLSAI1_SUPPORT) 633 #define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 634 #endif /* RCC_PLLSAI1_SUPPORT */ 635 #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 636 #define RCC_RNGCLKSOURCE_MSI RCC_CCIPR_CLK48SEL 637 /** 638 * @} 639 */ 640 641 #if defined(USB_OTG_FS) || defined(USB) 642 /** @defgroup RCCEx_USB_Clock_Source USB Clock Source 643 * @{ 644 */ 645 #if defined(RCC_HSI48_SUPPORT) 646 #define RCC_USBCLKSOURCE_HSI48 0x00000000U 647 #else 648 #define RCC_USBCLKSOURCE_NONE 0x00000000U 649 #endif /* RCC_HSI48_SUPPORT */ 650 #if defined(RCC_PLLSAI1_SUPPORT) 651 #define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 652 #endif /* RCC_PLLSAI1_SUPPORT */ 653 #define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 654 #define RCC_USBCLKSOURCE_MSI RCC_CCIPR_CLK48SEL 655 /** 656 * @} 657 */ 658 #endif /* USB_OTG_FS || USB */ 659 660 /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source 661 * @{ 662 */ 663 #define RCC_ADCCLKSOURCE_NONE 0x00000000U 664 #if defined(RCC_PLLSAI1_SUPPORT) 665 #define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 666 #endif /* RCC_PLLSAI1_SUPPORT */ 667 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 668 #define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 669 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ 670 #if defined(RCC_CCIPR_ADCSEL) 671 #define RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL 672 #else 673 #define RCC_ADCCLKSOURCE_SYSCLK 0x30000000U 674 #endif /* RCC_CCIPR_ADCSEL */ 675 /** 676 * @} 677 */ 678 679 #if defined(SWPMI1) 680 /** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source 681 * @{ 682 */ 683 #define RCC_SWPMI1CLKSOURCE_PCLK1 0x00000000U 684 #define RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL 685 /** 686 * @} 687 */ 688 #endif /* SWPMI1 */ 689 690 #if defined(DFSDM1_Filter0) 691 /** @defgroup RCCEx_DFSDM1_Clock_Source DFSDM1 Clock Source 692 * @{ 693 */ 694 #define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U 695 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 696 #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL 697 #else 698 #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL 699 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 700 /** 701 * @} 702 */ 703 704 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 705 /** @defgroup RCCEx_DFSDM1_Audio_Clock_Source DFSDM1 Audio Clock Source 706 * @{ 707 */ 708 #define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 0x00000000U 709 #define RCC_DFSDM1AUDIOCLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0 710 #define RCC_DFSDM1AUDIOCLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1 711 /** 712 * @} 713 */ 714 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 715 #endif /* DFSDM1_Filter0 */ 716 717 #if defined(LTDC) 718 /** @defgroup RCCEx_LTDC_Clock_Source LTDC Clock Source 719 * @{ 720 */ 721 #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 0x00000000U 722 #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0 723 #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1 724 #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 RCC_CCIPR2_PLLSAI2DIVR 725 /** 726 * @} 727 */ 728 #endif /* LTDC */ 729 730 #if defined(DSI) 731 /** @defgroup RCCEx_DSI_Clock_Source DSI Clock Source 732 * @{ 733 */ 734 #define RCC_DSICLKSOURCE_DSIPHY 0x00000000U 735 #define RCC_DSICLKSOURCE_PLLSAI2 RCC_CCIPR2_DSISEL 736 /** 737 * @} 738 */ 739 #endif /* DSI */ 740 741 #if defined(OCTOSPI1) || defined(OCTOSPI2) 742 /** @defgroup RCCEx_OSPI_Clock_Source OctoSPI Clock Source 743 * @{ 744 */ 745 #define RCC_OSPICLKSOURCE_SYSCLK 0x00000000U 746 #define RCC_OSPICLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 747 #define RCC_OSPICLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 748 /** 749 * @} 750 */ 751 #endif /* OCTOSPI1 || OCTOSPI2 */ 752 753 /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line 754 * @{ 755 */ 756 #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */ 757 /** 758 * @} 759 */ 760 761 #if defined(CRS) 762 763 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status 764 * @{ 765 */ 766 #define RCC_CRS_NONE 0x00000000U 767 #define RCC_CRS_TIMEOUT 0x00000001U 768 #define RCC_CRS_SYNCOK 0x00000002U 769 #define RCC_CRS_SYNCWARN 0x00000004U 770 #define RCC_CRS_SYNCERR 0x00000008U 771 #define RCC_CRS_SYNCMISS 0x00000010U 772 #define RCC_CRS_TRIMOVF 0x00000020U 773 /** 774 * @} 775 */ 776 777 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource 778 * @{ 779 */ 780 #define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ 781 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 782 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ 783 /** 784 * @} 785 */ 786 787 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider 788 * @{ 789 */ 790 #define RCC_CRS_SYNC_DIV1 0x00000000U /*!< Synchro Signal not divided (default) */ 791 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 792 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 793 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 794 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 795 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 796 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 797 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 798 /** 799 * @} 800 */ 801 802 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity 803 * @{ 804 */ 805 #define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ 806 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 807 /** 808 * @} 809 */ 810 811 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault 812 * @{ 813 */ 814 #define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds 815 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ 816 /** 817 * @} 818 */ 819 820 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault 821 * @{ 822 */ 823 #define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ 824 /** 825 * @} 826 */ 827 828 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault 829 * @{ 830 */ 831 #if defined(STM32L412xx) || defined(STM32L422xx) 832 #define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U /*!< The default value is 64, which corresponds to the middle of the trimming interval. 833 The trimming step is specified in the product datasheet. A higher TRIM value 834 corresponds to a higher output frequency */ 835 #else 836 #define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to the middle of the trimming interval. 837 The trimming step is specified in the product datasheet. A higher TRIM value 838 corresponds to a higher output frequency */ 839 #endif 840 /** 841 * @} 842 */ 843 844 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection 845 * @{ 846 */ 847 #define RCC_CRS_FREQERRORDIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ 848 #define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ 849 /** 850 * @} 851 */ 852 853 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources 854 * @{ 855 */ 856 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ 857 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ 858 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ 859 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ 860 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ 861 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ 862 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 863 864 /** 865 * @} 866 */ 867 868 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags 869 * @{ 870 */ 871 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 872 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 873 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ 874 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 875 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 876 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 877 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 878 879 /** 880 * @} 881 */ 882 883 #endif /* CRS */ 884 885 /** 886 * @} 887 */ 888 889 /* Exported macros -----------------------------------------------------------*/ 890 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 891 * @{ 892 */ 893 894 #if defined(RCC_PLLSAI1_SUPPORT) 895 896 /** 897 * @brief Macro to configure the PLLSAI1 clock multiplication and division factors. 898 * 899 * @note This function must be used only when the PLLSAI1 is disabled. 900 * @note PLLSAI1 clock source is common with the main PLL (configured through 901 * __HAL_RCC_PLL_CONFIG() macro) 902 * 903 @if STM32L4S9xx 904 * @param __PLLSAI1M__ specifies the division factor of PLLSAI1 input clock. 905 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 906 * 907 @endif 908 * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock. 909 * This parameter must be a number between 8 and 86. 910 * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO 911 * output frequency is between 64 and 344 MHz. 912 * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N 913 * 914 * @param __PLLSAI1P__ specifies the division factor for SAI clock. 915 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx 916 * else (2 to 31). 917 * SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P 918 * 919 * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock. 920 * This parameter must be in the range (2, 4, 6 or 8). 921 * USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q 922 * 923 * @param __PLLSAI1R__ specifies the division factor for SAR ADC clock. 924 * This parameter must be in the range (2, 4, 6 or 8). 925 * ADC clock frequency = f(PLLSAI1) / PLLSAI1R 926 * 927 * @retval None 928 */ 929 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 930 931 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 932 933 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ 934 WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ 935 ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ 936 ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ 937 ((__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) | \ 938 (((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)) 939 940 #else 941 942 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ 943 WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ 944 (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | \ 945 ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ 946 ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ 947 (((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)) 948 949 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 950 951 #else 952 953 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 954 955 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ 956 WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ 957 ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ 958 ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ 959 ((__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)) 960 961 #else 962 963 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ 964 WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ 965 (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | \ 966 ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ 967 ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)) 968 969 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 970 971 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 972 973 /** 974 * @brief Macro to configure the PLLSAI1 clock multiplication factor N. 975 * 976 * @note This function must be used only when the PLLSAI1 is disabled. 977 * @note PLLSAI1 clock source is common with the main PLL (configured through 978 * __HAL_RCC_PLL_CONFIG() macro) 979 * 980 * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock. 981 * This parameter must be a number between 8 and 86. 982 * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO 983 * output frequency is between 64 and 344 MHz. 984 * Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N 985 * 986 * @retval None 987 */ 988 #define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \ 989 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) 990 991 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 992 993 /** @brief Macro to configure the PLLSAI1 input clock division factor M. 994 * 995 * @note This function must be used only when the PLLSAI1 is disabled. 996 * @note PLLSAI1 clock source is common with the main PLL (configured through 997 * __HAL_RCC_PLL_CONFIG() macro) 998 * 999 * @param __PLLSAI1M__ specifies the division factor for PLLSAI1 clock. 1000 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 1001 * 1002 * @retval None 1003 */ 1004 1005 #define __HAL_RCC_PLLSAI1_DIVM_CONFIG(__PLLSAI1M__) \ 1006 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M, ((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) 1007 1008 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 1009 1010 /** @brief Macro to configure the PLLSAI1 clock division factor P. 1011 * 1012 * @note This function must be used only when the PLLSAI1 is disabled. 1013 * @note PLLSAI1 clock source is common with the main PLL (configured through 1014 * __HAL_RCC_PLL_CONFIG() macro) 1015 * 1016 * @param __PLLSAI1P__ specifies the division factor for SAI clock. 1017 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx 1018 * else (2 to 31). 1019 * Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P 1020 * 1021 * @retval None 1022 */ 1023 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 1024 1025 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \ 1026 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) 1027 1028 #else 1029 1030 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \ 1031 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) 1032 1033 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 1034 1035 /** @brief Macro to configure the PLLSAI1 clock division factor Q. 1036 * 1037 * @note This function must be used only when the PLLSAI1 is disabled. 1038 * @note PLLSAI1 clock source is common with the main PLL (configured through 1039 * __HAL_RCC_PLL_CONFIG() macro) 1040 * 1041 * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock. 1042 * This parameter must be in the range (2, 4, 6 or 8). 1043 * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q 1044 * 1045 * @retval None 1046 */ 1047 #define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \ 1048 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) 1049 1050 /** @brief Macro to configure the PLLSAI1 clock division factor R. 1051 * 1052 * @note This function must be used only when the PLLSAI1 is disabled. 1053 * @note PLLSAI1 clock source is common with the main PLL (configured through 1054 * __HAL_RCC_PLL_CONFIG() macro) 1055 * 1056 * @param __PLLSAI1R__ specifies the division factor for ADC clock. 1057 * This parameter must be in the range (2, 4, 6 or 8) 1058 * Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R 1059 * 1060 * @retval None 1061 */ 1062 #define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \ 1063 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) 1064 1065 /** 1066 * @brief Macros to enable or disable the PLLSAI1. 1067 * @note The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes. 1068 * @retval None 1069 */ 1070 1071 #define __HAL_RCC_PLLSAI1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON) 1072 1073 #define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON) 1074 1075 /** 1076 * @brief Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1). 1077 * @note Enabling and disabling those clocks can be done without the need to stop the PLL. 1078 * This is mainly used to save Power. 1079 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. 1080 * This parameter can be one or a combination of the following values: 1081 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve 1082 * high-quality audio performance on SAI interface in case. 1083 * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz), 1084 * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz). 1085 * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral. 1086 * @retval None 1087 */ 1088 1089 #define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) 1090 1091 #define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) 1092 1093 /** 1094 * @brief Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1). 1095 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. 1096 * This parameter can be one of the following values: 1097 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve 1098 * high-quality audio performance on SAI interface in case. 1099 * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz), 1100 * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz). 1101 * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral. 1102 * @retval SET / RESET 1103 */ 1104 #define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) 1105 1106 #endif /* RCC_PLLSAI1_SUPPORT */ 1107 1108 #if defined(RCC_PLLSAI2_SUPPORT) 1109 1110 /** 1111 * @brief Macro to configure the PLLSAI2 clock multiplication and division factors. 1112 * 1113 * @note This function must be used only when the PLLSAI2 is disabled. 1114 * @note PLLSAI2 clock source is common with the main PLL (configured through 1115 * __HAL_RCC_PLL_CONFIG() macro) 1116 * 1117 @if STM32L4S9xx 1118 * @param __PLLSAI2M__ specifies the division factor of PLLSAI2 input clock. 1119 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 1120 * 1121 @endif 1122 * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock. 1123 * This parameter must be a number between 8 and 86. 1124 * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO 1125 * output frequency is between 64 and 344 MHz. 1126 * 1127 * @param __PLLSAI2P__ specifies the division factor for SAI clock. 1128 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx 1129 * else (2 to 31). 1130 * SAI2 clock frequency = f(PLLSAI2) / PLLSAI2P 1131 * 1132 @if STM32L4S9xx 1133 * @param __PLLSAI2Q__ specifies the division factor for DSI clock. 1134 * This parameter must be in the range (2, 4, 6 or 8). 1135 * DSI clock frequency = f(PLLSAI2) / PLLSAI2Q 1136 * 1137 @endif 1138 * @param __PLLSAI2R__ specifies the division factor for SAR ADC clock. 1139 * This parameter must be in the range (2, 4, 6 or 8). 1140 * 1141 * @retval None 1142 */ 1143 1144 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 1145 1146 # if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) 1147 1148 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \ 1149 WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ 1150 ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \ 1151 ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ 1152 ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) | \ 1153 (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)) 1154 1155 # elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 1156 1157 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ 1158 WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ 1159 ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ 1160 ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) | \ 1161 (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)) 1162 1163 # else 1164 1165 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ 1166 WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ 1167 (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | \ 1168 ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ 1169 (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)) 1170 1171 # endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ 1172 1173 #else 1174 1175 # if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) 1176 1177 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \ 1178 WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ 1179 ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \ 1180 ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ 1181 ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) 1182 1183 # elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 1184 1185 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ 1186 WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ 1187 ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ 1188 ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) 1189 1190 # else 1191 1192 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ 1193 WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ 1194 (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | \ 1195 ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)) 1196 1197 # endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ 1198 1199 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ 1200 1201 1202 /** 1203 * @brief Macro to configure the PLLSAI2 clock multiplication factor N. 1204 * 1205 * @note This function must be used only when the PLLSAI2 is disabled. 1206 * @note PLLSAI2 clock source is common with the main PLL (configured through 1207 * __HAL_RCC_PLL_CONFIG() macro) 1208 * 1209 * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock. 1210 * This parameter must be a number between 8 and 86. 1211 * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO 1212 * output frequency is between 64 and 344 MHz. 1213 * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N 1214 * 1215 * @retval None 1216 */ 1217 #define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \ 1218 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) 1219 1220 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 1221 1222 /** @brief Macro to configure the PLLSAI2 input clock division factor M. 1223 * 1224 * @note This function must be used only when the PLLSAI2 is disabled. 1225 * @note PLLSAI2 clock source is common with the main PLL (configured through 1226 * __HAL_RCC_PLL_CONFIG() macro) 1227 * 1228 * @param __PLLSAI2M__ specifies the division factor for PLLSAI2 clock. 1229 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 1230 * 1231 * @retval None 1232 */ 1233 1234 #define __HAL_RCC_PLLSAI2_DIVM_CONFIG(__PLLSAI2M__) \ 1235 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M, ((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) 1236 1237 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ 1238 1239 /** @brief Macro to configure the PLLSAI2 clock division factor P. 1240 * 1241 * @note This function must be used only when the PLLSAI2 is disabled. 1242 * @note PLLSAI2 clock source is common with the main PLL (configured through 1243 * __HAL_RCC_PLL_CONFIG() macro) 1244 * 1245 * @param __PLLSAI2P__ specifies the division factor. 1246 * This parameter must be a number in the range (7 or 17). 1247 * Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__ 1248 * 1249 * @retval None 1250 */ 1251 #define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \ 1252 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) 1253 1254 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 1255 1256 /** @brief Macro to configure the PLLSAI2 clock division factor Q. 1257 * 1258 * @note This function must be used only when the PLLSAI2 is disabled. 1259 * @note PLLSAI2 clock source is common with the main PLL (configured through 1260 * __HAL_RCC_PLL_CONFIG() macro) 1261 * 1262 * @param __PLLSAI2Q__ specifies the division factor for USB/RNG/SDMMC1 clock. 1263 * This parameter must be in the range (2, 4, 6 or 8). 1264 * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI2) / PLLSAI2Q 1265 * 1266 * @retval None 1267 */ 1268 #define __HAL_RCC_PLLSAI2_DIVQ_CONFIG(__PLLSAI2Q__) \ 1269 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q, (((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) 1270 1271 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ 1272 1273 /** @brief Macro to configure the PLLSAI2 clock division factor R. 1274 * 1275 * @note This function must be used only when the PLLSAI2 is disabled. 1276 * @note PLLSAI2 clock source is common with the main PLL (configured through 1277 * __HAL_RCC_PLL_CONFIG() macro) 1278 * 1279 * @param __PLLSAI2R__ specifies the division factor. 1280 * This parameter must be in the range (2, 4, 6 or 8). 1281 * Use to set ADC clock frequency = f(PLLSAI2) / __PLLSAI2R__ 1282 * 1283 * @retval None 1284 */ 1285 #define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \ 1286 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) 1287 1288 /** 1289 * @brief Macros to enable or disable the PLLSAI2. 1290 * @note The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes. 1291 * @retval None 1292 */ 1293 1294 #define __HAL_RCC_PLLSAI2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON) 1295 1296 #define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON) 1297 1298 /** 1299 * @brief Macros to enable or disable each clock output (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK). 1300 * @note Enabling and disabling those clocks can be done without the need to stop the PLL. 1301 * This is mainly used to save Power. 1302 * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output. 1303 * This parameter can be one or a combination of the following values: 1304 @if STM32L486xx 1305 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 1306 * high-quality audio performance on SAI interface in case. 1307 * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. 1308 @endif 1309 @if STM32L4A6xx 1310 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 1311 * high-quality audio performance on SAI interface in case. 1312 * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. 1313 @endif 1314 @if STM32L4S9xx 1315 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 1316 * high-quality audio performance on SAI interface in case. 1317 * @arg @ref RCC_PLLSAI2_DSICLK Clock used to clock DSI peripheral. 1318 @endif 1319 * @retval None 1320 */ 1321 1322 #define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) 1323 1324 #define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) 1325 1326 /** 1327 * @brief Macro to get clock output enable status (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK). 1328 * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output. 1329 * This parameter can be one of the following values: 1330 @if STM32L486xx 1331 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 1332 * high-quality audio performance on SAI interface in case. 1333 * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. 1334 @endif 1335 @if STM32L4A6xx 1336 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 1337 * high-quality audio performance on SAI interface in case. 1338 * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. 1339 @endif 1340 @if STM32L4S9xx 1341 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 1342 * high-quality audio performance on SAI interface in case. 1343 * @arg @ref RCC_PLLSAI2_DSICLK Clock used to clock DSI peripheral. 1344 @endif 1345 * @retval SET / RESET 1346 */ 1347 #define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) 1348 1349 #endif /* RCC_PLLSAI2_SUPPORT */ 1350 1351 #if defined(SAI1) 1352 1353 /** 1354 * @brief Macro to configure the SAI1 clock source. 1355 * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived 1356 * from the PLLSAI1, system PLL or external clock (through a dedicated pin). 1357 * This parameter can be one of the following values: 1358 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK) 1359 @if STM32L486xx 1360 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2 1361 @endif 1362 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK) 1363 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) 1364 @if STM32L4S9xx 1365 * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16 1366 @endif 1367 * 1368 @if STM32L443xx 1369 * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2. 1370 @endif 1371 * 1372 * @retval None 1373 */ 1374 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 1375 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ 1376 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (__SAI1_CLKSOURCE__)) 1377 #else 1378 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ 1379 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__)) 1380 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 1381 1382 /** @brief Macro to get the SAI1 clock source. 1383 * @retval The clock source can be one of the following values: 1384 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK) 1385 @if STM32L486xx 1386 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2 1387 @endif 1388 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK) 1389 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) 1390 * 1391 * @note Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1 1392 * clock source when PLLs are disabled for devices without PLLSAI2. 1393 * 1394 */ 1395 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 1396 #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL)) 1397 #else 1398 #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)) 1399 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 1400 1401 #endif /* SAI1 */ 1402 1403 #if defined(SAI2) 1404 1405 /** 1406 * @brief Macro to configure the SAI2 clock source. 1407 * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived 1408 * from the PLLSAI2, system PLL or external clock (through a dedicated pin). 1409 * This parameter can be one of the following values: 1410 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK) 1411 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK) 1412 * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK) 1413 * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) 1414 @if STM32L4S9xx 1415 * @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16 1416 @endif 1417 * 1418 * @retval None 1419 */ 1420 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 1421 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ 1422 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (__SAI2_CLKSOURCE__)) 1423 #else 1424 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ 1425 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (__SAI2_CLKSOURCE__)) 1426 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 1427 1428 /** @brief Macro to get the SAI2 clock source. 1429 * @retval The clock source can be one of the following values: 1430 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK) 1431 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK) 1432 * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK) 1433 * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) 1434 */ 1435 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 1436 #define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL)) 1437 #else 1438 #define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL)) 1439 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 1440 1441 #endif /* SAI2 */ 1442 1443 /** @brief Macro to configure the I2C1 clock (I2C1CLK). 1444 * 1445 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. 1446 * This parameter can be one of the following values: 1447 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 1448 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 1449 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 1450 * @retval None 1451 */ 1452 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ 1453 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__)) 1454 1455 /** @brief Macro to get the I2C1 clock source. 1456 * @retval The clock source can be one of the following values: 1457 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 1458 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 1459 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 1460 */ 1461 #define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)) 1462 1463 #if defined(I2C2) 1464 1465 /** @brief Macro to configure the I2C2 clock (I2C2CLK). 1466 * 1467 * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. 1468 * This parameter can be one of the following values: 1469 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 1470 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 1471 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 1472 * @retval None 1473 */ 1474 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ 1475 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__)) 1476 1477 /** @brief Macro to get the I2C2 clock source. 1478 * @retval The clock source can be one of the following values: 1479 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 1480 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 1481 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 1482 */ 1483 #define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)) 1484 1485 #endif /* I2C2 */ 1486 1487 /** @brief Macro to configure the I2C3 clock (I2C3CLK). 1488 * 1489 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. 1490 * This parameter can be one of the following values: 1491 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 1492 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 1493 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 1494 * @retval None 1495 */ 1496 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ 1497 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__)) 1498 1499 /** @brief Macro to get the I2C3 clock source. 1500 * @retval The clock source can be one of the following values: 1501 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 1502 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 1503 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 1504 */ 1505 #define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)) 1506 1507 #if defined(I2C4) 1508 1509 /** @brief Macro to configure the I2C4 clock (I2C4CLK). 1510 * 1511 * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. 1512 * This parameter can be one of the following values: 1513 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock 1514 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 1515 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock 1516 * @retval None 1517 */ 1518 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ 1519 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__)) 1520 1521 /** @brief Macro to get the I2C4 clock source. 1522 * @retval The clock source can be one of the following values: 1523 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock 1524 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 1525 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock 1526 */ 1527 #define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL)) 1528 1529 #endif /* I2C4 */ 1530 1531 1532 /** @brief Macro to configure the USART1 clock (USART1CLK). 1533 * 1534 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. 1535 * This parameter can be one of the following values: 1536 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1537 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 1538 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 1539 * @arg @ref RCC_USART1CLKSOURCE_LSE SE selected as USART1 clock 1540 * @retval None 1541 */ 1542 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ 1543 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__)) 1544 1545 /** @brief Macro to get the USART1 clock source. 1546 * @retval The clock source can be one of the following values: 1547 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1548 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 1549 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 1550 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 1551 */ 1552 #define __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)) 1553 1554 /** @brief Macro to configure the USART2 clock (USART2CLK). 1555 * 1556 * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. 1557 * This parameter can be one of the following values: 1558 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 1559 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 1560 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 1561 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 1562 * @retval None 1563 */ 1564 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ 1565 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__)) 1566 1567 /** @brief Macro to get the USART2 clock source. 1568 * @retval The clock source can be one of the following values: 1569 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 1570 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 1571 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 1572 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 1573 */ 1574 #define __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)) 1575 1576 #if defined(USART3) 1577 1578 /** @brief Macro to configure the USART3 clock (USART3CLK). 1579 * 1580 * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. 1581 * This parameter can be one of the following values: 1582 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 1583 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 1584 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 1585 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 1586 * @retval None 1587 */ 1588 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ 1589 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__)) 1590 1591 /** @brief Macro to get the USART3 clock source. 1592 * @retval The clock source can be one of the following values: 1593 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 1594 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 1595 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 1596 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 1597 */ 1598 #define __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)) 1599 1600 #endif /* USART3 */ 1601 1602 #if defined(UART4) 1603 1604 /** @brief Macro to configure the UART4 clock (UART4CLK). 1605 * 1606 * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. 1607 * This parameter can be one of the following values: 1608 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 1609 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 1610 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock 1611 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 1612 * @retval None 1613 */ 1614 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ 1615 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__)) 1616 1617 /** @brief Macro to get the UART4 clock source. 1618 * @retval The clock source can be one of the following values: 1619 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 1620 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 1621 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock 1622 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 1623 */ 1624 #define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)) 1625 1626 #endif /* UART4 */ 1627 1628 #if defined(UART5) 1629 1630 /** @brief Macro to configure the UART5 clock (UART5CLK). 1631 * 1632 * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. 1633 * This parameter can be one of the following values: 1634 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 1635 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 1636 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock 1637 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 1638 * @retval None 1639 */ 1640 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ 1641 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__)) 1642 1643 /** @brief Macro to get the UART5 clock source. 1644 * @retval The clock source can be one of the following values: 1645 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 1646 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 1647 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock 1648 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 1649 */ 1650 #define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)) 1651 1652 #endif /* UART5 */ 1653 1654 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). 1655 * 1656 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. 1657 * This parameter can be one of the following values: 1658 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 1659 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 1660 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 1661 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 1662 * @retval None 1663 */ 1664 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ 1665 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__)) 1666 1667 /** @brief Macro to get the LPUART1 clock source. 1668 * @retval The clock source can be one of the following values: 1669 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 1670 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 1671 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 1672 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 1673 */ 1674 #define __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)) 1675 1676 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). 1677 * 1678 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. 1679 * This parameter can be one of the following values: 1680 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock 1681 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock 1682 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock 1683 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 1684 * @retval None 1685 */ 1686 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ 1687 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__)) 1688 1689 /** @brief Macro to get the LPTIM1 clock source. 1690 * @retval The clock source can be one of the following values: 1691 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 1692 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock 1693 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock 1694 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock 1695 */ 1696 #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)) 1697 1698 /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). 1699 * 1700 * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. 1701 * This parameter can be one of the following values: 1702 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock 1703 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock 1704 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI LSI selected as LPTIM2 clock 1705 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 1706 * @retval None 1707 */ 1708 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ 1709 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (__LPTIM2_CLKSOURCE__)) 1710 1711 /** @brief Macro to get the LPTIM2 clock source. 1712 * @retval The clock source can be one of the following values: 1713 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 1714 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPUART1 clock 1715 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPUART1 clock 1716 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPUART1 clock 1717 */ 1718 #define __HAL_RCC_GET_LPTIM2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)) 1719 1720 #if defined(SDMMC1) 1721 1722 /** @brief Macro to configure the SDMMC1 clock. 1723 * 1724 @if STM32L486xx 1725 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. 1726 @endif 1727 * 1728 @if STM32L443xx 1729 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. 1730 @endif 1731 * 1732 * @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source. 1733 * This parameter can be one of the following values: 1734 @if STM32L486xx 1735 * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48 1736 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock 1737 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock 1738 @endif 1739 @if STM32L443xx 1740 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 1741 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock 1742 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock 1743 @endif 1744 @if STM32L4S9xx 1745 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 1746 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock 1747 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock 1748 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" Clock selected as SDMMC1 clock 1749 @endif 1750 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" Clock selected as SDMMC1 clock 1751 * @retval None 1752 */ 1753 #if defined(RCC_CCIPR2_SDMMCSEL) 1754 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ 1755 do \ 1756 { \ 1757 if((__SDMMC1_CLKSOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) \ 1758 { \ 1759 SET_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ 1760 } \ 1761 else \ 1762 { \ 1763 CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ 1764 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__)); \ 1765 } \ 1766 } while(0) 1767 #else 1768 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ 1769 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__)) 1770 #endif /* RCC_CCIPR2_SDMMCSEL */ 1771 1772 /** @brief Macro to get the SDMMC1 clock. 1773 * @retval The clock source can be one of the following values: 1774 @if STM32L486xx 1775 * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48 1776 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock 1777 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock 1778 @endif 1779 @if STM32L443xx 1780 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 1781 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock 1782 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock 1783 @endif 1784 @if STM32L4S9xx 1785 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 1786 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock 1787 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock 1788 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" clock (PLLSAI3CLK) selected as SDMMC1 kernel clock 1789 @endif 1790 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock 1791 */ 1792 #if defined(RCC_CCIPR2_SDMMCSEL) 1793 #define __HAL_RCC_GET_SDMMC1_SOURCE() \ 1794 ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != 0U) ? RCC_SDMMC1CLKSOURCE_PLLP : (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) 1795 #else 1796 #define __HAL_RCC_GET_SDMMC1_SOURCE() \ 1797 (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) 1798 #endif /* RCC_CCIPR2_SDMMCSEL */ 1799 1800 #endif /* SDMMC1 */ 1801 1802 /** @brief Macro to configure the RNG clock. 1803 * 1804 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. 1805 * 1806 * @param __RNG_CLKSOURCE__ specifies the RNG clock source. 1807 * This parameter can be one of the following values: 1808 @if STM32L486xx 1809 * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48 1810 @endif 1811 @if STM32L443xx 1812 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48 1813 @endif 1814 * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock 1815 * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as RNG clock 1816 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock 1817 * @retval None 1818 */ 1819 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ 1820 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__)) 1821 1822 /** @brief Macro to get the RNG clock. 1823 * @retval The clock source can be one of the following values: 1824 @if STM32L486xx 1825 * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48 1826 @endif 1827 @if STM32L443xx 1828 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48 1829 @endif 1830 * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock 1831 * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock 1832 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as RNG clock 1833 */ 1834 #define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) 1835 1836 #if defined(USB_OTG_FS) || defined(USB) 1837 1838 /** @brief Macro to configure the USB clock (USBCLK). 1839 * 1840 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. 1841 * 1842 * @param __USB_CLKSOURCE__ specifies the USB clock source. 1843 * This parameter can be one of the following values: 1844 @if STM32L486xx 1845 * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48 1846 @endif 1847 @if STM32L443xx 1848 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 1849 @endif 1850 * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock 1851 * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock 1852 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock 1853 * @retval None 1854 */ 1855 #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ 1856 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__)) 1857 1858 /** @brief Macro to get the USB clock source. 1859 * @retval The clock source can be one of the following values: 1860 @if STM32L486xx 1861 * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48 1862 @endif 1863 @if STM32L443xx 1864 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 1865 @endif 1866 * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock 1867 * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock 1868 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock 1869 */ 1870 #define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) 1871 1872 #endif /* USB_OTG_FS || USB */ 1873 1874 #if defined(RCC_CCIPR_ADCSEL) 1875 1876 /** @brief Macro to configure the ADC interface clock. 1877 * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source. 1878 * This parameter can be one of the following values: 1879 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock 1880 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock 1881 @if STM32L486xx 1882 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices 1883 @endif 1884 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock 1885 * @retval None 1886 */ 1887 #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ 1888 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (__ADC_CLKSOURCE__)) 1889 1890 /** @brief Macro to get the ADC clock source. 1891 * @retval The clock source can be one of the following values: 1892 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock 1893 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock 1894 @if STM32L486xx 1895 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices 1896 @endif 1897 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock 1898 */ 1899 #define __HAL_RCC_GET_ADC_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)) 1900 #else 1901 1902 /** @brief Macro to get the ADC clock source. 1903 * @retval The clock source can be one of the following values: 1904 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock 1905 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock 1906 */ 1907 #define __HAL_RCC_GET_ADC_SOURCE() ((__HAL_RCC_ADC_IS_CLK_ENABLED() != 0U) ? RCC_ADCCLKSOURCE_SYSCLK : RCC_ADCCLKSOURCE_NONE) 1908 1909 #endif /* RCC_CCIPR_ADCSEL */ 1910 1911 #if defined(SWPMI1) 1912 1913 /** @brief Macro to configure the SWPMI1 clock. 1914 * @param __SWPMI1_CLKSOURCE__ specifies the SWPMI1 clock source. 1915 * This parameter can be one of the following values: 1916 * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock 1917 * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock 1918 * @retval None 1919 */ 1920 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \ 1921 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (__SWPMI1_CLKSOURCE__)) 1922 1923 /** @brief Macro to get the SWPMI1 clock source. 1924 * @retval The clock source can be one of the following values: 1925 * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock 1926 * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock 1927 */ 1928 #define __HAL_RCC_GET_SWPMI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL)) 1929 1930 #endif /* SWPMI1 */ 1931 1932 #if defined(DFSDM1_Filter0) 1933 /** @brief Macro to configure the DFSDM1 clock. 1934 * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. 1935 * This parameter can be one of the following values: 1936 * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock 1937 * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock 1938 * @retval None 1939 */ 1940 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 1941 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ 1942 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, (__DFSDM1_CLKSOURCE__)) 1943 #else 1944 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ 1945 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (__DFSDM1_CLKSOURCE__)) 1946 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 1947 1948 /** @brief Macro to get the DFSDM1 clock source. 1949 * @retval The clock source can be one of the following values: 1950 * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock 1951 * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock 1952 */ 1953 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 1954 #define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL)) 1955 #else 1956 #define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL)) 1957 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 1958 1959 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 1960 1961 /** @brief Macro to configure the DFSDM1 audio clock. 1962 * @param __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 audio clock source. 1963 * This parameter can be one of the following values: 1964 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1 SAI1 clock selected as DFSDM1 audio clock 1965 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock 1966 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock 1967 * @retval None 1968 */ 1969 #define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \ 1970 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, (__DFSDM1AUDIO_CLKSOURCE__)) 1971 1972 /** @brief Macro to get the DFSDM1 audio clock source. 1973 * @retval The clock source can be one of the following values: 1974 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1 SAI1 clock selected as DFSDM1 audio clock 1975 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock 1976 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock 1977 */ 1978 #define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL)) 1979 1980 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 1981 1982 #endif /* DFSDM1_Filter0 */ 1983 1984 #if defined(LTDC) 1985 1986 /** @brief Macro to configure the LTDC clock. 1987 * @param __LTDC_CLKSOURCE__ specifies the DSI clock source. 1988 * This parameter can be one of the following values: 1989 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 PLLSAI2 divider R divided by 2 clock selected as LTDC clock 1990 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 PLLSAI2 divider R divided by 4 clock selected as LTDC clock 1991 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 PLLSAI2 divider R divided by 8 clock selected as LTDC clock 1992 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 PLLSAI2 divider R divided by 16 clock selected as LTDC clock 1993 * @retval None 1994 */ 1995 #define __HAL_RCC_LTDC_CONFIG(__LTDC_CLKSOURCE__) \ 1996 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, (__LTDC_CLKSOURCE__)) 1997 1998 /** @brief Macro to get the LTDC clock source. 1999 * @retval The clock source can be one of the following values: 2000 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 PLLSAI2 divider R divided by 2 clock selected as LTDC clock 2001 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 PLLSAI2 divider R divided by 4 clock selected as LTDC clock 2002 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 PLLSAI2 divider R divided by 8 clock selected as LTDC clock 2003 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 PLLSAI2 divider R divided by 16 clock selected as LTDC clock 2004 */ 2005 #define __HAL_RCC_GET_LTDC_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR)) 2006 2007 #endif /* LTDC */ 2008 2009 #if defined(DSI) 2010 2011 /** @brief Macro to configure the DSI clock. 2012 * @param __DSI_CLKSOURCE__ specifies the DSI clock source. 2013 * This parameter can be one of the following values: 2014 * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock 2015 * @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock 2016 * @retval None 2017 */ 2018 #define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) \ 2019 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, (__DSI_CLKSOURCE__)) 2020 2021 /** @brief Macro to get the DSI clock source. 2022 * @retval The clock source can be one of the following values: 2023 * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock 2024 * @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock 2025 */ 2026 #define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DSISEL)) 2027 2028 #endif /* DSI */ 2029 2030 #if defined(OCTOSPI1) || defined(OCTOSPI2) 2031 2032 /** @brief Macro to configure the OctoSPI clock. 2033 * @param __OSPI_CLKSOURCE__ specifies the OctoSPI clock source. 2034 * This parameter can be one of the following values: 2035 * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock 2036 * @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock 2037 * @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock 2038 * @retval None 2039 */ 2040 #define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \ 2041 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, (__OSPI_CLKSOURCE__)) 2042 2043 /** @brief Macro to get the OctoSPI clock source. 2044 * @retval The clock source can be one of the following values: 2045 * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock 2046 * @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock 2047 * @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock 2048 */ 2049 #define __HAL_RCC_GET_OSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OSPISEL)) 2050 2051 #endif /* OCTOSPI1 || OCTOSPI2 */ 2052 2053 /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management 2054 * @brief macros to manage the specified RCC Flags and interrupts. 2055 * @{ 2056 */ 2057 #if defined(RCC_PLLSAI1_SUPPORT) 2058 2059 /** @brief Enable PLLSAI1RDY interrupt. 2060 * @retval None 2061 */ 2062 #define __HAL_RCC_PLLSAI1_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) 2063 2064 /** @brief Disable PLLSAI1RDY interrupt. 2065 * @retval None 2066 */ 2067 #define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) 2068 2069 /** @brief Clear the PLLSAI1RDY interrupt pending bit. 2070 * @retval None 2071 */ 2072 #define __HAL_RCC_PLLSAI1_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC) 2073 2074 /** @brief Check whether PLLSAI1RDY interrupt has occurred or not. 2075 * @retval TRUE or FALSE. 2076 */ 2077 #define __HAL_RCC_PLLSAI1_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF) 2078 2079 /** @brief Check whether the PLLSAI1RDY flag is set or not. 2080 * @retval TRUE or FALSE. 2081 */ 2082 #define __HAL_RCC_PLLSAI1_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)) 2083 2084 #endif /* RCC_PLLSAI1_SUPPORT */ 2085 2086 #if defined(RCC_PLLSAI2_SUPPORT) 2087 2088 /** @brief Enable PLLSAI2RDY interrupt. 2089 * @retval None 2090 */ 2091 #define __HAL_RCC_PLLSAI2_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) 2092 2093 /** @brief Disable PLLSAI2RDY interrupt. 2094 * @retval None 2095 */ 2096 #define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) 2097 2098 /** @brief Clear the PLLSAI2RDY interrupt pending bit. 2099 * @retval None 2100 */ 2101 #define __HAL_RCC_PLLSAI2_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC) 2102 2103 /** @brief Check whether the PLLSAI2RDY interrupt has occurred or not. 2104 * @retval TRUE or FALSE. 2105 */ 2106 #define __HAL_RCC_PLLSAI2_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF) 2107 2108 /** @brief Check whether the PLLSAI2RDY flag is set or not. 2109 * @retval TRUE or FALSE. 2110 */ 2111 #define __HAL_RCC_PLLSAI2_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY)) 2112 2113 #endif /* RCC_PLLSAI2_SUPPORT */ 2114 2115 2116 /** 2117 * @brief Enable the RCC LSE CSS Extended Interrupt Line. 2118 * @retval None 2119 */ 2120 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) 2121 2122 /** 2123 * @brief Disable the RCC LSE CSS Extended Interrupt Line. 2124 * @retval None 2125 */ 2126 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) 2127 2128 /** 2129 * @brief Enable the RCC LSE CSS Event Line. 2130 * @retval None. 2131 */ 2132 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) 2133 2134 /** 2135 * @brief Disable the RCC LSE CSS Event Line. 2136 * @retval None. 2137 */ 2138 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) 2139 2140 2141 /** 2142 * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger. 2143 * @retval None. 2144 */ 2145 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) 2146 2147 2148 /** 2149 * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. 2150 * @retval None. 2151 */ 2152 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) 2153 2154 2155 /** 2156 * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger. 2157 * @retval None. 2158 */ 2159 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) 2160 2161 /** 2162 * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. 2163 * @retval None. 2164 */ 2165 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) 2166 2167 /** 2168 * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 2169 * @retval None. 2170 */ 2171 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ 2172 do { \ 2173 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ 2174 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ 2175 } while(0) 2176 2177 /** 2178 * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 2179 * @retval None. 2180 */ 2181 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ 2182 do { \ 2183 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ 2184 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ 2185 } while(0) 2186 2187 /** 2188 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. 2189 * @retval EXTI RCC LSE CSS Line Status. 2190 */ 2191 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) 2192 2193 /** 2194 * @brief Clear the RCC LSE CSS EXTI flag. 2195 * @retval None. 2196 */ 2197 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) 2198 2199 /** 2200 * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line. 2201 * @retval None. 2202 */ 2203 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) 2204 2205 2206 #if defined(CRS) 2207 2208 /** 2209 * @brief Enable the specified CRS interrupts. 2210 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 2211 * This parameter can be any combination of the following values: 2212 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 2213 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 2214 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 2215 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 2216 * @retval None 2217 */ 2218 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 2219 2220 /** 2221 * @brief Disable the specified CRS interrupts. 2222 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 2223 * This parameter can be any combination of the following values: 2224 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 2225 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 2226 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 2227 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 2228 * @retval None 2229 */ 2230 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) 2231 2232 /** @brief Check whether the CRS interrupt has occurred or not. 2233 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 2234 * This parameter can be one of the following values: 2235 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 2236 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 2237 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 2238 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 2239 * @retval The new state of __INTERRUPT__ (SET or RESET). 2240 */ 2241 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) 2242 2243 /** @brief Clear the CRS interrupt pending bits 2244 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 2245 * This parameter can be any combination of the following values: 2246 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 2247 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 2248 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 2249 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 2250 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt 2251 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt 2252 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt 2253 */ 2254 /* CRS IT Error Mask */ 2255 #define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS) 2256 2257 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 2258 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ 2259 { \ 2260 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 2261 } \ 2262 else \ 2263 { \ 2264 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 2265 } \ 2266 } while(0) 2267 2268 /** 2269 * @brief Check whether the specified CRS flag is set or not. 2270 * @param __FLAG__ specifies the flag to check. 2271 * This parameter can be one of the following values: 2272 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 2273 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 2274 * @arg @ref RCC_CRS_FLAG_ERR Error 2275 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 2276 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 2277 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 2278 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 2279 * @retval The new state of _FLAG_ (TRUE or FALSE). 2280 */ 2281 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) 2282 2283 /** 2284 * @brief Clear the CRS specified FLAG. 2285 * @param __FLAG__ specifies the flag to clear. 2286 * This parameter can be one of the following values: 2287 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 2288 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 2289 * @arg @ref RCC_CRS_FLAG_ERR Error 2290 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 2291 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 2292 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 2293 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 2294 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR 2295 * @retval None 2296 */ 2297 2298 /* CRS Flag Error Mask */ 2299 #define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS) 2300 2301 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 2302 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ 2303 { \ 2304 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 2305 } \ 2306 else \ 2307 { \ 2308 WRITE_REG(CRS->ICR, (__FLAG__)); \ 2309 } \ 2310 } while(0) 2311 2312 #endif /* CRS */ 2313 2314 /** 2315 * @} 2316 */ 2317 2318 #if defined(CRS) 2319 2320 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features 2321 * @{ 2322 */ 2323 /** 2324 * @brief Enable the oscillator clock for frequency error counter. 2325 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 2326 * @retval None 2327 */ 2328 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) 2329 2330 /** 2331 * @brief Disable the oscillator clock for frequency error counter. 2332 * @retval None 2333 */ 2334 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) 2335 2336 /** 2337 * @brief Enable the automatic hardware adjustement of TRIM bits. 2338 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 2339 * @retval None 2340 */ 2341 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 2342 2343 /** 2344 * @brief Enable or disable the automatic hardware adjustement of TRIM bits. 2345 * @retval None 2346 */ 2347 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 2348 2349 /** 2350 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 2351 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 2352 * of the synchronization source after prescaling. It is then decreased by one in order to 2353 * reach the expected synchronization on the zero value. The formula is the following: 2354 * RELOAD = (fTARGET / fSYNC) -1 2355 * @param __FTARGET__ Target frequency (value in Hz) 2356 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 2357 * @retval None 2358 */ 2359 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) 2360 2361 /** 2362 * @} 2363 */ 2364 2365 #endif /* CRS */ 2366 2367 /** 2368 * @} 2369 */ 2370 2371 /* Exported functions --------------------------------------------------------*/ 2372 /** @addtogroup RCCEx_Exported_Functions 2373 * @{ 2374 */ 2375 2376 /** @addtogroup RCCEx_Exported_Functions_Group1 2377 * @{ 2378 */ 2379 2380 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 2381 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 2382 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 2383 2384 /** 2385 * @} 2386 */ 2387 2388 /** @addtogroup RCCEx_Exported_Functions_Group2 2389 * @{ 2390 */ 2391 #if defined(RCC_PLLSAI1_SUPPORT) 2392 2393 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init); 2394 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void); 2395 2396 #endif /* RCC_PLLSAI1_SUPPORT */ 2397 2398 #if defined(RCC_PLLSAI2_SUPPORT) 2399 2400 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init); 2401 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void); 2402 2403 #endif /* RCC_PLLSAI2_SUPPORT */ 2404 2405 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); 2406 void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange); 2407 void HAL_RCCEx_EnableLSECSS(void); 2408 void HAL_RCCEx_DisableLSECSS(void); 2409 void HAL_RCCEx_EnableLSECSS_IT(void); 2410 void HAL_RCCEx_LSECSS_IRQHandler(void); 2411 void HAL_RCCEx_LSECSS_Callback(void); 2412 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); 2413 void HAL_RCCEx_DisableLSCO(void); 2414 void HAL_RCCEx_EnableMSIPLLMode(void); 2415 void HAL_RCCEx_DisableMSIPLLMode(void); 2416 2417 /** 2418 * @} 2419 */ 2420 2421 #if defined(CRS) 2422 2423 /** @addtogroup RCCEx_Exported_Functions_Group3 2424 * @{ 2425 */ 2426 2427 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); 2428 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 2429 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 2430 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 2431 void HAL_RCCEx_CRS_IRQHandler(void); 2432 void HAL_RCCEx_CRS_SyncOkCallback(void); 2433 void HAL_RCCEx_CRS_SyncWarnCallback(void); 2434 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 2435 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 2436 2437 /** 2438 * @} 2439 */ 2440 2441 #endif /* CRS */ 2442 2443 /** 2444 * @} 2445 */ 2446 2447 /* Private macros ------------------------------------------------------------*/ 2448 /** @addtogroup RCCEx_Private_Macros 2449 * @{ 2450 */ 2451 2452 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ 2453 ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) 2454 2455 #if defined(STM32L412xx) || defined(STM32L422xx) 2456 2457 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 2458 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 2459 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 2460 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 2461 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 2462 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 2463 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 2464 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 2465 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 2466 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 2467 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 2468 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 2469 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 2470 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)) 2471 2472 #elif defined(STM32L431xx) 2473 2474 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 2475 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 2476 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 2477 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 2478 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 2479 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 2480 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 2481 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 2482 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 2483 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 2484 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 2485 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 2486 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ 2487 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 2488 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 2489 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) 2490 2491 #elif defined(STM32L432xx) || defined(STM32L442xx) 2492 2493 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 2494 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 2495 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 2496 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 2497 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 2498 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 2499 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 2500 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 2501 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 2502 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 2503 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 2504 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ 2505 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 2506 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)) 2507 2508 #elif defined(STM32L433xx) || defined(STM32L443xx) 2509 2510 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 2511 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 2512 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 2513 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 2514 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 2515 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 2516 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 2517 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 2518 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 2519 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 2520 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 2521 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 2522 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 2523 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ 2524 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 2525 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 2526 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) 2527 2528 #elif defined(STM32L451xx) 2529 2530 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 2531 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 2532 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 2533 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 2534 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 2535 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 2536 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 2537 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 2538 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 2539 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 2540 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 2541 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 2542 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 2543 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 2544 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ 2545 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 2546 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 2547 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) 2548 2549 #elif defined(STM32L452xx) || defined(STM32L462xx) 2550 2551 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 2552 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 2553 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 2554 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 2555 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 2556 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 2557 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 2558 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 2559 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 2560 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 2561 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 2562 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 2563 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 2564 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 2565 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 2566 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ 2567 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 2568 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 2569 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) 2570 2571 #elif defined(STM32L471xx) 2572 2573 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 2574 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 2575 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 2576 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 2577 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 2578 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 2579 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 2580 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 2581 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 2582 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 2583 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 2584 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 2585 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 2586 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ 2587 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 2588 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ 2589 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ 2590 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 2591 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 2592 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) 2593 2594 #elif defined(STM32L496xx) || defined(STM32L4A6xx) 2595 2596 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 2597 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 2598 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 2599 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 2600 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 2601 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 2602 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 2603 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 2604 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 2605 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 2606 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 2607 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 2608 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 2609 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 2610 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ 2611 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 2612 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 2613 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ 2614 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ 2615 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 2616 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 2617 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) 2618 2619 #elif defined(STM32L4R5xx) || defined(STM32L4S5xx) 2620 2621 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 2622 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 2623 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 2624 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 2625 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 2626 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 2627 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 2628 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 2629 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 2630 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 2631 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 2632 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 2633 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 2634 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 2635 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ 2636 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 2637 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 2638 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ 2639 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \ 2640 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 2641 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 2642 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ 2643 (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)) 2644 2645 #elif defined(STM32L4R7xx) || defined(STM32L4S7xx) 2646 2647 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 2648 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 2649 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 2650 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 2651 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 2652 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 2653 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 2654 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 2655 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 2656 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 2657 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 2658 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 2659 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 2660 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 2661 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ 2662 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 2663 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 2664 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ 2665 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \ 2666 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 2667 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 2668 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ 2669 (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) || \ 2670 (((__SELECTION__) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)) 2671 2672 #elif defined(STM32L4R9xx) || defined(STM32L4S9xx) 2673 2674 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 2675 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 2676 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 2677 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 2678 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 2679 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 2680 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 2681 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 2682 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 2683 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 2684 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 2685 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 2686 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 2687 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 2688 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ 2689 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 2690 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 2691 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ 2692 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \ 2693 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 2694 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 2695 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ 2696 (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) || \ 2697 (((__SELECTION__) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ 2698 (((__SELECTION__) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)) 2699 2700 #else 2701 2702 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 2703 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 2704 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 2705 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 2706 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 2707 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 2708 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 2709 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 2710 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 2711 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 2712 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 2713 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 2714 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 2715 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ 2716 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 2717 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 2718 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ 2719 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ 2720 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 2721 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 2722 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) 2723 2724 #endif /* STM32L412xx || STM32L422xx */ 2725 2726 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ 2727 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ 2728 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ 2729 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ 2730 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) 2731 2732 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ 2733 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ 2734 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ 2735 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ 2736 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) 2737 2738 #if defined(USART3) 2739 2740 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ 2741 (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ 2742 ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ 2743 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ 2744 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) 2745 2746 #endif /* USART3 */ 2747 2748 #if defined(UART4) 2749 2750 #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ 2751 (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ 2752 ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \ 2753 ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \ 2754 ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI)) 2755 2756 #endif /* UART4 */ 2757 2758 #if defined(UART5) 2759 2760 #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ 2761 (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ 2762 ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \ 2763 ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \ 2764 ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI)) 2765 2766 #endif /* UART5 */ 2767 2768 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ 2769 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ 2770 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ 2771 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ 2772 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) 2773 2774 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ 2775 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ 2776 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ 2777 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) 2778 2779 #if defined(I2C2) 2780 2781 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ 2782 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ 2783 ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ 2784 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) 2785 2786 #endif /* I2C2 */ 2787 2788 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ 2789 (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ 2790 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ 2791 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) 2792 2793 #if defined(I2C4) 2794 2795 #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ 2796 (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \ 2797 ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ 2798 ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)) 2799 2800 #endif /* I2C4 */ 2801 2802 #if defined(RCC_PLLSAI2_SUPPORT) 2803 2804 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 2805 #define IS_RCC_SAI1CLK(__SOURCE__) \ 2806 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ 2807 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \ 2808 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ 2809 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \ 2810 ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)) 2811 #else 2812 #define IS_RCC_SAI1CLK(__SOURCE__) \ 2813 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ 2814 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \ 2815 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ 2816 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) 2817 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 2818 2819 #elif defined(RCC_PLLSAI1_SUPPORT) 2820 2821 #define IS_RCC_SAI1CLK(__SOURCE__) \ 2822 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ 2823 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ 2824 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) 2825 2826 #endif /* RCC_PLLSAI2_SUPPORT */ 2827 2828 #if defined(RCC_PLLSAI2_SUPPORT) 2829 2830 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 2831 #define IS_RCC_SAI2CLK(__SOURCE__) \ 2832 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \ 2833 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \ 2834 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ 2835 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \ 2836 ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI)) 2837 #else 2838 #define IS_RCC_SAI2CLK(__SOURCE__) \ 2839 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \ 2840 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \ 2841 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ 2842 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN)) 2843 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 2844 2845 #endif /* RCC_PLLSAI2_SUPPORT */ 2846 2847 #define IS_RCC_LPTIM1CLK(__SOURCE__) \ 2848 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ 2849 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ 2850 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ 2851 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) 2852 2853 #define IS_RCC_LPTIM2CLK(__SOURCE__) \ 2854 (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ 2855 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ 2856 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ 2857 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) 2858 2859 #if defined(SDMMC1) 2860 #if defined(RCC_HSI48_SUPPORT) && defined(RCC_CCIPR2_SDMMCSEL) 2861 2862 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ 2863 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) || \ 2864 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \ 2865 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ 2866 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ 2867 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) 2868 2869 #elif defined(RCC_HSI48_SUPPORT) 2870 2871 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ 2872 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \ 2873 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ 2874 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ 2875 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) 2876 #else 2877 2878 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ 2879 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_NONE) || \ 2880 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ 2881 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ 2882 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) 2883 2884 #endif /* RCC_HSI48_SUPPORT */ 2885 #endif /* SDMMC1 */ 2886 2887 #if defined(RCC_HSI48_SUPPORT) 2888 2889 #if defined(RCC_PLLSAI1_SUPPORT) 2890 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ 2891 (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ 2892 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \ 2893 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ 2894 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) 2895 #else 2896 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ 2897 (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ 2898 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ 2899 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) 2900 #endif /* RCC_PLLSAI1_SUPPORT */ 2901 2902 #else 2903 2904 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ 2905 (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) || \ 2906 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \ 2907 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ 2908 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) 2909 2910 #endif /* RCC_HSI48_SUPPORT */ 2911 2912 #if defined(USB_OTG_FS) || defined(USB) 2913 #if defined(RCC_HSI48_SUPPORT) 2914 2915 #if defined(RCC_PLLSAI1_SUPPORT) 2916 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 2917 (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ 2918 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \ 2919 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ 2920 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) 2921 #else 2922 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 2923 (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ 2924 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ 2925 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) 2926 #endif /* RCC_PLLSAI1_SUPPORT */ 2927 2928 #else 2929 2930 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 2931 (((__SOURCE__) == RCC_USBCLKSOURCE_NONE) || \ 2932 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \ 2933 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ 2934 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) 2935 2936 #endif /* RCC_HSI48_SUPPORT */ 2937 #endif /* USB_OTG_FS || USB */ 2938 2939 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 2940 2941 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ 2942 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ 2943 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ 2944 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI2) || \ 2945 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) 2946 2947 #else 2948 2949 #if defined(RCC_PLLSAI1_SUPPORT) 2950 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ 2951 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ 2952 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ 2953 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) 2954 #else 2955 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ 2956 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ 2957 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) 2958 #endif /* RCC_PLLSAI1_SUPPORT */ 2959 2960 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ 2961 2962 #if defined(SWPMI1) 2963 2964 #define IS_RCC_SWPMI1CLKSOURCE(__SOURCE__) \ 2965 (((__SOURCE__) == RCC_SWPMI1CLKSOURCE_PCLK1) || \ 2966 ((__SOURCE__) == RCC_SWPMI1CLKSOURCE_HSI)) 2967 2968 #endif /* SWPMI1 */ 2969 2970 #if defined(DFSDM1_Filter0) 2971 2972 #define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) \ 2973 (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ 2974 ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK)) 2975 2976 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 2977 2978 #define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) \ 2979 (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \ 2980 ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_HSI) || \ 2981 ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_MSI)) 2982 2983 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 2984 2985 #endif /* DFSDM1_Filter0 */ 2986 2987 #if defined(LTDC) 2988 2989 #define IS_RCC_LTDCCLKSOURCE(__SOURCE__) \ 2990 (((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV2) || \ 2991 ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV4) || \ 2992 ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV8) || \ 2993 ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV16)) 2994 2995 #endif /* LTDC */ 2996 2997 #if defined(DSI) 2998 2999 #define IS_RCC_DSICLKSOURCE(__SOURCE__) \ 3000 (((__SOURCE__) == RCC_DSICLKSOURCE_DSIPHY) || \ 3001 ((__SOURCE__) == RCC_DSICLKSOURCE_PLLSAI2)) 3002 3003 #endif /* DSI */ 3004 3005 #if defined(OCTOSPI1) || defined(OCTOSPI2) 3006 3007 #define IS_RCC_OSPICLKSOURCE(__SOURCE__) \ 3008 (((__SOURCE__) == RCC_OSPICLKSOURCE_SYSCLK) || \ 3009 ((__SOURCE__) == RCC_OSPICLKSOURCE_MSI) || \ 3010 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL)) 3011 3012 #endif /* OCTOSPI1 || OCTOSPI2 */ 3013 3014 #if defined(RCC_PLLSAI1_SUPPORT) 3015 3016 #define IS_RCC_PLLSAI1SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) 3017 3018 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 3019 #define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) 3020 #else 3021 #define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) 3022 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 3023 3024 #define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) 3025 3026 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 3027 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) 3028 #else 3029 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U)) 3030 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 3031 3032 #define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 3033 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 3034 3035 #define IS_RCC_PLLSAI1R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 3036 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 3037 3038 #endif /* RCC_PLLSAI1_SUPPORT */ 3039 3040 #if defined(RCC_PLLSAI2_SUPPORT) 3041 3042 #define IS_RCC_PLLSAI2SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) 3043 3044 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 3045 #define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) 3046 #else 3047 #define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) 3048 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ 3049 3050 #define IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) 3051 3052 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 3053 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) 3054 #else 3055 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U)) 3056 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ 3057 3058 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 3059 #define IS_RCC_PLLSAI2Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 3060 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 3061 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ 3062 3063 #define IS_RCC_PLLSAI2R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 3064 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 3065 3066 #endif /* RCC_PLLSAI2_SUPPORT */ 3067 3068 #if defined(CRS) 3069 3070 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ 3071 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ 3072 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) 3073 3074 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ 3075 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ 3076 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ 3077 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) 3078 3079 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ 3080 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) 3081 3082 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) 3083 3084 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) 3085 3086 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) 3087 3088 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ 3089 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) 3090 3091 #endif /* CRS */ 3092 3093 /** 3094 * @} 3095 */ 3096 3097 /** 3098 * @} 3099 */ 3100 3101 /** 3102 * @} 3103 */ 3104 3105 #ifdef __cplusplus 3106 } 3107 #endif 3108 3109 #endif /* __STM32L4xx_HAL_RCC_EX_H */ 3110 3111 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 3112
