1 /****************************************************************************** 2 * 3 * Module Name: dmtbinfo2 - Table info for non-AML tables 4 * 5 *****************************************************************************/ 6 7 /****************************************************************************** 8 * 9 * 1. Copyright Notice 10 * 11 * Some or all of this work - Copyright (c) 1999 - 2023, Intel Corp. 12 * All rights reserved. 13 * 14 * 2. License 15 * 16 * 2.1. This is your license from Intel Corp. under its intellectual property 17 * rights. You may have additional license terms from the party that provided 18 * you this software, covering your right to use that party's intellectual 19 * property rights. 20 * 21 * 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a 22 * copy of the source code appearing in this file ("Covered Code") an 23 * irrevocable, perpetual, worldwide license under Intel's copyrights in the 24 * base code distributed originally by Intel ("Original Intel Code") to copy, 25 * make derivatives, distribute, use and display any portion of the Covered 26 * Code in any form, with the right to sublicense such rights; and 27 * 28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent 29 * license (with the right to sublicense), under only those claims of Intel 30 * patents that are infringed by the Original Intel Code, to make, use, sell, 31 * offer to sell, and import the Covered Code and derivative works thereof 32 * solely to the minimum extent necessary to exercise the above copyright 33 * license, and in no event shall the patent license extend to any additions 34 * to or modifications of the Original Intel Code. No other license or right 35 * is granted directly or by implication, estoppel or otherwise; 36 * 37 * The above copyright and patent license is granted only if the following 38 * conditions are met: 39 * 40 * 3. Conditions 41 * 42 * 3.1. Redistribution of Source with Rights to Further Distribute Source. 43 * Redistribution of source code of any substantial portion of the Covered 44 * Code or modification with rights to further distribute source must include 45 * the above Copyright Notice, the above License, this list of Conditions, 46 * and the following Disclaimer and Export Compliance provision. In addition, 47 * Licensee must cause all Covered Code to which Licensee contributes to 48 * contain a file documenting the changes Licensee made to create that Covered 49 * Code and the date of any change. Licensee must include in that file the 50 * documentation of any changes made by any predecessor Licensee. Licensee 51 * must include a prominent statement that the modification is derived, 52 * directly or indirectly, from Original Intel Code. 53 * 54 * 3.2. Redistribution of Source with no Rights to Further Distribute Source. 55 * Redistribution of source code of any substantial portion of the Covered 56 * Code or modification without rights to further distribute source must 57 * include the following Disclaimer and Export Compliance provision in the 58 * documentation and/or other materials provided with distribution. In 59 * addition, Licensee may not authorize further sublicense of source of any 60 * portion of the Covered Code, and must include terms to the effect that the 61 * license from Licensee to its licensee is limited to the intellectual 62 * property embodied in the software Licensee provides to its licensee, and 63 * not to intellectual property embodied in modifications its licensee may 64 * make. 65 * 66 * 3.3. Redistribution of Executable. Redistribution in executable form of any 67 * substantial portion of the Covered Code or modification must reproduce the 68 * above Copyright Notice, and the following Disclaimer and Export Compliance 69 * provision in the documentation and/or other materials provided with the 70 * distribution. 71 * 72 * 3.4. Intel retains all right, title, and interest in and to the Original 73 * Intel Code. 74 * 75 * 3.5. Neither the name Intel nor any other trademark owned or controlled by 76 * Intel shall be used in advertising or otherwise to promote the sale, use or 77 * other dealings in products derived from or relating to the Covered Code 78 * without prior written authorization from Intel. 79 * 80 * 4. Disclaimer and Export Compliance 81 * 82 * 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED 83 * HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE 84 * IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE, 85 * INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY 86 * UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY 87 * IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A 88 * PARTICULAR PURPOSE. 89 * 90 * 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES 91 * OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR 92 * COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT, 93 * SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY 94 * CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL 95 * HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS 96 * SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY 97 * LIMITED REMEDY. 98 * 99 * 4.3. Licensee shall not export, either directly or indirectly, any of this 100 * software or system incorporating such software without first obtaining any 101 * required license or other approval from the U. S. Department of Commerce or 102 * any other agency or department of the United States Government. In the 103 * event Licensee exports any such software from the United States or 104 * re-exports any such software from a foreign destination, Licensee shall 105 * ensure that the distribution and export/re-export of the software is in 106 * compliance with all laws, regulations, orders, or other restrictions of the 107 * U.S. Export Administration Regulations. Licensee agrees that neither it nor 108 * any of its subsidiaries will export/re-export any technical data, process, 109 * software, or service, directly or indirectly, to any country for which the 110 * United States government or any agency thereof requires an export license, 111 * other governmental approval, or letter of assurance, without first obtaining 112 * such license, approval or letter. 113 * 114 ***************************************************************************** 115 * 116 * Alternatively, you may choose to be licensed under the terms of the 117 * following license: 118 * 119 * Redistribution and use in source and binary forms, with or without 120 * modification, are permitted provided that the following conditions 121 * are met: 122 * 1. Redistributions of source code must retain the above copyright 123 * notice, this list of conditions, and the following disclaimer, 124 * without modification. 125 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 126 * substantially similar to the "NO WARRANTY" disclaimer below 127 * ("Disclaimer") and any redistribution must be conditioned upon 128 * including a substantially similar Disclaimer requirement for further 129 * binary redistribution. 130 * 3. Neither the names of the above-listed copyright holders nor the names 131 * of any contributors may be used to endorse or promote products derived 132 * from this software without specific prior written permission. 133 * 134 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 135 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 136 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 137 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 138 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 139 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 140 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 141 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 142 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 143 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 144 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 145 * 146 * Alternatively, you may choose to be licensed under the terms of the 147 * GNU General Public License ("GPL") version 2 as published by the Free 148 * Software Foundation. 149 * 150 *****************************************************************************/ 151 152 #include "acpi.h" 153 #include "accommon.h" 154 #include "acdisasm.h" 155 #include "actbinfo.h" 156 157 /* This module used for application-level code only */ 158 159 #define _COMPONENT ACPI_CA_DISASSEMBLER 160 ACPI_MODULE_NAME ("dmtbinfo2") 161 162 /* 163 * How to add a new table: 164 * 165 * - Add the C table definition to the actbl1.h or actbl2.h header. 166 * - Add ACPI_xxxx_OFFSET macro(s) for the table (and subtables) to list below. 167 * - Define the table in this file (for the disassembler). If any 168 * new data types are required (ACPI_DMT_*), see below. 169 * - Add an external declaration for the new table definition (AcpiDmTableInfo*) 170 * in acdisam.h 171 * - Add new table definition to the dispatch table in dmtable.c (AcpiDmTableData) 172 * If a simple table (with no subtables), no disassembly code is needed. 173 * Otherwise, create the AcpiDmDump* function for to disassemble the table 174 * and add it to the dmtbdump.c file. 175 * - Add an external declaration for the new AcpiDmDump* function in acdisasm.h 176 * - Add the new AcpiDmDump* function to the dispatch table in dmtable.c 177 * - Create a template for the new table 178 * - Add data table compiler support 179 * 180 * How to add a new data type (ACPI_DMT_*): 181 * 182 * - Add new type at the end of the ACPI_DMT list in acdisasm.h 183 * - Add length and implementation cases in dmtable.c (disassembler) 184 * - Add type and length cases in dtutils.c (DT compiler) 185 */ 186 187 /* 188 * Remaining tables are not consumed directly by the ACPICA subsystem 189 */ 190 191 /******************************************************************************* 192 * 193 * AGDI - Arm Generic Diagnostic Dump and Reset Device Interface 194 * 195 * Conforms to "ACPI for Arm Components 1.1, Platform Design Document" 196 * ARM DEN0093 v1.1 197 * 198 ******************************************************************************/ 199 200 ACPI_DMTABLE_INFO AcpiDmTableInfoAgdi[] = 201 { 202 {ACPI_DMT_UINT8, ACPI_AGDI_OFFSET (Flags), "Flags (decoded below)", 0}, 203 {ACPI_DMT_FLAG0, ACPI_AGDI_FLAG_OFFSET (Flags, 0), "Signalling mode", 0}, 204 {ACPI_DMT_UINT24, ACPI_AGDI_OFFSET (Reserved[0]), "Reserved", 0}, 205 {ACPI_DMT_UINT32, ACPI_AGDI_OFFSET (SdeiEvent), "SdeiEvent", 0}, 206 {ACPI_DMT_UINT32, ACPI_AGDI_OFFSET (Gsiv), "Gsiv", 0}, 207 ACPI_DMT_TERMINATOR 208 }; 209 210 211 /******************************************************************************* 212 * 213 * APMT - ARM Performance Monitoring Unit Table 214 * 215 * Conforms to: 216 * ARM Performance Monitoring Unit Architecture 1.0 Platform Design Document 217 * ARM DEN0117 v1.0 November 25, 2021 218 * 219 ******************************************************************************/ 220 221 ACPI_DMTABLE_INFO AcpiDmTableInfoApmtNode[] = 222 { 223 {ACPI_DMT_UINT16, ACPI_APMTN_OFFSET (Length), "Length of APMT Node", 0}, 224 {ACPI_DMT_UINT8, ACPI_APMTN_OFFSET (Flags), "Node Flags", 0}, 225 {ACPI_DMT_FLAG0, ACPI_APMTN_FLAG_OFFSET (Flags, 0), "Dual Page Extension", 0}, 226 {ACPI_DMT_FLAG1, ACPI_APMTN_FLAG_OFFSET (Flags, 0), "Processor Affinity Type", 0}, 227 {ACPI_DMT_FLAG2, ACPI_APMTN_FLAG_OFFSET (Flags, 0), "64-bit Atomic Support", 0}, 228 {ACPI_DMT_UINT8, ACPI_APMTN_OFFSET (Type), "Node Type", 0}, 229 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (Id), "Unique Node Identifier", 0}, 230 {ACPI_DMT_UINT64, ACPI_APMTN_OFFSET (InstPrimary), "Primary Node Instance", 0}, 231 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (InstSecondary), "Secondary Node Instance", 0}, 232 {ACPI_DMT_UINT64, ACPI_APMTN_OFFSET (BaseAddress0), "Page 0 Base Address", 0}, 233 {ACPI_DMT_UINT64, ACPI_APMTN_OFFSET (BaseAddress1), "Page 1 Base Address", 0}, 234 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (OvflwIrq), "Overflow Interrupt ID", 0}, 235 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (Reserved), "Reserved", 0}, 236 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (OvflwIrqFlags), "Overflow Interrupt Flags", 0}, 237 {ACPI_DMT_FLAG0, ACPI_APMTN_FLAG_OFFSET (OvflwIrqFlags, 0), "Interrupt Mode", 0}, 238 {ACPI_DMT_FLAG1, ACPI_APMTN_FLAG_OFFSET (OvflwIrqFlags, 0), "Interrupt Type", 0}, 239 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (ProcAffinity), "Processor Affinity", 0}, 240 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (ImplId), "Implementation ID", 0}, 241 ACPI_DMT_TERMINATOR 242 }; 243 244 245 /******************************************************************************* 246 * 247 * IORT - IO Remapping Table 248 * 249 ******************************************************************************/ 250 251 ACPI_DMTABLE_INFO AcpiDmTableInfoIort[] = 252 { 253 {ACPI_DMT_UINT32, ACPI_IORT_OFFSET (NodeCount), "Node Count", 0}, 254 {ACPI_DMT_UINT32, ACPI_IORT_OFFSET (NodeOffset), "Node Offset", 0}, 255 {ACPI_DMT_UINT32, ACPI_IORT_OFFSET (Reserved), "Reserved", 0}, 256 ACPI_DMT_TERMINATOR 257 }; 258 259 /* Optional padding field */ 260 261 ACPI_DMTABLE_INFO AcpiDmTableInfoIortPad[] = 262 { 263 {ACPI_DMT_RAW_BUFFER, 0, "Optional Padding", DT_OPTIONAL}, 264 ACPI_DMT_TERMINATOR 265 }; 266 267 /* Common Subtable header (one per Subtable) */ 268 269 ACPI_DMTABLE_INFO AcpiDmTableInfoIortHdr[] = 270 { 271 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Type), "Type", 0}, 272 {ACPI_DMT_UINT16, ACPI_IORTH_OFFSET (Length), "Length", DT_LENGTH}, 273 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Revision), "Revision", 0}, 274 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (Identifier), "Reserved", 0}, 275 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingCount), "Mapping Count", 0}, 276 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingOffset), "Mapping Offset", 0}, 277 ACPI_DMT_TERMINATOR 278 }; 279 280 /* Common Subtable header (one per Subtable)- Revision 3 */ 281 282 ACPI_DMTABLE_INFO AcpiDmTableInfoIortHdr3[] = 283 { 284 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Type), "Type", 0}, 285 {ACPI_DMT_UINT16, ACPI_IORTH_OFFSET (Length), "Length", DT_LENGTH}, 286 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Revision), "Revision", 0}, 287 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (Identifier), "Identifier", 0}, 288 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingCount), "Mapping Count", 0}, 289 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingOffset), "Mapping Offset", 0}, 290 ACPI_DMT_TERMINATOR 291 }; 292 293 ACPI_DMTABLE_INFO AcpiDmTableInfoIortMap[] = 294 { 295 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (InputBase), "Input base", DT_OPTIONAL}, 296 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (IdCount), "ID Count", 0}, 297 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (OutputBase), "Output Base", 0}, 298 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (OutputReference), "Output Reference", 0}, 299 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (Flags), "Flags (decoded below)", 0}, 300 {ACPI_DMT_FLAG0, ACPI_IORTM_FLAG_OFFSET (Flags, 0), "Single Mapping", 0}, 301 ACPI_DMT_TERMINATOR 302 }; 303 304 ACPI_DMTABLE_INFO AcpiDmTableInfoIortAcc[] = 305 { 306 {ACPI_DMT_UINT32, ACPI_IORTA_OFFSET (CacheCoherency), "Cache Coherency", 0}, 307 {ACPI_DMT_UINT8, ACPI_IORTA_OFFSET (Hints), "Hints (decoded below)", 0}, 308 {ACPI_DMT_FLAG0, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Transient", 0}, 309 {ACPI_DMT_FLAG1, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Write Allocate", 0}, 310 {ACPI_DMT_FLAG2, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Read Allocate", 0}, 311 {ACPI_DMT_FLAG3, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Override", 0}, 312 {ACPI_DMT_UINT16, ACPI_IORTA_OFFSET (Reserved), "Reserved", 0}, 313 {ACPI_DMT_UINT8, ACPI_IORTA_OFFSET (MemoryFlags), "Memory Flags (decoded below)", 0}, 314 {ACPI_DMT_FLAG0, ACPI_IORTA_FLAG_OFFSET (MemoryFlags, 0), "Coherency", 0}, 315 {ACPI_DMT_FLAG1, ACPI_IORTA_FLAG_OFFSET (MemoryFlags, 0), "Device Attribute", 0}, 316 ACPI_DMT_TERMINATOR 317 }; 318 319 /* IORT subtables */ 320 321 /* 0x00: ITS Group */ 322 323 ACPI_DMTABLE_INFO AcpiDmTableInfoIort0[] = 324 { 325 {ACPI_DMT_UINT32, ACPI_IORT0_OFFSET (ItsCount), "ItsCount", 0}, 326 ACPI_DMT_TERMINATOR 327 }; 328 329 ACPI_DMTABLE_INFO AcpiDmTableInfoIort0a[] = 330 { 331 {ACPI_DMT_UINT32, 0, "Identifiers", DT_OPTIONAL}, 332 ACPI_DMT_TERMINATOR 333 }; 334 335 /* 0x01: Named Component */ 336 337 ACPI_DMTABLE_INFO AcpiDmTableInfoIort1[] = 338 { 339 {ACPI_DMT_UINT32, ACPI_IORT1_OFFSET (NodeFlags), "Node Flags", 0}, 340 {ACPI_DMT_IORTMEM, ACPI_IORT1_OFFSET (MemoryProperties), "Memory Properties", 0}, 341 {ACPI_DMT_UINT8, ACPI_IORT1_OFFSET (MemoryAddressLimit), "Memory Size Limit", 0}, 342 {ACPI_DMT_STRING, ACPI_IORT1_OFFSET (DeviceName[0]), "Device Name", 0}, 343 ACPI_DMT_TERMINATOR 344 }; 345 346 ACPI_DMTABLE_INFO AcpiDmTableInfoIort1a[] = 347 { 348 {ACPI_DMT_RAW_BUFFER, 0, "Padding", DT_OPTIONAL}, 349 ACPI_DMT_TERMINATOR 350 }; 351 352 /* 0x02: PCI Root Complex */ 353 354 ACPI_DMTABLE_INFO AcpiDmTableInfoIort2[] = 355 { 356 {ACPI_DMT_IORTMEM, ACPI_IORT2_OFFSET (MemoryProperties), "Memory Properties", 0}, 357 {ACPI_DMT_UINT32, ACPI_IORT2_OFFSET (AtsAttribute), "ATS Attribute", 0}, 358 {ACPI_DMT_UINT32, ACPI_IORT2_OFFSET (PciSegmentNumber), "PCI Segment Number", 0}, 359 {ACPI_DMT_UINT8, ACPI_IORT2_OFFSET (MemoryAddressLimit), "Memory Size Limit", 0}, 360 {ACPI_DMT_UINT16, ACPI_IORT2_OFFSET (PasidCapabilities), "PASID Capabilities", 0}, 361 {ACPI_DMT_UINT8, ACPI_IORT2_OFFSET (Reserved[0]), "Reserved", 0}, 362 ACPI_DMT_TERMINATOR 363 }; 364 365 /* 0x03: SMMUv1/2 */ 366 367 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3[] = 368 { 369 {ACPI_DMT_UINT64, ACPI_IORT3_OFFSET (BaseAddress), "Base Address", 0}, 370 {ACPI_DMT_UINT64, ACPI_IORT3_OFFSET (Span), "Span", 0}, 371 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (Model), "Model", 0}, 372 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (Flags), "Flags (decoded below)", 0}, 373 {ACPI_DMT_FLAG0, ACPI_IORT3_FLAG_OFFSET (Flags, 0), "DVM Supported", 0}, 374 {ACPI_DMT_FLAG1, ACPI_IORT3_FLAG_OFFSET (Flags, 0), "Coherent Walk", 0}, 375 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (GlobalInterruptOffset), "Global Interrupt Offset", 0}, 376 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (ContextInterruptCount), "Context Interrupt Count", 0}, 377 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (ContextInterruptOffset), "Context Interrupt Offset", 0}, 378 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (PmuInterruptCount), "PMU Interrupt Count", 0}, 379 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (PmuInterruptOffset), "PMU Interrupt Offset", 0}, 380 ACPI_DMT_TERMINATOR 381 }; 382 383 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3a[] = 384 { 385 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgIrpt), "NSgIrpt", 0}, 386 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgIrptFlags), "NSgIrpt Flags (decoded below)", 0}, 387 {ACPI_DMT_FLAG0, ACPI_IORT3a_FLAG_OFFSET (NSgIrptFlags, 0), "Edge Triggered", 0}, 388 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgCfgIrpt), "NSgCfgIrpt", 0}, 389 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgCfgIrptFlags), "NSgCfgIrpt Flags (decoded below)", 0}, 390 {ACPI_DMT_FLAG0, ACPI_IORT3a_FLAG_OFFSET (NSgCfgIrptFlags, 0), "Edge Triggered", 0}, 391 ACPI_DMT_TERMINATOR 392 }; 393 394 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3b[] = 395 { 396 {ACPI_DMT_UINT64, 0, "Context Interrupt", DT_OPTIONAL}, 397 ACPI_DMT_TERMINATOR 398 }; 399 400 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3c[] = 401 { 402 {ACPI_DMT_UINT64, 0, "PMU Interrupt", DT_OPTIONAL}, 403 ACPI_DMT_TERMINATOR 404 }; 405 406 /* 0x04: SMMUv3 */ 407 408 ACPI_DMTABLE_INFO AcpiDmTableInfoIort4[] = 409 { 410 {ACPI_DMT_UINT64, ACPI_IORT4_OFFSET (BaseAddress), "Base Address", 0}, 411 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Flags), "Flags (decoded below)", 0}, 412 {ACPI_DMT_FLAG0, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "COHACC Override", 0}, 413 {ACPI_DMT_FLAG1, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "HTTU Override", 0}, 414 {ACPI_DMT_FLAG3, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "Proximity Domain Valid", 0}, 415 {ACPI_DMT_FLAG4, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "DeviceID Valid", 0}, 416 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Reserved), "Reserved", 0}, 417 {ACPI_DMT_UINT64, ACPI_IORT4_OFFSET (VatosAddress), "VATOS Address", 0}, 418 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Model), "Model", 0}, 419 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (EventGsiv), "Event GSIV", 0}, 420 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (PriGsiv), "PRI GSIV", 0}, 421 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (GerrGsiv), "GERR GSIV", 0}, 422 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (SyncGsiv), "Sync GSIV", 0}, 423 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Pxm), "Proximity Domain", 0}, 424 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (IdMappingIndex), "Device ID Mapping Index", 0}, 425 ACPI_DMT_TERMINATOR 426 }; 427 428 /* 0x05: PMCG */ 429 430 ACPI_DMTABLE_INFO AcpiDmTableInfoIort5[] = 431 { 432 {ACPI_DMT_UINT64, ACPI_IORT5_OFFSET (Page0BaseAddress), "Page 0 Base Address", 0}, 433 {ACPI_DMT_UINT32, ACPI_IORT5_OFFSET (OverflowGsiv), "Overflow Interrupt GSIV", 0}, 434 {ACPI_DMT_UINT32, ACPI_IORT5_OFFSET (NodeReference), "Node Reference", 0}, 435 {ACPI_DMT_UINT64, ACPI_IORT5_OFFSET (Page1BaseAddress), "Page 1 Base Address", 0}, 436 ACPI_DMT_TERMINATOR 437 }; 438 439 440 /* 0x06: RMR */ 441 442 ACPI_DMTABLE_INFO AcpiDmTableInfoIort6[] = 443 { 444 {ACPI_DMT_UINT32, ACPI_IORT6_OFFSET (Flags), "Flags (decoded below)", 0}, 445 {ACPI_DMT_FLAG0, ACPI_IORT6_FLAG_OFFSET (Flags, 0), "Remapping Permitted", 0}, 446 {ACPI_DMT_FLAG1, ACPI_IORT6_FLAG_OFFSET (Flags, 0), "Access Privileged", 0}, 447 {ACPI_DMT_FLAGS8_2, ACPI_IORT6_FLAG_OFFSET (Flags, 0), "Access Attributes", 0}, 448 {ACPI_DMT_UINT32, ACPI_IORT6_OFFSET (RmrCount), "Number of RMR Descriptors", 0}, 449 {ACPI_DMT_UINT32, ACPI_IORT6_OFFSET (RmrOffset), "RMR Descriptor Offset", 0}, 450 ACPI_DMT_TERMINATOR 451 }; 452 453 ACPI_DMTABLE_INFO AcpiDmTableInfoIort6a[] = 454 { 455 {ACPI_DMT_UINT64, ACPI_IORT6A_OFFSET (BaseAddress), "Base Address of RMR", DT_OPTIONAL}, 456 {ACPI_DMT_UINT64, ACPI_IORT6A_OFFSET (Length), "Length of RMR", 0}, 457 {ACPI_DMT_UINT32, ACPI_IORT6A_OFFSET (Reserved), "Reserved", 0}, 458 ACPI_DMT_TERMINATOR 459 }; 460 461 /******************************************************************************* 462 * 463 * IVRS - I/O Virtualization Reporting Structure 464 * 465 ******************************************************************************/ 466 467 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs[] = 468 { 469 {ACPI_DMT_UINT32, ACPI_IVRS_OFFSET (Info), "Virtualization Info", 0}, 470 {ACPI_DMT_UINT64, ACPI_IVRS_OFFSET (Reserved), "Reserved", 0}, 471 ACPI_DMT_TERMINATOR 472 }; 473 474 /* IVRS subtables */ 475 476 /* 0x10: I/O Virtualization Hardware Definition (IVHD) Block */ 477 478 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHware1[] = 479 { 480 {ACPI_DMT_IVRS, ACPI_IVRSH_OFFSET (Type), "Subtable Type", 0}, 481 {ACPI_DMT_UINT8, ACPI_IVRSH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 482 {ACPI_DMT_FLAG0, ACPI_IVRS_FLAG_OFFSET (Flags,0), "HtTunEn", 0}, 483 {ACPI_DMT_FLAG1, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PassPW", 0}, 484 {ACPI_DMT_FLAG2, ACPI_IVRS_FLAG_OFFSET (Flags,0), "ResPassPW", 0}, 485 {ACPI_DMT_FLAG3, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Isoc Control", 0}, 486 {ACPI_DMT_FLAG4, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Iotlb Support", 0}, 487 {ACPI_DMT_FLAG5, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Coherent", 0}, 488 {ACPI_DMT_FLAG6, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Prefetch Support", 0}, 489 {ACPI_DMT_FLAG7, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PPR Support", 0}, 490 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (Length), "Length", DT_LENGTH}, 491 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (DeviceId), "DeviceId", 0}, 492 {ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (CapabilityOffset), "Capability Offset", 0}, 493 {ACPI_DMT_UINT64, ACPI_IVRS0_OFFSET (BaseAddress), "Base Address", 0}, 494 {ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (PciSegmentGroup), "PCI Segment Group", 0}, 495 {ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (Info), "Virtualization Info", 0}, 496 {ACPI_DMT_UINT32, ACPI_IVRS0_OFFSET (FeatureReporting), "Feature Reporting", 0}, 497 ACPI_DMT_TERMINATOR 498 }; 499 500 /* 0x11, 0x40: I/O Virtualization Hardware Definition (IVHD) Block */ 501 502 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHware23[] = 503 { 504 {ACPI_DMT_IVRS, ACPI_IVRSH_OFFSET (Type), "Subtable Type", 0}, 505 {ACPI_DMT_UINT8, ACPI_IVRSH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 506 {ACPI_DMT_FLAG0, ACPI_IVRS_FLAG_OFFSET (Flags,0), "HtTunEn", 0}, 507 {ACPI_DMT_FLAG1, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PassPW", 0}, 508 {ACPI_DMT_FLAG2, ACPI_IVRS_FLAG_OFFSET (Flags,0), "ResPassPW", 0}, 509 {ACPI_DMT_FLAG3, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Isoc Control", 0}, 510 {ACPI_DMT_FLAG4, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Iotlb Support", 0}, 511 {ACPI_DMT_FLAG5, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Coherent", 0}, 512 {ACPI_DMT_FLAG6, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Prefetch Support", 0}, 513 {ACPI_DMT_FLAG7, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PPR Support", 0}, 514 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (Header.Length), "Length", DT_LENGTH}, 515 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (Header.DeviceId), "DeviceId", 0}, 516 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (CapabilityOffset), "Capability Offset", 0}, 517 {ACPI_DMT_UINT64, ACPI_IVRS01_OFFSET (BaseAddress), "Base Address", 0}, 518 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (PciSegmentGroup), "PCI Segment Group", 0}, 519 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (Info), "Virtualization Info", 0}, 520 {ACPI_DMT_UINT32, ACPI_IVRS01_OFFSET (Attributes), "Attributes", 0}, 521 {ACPI_DMT_UINT64, ACPI_IVRS01_OFFSET (EfrRegisterImage), "EFR Image", 0}, 522 {ACPI_DMT_UINT64, ACPI_IVRS01_OFFSET (Reserved), "Reserved", 0}, 523 ACPI_DMT_TERMINATOR 524 }; 525 526 /* 0x20, 0x21, 0x22: I/O Virtualization Memory Definition (IVMD) Device Entry Block */ 527 528 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsMemory[] = 529 { 530 {ACPI_DMT_IVRS, ACPI_IVRSH_OFFSET (Type), "Subtable Type", 0}, 531 {ACPI_DMT_UINT8, ACPI_IVRSH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 532 {ACPI_DMT_FLAG0, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Unity", 0}, 533 {ACPI_DMT_FLAG1, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Readable", 0}, 534 {ACPI_DMT_FLAG2, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Writeable", 0}, 535 {ACPI_DMT_FLAG3, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Exclusion Range", 0}, 536 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (Length), "Length", DT_LENGTH}, 537 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (DeviceId), "DeviceId", 0}, 538 {ACPI_DMT_UINT16, ACPI_IVRS1_OFFSET (AuxData), "Auxiliary Data", 0}, 539 {ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (Reserved), "Reserved", 0}, 540 {ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (StartAddress), "Start Address", 0}, 541 {ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (MemoryLength), "Memory Length", 0}, 542 ACPI_DMT_TERMINATOR 543 }; 544 545 /* Device entry header for IVHD block */ 546 547 #define ACPI_DMT_IVRS_DE_HEADER \ 548 {ACPI_DMT_IVRS_DE, ACPI_IVRSD_OFFSET (Type), "Subtable Type", 0}, \ 549 {ACPI_DMT_UINT16, ACPI_IVRSD_OFFSET (Id), "Device ID", 0}, \ 550 {ACPI_DMT_UINT8, ACPI_IVRSD_OFFSET (DataSetting), "Data Setting (decoded below)", 0}, \ 551 {ACPI_DMT_FLAG0, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "INITPass", 0}, \ 552 {ACPI_DMT_FLAG1, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "EIntPass", 0}, \ 553 {ACPI_DMT_FLAG2, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "NMIPass", 0}, \ 554 {ACPI_DMT_FLAG3, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "Reserved", 0}, \ 555 {ACPI_DMT_FLAGS4, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "System MGMT", 0}, \ 556 {ACPI_DMT_FLAG6, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "LINT0 Pass", 0}, \ 557 {ACPI_DMT_FLAG7, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "LINT1 Pass", 0} 558 559 /* 4-byte device entry (Types 1,2,3,4) */ 560 561 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs4[] = 562 { 563 ACPI_DMT_IVRS_DE_HEADER, 564 ACPI_DMT_TERMINATOR 565 }; 566 567 /* 8-byte device entry (Type Alias Select, Alias Start of Range) */ 568 569 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8a[] = 570 { 571 ACPI_DMT_IVRS_DE_HEADER, 572 {ACPI_DMT_UINT8, ACPI_IVRS8A_OFFSET (Reserved1), "Reserved", 0}, 573 {ACPI_DMT_UINT16, ACPI_IVRS8A_OFFSET (UsedId), "Source Used Device ID", 0}, 574 {ACPI_DMT_UINT8, ACPI_IVRS8A_OFFSET (Reserved2), "Reserved", 0}, 575 ACPI_DMT_TERMINATOR 576 }; 577 578 /* 8-byte device entry (Type Extended Select, Extended Start of Range) */ 579 580 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8b[] = 581 { 582 ACPI_DMT_IVRS_DE_HEADER, 583 {ACPI_DMT_UINT32, ACPI_IVRS8B_OFFSET (ExtendedData), "Extended Data", 0}, 584 ACPI_DMT_TERMINATOR 585 }; 586 587 /* 8-byte device entry (Type Special Device) */ 588 589 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8c[] = 590 { 591 ACPI_DMT_IVRS_DE_HEADER, 592 {ACPI_DMT_UINT8, ACPI_IVRS8C_OFFSET (Handle), "Handle", 0}, 593 {ACPI_DMT_UINT16, ACPI_IVRS8C_OFFSET (UsedId), "Source Used Device ID", 0}, 594 {ACPI_DMT_UINT8, ACPI_IVRS8C_OFFSET (Variety), "Variety", 0}, 595 ACPI_DMT_TERMINATOR 596 }; 597 598 /* Variable-length Device Entry Type 0xF0 */ 599 600 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHid[] = 601 { 602 ACPI_DMT_IVRS_DE_HEADER, 603 ACPI_DMT_TERMINATOR 604 }; 605 606 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsUidString[] = 607 { 608 {ACPI_DMT_UINT8, 0, "UID Format", DT_DESCRIBES_OPTIONAL}, 609 {ACPI_DMT_UINT8, 1, "UID Length", DT_DESCRIBES_OPTIONAL}, 610 {ACPI_DMT_IVRS_UNTERMINATED_STRING, 2, "UID", DT_OPTIONAL}, 611 ACPI_DMT_TERMINATOR 612 }; 613 614 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsUidInteger[] = 615 { 616 {ACPI_DMT_UINT8, 0, "UID Format", DT_DESCRIBES_OPTIONAL}, 617 {ACPI_DMT_UINT8, 1, "UID Length", DT_DESCRIBES_OPTIONAL}, 618 {ACPI_DMT_UINT64, 2, "UID", DT_OPTIONAL}, 619 ACPI_DMT_TERMINATOR 620 }; 621 622 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHidString[] = 623 { 624 {ACPI_DMT_NAME8, 0, "ACPI HID", 0}, 625 ACPI_DMT_TERMINATOR 626 }; 627 628 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHidInteger[] = 629 { 630 {ACPI_DMT_UINT64, 0, "ACPI HID", 0}, 631 ACPI_DMT_TERMINATOR 632 }; 633 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsCidString[] = 634 { 635 {ACPI_DMT_NAME8, 0, "ACPI CID", 0}, 636 ACPI_DMT_TERMINATOR 637 }; 638 639 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsCidInteger[] = 640 { 641 {ACPI_DMT_UINT64, 0, "ACPI CID", 0}, 642 ACPI_DMT_TERMINATOR 643 }; 644 645 646 /******************************************************************************* 647 * 648 * LPIT - Low Power Idle Table 649 * 650 ******************************************************************************/ 651 652 /* Main table consists only of the standard ACPI table header */ 653 654 /* Common Subtable header (one per Subtable) */ 655 656 ACPI_DMTABLE_INFO AcpiDmTableInfoLpitHdr[] = 657 { 658 {ACPI_DMT_LPIT, ACPI_LPITH_OFFSET (Type), "Subtable Type", 0}, 659 {ACPI_DMT_UINT32, ACPI_LPITH_OFFSET (Length), "Length", DT_LENGTH}, 660 {ACPI_DMT_UINT16, ACPI_LPITH_OFFSET (UniqueId), "Unique ID", 0}, 661 {ACPI_DMT_UINT16, ACPI_LPITH_OFFSET (Reserved), "Reserved", 0}, 662 {ACPI_DMT_UINT32, ACPI_LPITH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 663 {ACPI_DMT_FLAG0, ACPI_LPITH_FLAG_OFFSET (Flags, 0), "State Disabled", 0}, 664 {ACPI_DMT_FLAG1, ACPI_LPITH_FLAG_OFFSET (Flags, 0), "No Counter", 0}, 665 ACPI_DMT_TERMINATOR 666 }; 667 668 /* LPIT Subtables */ 669 670 /* 0: Native C-state */ 671 672 ACPI_DMTABLE_INFO AcpiDmTableInfoLpit0[] = 673 { 674 {ACPI_DMT_GAS, ACPI_LPIT0_OFFSET (EntryTrigger), "Entry Trigger", 0}, 675 {ACPI_DMT_UINT32, ACPI_LPIT0_OFFSET (Residency), "Residency", 0}, 676 {ACPI_DMT_UINT32, ACPI_LPIT0_OFFSET (Latency), "Latency", 0}, 677 {ACPI_DMT_GAS, ACPI_LPIT0_OFFSET (ResidencyCounter), "Residency Counter", 0}, 678 {ACPI_DMT_UINT64, ACPI_LPIT0_OFFSET (CounterFrequency), "Counter Frequency", 0}, 679 ACPI_DMT_TERMINATOR 680 }; 681 /******************************************************************************* 682 * 683 * MADT - Multiple APIC Description Table and subtables 684 * 685 ******************************************************************************/ 686 687 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt[] = 688 { 689 {ACPI_DMT_UINT32, ACPI_MADT_OFFSET (Address), "Local Apic Address", 0}, 690 {ACPI_DMT_UINT32, ACPI_MADT_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 691 {ACPI_DMT_FLAG0, ACPI_MADT_FLAG_OFFSET (Flags,0), "PC-AT Compatibility", 0}, 692 ACPI_DMT_TERMINATOR 693 }; 694 695 /* Common Subtable header (one per Subtable) */ 696 697 ACPI_DMTABLE_INFO AcpiDmTableInfoMadtHdr[] = 698 { 699 {ACPI_DMT_MADT, ACPI_MADTH_OFFSET (Type), "Subtable Type", 0}, 700 {ACPI_DMT_UINT8, ACPI_MADTH_OFFSET (Length), "Length", DT_LENGTH}, 701 ACPI_DMT_TERMINATOR 702 }; 703 704 /* MADT Subtables */ 705 706 /* 0: processor APIC */ 707 708 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt0[] = 709 { 710 {ACPI_DMT_UINT8, ACPI_MADT0_OFFSET (ProcessorId), "Processor ID", 0}, 711 {ACPI_DMT_UINT8, ACPI_MADT0_OFFSET (Id), "Local Apic ID", 0}, 712 {ACPI_DMT_UINT32, ACPI_MADT0_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG}, 713 {ACPI_DMT_FLAG0, ACPI_MADT0_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0}, 714 {ACPI_DMT_FLAG1, ACPI_MADT0_FLAG_OFFSET (LapicFlags,0), "Runtime Online Capable", 0}, 715 ACPI_DMT_TERMINATOR 716 }; 717 718 /* 1: IO APIC */ 719 720 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt1[] = 721 { 722 {ACPI_DMT_UINT8, ACPI_MADT1_OFFSET (Id), "I/O Apic ID", 0}, 723 {ACPI_DMT_UINT8, ACPI_MADT1_OFFSET (Reserved), "Reserved", 0}, 724 {ACPI_DMT_UINT32, ACPI_MADT1_OFFSET (Address), "Address", 0}, 725 {ACPI_DMT_UINT32, ACPI_MADT1_OFFSET (GlobalIrqBase), "Interrupt", 0}, 726 ACPI_DMT_TERMINATOR 727 }; 728 729 /* 2: Interrupt Override */ 730 731 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt2[] = 732 { 733 {ACPI_DMT_UINT8, ACPI_MADT2_OFFSET (Bus), "Bus", 0}, 734 {ACPI_DMT_UINT8, ACPI_MADT2_OFFSET (SourceIrq), "Source", 0}, 735 {ACPI_DMT_UINT32, ACPI_MADT2_OFFSET (GlobalIrq), "Interrupt", 0}, 736 {ACPI_DMT_UINT16, ACPI_MADT2_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 737 {ACPI_DMT_FLAGS0, ACPI_MADT2_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 738 {ACPI_DMT_FLAGS2, ACPI_MADT2_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 739 ACPI_DMT_TERMINATOR 740 }; 741 742 /* 3: NMI Sources */ 743 744 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt3[] = 745 { 746 {ACPI_DMT_UINT16, ACPI_MADT3_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 747 {ACPI_DMT_FLAGS0, ACPI_MADT3_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 748 {ACPI_DMT_FLAGS2, ACPI_MADT3_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 749 {ACPI_DMT_UINT32, ACPI_MADT3_OFFSET (GlobalIrq), "Interrupt", 0}, 750 ACPI_DMT_TERMINATOR 751 }; 752 753 /* 4: Local APIC NMI */ 754 755 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt4[] = 756 { 757 {ACPI_DMT_UINT8, ACPI_MADT4_OFFSET (ProcessorId), "Processor ID", 0}, 758 {ACPI_DMT_UINT16, ACPI_MADT4_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 759 {ACPI_DMT_FLAGS0, ACPI_MADT4_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 760 {ACPI_DMT_FLAGS2, ACPI_MADT4_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 761 {ACPI_DMT_UINT8, ACPI_MADT4_OFFSET (Lint), "Interrupt Input LINT", 0}, 762 ACPI_DMT_TERMINATOR 763 }; 764 765 /* 5: Address Override */ 766 767 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt5[] = 768 { 769 {ACPI_DMT_UINT16, ACPI_MADT5_OFFSET (Reserved), "Reserved", 0}, 770 {ACPI_DMT_UINT64, ACPI_MADT5_OFFSET (Address), "APIC Address", 0}, 771 ACPI_DMT_TERMINATOR 772 }; 773 774 /* 6: I/O Sapic */ 775 776 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt6[] = 777 { 778 {ACPI_DMT_UINT8, ACPI_MADT6_OFFSET (Id), "I/O Sapic ID", 0}, 779 {ACPI_DMT_UINT8, ACPI_MADT6_OFFSET (Reserved), "Reserved", 0}, 780 {ACPI_DMT_UINT32, ACPI_MADT6_OFFSET (GlobalIrqBase), "Interrupt Base", 0}, 781 {ACPI_DMT_UINT64, ACPI_MADT6_OFFSET (Address), "Address", 0}, 782 ACPI_DMT_TERMINATOR 783 }; 784 785 /* 7: Local Sapic */ 786 787 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt7[] = 788 { 789 {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (ProcessorId), "Processor ID", 0}, 790 {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (Id), "Local Sapic ID", 0}, 791 {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (Eid), "Local Sapic EID", 0}, 792 {ACPI_DMT_UINT24, ACPI_MADT7_OFFSET (Reserved[0]), "Reserved", 0}, 793 {ACPI_DMT_UINT32, ACPI_MADT7_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG}, 794 {ACPI_DMT_FLAG0, ACPI_MADT7_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0}, 795 {ACPI_DMT_UINT32, ACPI_MADT7_OFFSET (Uid), "Processor UID", 0}, 796 {ACPI_DMT_STRING, ACPI_MADT7_OFFSET (UidString[0]), "Processor UID String", 0}, 797 ACPI_DMT_TERMINATOR 798 }; 799 800 /* 8: Platform Interrupt Source */ 801 802 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt8[] = 803 { 804 {ACPI_DMT_UINT16, ACPI_MADT8_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 805 {ACPI_DMT_FLAGS0, ACPI_MADT8_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 806 {ACPI_DMT_FLAGS2, ACPI_MADT8_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 807 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Type), "InterruptType", 0}, 808 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Id), "Processor ID", 0}, 809 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Eid), "Processor EID", 0}, 810 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (IoSapicVector), "I/O Sapic Vector", 0}, 811 {ACPI_DMT_UINT32, ACPI_MADT8_OFFSET (GlobalIrq), "Interrupt", 0}, 812 {ACPI_DMT_UINT32, ACPI_MADT8_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 813 {ACPI_DMT_FLAG0, ACPI_MADT8_OFFSET (Flags), "CPEI Override", 0}, 814 ACPI_DMT_TERMINATOR 815 }; 816 817 /* 9: Processor Local X2_APIC (ACPI 4.0) */ 818 819 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt9[] = 820 { 821 {ACPI_DMT_UINT16, ACPI_MADT9_OFFSET (Reserved), "Reserved", 0}, 822 {ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (LocalApicId), "Processor x2Apic ID", 0}, 823 {ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG}, 824 {ACPI_DMT_FLAG0, ACPI_MADT9_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0}, 825 {ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (Uid), "Processor UID", 0}, 826 ACPI_DMT_TERMINATOR 827 }; 828 829 /* 10: Local X2_APIC NMI (ACPI 4.0) */ 830 831 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt10[] = 832 { 833 {ACPI_DMT_UINT16, ACPI_MADT10_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 834 {ACPI_DMT_FLAGS0, ACPI_MADT10_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 835 {ACPI_DMT_FLAGS2, ACPI_MADT10_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 836 {ACPI_DMT_UINT32, ACPI_MADT10_OFFSET (Uid), "Processor UID", 0}, 837 {ACPI_DMT_UINT8, ACPI_MADT10_OFFSET (Lint), "Interrupt Input LINT", 0}, 838 {ACPI_DMT_UINT24, ACPI_MADT10_OFFSET (Reserved[0]), "Reserved", 0}, 839 ACPI_DMT_TERMINATOR 840 }; 841 842 /* 11: Generic Interrupt Controller (ACPI 5.0) */ 843 844 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt11[] = 845 { 846 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (Reserved), "Reserved", 0}, 847 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (CpuInterfaceNumber), "CPU Interface Number", 0}, 848 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Uid), "Processor UID", 0}, 849 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 850 {ACPI_DMT_FLAG0, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Processor Enabled", 0}, 851 {ACPI_DMT_FLAG1, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Performance Interrupt Trigger Mode", 0}, 852 {ACPI_DMT_FLAG2, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Virtual GIC Interrupt Trigger Mode", 0}, 853 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (ParkingVersion), "Parking Protocol Version", 0}, 854 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (PerformanceInterrupt), "Performance Interrupt", 0}, 855 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ParkedAddress), "Parked Address", 0}, 856 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (BaseAddress), "Base Address", 0}, 857 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicvBaseAddress), "Virtual GIC Base Address", 0}, 858 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GichBaseAddress), "Hypervisor GIC Base Address", 0}, 859 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (VgicInterrupt), "Virtual GIC Interrupt", 0}, 860 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicrBaseAddress), "Redistributor Base Address", 0}, 861 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ArmMpidr), "ARM MPIDR", 0}, 862 {ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (EfficiencyClass), "Efficiency Class", 0}, 863 {ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (Reserved2[0]), "Reserved", 0}, 864 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (SpeInterrupt), "SPE Overflow Interrupt", 0}, 865 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (TrbeInterrupt), "TRBE Interrupt", 0}, 866 ACPI_DMT_TERMINATOR 867 }; 868 869 /* 12: Generic Interrupt Distributor (ACPI 5.0) */ 870 871 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt12[] = 872 { 873 {ACPI_DMT_UINT16, ACPI_MADT12_OFFSET (Reserved), "Reserved", 0}, 874 {ACPI_DMT_UINT32, ACPI_MADT12_OFFSET (GicId), "Local GIC Hardware ID", 0}, 875 {ACPI_DMT_UINT64, ACPI_MADT12_OFFSET (BaseAddress), "Base Address", 0}, 876 {ACPI_DMT_UINT32, ACPI_MADT12_OFFSET (GlobalIrqBase), "Interrupt Base", 0}, 877 {ACPI_DMT_UINT8, ACPI_MADT12_OFFSET (Version), "Version", 0}, 878 {ACPI_DMT_UINT24, ACPI_MADT12_OFFSET (Reserved2[0]), "Reserved", 0}, 879 ACPI_DMT_TERMINATOR 880 }; 881 882 /* 13: Generic MSI Frame (ACPI 5.1) */ 883 884 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt13[] = 885 { 886 {ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (Reserved), "Reserved", 0}, 887 {ACPI_DMT_UINT32, ACPI_MADT13_OFFSET (MsiFrameId), "MSI Frame ID", 0}, 888 {ACPI_DMT_UINT64, ACPI_MADT13_OFFSET (BaseAddress), "Base Address", 0}, 889 {ACPI_DMT_UINT32, ACPI_MADT13_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 890 {ACPI_DMT_FLAG0, ACPI_MADT13_FLAG_OFFSET (Flags,0), "Select SPI", 0}, 891 {ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (SpiCount), "SPI Count", 0}, 892 {ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (SpiBase), "SPI Base", 0}, 893 ACPI_DMT_TERMINATOR 894 }; 895 896 /* 14: Generic Redistributor (ACPI 5.1) */ 897 898 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt14[] = 899 { 900 {ACPI_DMT_UINT16, ACPI_MADT14_OFFSET (Reserved), "Reserved", 0}, 901 {ACPI_DMT_UINT64, ACPI_MADT14_OFFSET (BaseAddress), "Base Address", 0}, 902 {ACPI_DMT_UINT32, ACPI_MADT14_OFFSET (Length), "Length", 0}, 903 ACPI_DMT_TERMINATOR 904 }; 905 906 /* 15: Generic Translator (ACPI 6.0) */ 907 908 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt15[] = 909 { 910 {ACPI_DMT_UINT16, ACPI_MADT15_OFFSET (Reserved), "Reserved", 0}, 911 {ACPI_DMT_UINT32, ACPI_MADT15_OFFSET (TranslationId), "Translation ID", 0}, 912 {ACPI_DMT_UINT64, ACPI_MADT15_OFFSET (BaseAddress), "Base Address", 0}, 913 {ACPI_DMT_UINT32, ACPI_MADT15_OFFSET (Reserved2), "Reserved", 0}, 914 ACPI_DMT_TERMINATOR 915 }; 916 917 /* 16: Multiprocessor wakeup structure (ACPI 6.4) */ 918 919 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt16[] = 920 { 921 {ACPI_DMT_UINT16, ACPI_MADT16_OFFSET (MailboxVersion), "Mailbox Version", 0}, 922 {ACPI_DMT_UINT32, ACPI_MADT16_OFFSET (Reserved), "Reserved", 0}, 923 {ACPI_DMT_UINT64, ACPI_MADT16_OFFSET (BaseAddress), "Mailbox Address", 0}, 924 ACPI_DMT_TERMINATOR 925 }; 926 927 /* 17: core interrupt controller */ 928 929 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt17[] = 930 { 931 {ACPI_DMT_UINT8, ACPI_MADT17_OFFSET (Version), "Version", 0}, 932 {ACPI_DMT_UINT32, ACPI_MADT17_OFFSET (ProcessorId), "ProcessorId", 0}, 933 {ACPI_DMT_UINT32, ACPI_MADT17_OFFSET (CoreId), "CoreId", 0}, 934 {ACPI_DMT_UINT32, ACPI_MADT17_OFFSET (Flags), "Flags", 0}, 935 ACPI_DMT_TERMINATOR 936 }; 937 938 /* 18: Legacy I/O interrupt controller */ 939 940 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt18[] = 941 { 942 {ACPI_DMT_UINT8, ACPI_MADT18_OFFSET (Version), "Version", 0}, 943 {ACPI_DMT_UINT64, ACPI_MADT18_OFFSET (Address), "Address", 0}, 944 {ACPI_DMT_UINT16, ACPI_MADT18_OFFSET (Size), "Size", 0}, 945 {ACPI_DMT_UINT16, ACPI_MADT18_OFFSET (Cascade), "Cascade", 0}, 946 {ACPI_DMT_UINT64, ACPI_MADT18_OFFSET (CascadeMap), "CascadeMap", 0}, 947 ACPI_DMT_TERMINATOR 948 }; 949 950 /* 19: HT interrupt controller */ 951 952 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt19[] = 953 { 954 {ACPI_DMT_UINT8, ACPI_MADT19_OFFSET (Version), "Version", 0}, 955 {ACPI_DMT_UINT64, ACPI_MADT19_OFFSET (Address), "Address", 0}, 956 {ACPI_DMT_UINT16, ACPI_MADT19_OFFSET (Size), "Size", 0}, 957 {ACPI_DMT_UINT64, ACPI_MADT19_OFFSET (Cascade), "Cascade", 0}, 958 ACPI_DMT_TERMINATOR 959 }; 960 961 /* 20: Extend I/O interrupt controller */ 962 963 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt20[] = 964 { 965 {ACPI_DMT_UINT8, ACPI_MADT20_OFFSET (Version), "Version", 0}, 966 {ACPI_DMT_UINT8, ACPI_MADT20_OFFSET (Cascade), "Cascade", 0}, 967 {ACPI_DMT_UINT8, ACPI_MADT20_OFFSET (Node), "Node", 0}, 968 {ACPI_DMT_UINT64, ACPI_MADT20_OFFSET (NodeMap), "NodeMap", 0}, 969 ACPI_DMT_TERMINATOR 970 }; 971 972 /* 21: MSI controller */ 973 974 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt21[] = 975 { 976 {ACPI_DMT_UINT8, ACPI_MADT21_OFFSET (Version), "Version", 0}, 977 {ACPI_DMT_UINT64, ACPI_MADT21_OFFSET (MsgAddress), "MsgAddress", 0}, 978 {ACPI_DMT_UINT32, ACPI_MADT21_OFFSET (Start), "Start", 0}, 979 {ACPI_DMT_UINT32, ACPI_MADT21_OFFSET (Count), "Count", 0}, 980 ACPI_DMT_TERMINATOR 981 }; 982 983 /* 22: BIO interrupt controller */ 984 985 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt22[] = 986 { 987 {ACPI_DMT_UINT8, ACPI_MADT22_OFFSET (Version), "Version", 0}, 988 {ACPI_DMT_UINT64, ACPI_MADT22_OFFSET (Address), "Address", 0}, 989 {ACPI_DMT_UINT16, ACPI_MADT22_OFFSET (Size), "Size", 0}, 990 {ACPI_DMT_UINT16, ACPI_MADT22_OFFSET (Id), "Id", 0}, 991 {ACPI_DMT_UINT16, ACPI_MADT22_OFFSET (GsiBase), "GsiBase", 0}, 992 ACPI_DMT_TERMINATOR 993 }; 994 995 /* 23: LPC interrupt controller */ 996 997 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt23[] = 998 { 999 {ACPI_DMT_UINT8, ACPI_MADT23_OFFSET (Version), "Version", 0}, 1000 {ACPI_DMT_UINT64, ACPI_MADT23_OFFSET (Address), "Address", 0}, 1001 {ACPI_DMT_UINT16, ACPI_MADT23_OFFSET (Size), "Size", 0}, 1002 {ACPI_DMT_UINT8, ACPI_MADT23_OFFSET (Cascade), "Cascade", 0}, 1003 ACPI_DMT_TERMINATOR 1004 }; 1005 1006 /* 24: RINTC interrupt controller */ 1007 1008 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt24[] = 1009 { 1010 {ACPI_DMT_UINT8, ACPI_MADT24_OFFSET (Version), "Version", 0}, 1011 {ACPI_DMT_UINT8, ACPI_MADT24_OFFSET (Reserved), "Reserved", 0}, 1012 {ACPI_DMT_UINT32, ACPI_MADT24_OFFSET (Flags), "Flags", 0}, 1013 {ACPI_DMT_UINT64, ACPI_MADT24_OFFSET (HartId), "HartId", 0}, 1014 {ACPI_DMT_UINT32, ACPI_MADT24_OFFSET (Uid), "Uid", 0}, 1015 {ACPI_DMT_UINT32, ACPI_MADT24_OFFSET (ExtIntcId), "ExtIntcId", 0}, 1016 {ACPI_DMT_UINT64, ACPI_MADT24_OFFSET (ImsicAddr), "ImsicAddr", 0}, 1017 {ACPI_DMT_UINT32, ACPI_MADT24_OFFSET (ImsicSize), "ImsicSize", 0}, 1018 ACPI_DMT_TERMINATOR 1019 }; 1020 1021 /* 25: RISC-V IMSIC interrupt controller */ 1022 1023 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt25[] = 1024 { 1025 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (Version), "Version", 0}, 1026 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (Reserved), "Reserved", 0}, 1027 {ACPI_DMT_UINT32, ACPI_MADT25_OFFSET (Flags), "Flags", 0}, 1028 {ACPI_DMT_UINT16, ACPI_MADT25_OFFSET (NumIds), "NumIds", 0}, 1029 {ACPI_DMT_UINT16, ACPI_MADT25_OFFSET (NumGuestIds), "NumGuestIds", 0}, 1030 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (GuestIndexBits), "GuestIndexBits", 0}, 1031 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (HartIndexBits), "HartIndexBits", 0}, 1032 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (GroupIndexBits), "GroupIndexBits", 0}, 1033 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (GroupIndexShift), "GroupIndexShift", 0}, 1034 ACPI_DMT_TERMINATOR 1035 }; 1036 1037 /* 26: RISC-V APLIC interrupt controller */ 1038 1039 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt26[] = 1040 { 1041 {ACPI_DMT_UINT8, ACPI_MADT26_OFFSET (Version), "Version", 0}, 1042 {ACPI_DMT_UINT8, ACPI_MADT26_OFFSET (Id), "Id", 0}, 1043 {ACPI_DMT_UINT32, ACPI_MADT26_OFFSET (Flags), "Flags", 0}, 1044 {ACPI_DMT_UINT64, ACPI_MADT26_OFFSET (HwId), "HwId", 0}, 1045 {ACPI_DMT_UINT16, ACPI_MADT26_OFFSET (NumIdcs), "NumIdcs", 0}, 1046 {ACPI_DMT_UINT16, ACPI_MADT26_OFFSET (NumSources), "NumSources", 0}, 1047 {ACPI_DMT_UINT32, ACPI_MADT26_OFFSET (GsiBase), "GsiBase", 0}, 1048 {ACPI_DMT_UINT64, ACPI_MADT26_OFFSET (BaseAddr), "BaseAddr", 0}, 1049 {ACPI_DMT_UINT32, ACPI_MADT26_OFFSET (Size), "Size", 0}, 1050 ACPI_DMT_TERMINATOR 1051 }; 1052 1053 /* 27: RISC-V PLIC interrupt controller */ 1054 1055 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt27[] = 1056 { 1057 {ACPI_DMT_UINT8, ACPI_MADT27_OFFSET (Version), "Version", 0}, 1058 {ACPI_DMT_UINT8, ACPI_MADT27_OFFSET (Id), "Id", 0}, 1059 {ACPI_DMT_UINT64, ACPI_MADT27_OFFSET (HwId), "HwId", 0}, 1060 {ACPI_DMT_UINT16, ACPI_MADT27_OFFSET (NumIrqs), "NumIrqs", 0}, 1061 {ACPI_DMT_UINT16, ACPI_MADT27_OFFSET (MaxPrio), "MaxPrio", 0}, 1062 {ACPI_DMT_UINT32, ACPI_MADT27_OFFSET (Flags), "Flags", 0}, 1063 {ACPI_DMT_UINT32, ACPI_MADT27_OFFSET (Size), "Size", 0}, 1064 {ACPI_DMT_UINT64, ACPI_MADT27_OFFSET (BaseAddr), "BaseAddr", 0}, 1065 {ACPI_DMT_UINT32, ACPI_MADT27_OFFSET (GsiBase), "GsiBase", 0}, 1066 ACPI_DMT_TERMINATOR 1067 }; 1068 1069 /* 128: OEM data structure */ 1070 1071 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt128[] = 1072 { 1073 {ACPI_DMT_RAW_BUFFER, 0, "OEM Data", 0}, 1074 ACPI_DMT_TERMINATOR 1075 }; 1076 1077 /******************************************************************************* 1078 * 1079 * MCFG - PCI Memory Mapped Configuration table and Subtable 1080 * 1081 ******************************************************************************/ 1082 1083 ACPI_DMTABLE_INFO AcpiDmTableInfoMcfg[] = 1084 { 1085 {ACPI_DMT_UINT64, ACPI_MCFG_OFFSET (Reserved[0]), "Reserved", 0}, 1086 ACPI_DMT_TERMINATOR 1087 }; 1088 1089 ACPI_DMTABLE_INFO AcpiDmTableInfoMcfg0[] = 1090 { 1091 {ACPI_DMT_UINT64, ACPI_MCFG0_OFFSET (Address), "Base Address", 0}, 1092 {ACPI_DMT_UINT16, ACPI_MCFG0_OFFSET (PciSegment), "Segment Group Number", 0}, 1093 {ACPI_DMT_UINT8, ACPI_MCFG0_OFFSET (StartBusNumber), "Start Bus Number", 0}, 1094 {ACPI_DMT_UINT8, ACPI_MCFG0_OFFSET (EndBusNumber), "End Bus Number", 0}, 1095 {ACPI_DMT_UINT32, ACPI_MCFG0_OFFSET (Reserved), "Reserved", 0}, 1096 ACPI_DMT_TERMINATOR 1097 }; 1098 1099 1100 /******************************************************************************* 1101 * 1102 * MCHI - Management Controller Host Interface table 1103 * 1104 ******************************************************************************/ 1105 1106 ACPI_DMTABLE_INFO AcpiDmTableInfoMchi[] = 1107 { 1108 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (InterfaceType), "Interface Type", 0}, 1109 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (Protocol), "Protocol", 0}, 1110 {ACPI_DMT_UINT64, ACPI_MCHI_OFFSET (ProtocolData), "Protocol Data", 0}, 1111 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (InterruptType), "Interrupt Type", 0}, 1112 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (Gpe), "Gpe", 0}, 1113 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciDeviceFlag), "Pci Device Flag", 0}, 1114 {ACPI_DMT_UINT32, ACPI_MCHI_OFFSET (GlobalInterrupt), "Global Interrupt", 0}, 1115 {ACPI_DMT_GAS, ACPI_MCHI_OFFSET (ControlRegister), "Control Register", 0}, 1116 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciSegment), "Pci Segment", 0}, 1117 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciBus), "Pci Bus", 0}, 1118 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciDevice), "Pci Device", 0}, 1119 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciFunction), "Pci Function", 0}, 1120 ACPI_DMT_TERMINATOR 1121 }; 1122 1123 /******************************************************************************* 1124 * 1125 * MPAM - Memory System Resource Partitioning and Monitoring Tables 1126 * Arm's DEN0065 MPAM ACPI 2.0. December 2022. 1127 ******************************************************************************/ 1128 1129 /* MPAM subtables */ 1130 1131 /* 0: MPAM Resource Node Structure - A root MSC table. 1132 * Arm's DEN0065 MPAM ACPI 2.0. Table 4: MPAM MSC node body. 1133 */ 1134 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam0[] = 1135 { 1136 {ACPI_DMT_UINT16, ACPI_MPAM0_OFFSET (Length), "Length", 0}, 1137 {ACPI_DMT_UINT8, ACPI_MPAM0_OFFSET (InterfaceType), "Interface type", 0}, 1138 {ACPI_DMT_UINT8, ACPI_MPAM0_OFFSET (Reserved), "Reserved", 0}, 1139 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (Identifier), "Identifier", 0}, 1140 {ACPI_DMT_UINT64, ACPI_MPAM0_OFFSET (BaseAddress), "Base address", 0}, 1141 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (MMIOSize), "MMIO size", 0}, 1142 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (OverflowInterrupt), "Overflow interrupt", 0}, 1143 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (OverflowInterruptFlags), "Overflow interrupt flags", 0}, 1144 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (Reserved1), "Reserved1", 0}, 1145 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (OverflowInterruptAffinity), "Overflow interrupt affinity", 0}, 1146 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (ErrorInterrupt), "Error interrupt", 0}, 1147 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (ErrorInterruptFlags), "Error interrupt flags", 0}, 1148 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (Reserved2), "Reserved2", 0}, 1149 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (ErrorInterruptAffinity), "Error interrupt affinity", 0}, 1150 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (MaxNrdyUsec), "MAX_NRDY_USEC", 0}, 1151 {ACPI_DMT_NAME8, ACPI_MPAM0_OFFSET (HardwareIdLinkedDevice), "Hardware ID of linked device", 0}, 1152 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (InstanceIdLinkedDevice), "Instance ID of linked device", 0}, 1153 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (NumResouceNodes), "Number of resource nodes", 0}, 1154 1155 ACPI_DMT_TERMINATOR 1156 }; 1157 1158 /* 1: MPAM Resource (RIS) Node Structure - A subtable of MSC Nodes. 1159 * Arm's DEN0065 MPAM ACPI 2.0. Table 9: Resource node. 1160 */ 1161 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1[] = 1162 { 1163 {ACPI_DMT_UINT32, ACPI_MPAM1_OFFSET (Identifier), "Identifier", 0}, 1164 {ACPI_DMT_UINT8, ACPI_MPAM1_OFFSET (RISIndex), "RIS Index", 0}, 1165 {ACPI_DMT_UINT16, ACPI_MPAM1_OFFSET (Reserved1), "Reserved1", 0}, 1166 {ACPI_DMT_MPAM_LOCATOR, ACPI_MPAM1_OFFSET (LocatorType), "Locator type", 0}, 1167 ACPI_DMT_TERMINATOR 1168 }; 1169 1170 /* An RIS field part of the RIS subtable */ 1171 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1Deps[] = 1172 { 1173 {ACPI_DMT_UINT32, 0, "Number of functional dependencies", 0}, 1174 ACPI_DMT_TERMINATOR 1175 }; 1176 1177 /* 1A: MPAM Processor cache locator descriptor. A subtable of RIS. 1178 * Arm's DEN0065 MPAM ACPI 2.0. Table 13. 1179 */ 1180 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1A[] = 1181 { 1182 {ACPI_DMT_UINT64, ACPI_MPAM1A_OFFSET (CacheReference), "Cache reference", 0}, 1183 {ACPI_DMT_UINT32, ACPI_MPAM1A_OFFSET (Reserved), "Reserved", 0}, 1184 }; 1185 1186 /* 1B: MPAM Memory locator descriptor. A subtable of RIS. 1187 * Arm's DEN0065 MPAM ACPI 2.0. Table 14. 1188 */ 1189 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1B[] = 1190 { 1191 {ACPI_DMT_UINT64, ACPI_MPAM1B_OFFSET (ProximityDomain), "Proximity domain", 0}, 1192 {ACPI_DMT_UINT32, ACPI_MPAM1B_OFFSET (Reserved), "Reserved", 0}, 1193 }; 1194 1195 /* 1C: MPAM SMMU locator descriptor. A subtable of RIS. 1196 * Arm's DEN0065 MPAM ACPI 2.0. Table 15. 1197 */ 1198 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1C[] = 1199 { 1200 {ACPI_DMT_UINT64, ACPI_MPAM1C_OFFSET (SmmuInterface), "SMMU Interface", 0}, 1201 {ACPI_DMT_UINT32, ACPI_MPAM1C_OFFSET (Reserved), "Reserved", 0}, 1202 }; 1203 1204 /* 1D: MPAM Memory-side cache locator descriptor. A subtable of RIS. 1205 * Arm's DEN0065 MPAM ACPI 2.0. Table 16. 1206 */ 1207 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1D[] = 1208 { 1209 {ACPI_DMT_UINT56, ACPI_MPAM1D_OFFSET (Level), "Reserved", 0}, 1210 {ACPI_DMT_UINT8, ACPI_MPAM1D_OFFSET (Level), "Level", 0}, 1211 {ACPI_DMT_UINT32, ACPI_MPAM1D_OFFSET (Reference), "Reference", 0}, 1212 }; 1213 1214 /* 1E: MPAM ACPI device locator descriptor. A subtable of RIS. 1215 * Arm's DEN0065 MPAM ACPI 2.0. Table 17. 1216 */ 1217 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1E[] = 1218 { 1219 {ACPI_DMT_UINT64, ACPI_MPAM1E_OFFSET (AcpiHwId), "ACPI Hardware ID", 0}, 1220 {ACPI_DMT_UINT32, ACPI_MPAM1E_OFFSET (AcpiUniqueId), "ACPI Unique ID", 0}, 1221 }; 1222 1223 /* 1F: MPAM Interconnect locator descriptor. A subtable of RIS. 1224 * Arm's DEN0065 MPAM ACPI 2.0. Table 18. 1225 */ 1226 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1F[] = 1227 { 1228 {ACPI_DMT_UINT64, ACPI_MPAM1F_OFFSET (InterConnectDescTblOff), "Interconnect descriptor table offset", 0}, 1229 {ACPI_DMT_UINT32, ACPI_MPAM1F_OFFSET (Reserved), "Reserved", 0}, 1230 }; 1231 1232 /* 1G: MPAM Locator structure. 1233 * Arm's DEN0065 MPAM ACPI 2.0. Table 12. 1234 */ 1235 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1G[] = 1236 { 1237 {ACPI_DMT_UINT64, ACPI_MPAM1G_OFFSET (Descriptor1), "Descriptor1", 0}, 1238 {ACPI_DMT_UINT32, ACPI_MPAM1G_OFFSET (Descriptor2), "Descriptor2", 0}, 1239 }; 1240 1241 /* 2: MPAM Functional dependency descriptor. 1242 * Arm's DEN0065 MPAM ACPI 2.0. Table 10. 1243 */ 1244 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam2[] = 1245 { 1246 {ACPI_DMT_UINT32, ACPI_MPAM2_OFFSET (Producer), "Producer", 0}, 1247 {ACPI_DMT_UINT32, ACPI_MPAM2_OFFSET (Reserved), "Reserved", 0}, 1248 }; 1249 1250 1251 /******************************************************************************* 1252 * 1253 * MPST - Memory Power State Table 1254 * 1255 ******************************************************************************/ 1256 1257 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst[] = 1258 { 1259 {ACPI_DMT_UINT8, ACPI_MPST_OFFSET (ChannelId), "Channel ID", 0}, 1260 {ACPI_DMT_UINT24, ACPI_MPST_OFFSET (Reserved1[0]), "Reserved", 0}, 1261 {ACPI_DMT_UINT16, ACPI_MPST_OFFSET (PowerNodeCount), "Power Node Count", 0}, 1262 {ACPI_DMT_UINT16, ACPI_MPST_OFFSET (Reserved2), "Reserved", 0}, 1263 ACPI_DMT_TERMINATOR 1264 }; 1265 1266 /* MPST subtables */ 1267 1268 /* 0: Memory Power Node Structure */ 1269 1270 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst0[] = 1271 { 1272 {ACPI_DMT_UINT8, ACPI_MPST0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1273 {ACPI_DMT_FLAG0, ACPI_MPST0_FLAG_OFFSET (Flags,0), "Node Enabled", 0}, 1274 {ACPI_DMT_FLAG1, ACPI_MPST0_FLAG_OFFSET (Flags,0), "Power Managed", 0}, 1275 {ACPI_DMT_FLAG2, ACPI_MPST0_FLAG_OFFSET (Flags,0), "Hot Plug Capable", 0}, 1276 1277 {ACPI_DMT_UINT8, ACPI_MPST0_OFFSET (Reserved1), "Reserved", 0}, 1278 {ACPI_DMT_UINT16, ACPI_MPST0_OFFSET (NodeId), "Node ID", 0}, 1279 {ACPI_DMT_UINT32, ACPI_MPST0_OFFSET (Length), "Length", 0}, 1280 {ACPI_DMT_UINT64, ACPI_MPST0_OFFSET (RangeAddress), "Range Address", 0}, 1281 {ACPI_DMT_UINT64, ACPI_MPST0_OFFSET (RangeLength), "Range Length", 0}, 1282 {ACPI_DMT_UINT32, ACPI_MPST0_OFFSET (NumPowerStates), "Num Power States", 0}, 1283 {ACPI_DMT_UINT32, ACPI_MPST0_OFFSET (NumPhysicalComponents), "Num Physical Components", 0}, 1284 ACPI_DMT_TERMINATOR 1285 }; 1286 1287 /* 0A: Sub-subtable - Memory Power State Structure (follows Memory Power Node above) */ 1288 1289 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst0A[] = 1290 { 1291 {ACPI_DMT_UINT8, ACPI_MPST0A_OFFSET (PowerState), "Power State", 0}, 1292 {ACPI_DMT_UINT8, ACPI_MPST0A_OFFSET (InfoIndex), "InfoIndex", 0}, 1293 ACPI_DMT_TERMINATOR 1294 }; 1295 1296 /* 0B: Sub-subtable - Physical Component ID Structure (follows Memory Power State(s) above) */ 1297 1298 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst0B[] = 1299 { 1300 {ACPI_DMT_UINT16, ACPI_MPST0B_OFFSET (ComponentId), "Component Id", 0}, 1301 ACPI_DMT_TERMINATOR 1302 }; 1303 1304 /* 01: Power Characteristics Count (follows all Power Node(s) above) */ 1305 1306 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst1[] = 1307 { 1308 {ACPI_DMT_UINT16, ACPI_MPST1_OFFSET (CharacteristicsCount), "Characteristics Count", 0}, 1309 {ACPI_DMT_UINT16, ACPI_MPST1_OFFSET (Reserved), "Reserved", 0}, 1310 ACPI_DMT_TERMINATOR 1311 }; 1312 1313 /* 02: Memory Power State Characteristics Structure */ 1314 1315 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst2[] = 1316 { 1317 {ACPI_DMT_UINT8, ACPI_MPST2_OFFSET (StructureId), "Structure ID", 0}, 1318 {ACPI_DMT_UINT8, ACPI_MPST2_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1319 {ACPI_DMT_FLAG0, ACPI_MPST2_FLAG_OFFSET (Flags,0), "Memory Preserved", 0}, 1320 {ACPI_DMT_FLAG1, ACPI_MPST2_FLAG_OFFSET (Flags,0), "Auto Entry", 0}, 1321 {ACPI_DMT_FLAG2, ACPI_MPST2_FLAG_OFFSET (Flags,0), "Auto Exit", 0}, 1322 1323 {ACPI_DMT_UINT16, ACPI_MPST2_OFFSET (Reserved1), "Reserved", 0}, 1324 {ACPI_DMT_UINT32, ACPI_MPST2_OFFSET (AveragePower), "Average Power", 0}, 1325 {ACPI_DMT_UINT32, ACPI_MPST2_OFFSET (PowerSaving), "Power Saving", 0}, 1326 {ACPI_DMT_UINT64, ACPI_MPST2_OFFSET (ExitLatency), "Exit Latency", 0}, 1327 {ACPI_DMT_UINT64, ACPI_MPST2_OFFSET (Reserved2), "Reserved", 0}, 1328 ACPI_DMT_TERMINATOR 1329 }; 1330 1331 1332 /******************************************************************************* 1333 * 1334 * MSCT - Maximum System Characteristics Table (ACPI 4.0) 1335 * 1336 ******************************************************************************/ 1337 1338 ACPI_DMTABLE_INFO AcpiDmTableInfoMsct[] = 1339 { 1340 {ACPI_DMT_UINT32, ACPI_MSCT_OFFSET (ProximityOffset), "Proximity Offset", 0}, 1341 {ACPI_DMT_UINT32, ACPI_MSCT_OFFSET (MaxProximityDomains), "Max Proximity Domains", 0}, 1342 {ACPI_DMT_UINT32, ACPI_MSCT_OFFSET (MaxClockDomains), "Max Clock Domains", 0}, 1343 {ACPI_DMT_UINT64, ACPI_MSCT_OFFSET (MaxAddress), "Max Physical Address", 0}, 1344 ACPI_DMT_TERMINATOR 1345 }; 1346 1347 /* Subtable - Maximum Proximity Domain Information. Version 1 */ 1348 1349 ACPI_DMTABLE_INFO AcpiDmTableInfoMsct0[] = 1350 { 1351 {ACPI_DMT_UINT8, ACPI_MSCT0_OFFSET (Revision), "Revision", 0}, 1352 {ACPI_DMT_UINT8, ACPI_MSCT0_OFFSET (Length), "Length", DT_LENGTH}, 1353 {ACPI_DMT_UINT32, ACPI_MSCT0_OFFSET (RangeStart), "Domain Range Start", 0}, 1354 {ACPI_DMT_UINT32, ACPI_MSCT0_OFFSET (RangeEnd), "Domain Range End", 0}, 1355 {ACPI_DMT_UINT32, ACPI_MSCT0_OFFSET (ProcessorCapacity), "Processor Capacity", 0}, 1356 {ACPI_DMT_UINT64, ACPI_MSCT0_OFFSET (MemoryCapacity), "Memory Capacity", 0}, 1357 ACPI_DMT_TERMINATOR 1358 }; 1359 1360 1361 /******************************************************************************* 1362 * 1363 * NFIT - NVDIMM Firmware Interface Table and Subtables - (ACPI 6.0) 1364 * 1365 ******************************************************************************/ 1366 1367 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit[] = 1368 { 1369 {ACPI_DMT_UINT32, ACPI_NFIT_OFFSET (Reserved), "Reserved", 0}, 1370 ACPI_DMT_TERMINATOR 1371 }; 1372 1373 /* Common Subtable header */ 1374 1375 ACPI_DMTABLE_INFO AcpiDmTableInfoNfitHdr[] = 1376 { 1377 {ACPI_DMT_NFIT, ACPI_NFITH_OFFSET (Type), "Subtable Type", 0}, 1378 {ACPI_DMT_UINT16, ACPI_NFITH_OFFSET (Length), "Length", DT_LENGTH}, 1379 ACPI_DMT_TERMINATOR 1380 }; 1381 1382 /* 0: System Physical Address Range Structure */ 1383 1384 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit0[] = 1385 { 1386 {ACPI_DMT_UINT16, ACPI_NFIT0_OFFSET (RangeIndex), "Range Index", 0}, 1387 {ACPI_DMT_UINT16, ACPI_NFIT0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1388 {ACPI_DMT_FLAG0, ACPI_NFIT0_FLAG_OFFSET (Flags,0), "Add/Online Operation Only", 0}, 1389 {ACPI_DMT_FLAG1, ACPI_NFIT0_FLAG_OFFSET (Flags,0), "Proximity Domain Valid", 0}, 1390 {ACPI_DMT_FLAG2, ACPI_NFIT0_FLAG_OFFSET (Flags,0), "Location Cookie Valid", 0}, 1391 {ACPI_DMT_UINT32, ACPI_NFIT0_OFFSET (Reserved), "Reserved", 0}, 1392 {ACPI_DMT_UINT32, ACPI_NFIT0_OFFSET (ProximityDomain), "Proximity Domain", 0}, 1393 {ACPI_DMT_UUID, ACPI_NFIT0_OFFSET (RangeGuid[0]), "Region Type GUID", 0}, 1394 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (Address), "Address Range Base", 0}, 1395 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (Length), "Address Range Length", 0}, 1396 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (MemoryMapping), "Memory Map Attribute", 0}, 1397 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (LocationCookie), "Location Cookie", 0}, /* ACPI 6.4 */ 1398 ACPI_DMT_TERMINATOR 1399 }; 1400 1401 /* 1: Memory Device to System Address Range Map Structure */ 1402 1403 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit1[] = 1404 { 1405 {ACPI_DMT_UINT32, ACPI_NFIT1_OFFSET (DeviceHandle), "Device Handle", 0}, 1406 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (PhysicalId), "Physical Id", 0}, 1407 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (RegionId), "Region Id", 0}, 1408 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (RangeIndex), "Range Index", 0}, 1409 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (RegionIndex), "Control Region Index", 0}, 1410 {ACPI_DMT_UINT64, ACPI_NFIT1_OFFSET (RegionSize), "Region Size", 0}, 1411 {ACPI_DMT_UINT64, ACPI_NFIT1_OFFSET (RegionOffset), "Region Offset", 0}, 1412 {ACPI_DMT_UINT64, ACPI_NFIT1_OFFSET (Address), "Address Region Base", 0}, 1413 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (InterleaveIndex), "Interleave Index", 0}, 1414 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (InterleaveWays), "Interleave Ways", 0}, 1415 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (Flags), "Flags", DT_FLAG}, 1416 {ACPI_DMT_FLAG0, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Save to device failed", 0}, 1417 {ACPI_DMT_FLAG1, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Restore from device failed", 0}, 1418 {ACPI_DMT_FLAG2, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Platform flush failed", 0}, 1419 {ACPI_DMT_FLAG3, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Device not armed", 0}, 1420 {ACPI_DMT_FLAG4, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Health events observed", 0}, 1421 {ACPI_DMT_FLAG5, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Health events enabled", 0}, 1422 {ACPI_DMT_FLAG6, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Mapping failed", 0}, 1423 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (Reserved), "Reserved", 0}, 1424 ACPI_DMT_TERMINATOR 1425 }; 1426 1427 /* 2: Interleave Structure */ 1428 1429 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit2[] = 1430 { 1431 {ACPI_DMT_UINT16, ACPI_NFIT2_OFFSET (InterleaveIndex), "Interleave Index", 0}, 1432 {ACPI_DMT_UINT16, ACPI_NFIT2_OFFSET (Reserved), "Reserved", 0}, 1433 {ACPI_DMT_UINT32, ACPI_NFIT2_OFFSET (LineCount), "Line Count", 0}, 1434 {ACPI_DMT_UINT32, ACPI_NFIT2_OFFSET (LineSize), "Line Size", 0}, 1435 ACPI_DMT_TERMINATOR 1436 }; 1437 1438 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit2a[] = 1439 { 1440 {ACPI_DMT_UINT32, 0, "Line Offset", DT_OPTIONAL}, 1441 ACPI_DMT_TERMINATOR 1442 }; 1443 1444 /* 3: SMBIOS Management Information Structure */ 1445 1446 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit3[] = 1447 { 1448 {ACPI_DMT_UINT32, ACPI_NFIT3_OFFSET (Reserved), "Reserved", 0}, 1449 ACPI_DMT_TERMINATOR 1450 }; 1451 1452 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit3a[] = 1453 { 1454 {ACPI_DMT_RAW_BUFFER, 0, "SMBIOS Table Entries", DT_OPTIONAL}, 1455 ACPI_DMT_TERMINATOR 1456 }; 1457 1458 /* 4: NVDIMM Control Region Structure */ 1459 1460 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit4[] = 1461 { 1462 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (RegionIndex), "Region Index", 0}, 1463 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (VendorId), "Vendor Id", 0}, 1464 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (DeviceId), "Device Id", 0}, 1465 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (RevisionId), "Revision Id", 0}, 1466 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (SubsystemVendorId), "Subsystem Vendor Id", 0}, 1467 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (SubsystemDeviceId), "Subsystem Device Id", 0}, 1468 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (SubsystemRevisionId), "Subsystem Revision Id", 0}, 1469 {ACPI_DMT_UINT8, ACPI_NFIT4_OFFSET (ValidFields), "Valid Fields", 0}, 1470 {ACPI_DMT_UINT8, ACPI_NFIT4_OFFSET (ManufacturingLocation), "Manufacturing Location", 0}, 1471 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (ManufacturingDate), "Manufacturing Date", 0}, 1472 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Reserved[0]), "Reserved", 0}, 1473 {ACPI_DMT_UINT32, ACPI_NFIT4_OFFSET (SerialNumber), "Serial Number", 0}, 1474 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Code), "Code", 0}, 1475 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Windows), "Window Count", 0}, 1476 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (WindowSize), "Window Size", 0}, 1477 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (CommandOffset), "Command Offset", 0}, 1478 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (CommandSize), "Command Size", 0}, 1479 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (StatusOffset), "Status Offset", 0}, 1480 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (StatusSize), "Status Size", 0}, 1481 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Flags), "Flags", DT_FLAG}, 1482 {ACPI_DMT_FLAG0, ACPI_NFIT4_FLAG_OFFSET (Flags,0), "Windows buffered", 0}, 1483 {ACPI_DMT_UINT48, ACPI_NFIT4_OFFSET (Reserved1[0]), "Reserved1", 0}, 1484 ACPI_DMT_TERMINATOR 1485 }; 1486 1487 /* 5: NVDIMM Block Data Window Region Structure */ 1488 1489 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit5[] = 1490 { 1491 {ACPI_DMT_UINT16, ACPI_NFIT5_OFFSET (RegionIndex), "Region Index", 0}, 1492 {ACPI_DMT_UINT16, ACPI_NFIT5_OFFSET (Windows), "Window Count", 0}, 1493 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (Offset), "Offset", 0}, 1494 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (Size), "Size", 0}, 1495 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (Capacity), "Capacity", 0}, 1496 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (StartAddress), "Start Address", 0}, 1497 ACPI_DMT_TERMINATOR 1498 }; 1499 1500 /* 6: Flush Hint Address Structure */ 1501 1502 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit6[] = 1503 { 1504 {ACPI_DMT_UINT32, ACPI_NFIT6_OFFSET (DeviceHandle), "Device Handle", 0}, 1505 {ACPI_DMT_UINT16, ACPI_NFIT6_OFFSET (HintCount), "Hint Count", 0}, 1506 {ACPI_DMT_UINT48, ACPI_NFIT6_OFFSET (Reserved[0]), "Reserved", 0}, 1507 ACPI_DMT_TERMINATOR 1508 }; 1509 1510 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit6a[] = 1511 { 1512 {ACPI_DMT_UINT64, 0, "Hint Address", DT_OPTIONAL}, 1513 ACPI_DMT_TERMINATOR 1514 }; 1515 1516 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit7[] = 1517 { 1518 {ACPI_DMT_UINT8, ACPI_NFIT7_OFFSET (HighestCapability), "Highest Capability", 0}, 1519 {ACPI_DMT_UINT24, ACPI_NFIT7_OFFSET (Reserved[0]), "Reserved", 0}, 1520 {ACPI_DMT_UINT32, ACPI_NFIT7_OFFSET (Capabilities), "Capabilities (decoded below)", DT_FLAG}, 1521 {ACPI_DMT_FLAG0, ACPI_NFIT7_FLAG_OFFSET (Capabilities,0), "Cache Flush to NVDIMM", 0}, 1522 {ACPI_DMT_FLAG1, ACPI_NFIT7_FLAG_OFFSET (Capabilities,0), "Memory Flush to NVDIMM", 0}, 1523 {ACPI_DMT_FLAG2, ACPI_NFIT7_FLAG_OFFSET (Capabilities,0), "Memory Mirroring", 0}, 1524 {ACPI_DMT_UINT32, ACPI_NFIT7_OFFSET (Reserved2), "Reserved", 0}, 1525 ACPI_DMT_TERMINATOR 1526 }; 1527 1528 1529 /******************************************************************************* 1530 * 1531 * PCCT - Platform Communications Channel Table (ACPI 5.0) 1532 * 1533 ******************************************************************************/ 1534 1535 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct[] = 1536 { 1537 {ACPI_DMT_UINT32, ACPI_PCCT_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1538 {ACPI_DMT_FLAG0, ACPI_PCCT_FLAG_OFFSET (Flags,0), "Platform", 0}, 1539 {ACPI_DMT_UINT64, ACPI_PCCT_OFFSET (Reserved), "Reserved", 0}, 1540 ACPI_DMT_TERMINATOR 1541 }; 1542 1543 /* PCCT subtables */ 1544 1545 ACPI_DMTABLE_INFO AcpiDmTableInfoPcctHdr[] = 1546 { 1547 {ACPI_DMT_PCCT, ACPI_PCCT0_OFFSET (Header.Type), "Subtable Type", 0}, 1548 {ACPI_DMT_UINT8, ACPI_PCCT0_OFFSET (Header.Length), "Length", DT_LENGTH}, 1549 ACPI_DMT_TERMINATOR 1550 }; 1551 1552 /* 0: Generic Communications Subspace */ 1553 1554 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct0[] = 1555 { 1556 {ACPI_DMT_UINT48, ACPI_PCCT0_OFFSET (Reserved[0]), "Reserved", 0}, 1557 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (BaseAddress), "Base Address", 0}, 1558 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (Length), "Address Length", 0}, 1559 {ACPI_DMT_GAS, ACPI_PCCT0_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1560 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (PreserveMask), "Preserve Mask", 0}, 1561 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (WriteMask), "Write Mask", 0}, 1562 {ACPI_DMT_UINT32, ACPI_PCCT0_OFFSET (Latency), "Command Latency", 0}, 1563 {ACPI_DMT_UINT32, ACPI_PCCT0_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1564 {ACPI_DMT_UINT16, ACPI_PCCT0_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1565 ACPI_DMT_TERMINATOR 1566 }; 1567 1568 /* 1: HW-reduced Communications Subspace (ACPI 5.1) */ 1569 1570 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct1[] = 1571 { 1572 {ACPI_DMT_UINT32, ACPI_PCCT1_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 1573 {ACPI_DMT_UINT8, ACPI_PCCT1_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1574 {ACPI_DMT_FLAG0, ACPI_PCCT1_FLAG_OFFSET (Flags,0), "Polarity", 0}, 1575 {ACPI_DMT_FLAG1, ACPI_PCCT1_FLAG_OFFSET (Flags,0), "Mode", 0}, 1576 {ACPI_DMT_UINT8, ACPI_PCCT1_OFFSET (Reserved), "Reserved", 0}, 1577 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (BaseAddress), "Base Address", 0}, 1578 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (Length), "Address Length", 0}, 1579 {ACPI_DMT_GAS, ACPI_PCCT1_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1580 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (PreserveMask), "Preserve Mask", 0}, 1581 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (WriteMask), "Write Mask", 0}, 1582 {ACPI_DMT_UINT32, ACPI_PCCT1_OFFSET (Latency), "Command Latency", 0}, 1583 {ACPI_DMT_UINT32, ACPI_PCCT1_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1584 {ACPI_DMT_UINT16, ACPI_PCCT1_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1585 ACPI_DMT_TERMINATOR 1586 }; 1587 1588 /* 2: HW-reduced Communications Subspace Type 2 (ACPI 6.1) */ 1589 1590 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct2[] = 1591 { 1592 {ACPI_DMT_UINT32, ACPI_PCCT2_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 1593 {ACPI_DMT_UINT8, ACPI_PCCT2_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1594 {ACPI_DMT_FLAG0, ACPI_PCCT2_FLAG_OFFSET (Flags,0), "Polarity", 0}, 1595 {ACPI_DMT_FLAG1, ACPI_PCCT2_FLAG_OFFSET (Flags,0), "Mode", 0}, 1596 {ACPI_DMT_UINT8, ACPI_PCCT2_OFFSET (Reserved), "Reserved", 0}, 1597 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (BaseAddress), "Base Address", 0}, 1598 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (Length), "Address Length", 0}, 1599 {ACPI_DMT_GAS, ACPI_PCCT2_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1600 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (PreserveMask), "Preserve Mask", 0}, 1601 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (WriteMask), "Write Mask", 0}, 1602 {ACPI_DMT_UINT32, ACPI_PCCT2_OFFSET (Latency), "Command Latency", 0}, 1603 {ACPI_DMT_UINT32, ACPI_PCCT2_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1604 {ACPI_DMT_UINT16, ACPI_PCCT2_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1605 {ACPI_DMT_GAS, ACPI_PCCT2_OFFSET (PlatformAckRegister), "Platform ACK Register", 0}, 1606 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (AckPreserveMask), "ACK Preserve Mask", 0}, 1607 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (AckWriteMask), "ACK Write Mask", 0}, 1608 ACPI_DMT_TERMINATOR 1609 }; 1610 1611 /* 3: Extended PCC Master Subspace Type 3 (ACPI 6.2) */ 1612 1613 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct3[] = 1614 { 1615 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 1616 {ACPI_DMT_UINT8, ACPI_PCCT3_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1617 {ACPI_DMT_FLAG0, ACPI_PCCT3_FLAG_OFFSET (Flags,0), "Polarity", 0}, 1618 {ACPI_DMT_FLAG1, ACPI_PCCT3_FLAG_OFFSET (Flags,0), "Mode", 0}, 1619 {ACPI_DMT_UINT8, ACPI_PCCT3_OFFSET (Reserved1), "Reserved", 0}, 1620 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (BaseAddress), "Base Address", 0}, 1621 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (Length), "Address Length", 0}, 1622 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1623 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (PreserveMask), "Preserve Mask", 0}, 1624 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (WriteMask), "Write Mask", 0}, 1625 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (Latency), "Command Latency", 0}, 1626 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1627 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1628 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (PlatformAckRegister), "Platform ACK Register", 0}, 1629 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (AckPreserveMask), "ACK Preserve Mask", 0}, 1630 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (AckSetMask), "ACK Set Mask", 0}, 1631 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (Reserved2), "Reserved", 0}, 1632 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (CmdCompleteRegister), "Command Complete Register", 0}, 1633 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (CmdCompleteMask), "Command Complete Check Mask", 0}, 1634 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (CmdUpdateRegister), "Command Update Register", 0}, 1635 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (CmdUpdatePreserveMask), "Command Update Preserve Mask", 0}, 1636 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (CmdUpdateSetMask), "Command Update Set Mask", 0}, 1637 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (ErrorStatusRegister), "Error Status Register", 0}, 1638 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (ErrorStatusMask), "Error Status Mask", 0}, 1639 ACPI_DMT_TERMINATOR 1640 }; 1641 1642 /* 4: Extended PCC Slave Subspace Type 4 (ACPI 6.2) */ 1643 1644 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct4[] = 1645 { 1646 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 1647 {ACPI_DMT_UINT8, ACPI_PCCT4_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1648 {ACPI_DMT_FLAG0, ACPI_PCCT4_FLAG_OFFSET (Flags,0), "Polarity", 0}, 1649 {ACPI_DMT_FLAG1, ACPI_PCCT4_FLAG_OFFSET (Flags,0), "Mode", 0}, 1650 {ACPI_DMT_UINT8, ACPI_PCCT4_OFFSET (Reserved1), "Reserved", 0}, 1651 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (BaseAddress), "Base Address", 0}, 1652 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (Length), "Address Length", 0}, 1653 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1654 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (PreserveMask), "Preserve Mask", 0}, 1655 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (WriteMask), "Write Mask", 0}, 1656 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (Latency), "Command Latency", 0}, 1657 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1658 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1659 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (PlatformAckRegister), "Platform ACK Register", 0}, 1660 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (AckPreserveMask), "ACK Preserve Mask", 0}, 1661 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (AckSetMask), "ACK Set Mask", 0}, 1662 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (Reserved2), "Reserved", 0}, 1663 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (CmdCompleteRegister), "Command Complete Register", 0}, 1664 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (CmdCompleteMask), "Command Complete Check Mask", 0}, 1665 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (CmdUpdateRegister), "Command Update Register", 0}, 1666 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (CmdUpdatePreserveMask), "Command Update Preserve Mask", 0}, 1667 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (CmdUpdateSetMask), "Command Update Set Mask", 0}, 1668 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (ErrorStatusRegister), "Error Status Register", 0}, 1669 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (ErrorStatusMask), "Error Status Mask", 0}, 1670 ACPI_DMT_TERMINATOR 1671 }; 1672 1673 /* 5: HW Registers based Communications Subspace */ 1674 1675 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct5[] = 1676 { 1677 {ACPI_DMT_UINT16, ACPI_PCCT5_OFFSET (Version), "Version", 0}, 1678 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (BaseAddress), "Base Address", 0}, 1679 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (Length), "Length", 0}, 1680 {ACPI_DMT_GAS, ACPI_PCCT5_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1681 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (DoorbellPreserve), "Preserve Mask", 0}, 1682 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (DoorbellWrite), "Write Mask", 0}, 1683 {ACPI_DMT_GAS, ACPI_PCCT5_OFFSET (CmdCompleteRegister), "Command Complete Register", 0}, 1684 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (CmdCompleteMask), "Command Complete Check Mask", 0}, 1685 {ACPI_DMT_GAS, ACPI_PCCT5_OFFSET (ErrorStatusRegister), "Error Status Register", 0}, 1686 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (ErrorStatusMask), "Error Status Mask", 0}, 1687 {ACPI_DMT_UINT32, ACPI_PCCT5_OFFSET (NominalLatency), "Nominal Latency", 0}, 1688 {ACPI_DMT_UINT32, ACPI_PCCT5_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1689 ACPI_DMT_TERMINATOR 1690 }; 1691 1692 1693 /******************************************************************************* 1694 * 1695 * PDTT - Platform Debug Trigger Table (ACPI 6.2) 1696 * 1697 ******************************************************************************/ 1698 1699 ACPI_DMTABLE_INFO AcpiDmTableInfoPdtt[] = 1700 { 1701 {ACPI_DMT_UINT8, ACPI_PDTT_OFFSET (TriggerCount), "Trigger Count", 0}, 1702 {ACPI_DMT_UINT24, ACPI_PDTT_OFFSET (Reserved), "Reserved", 0}, 1703 {ACPI_DMT_UINT32, ACPI_PDTT_OFFSET (ArrayOffset), "Array Offset", 0}, 1704 ACPI_DMT_TERMINATOR 1705 }; 1706 1707 ACPI_DMTABLE_INFO AcpiDmTableInfoPdtt0[] = 1708 { 1709 {ACPI_DMT_UINT8, ACPI_PDTT0_OFFSET (SubchannelId), "Subchannel Id", 0}, 1710 {ACPI_DMT_UINT8, ACPI_PDTT0_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1711 {ACPI_DMT_FLAG0, ACPI_PDTT0_FLAG_OFFSET (Flags,0), "Runtime Trigger", 0}, 1712 {ACPI_DMT_FLAG1, ACPI_PDTT0_FLAG_OFFSET (Flags,0), "Wait for Completion", 0}, 1713 {ACPI_DMT_FLAG2, ACPI_PDTT0_FLAG_OFFSET (Flags,0), "Trigger Order", 0}, 1714 ACPI_DMT_TERMINATOR 1715 }; 1716 1717 1718 /******************************************************************************* 1719 * 1720 * PHAT - Platform Health Assessment Table (ACPI 6.4) 1721 * 1722 ******************************************************************************/ 1723 1724 /* Common subtable header */ 1725 1726 ACPI_DMTABLE_INFO AcpiDmTableInfoPhatHdr[] = 1727 { 1728 {ACPI_DMT_PHAT, ACPI_PHATH_OFFSET (Type), "Subtable Type", 0}, 1729 {ACPI_DMT_UINT16, ACPI_PHATH_OFFSET (Length), "Length", DT_LENGTH}, 1730 {ACPI_DMT_UINT8, ACPI_PHATH_OFFSET (Revision), "Revision", 0}, 1731 ACPI_DMT_TERMINATOR 1732 }; 1733 1734 /* 0: Firmware version table */ 1735 1736 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat0[] = 1737 { 1738 {ACPI_DMT_UINT24, ACPI_PHAT0_OFFSET (Reserved), "Reserved", 0}, 1739 {ACPI_DMT_UINT32, ACPI_PHAT0_OFFSET (ElementCount), "Element Count", 0}, 1740 ACPI_DMT_TERMINATOR 1741 }; 1742 1743 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat0a[] = 1744 { 1745 {ACPI_DMT_UUID, ACPI_PHAT0A_OFFSET (Guid), "GUID", 0}, 1746 {ACPI_DMT_UINT64, ACPI_PHAT0A_OFFSET (VersionValue), "Version Value", 0}, 1747 {ACPI_DMT_UINT32, ACPI_PHAT0A_OFFSET (ProducerId), "Producer ID", 0}, 1748 ACPI_DMT_TERMINATOR 1749 }; 1750 1751 /* 1: Firmware Health Data Record */ 1752 1753 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat1[] = 1754 { 1755 {ACPI_DMT_UINT16, ACPI_PHAT1_OFFSET (Reserved), "Reserved", 0}, 1756 {ACPI_DMT_UINT8, ACPI_PHAT1_OFFSET (Health), "Health", 0}, 1757 {ACPI_DMT_UUID, ACPI_PHAT1_OFFSET (DeviceGuid), "Device GUID", 0}, 1758 {ACPI_DMT_UINT32, ACPI_PHAT1_OFFSET (DeviceSpecificOffset), "Device-Specific Offset", 0}, 1759 ACPI_DMT_TERMINATOR 1760 }; 1761 1762 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat1a[] = 1763 { 1764 {ACPI_DMT_UNICODE, 0, "Device Path", 0}, 1765 ACPI_DMT_TERMINATOR 1766 }; 1767 1768 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat1b[] = 1769 { 1770 {ACPI_DMT_RAW_BUFFER, 0, "Device-Specific Data", DT_OPTIONAL}, 1771 ACPI_DMT_TERMINATOR 1772 }; 1773 1774 1775 /******************************************************************************* 1776 * 1777 * PMTT - Platform Memory Topology Table 1778 * 1779 ******************************************************************************/ 1780 1781 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt[] = 1782 { 1783 {ACPI_DMT_UINT32, ACPI_PMTT_OFFSET (MemoryDeviceCount), "Memory Device Count", 0}, 1784 ACPI_DMT_TERMINATOR 1785 }; 1786 1787 /* Common Subtable header (one per Subtable) */ 1788 1789 #define ACPI_DM_PMTT_HEADER \ 1790 {ACPI_DMT_PMTT, ACPI_PMTTH_OFFSET (Type), "Subtable Type", 0}, \ 1791 {ACPI_DMT_UINT8, ACPI_PMTTH_OFFSET (Reserved1), "Reserved", 0}, \ 1792 {ACPI_DMT_UINT16, ACPI_PMTTH_OFFSET (Length), "Length", DT_LENGTH}, \ 1793 {ACPI_DMT_UINT16, ACPI_PMTTH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, \ 1794 {ACPI_DMT_FLAG0, ACPI_PMTTH_FLAG_OFFSET (Flags,0), "Top-level Device", 0}, \ 1795 {ACPI_DMT_FLAG1, ACPI_PMTTH_FLAG_OFFSET (Flags,0), "Physical Element", 0}, \ 1796 {ACPI_DMT_FLAGS2, ACPI_PMTTH_FLAG_OFFSET (Flags,0), "Memory Type", 0}, \ 1797 {ACPI_DMT_UINT16, ACPI_PMTTH_OFFSET (Reserved2), "Reserved", 0}, \ 1798 {ACPI_DMT_UINT32, ACPI_PMTTH_OFFSET (MemoryDeviceCount), "Memory Device Count", 0} 1799 1800 /* PMTT Subtables */ 1801 1802 /* 0: Socket */ 1803 1804 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt0[] = 1805 { 1806 ACPI_DM_PMTT_HEADER, 1807 {ACPI_DMT_UINT16, ACPI_PMTT0_OFFSET (SocketId), "Socket ID", 0}, 1808 {ACPI_DMT_UINT16, ACPI_PMTT0_OFFSET (Reserved), "Reserved", 0}, 1809 ACPI_DMT_TERMINATOR 1810 }; 1811 1812 /* 1: Memory Controller */ 1813 1814 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt1[] = 1815 { 1816 ACPI_DM_PMTT_HEADER, 1817 {ACPI_DMT_UINT16, ACPI_PMTT1_OFFSET (ControllerId), "Controller ID", 0}, 1818 {ACPI_DMT_UINT16, ACPI_PMTT1_OFFSET (Reserved), "Reserved", 0}, 1819 ACPI_DMT_TERMINATOR 1820 }; 1821 1822 /* 2: Physical Component */ 1823 1824 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt2[] = 1825 { 1826 ACPI_DM_PMTT_HEADER, 1827 {ACPI_DMT_UINT32, ACPI_PMTT2_OFFSET (BiosHandle), "Bios Handle", 0}, 1828 ACPI_DMT_TERMINATOR 1829 }; 1830 1831 /* 0xFF: Vendor Specific */ 1832 1833 ACPI_DMTABLE_INFO AcpiDmTableInfoPmttVendor[] = 1834 { 1835 ACPI_DM_PMTT_HEADER, 1836 {ACPI_DMT_UUID, ACPI_PMTT_VENDOR_OFFSET (TypeUuid), "Type Uuid", 0}, 1837 {ACPI_DMT_PMTT_VENDOR, ACPI_PMTT_VENDOR_OFFSET (Specific), "Vendor Data", 0}, 1838 ACPI_DMT_TERMINATOR 1839 }; 1840 1841 1842 /******************************************************************************* 1843 * 1844 * PPTT - Processor Properties Topology Table (ACPI 6.2) 1845 * 1846 ******************************************************************************/ 1847 1848 /* Main table consists of only the standard ACPI header - subtables follow */ 1849 1850 /* Common Subtable header (one per Subtable) */ 1851 1852 ACPI_DMTABLE_INFO AcpiDmTableInfoPpttHdr[] = 1853 { 1854 {ACPI_DMT_PPTT, ACPI_PPTTH_OFFSET (Type), "Subtable Type", 0}, 1855 {ACPI_DMT_UINT8, ACPI_PPTTH_OFFSET (Length), "Length", 0}, 1856 ACPI_DMT_TERMINATOR 1857 }; 1858 1859 /* 0: Processor hierarchy node */ 1860 1861 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt0[] = 1862 { 1863 {ACPI_DMT_UINT16, ACPI_PPTT0_OFFSET (Reserved), "Reserved", 0}, 1864 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (Flags), "Flags (decoded below)", 0}, 1865 {ACPI_DMT_FLAG0, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "Physical package", 0}, 1866 {ACPI_DMT_FLAG1, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "ACPI Processor ID valid", 0}, 1867 {ACPI_DMT_FLAG2, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "Processor is a thread", 0}, 1868 {ACPI_DMT_FLAG3, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "Node is a leaf", 0}, 1869 {ACPI_DMT_FLAG4, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "Identical Implementation", 0}, 1870 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (Parent), "Parent", 0}, 1871 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (AcpiProcessorId), "ACPI Processor ID", 0}, 1872 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (NumberOfPrivResources), "Private Resource Number", 0}, 1873 ACPI_DMT_TERMINATOR 1874 }; 1875 1876 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt0a[] = 1877 { 1878 {ACPI_DMT_UINT32, 0, "Private Resource", DT_OPTIONAL}, 1879 ACPI_DMT_TERMINATOR 1880 }; 1881 1882 /* 1: Cache type */ 1883 1884 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt1[] = 1885 { 1886 {ACPI_DMT_UINT16, ACPI_PPTT1_OFFSET (Reserved), "Reserved", 0}, 1887 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (Flags), "Flags (decoded below)", 0}, 1888 {ACPI_DMT_FLAG0, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Size valid", 0}, 1889 {ACPI_DMT_FLAG1, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Number of Sets valid", 0}, 1890 {ACPI_DMT_FLAG2, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Associativity valid", 0}, 1891 {ACPI_DMT_FLAG3, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Allocation Type valid", 0}, 1892 {ACPI_DMT_FLAG4, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Cache Type valid", 0}, 1893 {ACPI_DMT_FLAG5, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Write Policy valid", 0}, 1894 {ACPI_DMT_FLAG6, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Line Size valid", 0}, 1895 {ACPI_DMT_FLAG7, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Cache ID valid", 0}, 1896 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (NextLevelOfCache), "Next Level of Cache", 0}, 1897 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (Size), "Size", 0}, 1898 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (NumberOfSets), "Number of Sets", 0}, 1899 {ACPI_DMT_UINT8, ACPI_PPTT1_OFFSET (Associativity), "Associativity", 0}, 1900 {ACPI_DMT_UINT8, ACPI_PPTT1_OFFSET (Attributes), "Attributes", 0}, 1901 {ACPI_DMT_FLAGS0, ACPI_PPTT1_OFFSET (Attributes), "Allocation Type", 0}, 1902 {ACPI_DMT_FLAGS2, ACPI_PPTT1_OFFSET (Attributes), "Cache Type", 0}, 1903 {ACPI_DMT_FLAG4, ACPI_PPTT1_OFFSET (Attributes), "Write Policy", 0}, 1904 {ACPI_DMT_UINT16, ACPI_PPTT1_OFFSET (LineSize), "Line Size", 0}, 1905 ACPI_DMT_TERMINATOR 1906 }; 1907 1908 /* 1: cache type v1 */ 1909 1910 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt1a[] = 1911 { 1912 {ACPI_DMT_UINT32, ACPI_PPTT1A_OFFSET (CacheId), "Cache ID", 0}, 1913 ACPI_DMT_TERMINATOR 1914 }; 1915 1916 /* 2: ID */ 1917 1918 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt2[] = 1919 { 1920 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (Reserved), "Reserved", 0}, 1921 {ACPI_DMT_UINT32, ACPI_PPTT2_OFFSET (VendorId), "Vendor ID", 0}, 1922 {ACPI_DMT_UINT64, ACPI_PPTT2_OFFSET (Level1Id), "Level1 ID", 0}, 1923 {ACPI_DMT_UINT64, ACPI_PPTT2_OFFSET (Level2Id), "Level2 ID", 0}, 1924 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (MajorRev), "Major revision", 0}, 1925 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (MinorRev), "Minor revision", 0}, 1926 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (SpinRev), "Spin revision", 0}, 1927 ACPI_DMT_TERMINATOR 1928 }; 1929 1930 1931 /******************************************************************************* 1932 * 1933 * PRMT - Platform Runtime Mechanism Table 1934 * Version 1 1935 * 1936 ******************************************************************************/ 1937 1938 ACPI_DMTABLE_INFO AcpiDmTableInfoPrmtHdr[] = 1939 { 1940 {ACPI_DMT_UUID, ACPI_PRMTH_OFFSET (PlatformGuid[0]), "Platform GUID", 0}, 1941 {ACPI_DMT_UINT32, ACPI_PRMTH_OFFSET (ModuleInfoOffset), "Module info offset", 0}, 1942 {ACPI_DMT_UINT32, ACPI_PRMTH_OFFSET (ModuleInfoCount), "Module info count", 0}, 1943 ACPI_DMT_NEW_LINE, 1944 ACPI_DMT_TERMINATOR 1945 1946 }; 1947 1948 ACPI_DMTABLE_INFO AcpiDmTableInfoPrmtModule[] = 1949 { 1950 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (Revision), "Revision", 0}, 1951 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (Length), "Length", 0}, 1952 {ACPI_DMT_UUID, ACPI_PRMT0_OFFSET (ModuleGuid[0]), "Module GUID", 0}, 1953 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (MajorRev), "Major Revision", 0}, 1954 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (MinorRev), "Minor Revision", 0}, 1955 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (HandlerInfoCount), "Handler Info Count", 0}, 1956 {ACPI_DMT_UINT32, ACPI_PRMT0_OFFSET (HandlerInfoOffset), "Handler Info Offset", 0}, 1957 {ACPI_DMT_UINT64, ACPI_PRMT0_OFFSET (MmioListPointer), "Mmio List pointer", 0}, 1958 ACPI_DMT_NEW_LINE, 1959 ACPI_DMT_TERMINATOR 1960 1961 }; 1962 1963 ACPI_DMTABLE_INFO AcpiDmTableInfoPrmtHandler[] = 1964 { 1965 {ACPI_DMT_UINT16, ACPI_PRMT1_OFFSET (Revision), "Revision", 0}, 1966 {ACPI_DMT_UINT16, ACPI_PRMT1_OFFSET (Length), "Length", 0}, 1967 {ACPI_DMT_UUID, ACPI_PRMT1_OFFSET (HandlerGuid[0]), "Handler GUID", 0}, 1968 {ACPI_DMT_UINT64, ACPI_PRMT1_OFFSET (HandlerAddress), "Handler address", 0}, 1969 {ACPI_DMT_UINT64, ACPI_PRMT1_OFFSET (StaticDataBufferAddress),"Static Data Address", 0}, 1970 {ACPI_DMT_UINT64, ACPI_PRMT1_OFFSET (AcpiParamBufferAddress), "ACPI Parameter Address", 0}, 1971 ACPI_DMT_NEW_LINE, 1972 ACPI_DMT_TERMINATOR 1973 1974 }; 1975 1976 1977 /******************************************************************************* 1978 * 1979 * RASF - RAS Feature table 1980 * 1981 ******************************************************************************/ 1982 1983 ACPI_DMTABLE_INFO AcpiDmTableInfoRasf[] = 1984 { 1985 {ACPI_DMT_BUF12, ACPI_RASF_OFFSET (ChannelId[0]), "Channel ID", 0}, 1986 ACPI_DMT_TERMINATOR 1987 }; 1988 1989 1990 /******************************************************************************* 1991 * 1992 * RAS2 - RAS2 Feature table (ACPI 6.5) 1993 * 1994 ******************************************************************************/ 1995 1996 ACPI_DMTABLE_INFO AcpiDmTableInfoRas2[] = 1997 { 1998 {ACPI_DMT_UINT16, ACPI_RAS2_OFFSET (Reserved), "Reserved", 0}, 1999 {ACPI_DMT_UINT16, ACPI_RAS2_OFFSET (NumPccDescs), "Number of PCC Descriptors", 0}, 2000 ACPI_DMT_TERMINATOR 2001 }; 2002 2003 /* RAS2 PCC Descriptor */ 2004 2005 ACPI_DMTABLE_INFO AcpiDmTableInfoRas2PccDesc[] = 2006 { 2007 {ACPI_DMT_UINT8, ACPI_RAS2_PCC_DESC_OFFSET (ChannelId), "Channel ID", 0}, 2008 {ACPI_DMT_UINT16, ACPI_RAS2_PCC_DESC_OFFSET (Reserved), "Reserved", 0}, 2009 {ACPI_DMT_UINT8, ACPI_RAS2_PCC_DESC_OFFSET (FeatureType), "Feature Type", 0}, 2010 {ACPI_DMT_UINT32, ACPI_RAS2_PCC_DESC_OFFSET (Instance), "Instance", 0}, 2011 ACPI_DMT_TERMINATOR 2012 }; 2013 2014 2015 /******************************************************************************* 2016 * 2017 * RGRT - Regulatory Graphics Resource Table 2018 * 2019 ******************************************************************************/ 2020 2021 ACPI_DMTABLE_INFO AcpiDmTableInfoRgrt[] = 2022 { 2023 {ACPI_DMT_UINT16, ACPI_RGRT_OFFSET (Version), "Version", 0}, 2024 {ACPI_DMT_RGRT, ACPI_RGRT_OFFSET (ImageType), "Image Type", 0}, 2025 {ACPI_DMT_UINT8, ACPI_RGRT_OFFSET (Reserved), "Reserved", 0}, 2026 ACPI_DMT_TERMINATOR 2027 }; 2028 2029 /* 2030 * We treat the binary image field as its own subtable (to make 2031 * ACPI_DMT_RAW_BUFFER work properly). 2032 */ 2033 ACPI_DMTABLE_INFO AcpiDmTableInfoRgrt0[] = 2034 { 2035 {ACPI_DMT_RAW_BUFFER, 0, "Image", 0}, 2036 ACPI_DMT_TERMINATOR 2037 }; 2038 2039 2040 /******************************************************************************* 2041 * 2042 * RHCT - RISC-V Hart Capabilities Table 2043 * 2044 ******************************************************************************/ 2045 2046 ACPI_DMTABLE_INFO AcpiDmTableInfoRhct[] = 2047 { 2048 {ACPI_DMT_UINT32, ACPI_RHCT_OFFSET (Flags), "Flags", 0}, 2049 {ACPI_DMT_UINT64, ACPI_RHCT_OFFSET (TimeBaseFreq), "Timer Base Frequency", 0}, 2050 {ACPI_DMT_UINT32, ACPI_RHCT_OFFSET (NodeCount), "Number of nodes", 0}, 2051 {ACPI_DMT_UINT32, ACPI_RHCT_OFFSET (NodeOffset), "Offset to the node array", 0}, 2052 ACPI_DMT_TERMINATOR 2053 }; 2054 2055 2056 /* Common Subtable header (one per Subtable) */ 2057 2058 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctNodeHdr[] = 2059 { 2060 {ACPI_DMT_RHCT, ACPI_RHCTH_OFFSET (Type), "Subtable Type", 0}, 2061 {ACPI_DMT_UINT16, ACPI_RHCTH_OFFSET (Length), "Length", 0}, 2062 {ACPI_DMT_UINT16, ACPI_RHCTH_OFFSET (Revision), "Revision", 0}, 2063 ACPI_DMT_TERMINATOR 2064 }; 2065 2066 /* 0: ISA string type */ 2067 2068 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctIsa1[] = 2069 { 2070 {ACPI_DMT_UINT16, ACPI_RHCT0_OFFSET (IsaLength), "ISA string length", 0}, 2071 {ACPI_DMT_STRING, ACPI_RHCT0_OFFSET (Isa[0]), "ISA string", 0}, 2072 ACPI_DMT_TERMINATOR 2073 }; 2074 2075 2076 /* Optional padding field */ 2077 2078 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctIsaPad[] = 2079 { 2080 {ACPI_DMT_RAW_BUFFER, 0, "Optional Padding", DT_OPTIONAL}, 2081 ACPI_DMT_TERMINATOR 2082 }; 2083 2084 /* 1: CMO node type */ 2085 2086 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctCmo1[] = 2087 { 2088 {ACPI_DMT_UINT8, ACPI_RHCT1_OFFSET (Reserved), "Reserved", 0}, 2089 {ACPI_DMT_UINT8, ACPI_RHCT1_OFFSET (CbomSize), "CBOM Block Size", 0}, 2090 {ACPI_DMT_UINT8, ACPI_RHCT1_OFFSET (CbopSize), "CBOP Block Size", 0}, 2091 {ACPI_DMT_UINT8, ACPI_RHCT1_OFFSET (CbozSize), "CBOZ Block Size", 0}, 2092 ACPI_DMT_TERMINATOR 2093 }; 2094 2095 /* 2: MMU node type */ 2096 2097 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctMmu1[] = 2098 { 2099 {ACPI_DMT_UINT8, ACPI_RHCT2_OFFSET (Reserved), "Reserved", 0}, 2100 {ACPI_DMT_UINT8, ACPI_RHCT2_OFFSET (MmuType), "MMU Type", 0}, 2101 ACPI_DMT_TERMINATOR 2102 }; 2103 2104 /* 0xFFFF: Hart Info type */ 2105 2106 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctHartInfo1[] = 2107 { 2108 {ACPI_DMT_UINT16, ACPI_RHCTFFFF_OFFSET (NumOffsets), "Number of offsets", 0}, 2109 {ACPI_DMT_UINT32, ACPI_RHCTFFFF_OFFSET (Uid), "Processor UID", 0}, 2110 ACPI_DMT_TERMINATOR 2111 }; 2112 2113 2114 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctHartInfo2[] = 2115 { 2116 {ACPI_DMT_UINT32, 0, "Nodes", DT_OPTIONAL}, 2117 ACPI_DMT_TERMINATOR 2118 }; 2119 2120 2121 /******************************************************************************* 2122 * 2123 * S3PT - S3 Performance Table 2124 * 2125 ******************************************************************************/ 2126 2127 ACPI_DMTABLE_INFO AcpiDmTableInfoS3pt[] = 2128 { 2129 {ACPI_DMT_SIG, ACPI_S3PT_OFFSET (Signature[0]), "Signature", 0}, 2130 {ACPI_DMT_UINT32, ACPI_S3PT_OFFSET (Length), "Length", DT_LENGTH}, 2131 ACPI_DMT_TERMINATOR 2132 }; 2133 2134 /* S3PT subtable header */ 2135 2136 ACPI_DMTABLE_INFO AcpiDmTableInfoS3ptHdr[] = 2137 { 2138 {ACPI_DMT_UINT16, ACPI_S3PTH_OFFSET (Type), "Type", 0}, 2139 {ACPI_DMT_UINT8, ACPI_S3PTH_OFFSET (Length), "Length", DT_LENGTH}, 2140 {ACPI_DMT_UINT8, ACPI_S3PTH_OFFSET (Revision), "Revision", 0}, 2141 ACPI_DMT_TERMINATOR 2142 }; 2143 2144 /* 0: Basic S3 Resume Performance Record */ 2145 2146 ACPI_DMTABLE_INFO AcpiDmTableInfoS3pt0[] = 2147 { 2148 {ACPI_DMT_UINT32, ACPI_S3PT0_OFFSET (ResumeCount), "Resume Count", 0}, 2149 {ACPI_DMT_UINT64, ACPI_S3PT0_OFFSET (FullResume), "Full Resume", 0}, 2150 {ACPI_DMT_UINT64, ACPI_S3PT0_OFFSET (AverageResume), "Average Resume", 0}, 2151 ACPI_DMT_TERMINATOR 2152 }; 2153 2154 /* 1: Basic S3 Suspend Performance Record */ 2155 2156 ACPI_DMTABLE_INFO AcpiDmTableInfoS3pt1[] = 2157 { 2158 {ACPI_DMT_UINT64, ACPI_S3PT1_OFFSET (SuspendStart), "Suspend Start", 0}, 2159 {ACPI_DMT_UINT64, ACPI_S3PT1_OFFSET (SuspendEnd), "Suspend End", 0}, 2160 ACPI_DMT_TERMINATOR 2161 }; 2162 2163 2164 /******************************************************************************* 2165 * 2166 * SBST - Smart Battery Specification Table 2167 * 2168 ******************************************************************************/ 2169 2170 ACPI_DMTABLE_INFO AcpiDmTableInfoSbst[] = 2171 { 2172 {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (WarningLevel), "Warning Level", 0}, 2173 {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (LowLevel), "Low Level", 0}, 2174 {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (CriticalLevel), "Critical Level", 0}, 2175 ACPI_DMT_TERMINATOR 2176 }; 2177 2178 2179 /******************************************************************************* 2180 * 2181 * SDEI - Software Delegated Exception Interface Descriptor Table 2182 * 2183 ******************************************************************************/ 2184 2185 ACPI_DMTABLE_INFO AcpiDmTableInfoSdei[] = 2186 { 2187 ACPI_DMT_TERMINATOR 2188 }; 2189 2190 2191 /******************************************************************************* 2192 * 2193 * SDEV - Secure Devices Table (ACPI 6.2) 2194 * 2195 ******************************************************************************/ 2196 2197 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev[] = 2198 { 2199 ACPI_DMT_TERMINATOR 2200 }; 2201 2202 /* Common Subtable header (one per Subtable) */ 2203 2204 ACPI_DMTABLE_INFO AcpiDmTableInfoSdevHdr[] = 2205 { 2206 {ACPI_DMT_SDEV, ACPI_SDEVH_OFFSET (Type), "Subtable Type", 0}, 2207 {ACPI_DMT_UINT8, ACPI_SDEVH_OFFSET (Flags), "Flags (decoded below)", 0}, 2208 {ACPI_DMT_FLAG0, ACPI_SDEVH_FLAG_OFFSET (Flags,0), "Allow handoff to unsecure OS", 0}, 2209 {ACPI_DMT_FLAG1, ACPI_SDEVH_FLAG_OFFSET (Flags,0), "Secure access components present", 0}, 2210 {ACPI_DMT_UINT16, ACPI_SDEVH_OFFSET (Length), "Length", DT_LENGTH}, 2211 ACPI_DMT_TERMINATOR 2212 }; 2213 2214 /* SDEV Subtables */ 2215 2216 /* 0: Namespace Device Based Secure Device Structure */ 2217 2218 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev0[] = 2219 { 2220 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (DeviceIdOffset), "Device ID Offset", 0}, 2221 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (DeviceIdLength), "Device ID Length", 0}, 2222 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (VendorDataOffset), "Vendor Data Offset", 0}, 2223 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (VendorDataLength), "Vendor Data Length", 0}, 2224 ACPI_DMT_TERMINATOR 2225 }; 2226 2227 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev0a[] = 2228 { 2229 {ACPI_DMT_STRING, 0, "Namepath", 0}, 2230 ACPI_DMT_TERMINATOR 2231 }; 2232 2233 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev0b[] = 2234 { 2235 {ACPI_DMT_UINT16, ACPI_SDEV0B_OFFSET (SecureComponentOffset), "Secure Access Components Offset", 0}, 2236 {ACPI_DMT_UINT16, ACPI_SDEV0B_OFFSET (SecureComponentLength), "Secure Access Components Length", 0}, 2237 ACPI_DMT_TERMINATOR 2238 }; 2239 2240 /* Secure access components */ 2241 2242 /* Common secure access components header secure access component */ 2243 2244 ACPI_DMTABLE_INFO AcpiDmTableInfoSdevSecCompHdr[] = 2245 { 2246 {ACPI_DMT_UINT8, ACPI_SDEVCH_OFFSET (Type), "Secure Component Type", 0}, 2247 {ACPI_DMT_UINT8, ACPI_SDEVCH_OFFSET (Flags), "Flags (decoded below)", 0}, 2248 {ACPI_DMT_UINT16, ACPI_SDEVCH_OFFSET (Length), "Length", 0}, 2249 ACPI_DMT_TERMINATOR 2250 }; 2251 2252 /* 0: Identification Based Secure Access Component */ 2253 2254 ACPI_DMTABLE_INFO AcpiDmTableInfoSdevSecCompId[] = 2255 { 2256 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (HardwareIdOffset), "Hardware ID Offset", 0}, 2257 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (HardwareIdLength), "Hardware ID Length", 0}, 2258 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (SubsystemIdOffset), "Subsystem ID Offset", 0}, 2259 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (SubsystemIdLength), "Subsystem ID Length", 0}, 2260 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (HardwareRevision), "Hardware Revision", 0}, 2261 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (HardwareRevPresent), "Hardware Rev Present", 0}, 2262 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (ClassCodePresent), "Class Code Present", 0}, 2263 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (PciBaseClass), "PCI Base Class", 0}, 2264 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (PciSubClass), "PCI SubClass", 0}, 2265 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (PciProgrammingXface), "PCI Programming Xface", 0}, 2266 ACPI_DMT_TERMINATOR 2267 }; 2268 2269 /* 1: Memory Based Secure Access Component */ 2270 2271 ACPI_DMTABLE_INFO AcpiDmTableInfoSdevSecCompMem[] = 2272 { 2273 {ACPI_DMT_UINT32, ACPI_SDEVC1_OFFSET (Reserved), "Reserved", 0}, 2274 {ACPI_DMT_UINT64, ACPI_SDEVC1_OFFSET (MemoryBaseAddress), "Memory Base Address", 0}, 2275 {ACPI_DMT_UINT64, ACPI_SDEVC1_OFFSET (MemoryLength), "Memory Length", 0}, 2276 ACPI_DMT_TERMINATOR 2277 }; 2278 2279 2280 /* 1: PCIe Endpoint Device Based Device Structure */ 2281 2282 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev1[] = 2283 { 2284 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (Segment), "Segment", 0}, 2285 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (StartBus), "Start Bus", 0}, 2286 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (PathOffset), "Path Offset", 0}, 2287 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (PathLength), "Path Length", 0}, 2288 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (VendorDataOffset), "Vendor Data Offset", 0}, 2289 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (VendorDataLength), "Vendor Data Length", 0}, 2290 ACPI_DMT_TERMINATOR 2291 }; 2292 2293 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev1a[] = 2294 { 2295 {ACPI_DMT_UINT8, ACPI_SDEV1A_OFFSET (Device), "Device", 0}, 2296 {ACPI_DMT_UINT8, ACPI_SDEV1A_OFFSET (Function), "Function", 0}, 2297 ACPI_DMT_TERMINATOR 2298 }; 2299 2300 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev1b[] = 2301 { 2302 {ACPI_DMT_RAW_BUFFER, 0, "Vendor Data", 0}, /*, DT_OPTIONAL}, */ 2303 ACPI_DMT_TERMINATOR 2304 }; 2305 2306 /*! [End] no source code translation !*/ 2307
