1 /** 2 * \file 3 * 4 * \brief Component description for AC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_AC_COMPONENT_ 30 #define _SAML21_AC_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR AC */ 34 /* ========================================================================== */ 35 /** \addtogroup SAML21_AC Analog Comparators */ 36 /*@{*/ 37 38 #define AC_U2245 39 #define REV_AC 0x101 40 41 /* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 46 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 47 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 48 } bit; /*!< Structure used for bit access */ 49 uint8_t reg; /*!< Type used for register access */ 50 } AC_CTRLA_Type; 51 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 52 53 #define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ 54 #define AC_CTRLA_RESETVALUE _U(0x00) /**< \brief (AC_CTRLA reset_value) Control A */ 55 56 #define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ 57 #define AC_CTRLA_SWRST (_U(0x1) << AC_CTRLA_SWRST_Pos) 58 #define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ 59 #define AC_CTRLA_ENABLE (_U(0x1) << AC_CTRLA_ENABLE_Pos) 60 #define AC_CTRLA_MASK _U(0x03) /**< \brief (AC_CTRLA) MASK Register */ 61 62 /* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ 63 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 64 typedef union { 65 struct { 66 uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ 67 uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ 68 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 69 } bit; /*!< Structure used for bit access */ 70 struct { 71 uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ 72 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 73 } vec; /*!< Structure used for vec access */ 74 uint8_t reg; /*!< Type used for register access */ 75 } AC_CTRLB_Type; 76 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 77 78 #define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ 79 #define AC_CTRLB_RESETVALUE _U(0x00) /**< \brief (AC_CTRLB reset_value) Control B */ 80 81 #define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ 82 #define AC_CTRLB_START0 (1 << AC_CTRLB_START0_Pos) 83 #define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ 84 #define AC_CTRLB_START1 (1 << AC_CTRLB_START1_Pos) 85 #define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ 86 #define AC_CTRLB_START_Msk (_U(0x3) << AC_CTRLB_START_Pos) 87 #define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) 88 #define AC_CTRLB_MASK _U(0x03) /**< \brief (AC_CTRLB) MASK Register */ 89 90 /* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ 91 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 92 typedef union { 93 struct { 94 uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ 95 uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ 96 uint16_t :2; /*!< bit: 2.. 3 Reserved */ 97 uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ 98 uint16_t :3; /*!< bit: 5.. 7 Reserved */ 99 uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */ 100 uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */ 101 uint16_t :2; /*!< bit: 10..11 Reserved */ 102 uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */ 103 uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */ 104 uint16_t :2; /*!< bit: 14..15 Reserved */ 105 } bit; /*!< Structure used for bit access */ 106 struct { 107 uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ 108 uint16_t :2; /*!< bit: 2.. 3 Reserved */ 109 uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ 110 uint16_t :3; /*!< bit: 5.. 7 Reserved */ 111 uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */ 112 uint16_t :2; /*!< bit: 10..11 Reserved */ 113 uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */ 114 uint16_t :2; /*!< bit: 14..15 Reserved */ 115 } vec; /*!< Structure used for vec access */ 116 uint16_t reg; /*!< Type used for register access */ 117 } AC_EVCTRL_Type; 118 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 119 120 #define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ 121 #define AC_EVCTRL_RESETVALUE _U(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */ 122 123 #define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ 124 #define AC_EVCTRL_COMPEO0 (1 << AC_EVCTRL_COMPEO0_Pos) 125 #define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ 126 #define AC_EVCTRL_COMPEO1 (1 << AC_EVCTRL_COMPEO1_Pos) 127 #define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ 128 #define AC_EVCTRL_COMPEO_Msk (_U(0x3) << AC_EVCTRL_COMPEO_Pos) 129 #define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) 130 #define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ 131 #define AC_EVCTRL_WINEO0 (1 << AC_EVCTRL_WINEO0_Pos) 132 #define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ 133 #define AC_EVCTRL_WINEO_Msk (_U(0x1) << AC_EVCTRL_WINEO_Pos) 134 #define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) 135 #define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */ 136 #define AC_EVCTRL_COMPEI0 (1 << AC_EVCTRL_COMPEI0_Pos) 137 #define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */ 138 #define AC_EVCTRL_COMPEI1 (1 << AC_EVCTRL_COMPEI1_Pos) 139 #define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */ 140 #define AC_EVCTRL_COMPEI_Msk (_U(0x3) << AC_EVCTRL_COMPEI_Pos) 141 #define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) 142 #define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */ 143 #define AC_EVCTRL_INVEI0 (1 << AC_EVCTRL_INVEI0_Pos) 144 #define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */ 145 #define AC_EVCTRL_INVEI1 (1 << AC_EVCTRL_INVEI1_Pos) 146 #define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */ 147 #define AC_EVCTRL_INVEI_Msk (_U(0x3) << AC_EVCTRL_INVEI_Pos) 148 #define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos)) 149 #define AC_EVCTRL_MASK _U(0x3313) /**< \brief (AC_EVCTRL) MASK Register */ 150 151 /* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ 152 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 153 typedef union { 154 struct { 155 uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ 156 uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ 157 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 158 uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ 159 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 160 } bit; /*!< Structure used for bit access */ 161 struct { 162 uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ 163 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 164 uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ 165 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 166 } vec; /*!< Structure used for vec access */ 167 uint8_t reg; /*!< Type used for register access */ 168 } AC_INTENCLR_Type; 169 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 170 171 #define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ 172 #define AC_INTENCLR_RESETVALUE _U(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ 173 174 #define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ 175 #define AC_INTENCLR_COMP0 (1 << AC_INTENCLR_COMP0_Pos) 176 #define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ 177 #define AC_INTENCLR_COMP1 (1 << AC_INTENCLR_COMP1_Pos) 178 #define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ 179 #define AC_INTENCLR_COMP_Msk (_U(0x3) << AC_INTENCLR_COMP_Pos) 180 #define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) 181 #define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ 182 #define AC_INTENCLR_WIN0 (1 << AC_INTENCLR_WIN0_Pos) 183 #define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ 184 #define AC_INTENCLR_WIN_Msk (_U(0x1) << AC_INTENCLR_WIN_Pos) 185 #define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) 186 #define AC_INTENCLR_MASK _U(0x13) /**< \brief (AC_INTENCLR) MASK Register */ 187 188 /* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ 189 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 190 typedef union { 191 struct { 192 uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ 193 uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ 194 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 195 uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ 196 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 197 } bit; /*!< Structure used for bit access */ 198 struct { 199 uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ 200 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 201 uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ 202 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 203 } vec; /*!< Structure used for vec access */ 204 uint8_t reg; /*!< Type used for register access */ 205 } AC_INTENSET_Type; 206 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 207 208 #define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ 209 #define AC_INTENSET_RESETVALUE _U(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ 210 211 #define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ 212 #define AC_INTENSET_COMP0 (1 << AC_INTENSET_COMP0_Pos) 213 #define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ 214 #define AC_INTENSET_COMP1 (1 << AC_INTENSET_COMP1_Pos) 215 #define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ 216 #define AC_INTENSET_COMP_Msk (_U(0x3) << AC_INTENSET_COMP_Pos) 217 #define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) 218 #define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ 219 #define AC_INTENSET_WIN0 (1 << AC_INTENSET_WIN0_Pos) 220 #define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ 221 #define AC_INTENSET_WIN_Msk (_U(0x1) << AC_INTENSET_WIN_Pos) 222 #define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) 223 #define AC_INTENSET_MASK _U(0x13) /**< \brief (AC_INTENSET) MASK Register */ 224 225 /* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ 226 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 227 typedef union { // __I to avoid read-modify-write on write-to-clear register 228 struct { 229 __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ 230 __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ 231 __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ 232 __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ 233 __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ 234 } bit; /*!< Structure used for bit access */ 235 struct { 236 __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ 237 __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ 238 __I uint8_t WIN:1; /*!< bit: 4 Window x */ 239 __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ 240 } vec; /*!< Structure used for vec access */ 241 uint8_t reg; /*!< Type used for register access */ 242 } AC_INTFLAG_Type; 243 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 244 245 #define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ 246 #define AC_INTFLAG_RESETVALUE _U(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ 247 248 #define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ 249 #define AC_INTFLAG_COMP0 (1 << AC_INTFLAG_COMP0_Pos) 250 #define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ 251 #define AC_INTFLAG_COMP1 (1 << AC_INTFLAG_COMP1_Pos) 252 #define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ 253 #define AC_INTFLAG_COMP_Msk (_U(0x3) << AC_INTFLAG_COMP_Pos) 254 #define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) 255 #define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ 256 #define AC_INTFLAG_WIN0 (1 << AC_INTFLAG_WIN0_Pos) 257 #define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ 258 #define AC_INTFLAG_WIN_Msk (_U(0x1) << AC_INTFLAG_WIN_Pos) 259 #define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) 260 #define AC_INTFLAG_MASK _U(0x13) /**< \brief (AC_INTFLAG) MASK Register */ 261 262 /* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */ 263 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 264 typedef union { 265 struct { 266 uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ 267 uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ 268 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 269 uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ 270 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 271 } bit; /*!< Structure used for bit access */ 272 struct { 273 uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ 274 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 275 } vec; /*!< Structure used for vec access */ 276 uint8_t reg; /*!< Type used for register access */ 277 } AC_STATUSA_Type; 278 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 279 280 #define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */ 281 #define AC_STATUSA_RESETVALUE _U(0x00) /**< \brief (AC_STATUSA reset_value) Status A */ 282 283 #define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ 284 #define AC_STATUSA_STATE0 (1 << AC_STATUSA_STATE0_Pos) 285 #define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ 286 #define AC_STATUSA_STATE1 (1 << AC_STATUSA_STATE1_Pos) 287 #define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ 288 #define AC_STATUSA_STATE_Msk (_U(0x3) << AC_STATUSA_STATE_Pos) 289 #define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) 290 #define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ 291 #define AC_STATUSA_WSTATE0_Msk (_U(0x3) << AC_STATUSA_WSTATE0_Pos) 292 #define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) 293 #define AC_STATUSA_WSTATE0_ABOVE_Val _U(0x0) /**< \brief (AC_STATUSA) Signal is above window */ 294 #define AC_STATUSA_WSTATE0_INSIDE_Val _U(0x1) /**< \brief (AC_STATUSA) Signal is inside window */ 295 #define AC_STATUSA_WSTATE0_BELOW_Val _U(0x2) /**< \brief (AC_STATUSA) Signal is below window */ 296 #define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) 297 #define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) 298 #define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) 299 #define AC_STATUSA_MASK _U(0x33) /**< \brief (AC_STATUSA) MASK Register */ 300 301 /* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */ 302 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 303 typedef union { 304 struct { 305 uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ 306 uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ 307 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 308 } bit; /*!< Structure used for bit access */ 309 struct { 310 uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ 311 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 312 } vec; /*!< Structure used for vec access */ 313 uint8_t reg; /*!< Type used for register access */ 314 } AC_STATUSB_Type; 315 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 316 317 #define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */ 318 #define AC_STATUSB_RESETVALUE _U(0x00) /**< \brief (AC_STATUSB reset_value) Status B */ 319 320 #define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ 321 #define AC_STATUSB_READY0 (1 << AC_STATUSB_READY0_Pos) 322 #define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ 323 #define AC_STATUSB_READY1 (1 << AC_STATUSB_READY1_Pos) 324 #define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ 325 #define AC_STATUSB_READY_Msk (_U(0x3) << AC_STATUSB_READY_Pos) 326 #define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) 327 #define AC_STATUSB_MASK _U(0x03) /**< \brief (AC_STATUSB) MASK Register */ 328 329 /* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ 330 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 331 typedef union { 332 struct { 333 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ 334 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 335 } bit; /*!< Structure used for bit access */ 336 uint8_t reg; /*!< Type used for register access */ 337 } AC_DBGCTRL_Type; 338 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 339 340 #define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */ 341 #define AC_DBGCTRL_RESETVALUE _U(0x00) /**< \brief (AC_DBGCTRL reset_value) Debug Control */ 342 343 #define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */ 344 #define AC_DBGCTRL_DBGRUN (_U(0x1) << AC_DBGCTRL_DBGRUN_Pos) 345 #define AC_DBGCTRL_MASK _U(0x01) /**< \brief (AC_DBGCTRL) MASK Register */ 346 347 /* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ 348 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 349 typedef union { 350 struct { 351 uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ 352 uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ 353 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 354 } bit; /*!< Structure used for bit access */ 355 uint8_t reg; /*!< Type used for register access */ 356 } AC_WINCTRL_Type; 357 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 358 359 #define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */ 360 #define AC_WINCTRL_RESETVALUE _U(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */ 361 362 #define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ 363 #define AC_WINCTRL_WEN0 (_U(0x1) << AC_WINCTRL_WEN0_Pos) 364 #define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ 365 #define AC_WINCTRL_WINTSEL0_Msk (_U(0x3) << AC_WINCTRL_WINTSEL0_Pos) 366 #define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) 367 #define AC_WINCTRL_WINTSEL0_ABOVE_Val _U(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */ 368 #define AC_WINCTRL_WINTSEL0_INSIDE_Val _U(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ 369 #define AC_WINCTRL_WINTSEL0_BELOW_Val _U(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */ 370 #define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ 371 #define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) 372 #define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) 373 #define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) 374 #define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) 375 #define AC_WINCTRL_MASK _U(0x07) /**< \brief (AC_WINCTRL) MASK Register */ 376 377 /* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ 378 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 379 typedef union { 380 struct { 381 uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ 382 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 383 } bit; /*!< Structure used for bit access */ 384 uint8_t reg; /*!< Type used for register access */ 385 } AC_SCALER_Type; 386 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 387 388 #define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */ 389 #define AC_SCALER_RESETVALUE _U(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */ 390 391 #define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ 392 #define AC_SCALER_VALUE_Msk (_U(0x3F) << AC_SCALER_VALUE_Pos) 393 #define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) 394 #define AC_SCALER_MASK _U(0x3F) /**< \brief (AC_SCALER) MASK Register */ 395 396 /* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ 397 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 398 typedef union { 399 struct { 400 uint32_t :1; /*!< bit: 0 Reserved */ 401 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 402 uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */ 403 uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */ 404 uint32_t :1; /*!< bit: 5 Reserved */ 405 uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 406 uint32_t :1; /*!< bit: 7 Reserved */ 407 uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ 408 uint32_t :1; /*!< bit: 11 Reserved */ 409 uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */ 410 uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ 411 uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */ 412 uint32_t :1; /*!< bit: 18 Reserved */ 413 uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */ 414 uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */ 415 uint32_t :2; /*!< bit: 22..23 Reserved */ 416 uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ 417 uint32_t :1; /*!< bit: 27 Reserved */ 418 uint32_t OUT:2; /*!< bit: 28..29 Output */ 419 uint32_t :2; /*!< bit: 30..31 Reserved */ 420 } bit; /*!< Structure used for bit access */ 421 uint32_t reg; /*!< Type used for register access */ 422 } AC_COMPCTRL_Type; 423 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 424 425 #define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ 426 #define AC_COMPCTRL_RESETVALUE _U(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ 427 428 #define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */ 429 #define AC_COMPCTRL_ENABLE (_U(0x1) << AC_COMPCTRL_ENABLE_Pos) 430 #define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ 431 #define AC_COMPCTRL_SINGLE (_U(0x1) << AC_COMPCTRL_SINGLE_Pos) 432 #define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */ 433 #define AC_COMPCTRL_INTSEL_Msk (_U(0x3) << AC_COMPCTRL_INTSEL_Pos) 434 #define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) 435 #define AC_COMPCTRL_INTSEL_TOGGLE_Val _U(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ 436 #define AC_COMPCTRL_INTSEL_RISING_Val _U(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ 437 #define AC_COMPCTRL_INTSEL_FALLING_Val _U(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ 438 #define AC_COMPCTRL_INTSEL_EOC_Val _U(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ 439 #define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) 440 #define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) 441 #define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) 442 #define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) 443 #define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */ 444 #define AC_COMPCTRL_RUNSTDBY (_U(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) 445 #define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ 446 #define AC_COMPCTRL_MUXNEG_Msk (_U(0x7) << AC_COMPCTRL_MUXNEG_Pos) 447 #define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) 448 #define AC_COMPCTRL_MUXNEG_PIN0_Val _U(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ 449 #define AC_COMPCTRL_MUXNEG_PIN1_Val _U(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ 450 #define AC_COMPCTRL_MUXNEG_PIN2_Val _U(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ 451 #define AC_COMPCTRL_MUXNEG_PIN3_Val _U(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ 452 #define AC_COMPCTRL_MUXNEG_GND_Val _U(0x4) /**< \brief (AC_COMPCTRL) Ground */ 453 #define AC_COMPCTRL_MUXNEG_VSCALE_Val _U(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */ 454 #define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ 455 #define AC_COMPCTRL_MUXNEG_DAC_Val _U(0x7) /**< \brief (AC_COMPCTRL) DAC output */ 456 #define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) 457 #define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) 458 #define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) 459 #define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) 460 #define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) 461 #define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) 462 #define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) 463 #define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) 464 #define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ 465 #define AC_COMPCTRL_MUXPOS_Msk (_U(0x7) << AC_COMPCTRL_MUXPOS_Pos) 466 #define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) 467 #define AC_COMPCTRL_MUXPOS_PIN0_Val _U(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ 468 #define AC_COMPCTRL_MUXPOS_PIN1_Val _U(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ 469 #define AC_COMPCTRL_MUXPOS_PIN2_Val _U(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ 470 #define AC_COMPCTRL_MUXPOS_PIN3_Val _U(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ 471 #define AC_COMPCTRL_MUXPOS_VSCALE_Val _U(0x4) /**< \brief (AC_COMPCTRL) VDD Scaler */ 472 #define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) 473 #define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) 474 #define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) 475 #define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) 476 #define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) 477 #define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ 478 #define AC_COMPCTRL_SWAP (_U(0x1) << AC_COMPCTRL_SWAP_Pos) 479 #define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */ 480 #define AC_COMPCTRL_SPEED_Msk (_U(0x3) << AC_COMPCTRL_SPEED_Pos) 481 #define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) 482 #define AC_COMPCTRL_SPEED_LOW_Val _U(0x0) /**< \brief (AC_COMPCTRL) Low speed */ 483 #define AC_COMPCTRL_SPEED_MEDLOW_Val _U(0x1) /**< \brief (AC_COMPCTRL) Medium low speed */ 484 #define AC_COMPCTRL_SPEED_MEDHIGH_Val _U(0x2) /**< \brief (AC_COMPCTRL) Medium high speed */ 485 #define AC_COMPCTRL_SPEED_HIGH_Val _U(0x3) /**< \brief (AC_COMPCTRL) High speed */ 486 #define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) 487 #define AC_COMPCTRL_SPEED_MEDLOW (AC_COMPCTRL_SPEED_MEDLOW_Val << AC_COMPCTRL_SPEED_Pos) 488 #define AC_COMPCTRL_SPEED_MEDHIGH (AC_COMPCTRL_SPEED_MEDHIGH_Val << AC_COMPCTRL_SPEED_Pos) 489 #define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) 490 #define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ 491 #define AC_COMPCTRL_HYSTEN (_U(0x1) << AC_COMPCTRL_HYSTEN_Pos) 492 #define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */ 493 #define AC_COMPCTRL_HYST_Msk (_U(0x3) << AC_COMPCTRL_HYST_Pos) 494 #define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos)) 495 #define AC_COMPCTRL_HYST_HYST50_Val _U(0x0) /**< \brief (AC_COMPCTRL) 50mV */ 496 #define AC_COMPCTRL_HYST_HYST70_Val _U(0x1) /**< \brief (AC_COMPCTRL) 70mV */ 497 #define AC_COMPCTRL_HYST_HYST90_Val _U(0x2) /**< \brief (AC_COMPCTRL) 90mV */ 498 #define AC_COMPCTRL_HYST_HYST110_Val _U(0x3) /**< \brief (AC_COMPCTRL) 110mV */ 499 #define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos) 500 #define AC_COMPCTRL_HYST_HYST70 (AC_COMPCTRL_HYST_HYST70_Val << AC_COMPCTRL_HYST_Pos) 501 #define AC_COMPCTRL_HYST_HYST90 (AC_COMPCTRL_HYST_HYST90_Val << AC_COMPCTRL_HYST_Pos) 502 #define AC_COMPCTRL_HYST_HYST110 (AC_COMPCTRL_HYST_HYST110_Val << AC_COMPCTRL_HYST_Pos) 503 #define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ 504 #define AC_COMPCTRL_FLEN_Msk (_U(0x7) << AC_COMPCTRL_FLEN_Pos) 505 #define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) 506 #define AC_COMPCTRL_FLEN_OFF_Val _U(0x0) /**< \brief (AC_COMPCTRL) No filtering */ 507 #define AC_COMPCTRL_FLEN_MAJ3_Val _U(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ 508 #define AC_COMPCTRL_FLEN_MAJ5_Val _U(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ 509 #define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) 510 #define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) 511 #define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) 512 #define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */ 513 #define AC_COMPCTRL_OUT_Msk (_U(0x3) << AC_COMPCTRL_OUT_Pos) 514 #define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) 515 #define AC_COMPCTRL_OUT_OFF_Val _U(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ 516 #define AC_COMPCTRL_OUT_ASYNC_Val _U(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ 517 #define AC_COMPCTRL_OUT_SYNC_Val _U(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ 518 #define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) 519 #define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) 520 #define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) 521 #define AC_COMPCTRL_MASK _U(0x373BF75E) /**< \brief (AC_COMPCTRL) MASK Register */ 522 523 /* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */ 524 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 525 typedef union { 526 struct { 527 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ 528 uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ 529 uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */ 530 uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */ 531 uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */ 532 uint32_t :27; /*!< bit: 5..31 Reserved */ 533 } bit; /*!< Structure used for bit access */ 534 struct { 535 uint32_t :3; /*!< bit: 0.. 2 Reserved */ 536 uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */ 537 uint32_t :27; /*!< bit: 5..31 Reserved */ 538 } vec; /*!< Structure used for vec access */ 539 uint32_t reg; /*!< Type used for register access */ 540 } AC_SYNCBUSY_Type; 541 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 542 543 #define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */ 544 #define AC_SYNCBUSY_RESETVALUE _U(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */ 545 546 #define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */ 547 #define AC_SYNCBUSY_SWRST (_U(0x1) << AC_SYNCBUSY_SWRST_Pos) 548 #define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */ 549 #define AC_SYNCBUSY_ENABLE (_U(0x1) << AC_SYNCBUSY_ENABLE_Pos) 550 #define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */ 551 #define AC_SYNCBUSY_WINCTRL (_U(0x1) << AC_SYNCBUSY_WINCTRL_Pos) 552 #define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */ 553 #define AC_SYNCBUSY_COMPCTRL0 (1 << AC_SYNCBUSY_COMPCTRL0_Pos) 554 #define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */ 555 #define AC_SYNCBUSY_COMPCTRL1 (1 << AC_SYNCBUSY_COMPCTRL1_Pos) 556 #define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */ 557 #define AC_SYNCBUSY_COMPCTRL_Msk (_U(0x3) << AC_SYNCBUSY_COMPCTRL_Pos) 558 #define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos)) 559 #define AC_SYNCBUSY_MASK _U(0x0000001F) /**< \brief (AC_SYNCBUSY) MASK Register */ 560 561 /** \brief AC hardware registers */ 562 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 563 typedef struct { 564 __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ 565 __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ 566 __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ 567 __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ 568 __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ 569 __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ 570 __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */ 571 __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */ 572 __IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */ 573 __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */ 574 RoReg8 Reserved1[0x1]; 575 __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */ 576 RoReg8 Reserved2[0x2]; 577 __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ 578 RoReg8 Reserved3[0x8]; 579 __I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */ 580 } Ac; 581 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 582 583 /*@}*/ 584 585 #endif /* _SAML21_AC_COMPONENT_ */ 586
