1 /* 2 * Copyright (c) 2022 ITE. 3 * Copyright 2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _FSL_IT6161_H_ 9 #define _FSL_IT6161_H_ 10 11 #include "fsl_video_common.h" 12 #include "fsl_video_i2c.h" 13 #include "fsl_display.h" 14 #include "fsl_common.h" 15 #include "mipi_rx.h" 16 #include "hdmi_tx.h" 17 18 /******************************************************************************* 19 * Definitions 20 ******************************************************************************/ 21 #define F_AUDIO_ON (1U << 7U) 22 #define F_AUDIO_HBR (1U << 6U) 23 #define F_AUDIO_DSD (1U << 5U) 24 #define F_AUDIO_NLPCM (1U << 4U) 25 #define F_AUDIO_LAYOUT_1 (1U << 3U) 26 #define F_AUDIO_LAYOUT_0 (0U << 3U) 27 // HBR - 1100 28 // DSD - 1010 29 // NLPCM - 1001 30 // LPCM - 1000 31 #define T_AUDIO_MASK (0xF0) 32 #define T_AUDIO_OFF (0U) 33 #define T_AUDIO_HBR (F_AUDIO_ON | F_AUDIO_HBR) 34 #define T_AUDIO_DSD (F_AUDIO_ON | F_AUDIO_DSD) 35 #define T_AUDIO_NLPCM (F_AUDIO_ON | F_AUDIO_NLPCM) 36 #define T_AUDIO_LPCM (F_AUDIO_ON) 37 38 /* Video Data Type */ 39 #define F_MODE_RGB444 (0x00U) 40 #define F_MODE_YUV422 (0x01U) 41 #define F_MODE_YUV444 (0x02U) 42 #define F_MODE_CLRMOD_MASK (0x03U) 43 44 #define F_VIDMODE_ITU709 (1U << 4U) 45 #define F_VIDMODE_ITU601 (0U) 46 47 #define F_VIDMODE_0_255 (0U) 48 #define F_VIDMODE_16_235 (1U << 5U) 49 50 #define F_VIDMODE_EN_UDFILT (1U << 6U) 51 #define F_VIDMODE_EN_DITHER (1U << 7U) 52 53 /* sample clock */ 54 #define AUDFS_22p05KHz (0x04U) 55 #define AUDFS_44p1KHz (0x00U) 56 #define AUDFS_88p2KHz (0x08U) 57 #define AUDFS_176p4KHz (0x0CU) 58 #define AUDFS_24KHz (0x06U) 59 #define AUDFS_48KHz (0x02U) 60 #define AUDFS_96KHz (0x0AU) 61 #define AUDFS_192KHz (0x0EU) 62 #define AUDFS_768KHz (0x09U) 63 #define AUDFS_32KHz (0x03U) 64 #define AUDFS_OTHER (0x01U) 65 66 #ifndef BIT 67 #define BIT(nr) ((0x01U) << (nr)) 68 #endif 69 70 #define DEMO_HDMI_RESOLUSION (HDMI_480p60_16x9) 71 #define DEMO_HDMI_COLOR_MODE (HDMI_RGB444) 72 73 #define delay1ms(x) SDK_DelayAtLeastUs((x) * 1000, SystemCoreClock) 74 75 #define MIPIRX_LANE_NUM (4) /* 1~4 */ 76 77 /* I2C Address */ 78 #define HDMI_TX_ADDR (0x4C) 79 #define HDMI_TX_CEC_ADDR (0x4E) 80 #define HDMI_TX_CEC_I2C_SLAVE_ADDR (0x9C) 81 #define MIPI_RX_ADDR (0x6C) 82 83 #define IT6161_I2C_ModifyReg(handle, addr, reg, mask, value) \ 84 VIDEO_I2C_ModifyReg(addr, kVIDEO_RegAddr8Bit, (reg), kVIDEO_RegWidth8Bit, mask, (value), \ 85 ((const it6161_resource_t *)((handle)->resource))->i2cReceiveFunc, \ 86 ((const it6161_resource_t *)((handle)->resource))->i2cSendFunc) 87 88 #define IT6161_I2C_WriteReg(handle, addr, reg, value) \ 89 VIDEO_I2C_WriteReg(addr, kVIDEO_RegAddr8Bit, (reg), kVIDEO_RegWidth8Bit, (value), \ 90 ((const it6161_resource_t *)((handle)->resource))->i2cSendFunc) 91 92 #define IT6161_I2C_WriteRegs(handle, addr, reg, value, len) \ 93 VIDEO_I2C_WriteReg(addr, kVIDEO_RegAddr8Bit, reg, (video_reg_width_t)len, value, \ 94 ((const it6161_resource_t *)((handle)->resource))->i2cSendFunc) 95 96 #define IT6161_I2C_ReadRegs(handle, addr, reg, value, len) \ 97 VIDEO_I2C_ReadReg(addr, kVIDEO_RegAddr8Bit, reg, (video_reg_width_t)len, (value), \ 98 ((const it6161_resource_t *)((handle)->resource))->i2cReceiveFunc) 99 100 #define HDMITX_ReadI2C_Byte(handle, RegAddr, pValue) IT6161_I2C_ReadRegs(handle, HDMI_TX_ADDR, RegAddr, pValue, 1) 101 #define HDMITX_WriteI2C_Byte(handle, RegAddr, value) IT6161_I2C_WriteReg(handle, HDMI_TX_ADDR, RegAddr, value) 102 #define HDMITX_ReadI2C_Bytes(handle, RegAddr, pValue, num) \ 103 IT6161_I2C_ReadRegs(handle, HDMI_TX_ADDR, RegAddr, pValue, num) 104 #define HDMITX_WriteI2C_Bytes(handle, RegAddr, pValue, num) \ 105 IT6161_I2C_WriteRegs(handle, HDMI_TX_ADDR, RegAddr, pValue, num) 106 #define HDMITX_SetI2C_Byte(handle, RegAddr, Mask, Value) \ 107 IT6161_I2C_ModifyReg(handle, HDMI_TX_ADDR, RegAddr, Mask, Value) 108 109 #define HDMITX_CEC_ReadI2C_Byte(handle, RegAddr, pValue) \ 110 IT6161_I2C_ReadRegs(handle, HDMI_TX_CEC_ADDR, RegAddr, pValue, 1) 111 #define HDMITX_CEC_WriteI2C_Byte(handle, RegAddr, value) IT6161_I2C_WriteReg(handle, HDMI_TX_CEC_ADDR, RegAddr, value) 112 #define HDMITX_CEC_ReadI2C_Bytes(handle, RegAddr, pValue, num) \ 113 IT6161_I2C_ReadRegs(handle, HDMI_TX_CEC_ADDR, RegAddr, pValue, num) 114 #define HDMITX_CEC_WriteI2C_Bytes(handle, RegAddr, pValue, num) \ 115 IT6161_I2C_WriteRegs(handle, HDMI_TX_CEC_ADDR, RegAddr, pValue, num) 116 #define HDMITX_CEC_SetI2C_Byte(handle, RegAddr, Mask, Value) \ 117 IT6161_I2C_ModifyReg(handle, HDMI_TX_CEC_ADDR, RegAddr, Mask, Value) 118 119 #define MIPIRX_ReadI2C_Byte(handle, RegAddr, pValue) IT6161_I2C_ReadRegs(handle, MIPI_RX_ADDR, RegAddr, pValue, 1) 120 #define MIPIRX_WriteI2C_Byte(handle, RegAddr, value) IT6161_I2C_WriteReg(handle, MIPI_RX_ADDR, RegAddr, value) 121 #define MIPIRX_ReadI2C_Bytes(handle, RegAddr, pValue, num) \ 122 IT6161_I2C_ReadRegs(handle, MIPI_RX_ADDR, RegAddr, pValue, num) 123 #define MIPIRX_SetI2C_Byte(handle, RegAddr, Mask, Value) \ 124 IT6161_I2C_ModifyReg(handle, MIPI_RX_ADDR, RegAddr, Mask, Value) 125 126 /*! 127 * @brief IT6161 resource. 128 * 129 * The I2C instance should be initialized before calling @ref IT6161_Init. 130 */ 131 132 /* ported from linu kernel: include/drm/drm_modes.h(struct drm_display_mode) */ 133 typedef struct display_mode 134 { 135 uint16_t hdisplay; /* horizontal display size */ 136 uint16_t hsync_start; /* horizontal sync start */ 137 uint16_t hsync_end; /* horizontal sync end */ 138 uint16_t htotal; /* horizontal total size */ 139 uint16_t vdisplay; /* vertical display size */ 140 uint16_t vsync_start; /* vertical sync start */ 141 uint16_t vsync_end; /* vertical sync end */ 142 uint16_t vtotal; /* vertical total size */ 143 } display_mode_t; 144 145 typedef struct it6161_hdmi_tx_cfg 146 { 147 uint8_t hdmitx_bypass_mode; 148 uint8_t tx_clk_stable; 149 uint8_t tx_vid_stable; 150 uint8_t de_generation_enable; 151 uint8_t vertical_sync_polarity; 152 uint8_t horizontal_sync_polarity; 153 uint8_t de_only_in; 154 uint32_t rclk; 155 uint32_t pclk; 156 uint8_t input_color_space; 157 uint8_t output_color_space; 158 uint8_t support_audio; 159 uint8_t input_audio_type; 160 uint8_t input_audio_interface; 161 uint32_t input_audio_sample_freq; 162 uint8_t output_channel; 163 uint8_t hdmi_mode; 164 uint8_t bAudioChannelEnable; 165 bool pclk_div2; /* Input Data Format Register 0x70, Reg_PCLKDiv2, 0: IO latch clock = TxCLK, 1: IO latch clock = 1/2 * TxCLK */ 166 display_mode_t mode; 167 } it6161_hdmi_tx_cfg_t; 168 169 typedef struct it6161_mipi_rx_cfg 170 { 171 uint8_t lanes; 172 uint8_t mipirx_lane_swap; 173 uint8_t mipirx_dpdn_swap; 174 uint8_t inverse_mclk; 175 uint8_t inverse_pclk; 176 uint8_t enable_standby_mode; 177 uint8_t enable_standby_to_reset; 178 uint8_t enable_iddq_mode; 179 uint8_t pd_ref_clk; /* when PDREFCLK=TRUE, 0:div2, 1:div4, 2:div8, 3:div16 */ 180 uint8_t pd_ref_cnt; 181 uint8_t hs_settle_num; 182 uint8_t hs_trailing_skip_stage; 183 uint8_t enable_sync_bit_error_tolerance; 184 uint8_t enable_multi_lane_deskew; 185 uint8_t force_continuous_clock_mode; 186 uint8_t ppi_debug_selection; 187 uint8_t ignore_null_packet; 188 uint8_t ignore_blank_packet; 189 uint8_t enable_dummy_ecc_error; 190 uint8_t sel_eotp; 191 uint8_t lm_debug_selection; 192 uint8_t auto_sync_falling; 193 uint8_t interlaced_mode; 194 uint8_t user_define_timming; 195 uint8_t prec_update; 196 uint8_t mrec_update; 197 uint8_t v_timing_resync_selction; /* 0:Div2, 1:Div4, 2:Div8, 3:Div16, 4:Div32 */ 198 uint8_t enable_v_timing_resync_enhance_mode; 199 uint8_t enable_frame_resync; 200 uint16_t pps_fifo_read_start_point; 201 uint8_t enable_h_timing_resync; 202 uint8_t enable_v_timing_resync; 203 uint8_t enable_fifo_auto_reset; 204 uint8_t enable_overflow_auto_reset; 205 uint8_t enable_mclk_horizontal_average; 206 uint8_t allowable_mclk_horizontal_shift_value; 207 uint8_t allowable_pclk_horizontal_shift_value; 208 uint8_t enable_external_pclk; 209 uint8_t bypass_through_mode; 210 uint8_t enable_ttl_tx_crc; 211 uint8_t crc_frame_number; 212 uint32_t rclk; 213 uint32_t pclk; 214 } it6161_mipi_rx_cfg_t; 215 216 enum it6161_active_level 217 { 218 LOW_LVL, 219 HIGH_LVL, 220 }; 221 222 enum hdmi_packet_type 223 { 224 HDMI_PACKET_TYPE_NULL = 0x00, 225 HDMI_PACKET_TYPE_AUDIO_CLOCK_REGEN = 0x01, 226 HDMI_PACKET_TYPE_AUDIO_SAMPLE = 0x02, 227 HDMI_PACKET_TYPE_GENERAL_CONTROL = 0x03, 228 HDMI_PACKET_TYPE_ACP = 0x04, 229 HDMI_PACKET_TYPE_ISRC1 = 0x05, 230 HDMI_PACKET_TYPE_ISRC2 = 0x06, 231 HDMI_PACKET_TYPE_ONE_BIT_AUDIO_SAMPLE = 0x07, 232 HDMI_PACKET_TYPE_DST_AUDIO = 0x08, 233 HDMI_PACKET_TYPE_HBR_AUDIO_STREAM = 0x09, 234 HDMI_PACKET_TYPE_GAMUT_METADATA = 0x0a, 235 /* + enum hdmi_infoframe_type */ 236 }; 237 238 enum hdmi_infoframe_type 239 { 240 HDMI_INFOFRAME_TYPE_VENDOR = 0x81, 241 HDMI_INFOFRAME_TYPE_AVI = 0x82, 242 HDMI_INFOFRAME_TYPE_SPD = 0x83, 243 HDMI_INFOFRAME_TYPE_AUDIO = 0x84, 244 HDMI_INFOFRAME_TYPE_DRM = 0x87, 245 }; 246 247 #define HDMI_IEEE_OUI 0x000c03 248 #define HDMI_FORUM_IEEE_OUI 0xc45dd8 249 #define HDMI_INFOFRAME_HEADER_SIZE 4U 250 #define HDMI_AVI_INFOFRAME_SIZE 13U 251 #define HDMI_SPD_INFOFRAME_SIZE 25 252 #define HDMI_AUDIO_INFOFRAME_SIZE 10U 253 #define HDMI_DRM_INFOFRAME_SIZE 26 254 #define HDMI_VENDOR_INFOFRAME_SIZE 4 255 256 #define HDMI_INFOFRAME_SIZE(type) (HDMI_INFOFRAME_HEADER_SIZE + HDMI_##type##_INFOFRAME_SIZE) 257 258 struct hdmi_any_infoframe 259 { 260 enum hdmi_infoframe_type type; 261 uint8_t version; 262 uint8_t length; 263 }; 264 265 enum hdmi_colorspace 266 { 267 HDMI_COLORSPACE_RGB, 268 HDMI_COLORSPACE_YUV422, 269 HDMI_COLORSPACE_YUV444, 270 HDMI_COLORSPACE_YUV420, 271 HDMI_COLORSPACE_RESERVED4, 272 HDMI_COLORSPACE_RESERVED5, 273 HDMI_COLORSPACE_RESERVED6, 274 HDMI_COLORSPACE_IDO_DEFINED, 275 }; 276 277 enum hdmi_scan_mode 278 { 279 HDMI_SCAN_MODE_NONE, 280 HDMI_SCAN_MODE_OVERSCAN, 281 HDMI_SCAN_MODE_UNDERSCAN, 282 HDMI_SCAN_MODE_RESERVED, 283 }; 284 285 enum hdmi_colorimetry 286 { 287 HDMI_COLORIMETRY_NONE, 288 HDMI_COLORIMETRY_ITU_601, 289 HDMI_COLORIMETRY_ITU_709, 290 HDMI_COLORIMETRY_EXTENDED, 291 }; 292 293 enum hdmi_picture_aspect 294 { 295 HDMI_PICTURE_ASPECT_NONE, 296 HDMI_PICTURE_ASPECT_4_3, 297 HDMI_PICTURE_ASPECT_16_9, 298 HDMI_PICTURE_ASPECT_64_27, 299 HDMI_PICTURE_ASPECT_256_135, 300 HDMI_PICTURE_ASPECT_RESERVED, 301 }; 302 303 enum hdmi_active_aspect 304 { 305 HDMI_ACTIVE_ASPECT_16_9_TOP = 2, 306 HDMI_ACTIVE_ASPECT_14_9_TOP = 3, 307 HDMI_ACTIVE_ASPECT_16_9_CENTER = 4, 308 HDMI_ACTIVE_ASPECT_PICTURE = 8, 309 HDMI_ACTIVE_ASPECT_4_3 = 9, 310 HDMI_ACTIVE_ASPECT_16_9 = 10, 311 HDMI_ACTIVE_ASPECT_14_9 = 11, 312 HDMI_ACTIVE_ASPECT_4_3_SP_14_9 = 13, 313 HDMI_ACTIVE_ASPECT_16_9_SP_14_9 = 14, 314 HDMI_ACTIVE_ASPECT_16_9_SP_4_3 = 15, 315 }; 316 317 enum hdmi_extended_colorimetry 318 { 319 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601, 320 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709, 321 HDMI_EXTENDED_COLORIMETRY_S_YCC_601, 322 HDMI_EXTENDED_COLORIMETRY_OPYCC_601, 323 HDMI_EXTENDED_COLORIMETRY_OPRGB, 324 325 /* The following EC values are only defined in CEA-861-F. */ 326 HDMI_EXTENDED_COLORIMETRY_BT2020_CONST_LUM, 327 HDMI_EXTENDED_COLORIMETRY_BT2020, 328 HDMI_EXTENDED_COLORIMETRY_RESERVED, 329 }; 330 331 enum hdmi_quantization_range 332 { 333 HDMI_QUANTIZATION_RANGE_DEFAULT, 334 HDMI_QUANTIZATION_RANGE_LIMITED, 335 HDMI_QUANTIZATION_RANGE_FULL, 336 HDMI_QUANTIZATION_RANGE_RESERVED, 337 }; 338 339 /* non-uniform picture scaling */ 340 enum hdmi_nups 341 { 342 HDMI_NUPS_UNKNOWN, 343 HDMI_NUPS_HORIZONTAL, 344 HDMI_NUPS_VERTICAL, 345 HDMI_NUPS_BOTH, 346 }; 347 348 enum hdmi_ycc_quantization_range 349 { 350 HDMI_YCC_QUANTIZATION_RANGE_LIMITED, 351 HDMI_YCC_QUANTIZATION_RANGE_FULL, 352 }; 353 354 enum hdmi_content_type 355 { 356 HDMI_CONTENT_TYPE_GRAPHICS, 357 HDMI_CONTENT_TYPE_PHOTO, 358 HDMI_CONTENT_TYPE_CINEMA, 359 HDMI_CONTENT_TYPE_GAME, 360 }; 361 362 enum hdmi_metadata_type 363 { 364 HDMI_STATIC_METADATA_TYPE1 = 1, 365 }; 366 367 enum hdmi_eotf 368 { 369 HDMI_EOTF_TRADITIONAL_GAMMA_SDR, 370 HDMI_EOTF_TRADITIONAL_GAMMA_HDR, 371 HDMI_EOTF_SMPTE_ST2084, 372 HDMI_EOTF_BT_2100_HLG, 373 }; 374 375 enum hdmi_audio_coding_type 376 { 377 HDMI_AUDIO_CODING_TYPE_STREAM, 378 HDMI_AUDIO_CODING_TYPE_PCM, 379 HDMI_AUDIO_CODING_TYPE_AC3, 380 HDMI_AUDIO_CODING_TYPE_MPEG1, 381 HDMI_AUDIO_CODING_TYPE_MP3, 382 HDMI_AUDIO_CODING_TYPE_MPEG2, 383 HDMI_AUDIO_CODING_TYPE_AAC_LC, 384 HDMI_AUDIO_CODING_TYPE_DTS, 385 HDMI_AUDIO_CODING_TYPE_ATRAC, 386 HDMI_AUDIO_CODING_TYPE_DSD, 387 HDMI_AUDIO_CODING_TYPE_EAC3, 388 HDMI_AUDIO_CODING_TYPE_DTS_HD, 389 HDMI_AUDIO_CODING_TYPE_MLP, 390 HDMI_AUDIO_CODING_TYPE_DST, 391 HDMI_AUDIO_CODING_TYPE_WMA_PRO, 392 HDMI_AUDIO_CODING_TYPE_CXT, 393 }; 394 395 enum hdmi_audio_sample_size 396 { 397 HDMI_AUDIO_SAMPLE_SIZE_STREAM, 398 HDMI_AUDIO_SAMPLE_SIZE_16, 399 HDMI_AUDIO_SAMPLE_SIZE_20, 400 HDMI_AUDIO_SAMPLE_SIZE_24, 401 }; 402 403 enum hdmi_audio_sample_frequency 404 { 405 HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM, 406 HDMI_AUDIO_SAMPLE_FREQUENCY_32000, 407 HDMI_AUDIO_SAMPLE_FREQUENCY_44100, 408 HDMI_AUDIO_SAMPLE_FREQUENCY_48000, 409 HDMI_AUDIO_SAMPLE_FREQUENCY_88200, 410 HDMI_AUDIO_SAMPLE_FREQUENCY_96000, 411 HDMI_AUDIO_SAMPLE_FREQUENCY_176400, 412 HDMI_AUDIO_SAMPLE_FREQUENCY_192000, 413 }; 414 415 enum hdmi_audio_coding_type_ext 416 { 417 /* Refer to Audio Coding Type (CT) field in Data Byte 1 */ 418 HDMI_AUDIO_CODING_TYPE_EXT_CT, 419 420 /* 421 * The next three CXT values are defined in CEA-861-E only. 422 * They do not exist in older versions, and in CEA-861-F they are 423 * defined as 'Not in use'. 424 */ 425 HDMI_AUDIO_CODING_TYPE_EXT_HE_AAC, 426 HDMI_AUDIO_CODING_TYPE_EXT_HE_AAC_V2, 427 HDMI_AUDIO_CODING_TYPE_EXT_MPEG_SURROUND, 428 429 /* The following CXT values are only defined in CEA-861-F. */ 430 HDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC, 431 HDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC_V2, 432 HDMI_AUDIO_CODING_TYPE_EXT_MPEG4_AAC_LC, 433 HDMI_AUDIO_CODING_TYPE_EXT_DRA, 434 HDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC_SURROUND, 435 HDMI_AUDIO_CODING_TYPE_EXT_MPEG4_AAC_LC_SURROUND = 10, 436 }; 437 438 struct hdmi_avi_infoframe 439 { 440 enum hdmi_infoframe_type type; 441 uint8_t version; 442 uint8_t length; 443 enum hdmi_colorspace colorspace; 444 enum hdmi_scan_mode scan_mode; 445 enum hdmi_colorimetry colorimetry; 446 enum hdmi_picture_aspect picture_aspect; 447 enum hdmi_active_aspect active_aspect; 448 bool itc; 449 enum hdmi_extended_colorimetry extended_colorimetry; 450 enum hdmi_quantization_range quantization_range; 451 enum hdmi_nups nups; 452 uint8_t video_code; 453 enum hdmi_ycc_quantization_range ycc_quantization_range; 454 enum hdmi_content_type content_type; 455 uint8_t pixel_repeat; 456 uint32_t top_bar; 457 uint32_t bottom_bar; 458 uint32_t left_bar; 459 uint32_t right_bar; 460 }; 461 462 struct hdmi_audio_infoframe 463 { 464 enum hdmi_infoframe_type type; 465 uint8_t version; 466 uint8_t length; 467 uint8_t channels; 468 enum hdmi_audio_coding_type coding_type; 469 enum hdmi_audio_sample_frequency sample_frequency; 470 enum hdmi_audio_sample_size sample_size; 471 enum hdmi_audio_coding_type_ext coding_type_ext; 472 uint8_t channel_allocation; 473 uint8_t level_shift_value; 474 bool downmix_inhibit; 475 }; 476 477 typedef struct it6161_cfg 478 { 479 it6161_mipi_rx_cfg_t mipi_rx; 480 it6161_hdmi_tx_cfg_t hdmi_tx; 481 display_mode_t mode; 482 struct hdmi_avi_infoframe source_avi_infoframe; 483 } it6161_cfg_t; 484 485 typedef struct _it6161_resource 486 { 487 video_i2c_send_func_t i2cSendFunc; /* I2C send function. */ 488 video_i2c_receive_func_t i2cReceiveFunc; /* I2C receive function. */ 489 void (*pullResetPin)(bool pullUp); /* Function to pull reset pin high or low. */ 490 uint8_t i2cAddr; /* I2C address, 0x4C or 0x6C. */ 491 } it6161_resource_t; 492 493 extern it6161_cfg_t it6161; 494 extern const display_operations_t it6161_ops; 495 496 /* default configurations */ 497 /* define EN_MIPIRX_BYPASS_MODE to 0x01 when want to debug input signals(MIPI_DSI) */ 498 #if 0 499 #define EN_MIPIRX_BYPASS_MODE (0x01U) 500 #else 501 #define EN_MIPIRX_BYPASS_MODE (0x00U) 502 #endif 503 504 #if (EN_MIPIRX_BYPASS_MODE == 0x01U) 505 #define EN_HDMITX_BYPASS_MODE (0x01U) 506 #else 507 #define EN_HDMITX_BYPASS_MODE (0x00U) 508 #endif 509 510 #if (EN_MIPIRX_BYPASS_MODE == 0x01U) 511 #define PREC_UPDATE (0x01U) 512 #define MREC_UPDATE (0x01U) 513 #else 514 #define PREC_UPDATE (0x00U) 515 #define MREC_UPDATE (0x00U) 516 #endif 517 518 #ifndef HDMI_TX_SUPPORT_AUDIO 519 #define HDMI_TX_SUPPORT_AUDIO (false) 520 #endif 521 #ifndef HDMI_TX_OUTPUT_CHANNEL 522 #define HDMI_TX_OUTPUT_CHANNEL (0x02U) /* 2,3,4,5,6,7,8 */ 523 #endif 524 #ifndef HDMI_TX_INPUT_AUDIO_TYPE 525 #define HDMI_TX_INPUT_AUDIO_TYPE (T_AUDIO_LPCM) 526 #endif 527 #ifndef HDMI_TX_INPUT_AUDIO_INTERFACE 528 #define HDMI_TX_INPUT_AUDIO_INTERFACE (AUDIO_IF_I2S) 529 #endif 530 #ifndef HDMI_TX_INPUT_AUDIO_SAMPLE_FREQ 531 #define HDMI_TX_INPUT_AUDIO_SAMPLE_FREQ (AUDFS_48KHz) 532 #endif 533 #ifndef HDMI_TX_PCLK_DIV2 534 #define HDMI_TX_PCLK_DIV2 (false) 535 #endif 536 #define NRTXRCLK (0x01U) /* true:set TRCLK by self */ 537 #define FORCE_TXCLK_STABLE (0x01U) 538 #define STABLE_LINEPIEXELCNT_SENSITIVITY (0x01U) 539 #define RCLK_FREQ_SEL (0x01U) /* false: 10MHz(div1); true: 20 MHz(OSSDIV2) */ 540 #define FORCE_TX_CLK_STABLE (0x01U) 541 #define FORCE_TX_VID_STABLE (0x01U) 542 #define V_SYNC_POL (0x00U) /* 0: active low; 1: active high */ 543 #define H_SYNC_POL (0x00U) /* 0: active low; 1: active high */ 544 #if (EN_MIPIRX_BYPASS_MODE == 0x01U) 545 #define EN_HDMITX_BYPASS_MODE (0x01U) 546 #else 547 #define EN_HDMITX_BYPASS_MODE (0x00U) 548 #endif 549 550 /* DEBUG MACROS */ 551 #ifndef DEBUG_DUMP_HDMITX_REGISTER 552 #define DEBUG_DUMP_HDMITX_REGISTER (0x00U) 553 #endif 554 #ifndef DEBUG_DUMP_MIPIRX_REGISTER 555 #define DEBUG_DUMP_MIPIRX_REGISTER (0x00U) 556 #endif 557 558 #if 1 559 #define MIPIRX_DEBUG_PRINTF(...) 560 #else 561 #define MIPIRX_DEBUG_PRINTF PRINTF 562 #endif 563 #if 1 564 #define HDMITX_DEBUG_PRINTF(...) 565 #else 566 #define HDMITX_DEBUG_PRINTF PRINTF 567 #endif 568 569 /******************************************************************************* 570 * API 571 ******************************************************************************/ 572 573 #if defined(__cplusplus) 574 extern "C" { 575 #endif 576 577 status_t IT6161_Init(display_handle_t *handle, const display_config_t *config); 578 579 status_t IT6161_Deinit(display_handle_t *handle); 580 581 status_t IT6161_Start(display_handle_t *handle); 582 583 status_t IT6161_Stop(display_handle_t *handle); 584 585 void IT6161_Interrupt(display_handle_t *handle); 586 #if defined(__cplusplus) 587 } 588 #endif 589 590 void HDMITX_RegEE_Process(display_handle_t *handle, uint8_t RegEE); 591 592 void HDMITX_Reg06_Process(display_handle_t *handle, uint8_t Reg06); 593 594 void HDMITX_Reg08_Process(display_handle_t *handle, uint8_t Reg08); 595 596 void HDMI_InfoframeSetChecksum(void *buffer, int32_t size); 597 598 void HDMI_AviInfoframeInit(struct hdmi_avi_infoframe *frame); 599 600 int32_t HDMITX_CalcPclk(display_handle_t *handle); 601 602 uint8_t HDMI_InfoframeChecksum(void *buffer, int32_t size); 603 604 int32_t HDMI_AviInfoframePack(struct hdmi_avi_infoframe *frame, void *buffer, int32_t size); 605 606 int32_t HDMI_AudioInfoframePack(struct hdmi_audio_infoframe *frame, void *buffer, int32_t size); 607 608 void it6161_SetIntActiveLevel(display_handle_t *handle, enum it6161_active_level level); 609 610 void it6161_IntMaskEnable(display_handle_t *handle); 611 612 void it6161_HDMITX_Init(display_handle_t *handle); 613 614 #endif /* _FSL_IT6161_H_ */ 615
