1 /**
2   ******************************************************************************
3   * @file    asm330lhh_reg.h
4   * @author  Sensors Software Solution Team
5   * @brief   This file contains all the functions prototypes for the
6   *          asm330lhh_reg.c driver.
7   ******************************************************************************
8   * @attention
9   *
10   * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.
11   * All rights reserved.</center></h2>
12   *
13   * This software component is licensed by ST under BSD 3-Clause license,
14   * the "License"; You may not use this file except in compliance with the
15   * License. You may obtain a copy of the License at:
16   *                        opensource.org/licenses/BSD-3-Clause
17   *
18   ******************************************************************************
19   */
20 
21 /* Define to prevent recursive inclusion -------------------------------------*/
22 #ifndef ASM330LHH_REGS_H
23 #define ASM330LHH_REGS_H
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
29 /* Includes ------------------------------------------------------------------*/
30 #include <stdint.h>
31 #include <stddef.h>
32 #include <math.h>
33 
34 /** @addtogroup ASM330LHH
35   * @{
36   *
37   */
38 
39 /** @defgroup  Endianness definitions
40   * @{
41   *
42   */
43 
44 #ifndef DRV_BYTE_ORDER
45 #ifndef __BYTE_ORDER__
46 
47 #define DRV_LITTLE_ENDIAN 1234
48 #define DRV_BIG_ENDIAN    4321
49 
50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture
51   * by uncommenting the define which fits your platform endianness
52   */
53 //#define DRV_BYTE_ORDER    DRV_BIG_ENDIAN
54 #define DRV_BYTE_ORDER    DRV_LITTLE_ENDIAN
55 
56 #else /* defined __BYTE_ORDER__ */
57 
58 #define DRV_LITTLE_ENDIAN  __ORDER_LITTLE_ENDIAN__
59 #define DRV_BIG_ENDIAN     __ORDER_BIG_ENDIAN__
60 #define DRV_BYTE_ORDER     __BYTE_ORDER__
61 
62 #endif /* __BYTE_ORDER__*/
63 #endif /* DRV_BYTE_ORDER */
64 
65 /**
66   * @}
67   *
68   */
69 
70 /** @defgroup STMicroelectronics sensors common types
71   * @{
72   *
73   */
74 
75 #ifndef MEMS_SHARED_TYPES
76 #define MEMS_SHARED_TYPES
77 
78 typedef struct
79 {
80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
81   uint8_t bit0       : 1;
82   uint8_t bit1       : 1;
83   uint8_t bit2       : 1;
84   uint8_t bit3       : 1;
85   uint8_t bit4       : 1;
86   uint8_t bit5       : 1;
87   uint8_t bit6       : 1;
88   uint8_t bit7       : 1;
89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
90   uint8_t bit7       : 1;
91   uint8_t bit6       : 1;
92   uint8_t bit5       : 1;
93   uint8_t bit4       : 1;
94   uint8_t bit3       : 1;
95   uint8_t bit2       : 1;
96   uint8_t bit1       : 1;
97   uint8_t bit0       : 1;
98 #endif /* DRV_BYTE_ORDER */
99 } bitwise_t;
100 
101 #define PROPERTY_DISABLE                (0U)
102 #define PROPERTY_ENABLE                 (1U)
103 
104 /** @addtogroup  Interfaces_Functions
105   * @brief       This section provide a set of functions used to read and
106   *              write a generic register of the device.
107   *              MANDATORY: return 0 -> no Error.
108   * @{
109   *
110   */
111 
112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec);
115 
116 typedef struct
117 {
118   /** Component mandatory fields **/
119   stmdev_write_ptr  write_reg;
120   stmdev_read_ptr   read_reg;
121   /** Component optional fields **/
122   stmdev_mdelay_ptr   mdelay;
123   /** Customizable optional pointer **/
124   void *handle;
125 } stmdev_ctx_t;
126 
127 /**
128   * @}
129   *
130   */
131 
132 #endif /* MEMS_SHARED_TYPES */
133 
134 #ifndef MEMS_UCF_SHARED_TYPES
135 #define MEMS_UCF_SHARED_TYPES
136 
137 /** @defgroup    Generic address-data structure definition
138   * @brief       This structure is useful to load a predefined configuration
139   *              of a sensor.
140   *              You can create a sensor configuration by your own or using
141   *              Unico / Unicleo tools available on STMicroelectronics
142   *              web site.
143   *
144   * @{
145   *
146   */
147 
148 typedef struct
149 {
150   uint8_t address;
151   uint8_t data;
152 } ucf_line_t;
153 
154 /**
155   * @}
156   *
157   */
158 
159 #endif /* MEMS_UCF_SHARED_TYPES */
160 
161 /**
162   * @}
163   *
164   */
165 
166 /** @defgroup ASM330LHH Infos
167   * @{
168   *
169   */
170 
171 /** I2C Device Address 8 bit format  if SA0=0 -> D5 if SA0=1 -> D7 **/
172 #define ASM330LHH_I2C_ADD_L                    0xD5U
173 #define ASM330LHH_I2C_ADD_H                    0xD7U
174 
175 /** Device Identification (Who am I) **/
176 #define ASM330LHH_ID                           0x6BU
177 
178 /**
179   * @}
180   *
181   */
182 
183 #define ASM330LHH_PIN_CTRL                     0x02U
184 typedef struct
185 {
186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
187   uint8_t not_used_01              : 6;
188   uint8_t sdo_pu_en                : 1;
189   uint8_t not_used_02              : 1;
190 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
191   uint8_t not_used_02              : 1;
192   uint8_t sdo_pu_en                : 1;
193   uint8_t not_used_01              : 6;
194 #endif /* DRV_BYTE_ORDER */
195 } asm330lhh_pin_ctrl_t;
196 
197 #define ASM330LHH_FIFO_CTRL1                   0x07U
198 typedef struct
199 {
200   uint8_t wtm                      : 8;
201 } asm330lhh_fifo_ctrl1_t;
202 
203 #define ASM330LHH_FIFO_CTRL2                   0x08U
204 typedef struct
205 {
206 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
207   uint8_t wtm                      : 1;
208   uint8_t not_used_01              : 3;
209   uint8_t odrchg_en                : 1;
210   uint8_t not_used_02              : 2;
211   uint8_t stop_on_wtm              : 1;
212 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
213   uint8_t stop_on_wtm              : 1;
214   uint8_t not_used_02              : 2;
215   uint8_t odrchg_en                : 1;
216   uint8_t not_used_01              : 3;
217   uint8_t wtm                      : 1;
218 #endif /* DRV_BYTE_ORDER */
219 } asm330lhh_fifo_ctrl2_t;
220 
221 #define ASM330LHH_FIFO_CTRL3                   0x09U
222 typedef struct
223 {
224 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
225   uint8_t bdr_xl                   : 4;
226   uint8_t bdr_gy                   : 4;
227 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
228   uint8_t bdr_gy                   : 4;
229   uint8_t bdr_xl                   : 4;
230 #endif /* DRV_BYTE_ORDER */
231 } asm330lhh_fifo_ctrl3_t;
232 
233 #define ASM330LHH_FIFO_CTRL4                   0x0AU
234 typedef struct
235 {
236 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
237   uint8_t fifo_mode                : 3;
238   uint8_t not_used_01              : 1;
239   uint8_t odr_t_batch              : 2;
240   uint8_t dec_ts_batch             : 2;
241 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
242   uint8_t dec_ts_batch             : 2;
243   uint8_t odr_t_batch              : 2;
244   uint8_t not_used_01              : 1;
245   uint8_t fifo_mode                : 3;
246 #endif /* DRV_BYTE_ORDER */
247 } asm330lhh_fifo_ctrl4_t;
248 
249 #define ASM330LHH_COUNTER_BDR_REG1             0x0BU
250 typedef struct
251 {
252 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
253   uint8_t cnt_bdr_th               : 2;
254   uint8_t not_used_01              : 3;
255   uint8_t trig_counter_bdr         : 1;
256   uint8_t rst_counter_bdr          : 1;
257   uint8_t dataready_pulsed         : 1;
258 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
259   uint8_t dataready_pulsed         : 1;
260   uint8_t rst_counter_bdr          : 1;
261   uint8_t trig_counter_bdr         : 1;
262   uint8_t not_used_01              : 3;
263   uint8_t cnt_bdr_th               : 2;
264 #endif /* DRV_BYTE_ORDER */
265 } asm330lhh_counter_bdr_reg1_t;
266 
267 #define ASM330LHH_COUNTER_BDR_REG2             0x0CU
268 typedef struct
269 {
270   uint8_t cnt_bdr_th               : 8;
271 } asm330lhh_counter_bdr_reg2_t;
272 
273 #define ASM330LHH_INT1_CTRL                    0x0DU
274 typedef struct
275 {
276 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
277   uint8_t int1_drdy_xl             : 1;
278   uint8_t int1_drdy_g              : 1;
279   uint8_t int1_boot                : 1;
280   uint8_t int1_fifo_th             : 1;
281   uint8_t int1_fifo_ovr            : 1;
282   uint8_t int1_fifo_full           : 1;
283   uint8_t int1_cnt_bdr             : 1;
284   uint8_t den_drdy_flag            : 1;
285 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
286   uint8_t den_drdy_flag            : 1;
287   uint8_t int1_cnt_bdr             : 1;
288   uint8_t int1_fifo_full           : 1;
289   uint8_t int1_fifo_ovr            : 1;
290   uint8_t int1_fifo_th             : 1;
291   uint8_t int1_boot                : 1;
292   uint8_t int1_drdy_g              : 1;
293   uint8_t int1_drdy_xl             : 1;
294 #endif /* DRV_BYTE_ORDER */
295 } asm330lhh_int1_ctrl_t;
296 
297 #define ASM330LHH_INT2_CTRL                    0x0EU
298 typedef struct
299 {
300 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
301   uint8_t int2_drdy_xl             : 1;
302   uint8_t int2_drdy_g              : 1;
303   uint8_t int2_drdy_temp           : 1;
304   uint8_t int2_fifo_th             : 1;
305   uint8_t int2_fifo_ovr            : 1;
306   uint8_t int2_fifo_full           : 1;
307   uint8_t int2_cnt_bdr             : 1;
308   uint8_t not_used_01              : 1;
309 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
310   uint8_t not_used_01              : 1;
311   uint8_t int2_cnt_bdr             : 1;
312   uint8_t int2_fifo_full           : 1;
313   uint8_t int2_fifo_ovr            : 1;
314   uint8_t int2_fifo_th             : 1;
315   uint8_t int2_drdy_temp           : 1;
316   uint8_t int2_drdy_g              : 1;
317   uint8_t int2_drdy_xl             : 1;
318 #endif /* DRV_BYTE_ORDER */
319 } asm330lhh_int2_ctrl_t;
320 
321 #define ASM330LHH_WHO_AM_I                     0x0FU
322 #define ASM330LHH_CTRL1_XL                     0x10U
323 typedef struct
324 {
325 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
326   uint8_t not_used_01              : 1;
327   uint8_t lpf2_xl_en               : 1;
328   uint8_t fs_xl                    : 2;
329   uint8_t odr_xl                   : 4;
330 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
331   uint8_t odr_xl                   : 4;
332   uint8_t fs_xl                    : 2;
333   uint8_t lpf2_xl_en               : 1;
334   uint8_t not_used_01              : 1;
335 #endif /* DRV_BYTE_ORDER */
336 } asm330lhh_ctrl1_xl_t;
337 
338 #define ASM330LHH_CTRL2_G                      0x11U
339 typedef struct
340 {
341 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
342   uint8_t fs_g                     : 4; /* fs_4000 + fs_125 + fs_g */
343   uint8_t odr_g                    : 4;
344 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
345   uint8_t odr_g                    : 4;
346   uint8_t fs_g                     : 4; /* fs_4000 + fs_125 + fs_g */
347 #endif /* DRV_BYTE_ORDER */
348 } asm330lhh_ctrl2_g_t;
349 
350 #define ASM330LHH_CTRL3_C                      0x12U
351 typedef struct
352 {
353 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
354   uint8_t sw_reset                 : 1;
355   uint8_t not_used_01              : 1;
356   uint8_t if_inc                   : 1;
357   uint8_t sim                      : 1;
358   uint8_t pp_od                    : 1;
359   uint8_t h_lactive                : 1;
360   uint8_t bdu                      : 1;
361   uint8_t boot                     : 1;
362 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
363   uint8_t boot                     : 1;
364   uint8_t bdu                      : 1;
365   uint8_t h_lactive                : 1;
366   uint8_t pp_od                    : 1;
367   uint8_t sim                      : 1;
368   uint8_t if_inc                   : 1;
369   uint8_t not_used_01              : 1;
370   uint8_t sw_reset                 : 1;
371 #endif /* DRV_BYTE_ORDER */
372 } asm330lhh_ctrl3_c_t;
373 
374 #define ASM330LHH_CTRL4_C                      0x13U
375 typedef struct
376 {
377 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
378   uint8_t not_used_01              : 1;
379   uint8_t lpf1_sel_g               : 1;
380   uint8_t i2c_disable              : 1;
381   uint8_t drdy_mask                : 1;
382   uint8_t not_used_02              : 1;
383   uint8_t int2_on_int1             : 1;
384   uint8_t sleep_g                  : 1;
385   uint8_t not_used_03              : 1;
386 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
387   uint8_t not_used_03              : 1;
388   uint8_t sleep_g                  : 1;
389   uint8_t int2_on_int1             : 1;
390   uint8_t not_used_02              : 1;
391   uint8_t drdy_mask                : 1;
392   uint8_t i2c_disable              : 1;
393   uint8_t lpf1_sel_g               : 1;
394   uint8_t not_used_01              : 1;
395 #endif /* DRV_BYTE_ORDER */
396 } asm330lhh_ctrl4_c_t;
397 
398 #define ASM330LHH_CTRL5_C                      0x14U
399 typedef struct
400 {
401 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
402   uint8_t st_xl                    : 2;
403   uint8_t st_g                     : 2;
404   uint8_t not_used_01              : 1;
405   uint8_t rounding                 : 2;
406   uint8_t not_used_02              : 1;
407 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
408   uint8_t not_used_02              : 1;
409   uint8_t rounding                 : 2;
410   uint8_t not_used_01              : 1;
411   uint8_t st_g                     : 2;
412   uint8_t st_xl                    : 2;
413 #endif /* DRV_BYTE_ORDER */
414 } asm330lhh_ctrl5_c_t;
415 
416 #define ASM330LHH_CTRL6_C                      0x15U
417 typedef struct
418 {
419 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
420   uint8_t ftype                    : 3;
421   uint8_t usr_off_w                : 1;
422   uint8_t not_used_01              : 1;
423   uint8_t den_mode                 : 3;   /* trig_en + lvl1_en + lvl2_en */
424 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
425   uint8_t den_mode                 : 3;   /* trig_en + lvl1_en + lvl2_en */
426   uint8_t not_used_01              : 1;
427   uint8_t usr_off_w                : 1;
428   uint8_t ftype                    : 3;
429 #endif /* DRV_BYTE_ORDER */
430 } asm330lhh_ctrl6_c_t;
431 
432 #define ASM330LHH_CTRL7_G                      0x16U
433 typedef struct
434 {
435 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
436   uint8_t not_used_01              : 1;
437   uint8_t usr_off_on_out           : 1;
438   uint8_t not_used_02              : 2;
439   uint8_t hpm_g                    : 2;
440   uint8_t hp_en_g                  : 1;
441   uint8_t not_used_03              : 1;
442 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
443   uint8_t not_used_03              : 1;
444   uint8_t hp_en_g                  : 1;
445   uint8_t hpm_g                    : 2;
446   uint8_t not_used_02              : 2;
447   uint8_t usr_off_on_out           : 1;
448   uint8_t not_used_01              : 1;
449 #endif /* DRV_BYTE_ORDER */
450 } asm330lhh_ctrl7_g_t;
451 
452 #define ASM330LHH_CTRL8_XL                     0x17U
453 typedef struct
454 {
455 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
456   uint8_t low_pass_on_6d           : 1;
457   uint8_t not_used_01              : 1;
458   uint8_t hp_slope_xl_en           : 1;
459   uint8_t fastsettl_mode_xl        : 1;
460   uint8_t hp_ref_mode_xl           : 1;
461   uint8_t hpcf_xl                  : 3;
462 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
463   uint8_t hpcf_xl                  : 3;
464   uint8_t hp_ref_mode_xl           : 1;
465   uint8_t fastsettl_mode_xl        : 1;
466   uint8_t hp_slope_xl_en           : 1;
467   uint8_t not_used_01              : 1;
468   uint8_t low_pass_on_6d           : 1;
469 #endif /* DRV_BYTE_ORDER */
470 } asm330lhh_ctrl8_xl_t;
471 
472 #define ASM330LHH_CTRL9_XL                     0x18U
473 typedef struct
474 {
475 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
476   uint8_t not_used_01              : 1;
477   uint8_t device_conf              : 1;
478   uint8_t den_lh                   : 1;
479   uint8_t den_xl_g                 : 2;   /* den_xl_en + den_xl_g */
480   uint8_t den_z                    : 1;
481   uint8_t den_y                    : 1;
482   uint8_t den_x                    : 1;
483 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
484   uint8_t den_x                    : 1;
485   uint8_t den_y                    : 1;
486   uint8_t den_z                    : 1;
487   uint8_t den_xl_g                 : 2;   /* den_xl_en + den_xl_g */
488   uint8_t den_lh                   : 1;
489   uint8_t device_conf              : 1;
490   uint8_t not_used_01              : 1;
491 #endif /* DRV_BYTE_ORDER */
492 } asm330lhh_ctrl9_xl_t;
493 
494 #define ASM330LHH_CTRL10_C                     0x19U
495 typedef struct
496 {
497 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
498   uint8_t not_used_01              : 5;
499   uint8_t timestamp_en             : 1;
500   uint8_t not_used_02              : 2;
501 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
502   uint8_t not_used_02              : 2;
503   uint8_t timestamp_en             : 1;
504   uint8_t not_used_01              : 5;
505 #endif /* DRV_BYTE_ORDER */
506 } asm330lhh_ctrl10_c_t;
507 
508 #define ASM330LHH_ALL_INT_SRC                  0x1AU
509 typedef struct
510 {
511 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
512   uint8_t ff_ia                    : 1;
513   uint8_t wu_ia                    : 1;
514   uint8_t not_used_01              : 2;
515   uint8_t d6d_ia                   : 1;
516   uint8_t sleep_change_ia          : 1;
517   uint8_t not_used_02              : 1;
518   uint8_t timestamp_endcount       : 1;
519 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
520   uint8_t timestamp_endcount       : 1;
521   uint8_t not_used_02              : 1;
522   uint8_t sleep_change_ia          : 1;
523   uint8_t d6d_ia                   : 1;
524   uint8_t not_used_01              : 2;
525   uint8_t wu_ia                    : 1;
526   uint8_t ff_ia                    : 1;
527 #endif /* DRV_BYTE_ORDER */
528 } asm330lhh_all_int_src_t;
529 
530 #define ASM330LHH_WAKE_UP_SRC                  0x1BU
531 typedef struct
532 {
533 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
534   uint8_t z_wu                     : 1;
535   uint8_t y_wu                     : 1;
536   uint8_t x_wu                     : 1;
537   uint8_t wu_ia                    : 1;
538   uint8_t sleep_state              : 1;
539   uint8_t ff_ia                    : 1;
540   uint8_t sleep_change_ia          : 1;
541   uint8_t not_used_01              : 1;
542 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
543   uint8_t not_used_01              : 1;
544   uint8_t sleep_change_ia          : 1;
545   uint8_t ff_ia                    : 1;
546   uint8_t sleep_state              : 1;
547   uint8_t wu_ia                    : 1;
548   uint8_t x_wu                     : 1;
549   uint8_t y_wu                     : 1;
550   uint8_t z_wu                     : 1;
551 #endif /* DRV_BYTE_ORDER */
552 } asm330lhh_wake_up_src_t;
553 
554 #define ASM330LHH_D6D_SRC                      0x1DU
555 typedef struct
556 {
557 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
558   uint8_t xl                       : 1;
559   uint8_t xh                       : 1;
560   uint8_t yl                       : 1;
561   uint8_t yh                       : 1;
562   uint8_t zl                       : 1;
563   uint8_t zh                       : 1;
564   uint8_t d6d_ia                   : 1;
565   uint8_t den_drdy                 : 1;
566 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
567   uint8_t den_drdy                 : 1;
568   uint8_t d6d_ia                   : 1;
569   uint8_t zh                       : 1;
570   uint8_t zl                       : 1;
571   uint8_t yh                       : 1;
572   uint8_t yl                       : 1;
573   uint8_t xh                       : 1;
574   uint8_t xl                       : 1;
575 #endif /* DRV_BYTE_ORDER */
576 } asm330lhh_d6d_src_t;
577 
578 #define ASM330LHH_STATUS_REG                   0x1EU
579 typedef struct
580 {
581 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
582   uint8_t xlda                     : 1;
583   uint8_t gda                      : 1;
584   uint8_t tda                      : 1;
585   uint8_t not_used_01              : 5;
586 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
587   uint8_t not_used_01              : 5;
588   uint8_t tda                      : 1;
589   uint8_t gda                      : 1;
590   uint8_t xlda                     : 1;
591 #endif /* DRV_BYTE_ORDER */
592 } asm330lhh_status_reg_t;
593 
594 #define ASM330LHH_OUT_TEMP_L                   0x20U
595 #define ASM330LHH_OUT_TEMP_H                   0x21U
596 #define ASM330LHH_OUTX_L_G                     0x22U
597 #define ASM330LHH_OUTX_H_G                     0x23U
598 #define ASM330LHH_OUTY_L_G                     0x24U
599 #define ASM330LHH_OUTY_H_G                     0x25U
600 #define ASM330LHH_OUTZ_L_G                     0x26U
601 #define ASM330LHH_OUTZ_H_G                     0x27U
602 #define ASM330LHH_OUTX_L_A                     0x28U
603 #define ASM330LHH_OUTX_H_A                     0x29U
604 #define ASM330LHH_OUTY_L_A                     0x2AU
605 #define ASM330LHH_OUTY_H_A                     0x2BU
606 #define ASM330LHH_OUTZ_L_A                     0x2CU
607 #define ASM330LHH_OUTZ_H_A                     0x2DU
608 #define ASM330LHH_FIFO_STATUS1                 0x3AU
609 typedef struct
610 {
611   uint8_t diff_fifo                : 8;
612 } asm330lhh_fifo_status1_t;
613 
614 #define ASM330LHH_FIFO_STATUS2                 0x3BU
615 typedef struct
616 {
617 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
618   uint8_t diff_fifo                : 2;
619   uint8_t not_used_01              : 1;
620   uint8_t fifo_ovr_latched         : 1;
621   uint8_t counter_bdr_ia           : 1;
622   uint8_t fifo_full_ia             : 1;
623   uint8_t fifo_ovr_ia              : 1;
624   uint8_t fifo_wtm_ia              : 1;
625 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
626   uint8_t fifo_wtm_ia              : 1;
627   uint8_t fifo_ovr_ia              : 1;
628   uint8_t fifo_full_ia             : 1;
629   uint8_t counter_bdr_ia           : 1;
630   uint8_t fifo_ovr_latched         : 1;
631   uint8_t not_used_01              : 1;
632   uint8_t diff_fifo                : 2;
633 #endif /* DRV_BYTE_ORDER */
634 } asm330lhh_fifo_status2_t;
635 
636 #define ASM330LHH_TIMESTAMP0                   0x40U
637 #define ASM330LHH_TIMESTAMP1                   0x41U
638 #define ASM330LHH_TIMESTAMP2                   0x42U
639 #define ASM330LHH_TIMESTAMP3                   0x43U
640 #define ASM330LHH_INT_CFG0                     0x56U
641 typedef struct
642 {
643 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
644   uint8_t lir                      : 1;
645   uint8_t not_used_01              : 3;
646   uint8_t slope_fds                : 1;
647   uint8_t sleep_status_on_int      : 1;
648   uint8_t int_clr_on_read          : 1;
649   uint8_t not_used_02              : 1;
650 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
651   uint8_t not_used_02              : 1;
652   uint8_t int_clr_on_read          : 1;
653   uint8_t sleep_status_on_int      : 1;
654   uint8_t slope_fds                : 1;
655   uint8_t not_used_01              : 3;
656   uint8_t lir                      : 1;
657 #endif /* DRV_BYTE_ORDER */
658 } asm330lhh_int_cfg0_t;
659 
660 #define ASM330LHH_INT_CFG1                     0x58U
661 typedef struct
662 {
663 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
664   uint8_t not_used_01              : 5;
665   uint8_t inact_en                 : 2;
666   uint8_t interrupts_enable        : 1;
667 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
668   uint8_t interrupts_enable        : 1;
669   uint8_t inact_en                 : 2;
670   uint8_t not_used_01              : 5;
671 #endif /* DRV_BYTE_ORDER */
672 } asm330lhh_int_cfg1_t;
673 
674 #define ASM330LHH_THS_6D                       0x59U
675 typedef struct
676 {
677 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
678   uint8_t not_used_01              : 5;
679   uint8_t sixd_ths                 : 2;
680   uint8_t d4d_en                   : 1;
681 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
682   uint8_t d4d_en                   : 1;
683   uint8_t sixd_ths                 : 2;
684   uint8_t not_used_01              : 5;
685 #endif /* DRV_BYTE_ORDER */
686 } asm330lhh_ths_6d_t;
687 
688 #define ASM330LHH_WAKE_UP_THS                  0x5BU
689 typedef struct
690 {
691 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
692   uint8_t wk_ths                   : 6;
693   uint8_t usr_off_on_wu            : 1;
694   uint8_t not_used_01              : 1;
695 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
696   uint8_t not_used_01              : 1;
697   uint8_t usr_off_on_wu            : 1;
698   uint8_t wk_ths                   : 6;
699 #endif /* DRV_BYTE_ORDER */
700 } asm330lhh_wake_up_ths_t;
701 
702 #define ASM330LHH_WAKE_UP_DUR                  0x5CU
703 typedef struct
704 {
705 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
706   uint8_t sleep_dur                : 4;
707   uint8_t wake_ths_w               : 1;
708   uint8_t wake_dur                 : 2;
709   uint8_t ff_dur                   : 1;
710 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
711   uint8_t ff_dur                   : 1;
712   uint8_t wake_dur                 : 2;
713   uint8_t wake_ths_w               : 1;
714   uint8_t sleep_dur                : 4;
715 #endif /* DRV_BYTE_ORDER */
716 } asm330lhh_wake_up_dur_t;
717 
718 #define ASM330LHH_FREE_FALL                    0x5DU
719 typedef struct
720 {
721 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
722   uint8_t ff_ths                   : 3;
723   uint8_t ff_dur                   : 5;
724 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
725   uint8_t ff_dur                   : 5;
726   uint8_t ff_ths                   : 3;
727 #endif /* DRV_BYTE_ORDER */
728 } asm330lhh_free_fall_t;
729 
730 #define ASM330LHH_MD1_CFG                      0x5EU
731 typedef struct
732 {
733 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
734   uint8_t not_used_01              : 2;
735   uint8_t int1_6d                  : 1;
736   uint8_t not_used_02              : 1;
737   uint8_t int1_ff                  : 1;
738   uint8_t int1_wu                  : 1;
739   uint8_t not_used_03              : 1;
740   uint8_t int1_sleep_change        : 1;
741 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
742   uint8_t int1_sleep_change        : 1;
743   uint8_t not_used_03              : 1;
744   uint8_t int1_wu                  : 1;
745   uint8_t int1_ff                  : 1;
746   uint8_t not_used_02              : 1;
747   uint8_t int1_6d                  : 1;
748   uint8_t not_used_01              : 2;
749 #endif /* DRV_BYTE_ORDER */
750 } asm330lhh_md1_cfg_t;
751 
752 #define ASM330LHH_MD2_CFG                      0x5FU
753 typedef struct
754 {
755 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
756   uint8_t int2_timestamp           : 1;
757   uint8_t not_used_01              : 1;
758   uint8_t int2_6d                  : 1;
759   uint8_t not_used_02              : 1;
760   uint8_t int2_ff                  : 1;
761   uint8_t int2_wu                  : 1;
762   uint8_t not_used_03              : 1;
763   uint8_t int2_sleep_change        : 1;
764 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
765   uint8_t int2_sleep_change        : 1;
766   uint8_t not_used_03              : 1;
767   uint8_t int2_wu                  : 1;
768   uint8_t int2_ff                  : 1;
769   uint8_t not_used_02              : 1;
770   uint8_t int2_6d                  : 1;
771   uint8_t not_used_01              : 1;
772   uint8_t int2_timestamp           : 1;
773 #endif /* DRV_BYTE_ORDER */
774 } asm330lhh_md2_cfg_t;
775 
776 #define ASM330LHH_INTERNAL_FREQ_FINE           0x63U
777 typedef struct
778 {
779   uint8_t freq_fine                : 8;
780 } asm330lhh_internal_freq_fine_t;
781 
782 #define ASM330LHH_X_OFS_USR                    0x73U
783 #define ASM330LHH_Y_OFS_USR                    0x74U
784 #define ASM330LHH_Z_OFS_USR                    0x75U
785 #define ASM330LHH_FIFO_DATA_OUT_TAG            0x78U
786 typedef struct
787 {
788 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
789   uint8_t tag_parity               : 1;
790   uint8_t tag_cnt                  : 2;
791   uint8_t tag_sensor               : 5;
792 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
793   uint8_t tag_sensor               : 5;
794   uint8_t tag_cnt                  : 2;
795   uint8_t tag_parity               : 1;
796 #endif /* DRV_BYTE_ORDER */
797 } asm330lhh_fifo_data_out_tag_t;
798 
799 #define ASM330LHH_FIFO_DATA_OUT_X_L            0x79U
800 #define ASM330LHH_FIFO_DATA_OUT_X_H            0x7AU
801 #define ASM330LHH_FIFO_DATA_OUT_Y_L            0x7BU
802 #define ASM330LHH_FIFO_DATA_OUT_Y_H            0x7CU
803 #define ASM330LHH_FIFO_DATA_OUT_Z_L            0x7DU
804 #define ASM330LHH_FIFO_DATA_OUT_Z_H            0x7EU
805 
806 /**
807   * @defgroup ASM330LHH_Register_Union
808   * @brief    This union group all the registers having a bit-field
809   *           description.
810   *           This union is useful but it's not needed by the driver.
811   *
812   *           REMOVING this union you are compliant with:
813   *           MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
814   *
815   * @{
816   *
817   */
818 typedef union
819 {
820   asm330lhh_pin_ctrl_t                      pin_ctrl;
821   asm330lhh_fifo_ctrl1_t                    fifo_ctrl1;
822   asm330lhh_fifo_ctrl2_t                    fifo_ctrl2;
823   asm330lhh_fifo_ctrl3_t                    fifo_ctrl3;
824   asm330lhh_fifo_ctrl4_t                    fifo_ctrl4;
825   asm330lhh_counter_bdr_reg1_t              counter_bdr_reg1;
826   asm330lhh_counter_bdr_reg2_t              counter_bdr_reg2;
827   asm330lhh_int1_ctrl_t                     int1_ctrl;
828   asm330lhh_int2_ctrl_t                     int2_ctrl;
829   asm330lhh_ctrl1_xl_t                      ctrl1_xl;
830   asm330lhh_ctrl2_g_t                       ctrl2_g;
831   asm330lhh_ctrl3_c_t                       ctrl3_c;
832   asm330lhh_ctrl4_c_t                       ctrl4_c;
833   asm330lhh_ctrl5_c_t                       ctrl5_c;
834   asm330lhh_ctrl6_c_t                       ctrl6_c;
835   asm330lhh_ctrl7_g_t                       ctrl7_g;
836   asm330lhh_ctrl8_xl_t                      ctrl8_xl;
837   asm330lhh_ctrl9_xl_t                      ctrl9_xl;
838   asm330lhh_ctrl10_c_t                      ctrl10_c;
839   asm330lhh_all_int_src_t                   all_int_src;
840   asm330lhh_wake_up_src_t                   wake_up_src;
841   asm330lhh_d6d_src_t                       d6d_src;
842   asm330lhh_status_reg_t                    status_reg;
843   asm330lhh_fifo_status1_t                  fifo_status1;
844   asm330lhh_fifo_status2_t                  fifo_status2;
845   asm330lhh_int_cfg0_t                      int_cfg0;
846   asm330lhh_int_cfg1_t                      int_cfg1;
847   asm330lhh_ths_6d_t                        ths_6d;
848   asm330lhh_wake_up_ths_t                   wake_up_ths;
849   asm330lhh_wake_up_dur_t                   wake_up_dur;
850   asm330lhh_free_fall_t                     free_fall;
851   asm330lhh_md1_cfg_t                       md1_cfg;
852   asm330lhh_md2_cfg_t                       md2_cfg;
853   asm330lhh_internal_freq_fine_t            internal_freq_fine;
854   asm330lhh_fifo_data_out_tag_t             fifo_data_out_tag;
855   bitwise_t                                 bitwise;
856   uint8_t                                   byte;
857 } asm330lhh_reg_t;
858 
859 /**
860   * @}
861   *
862   */
863 
864 #ifndef __weak
865 #define __weak __attribute__((weak))
866 #endif /* __weak */
867 
868 /*
869  * These are the basic platform dependent I/O routines to read
870  * and write device registers connected on a standard bus.
871  * The driver keeps offering a default implementation based on function
872  * pointers to read/write routines for backward compatibility.
873  * The __weak directive allows the final application to overwrite
874  * them with a custom implementation.
875  */
876 
877 int32_t asm330lhh_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
878                            uint8_t *data,
879                            uint16_t len);
880 int32_t asm330lhh_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
881                             uint8_t *data,
882                             uint16_t len);
883 
884 float_t asm330lhh_from_fs2g_to_mg(int16_t lsb);
885 float_t asm330lhh_from_fs4g_to_mg(int16_t lsb);
886 float_t asm330lhh_from_fs8g_to_mg(int16_t lsb);
887 float_t asm330lhh_from_fs16g_to_mg(int16_t lsb);
888 
889 float_t asm330lhh_from_fs125dps_to_mdps(int16_t lsb);
890 float_t asm330lhh_from_fs250dps_to_mdps(int16_t lsb);
891 float_t asm330lhh_from_fs500dps_to_mdps(int16_t lsb);
892 float_t asm330lhh_from_fs1000dps_to_mdps(int16_t lsb);
893 float_t asm330lhh_from_fs2000dps_to_mdps(int16_t lsb);
894 float_t asm330lhh_from_fs4000dps_to_mdps(int16_t lsb);
895 
896 float_t asm330lhh_from_lsb_to_celsius(int16_t lsb);
897 
898 float_t asm330lhh_from_lsb_to_nsec(int32_t lsb);
899 
900 typedef enum
901 {
902   ASM330LHH_2g   = 0,
903   ASM330LHH_16g  = 1, /* if XL_FS_MODE = '1' -> ASM330LHH_2g */
904   ASM330LHH_4g   = 2,
905   ASM330LHH_8g   = 3,
906 } asm330lhh_fs_xl_t;
907 int32_t asm330lhh_xl_full_scale_set(stmdev_ctx_t *ctx,
908                                     asm330lhh_fs_xl_t val);
909 int32_t asm330lhh_xl_full_scale_get(stmdev_ctx_t *ctx,
910                                     asm330lhh_fs_xl_t *val);
911 
912 typedef enum
913 {
914   ASM330LHH_XL_ODR_OFF    = 0,
915   ASM330LHH_XL_ODR_12Hz5  = 1,
916   ASM330LHH_XL_ODR_26Hz   = 2,
917   ASM330LHH_XL_ODR_52Hz   = 3,
918   ASM330LHH_XL_ODR_104Hz  = 4,
919   ASM330LHH_XL_ODR_208Hz  = 5,
920   ASM330LHH_XL_ODR_417Hz  = 6,
921   ASM330LHH_XL_ODR_833Hz  = 7,
922   ASM330LHH_XL_ODR_1667Hz = 8,
923   ASM330LHH_XL_ODR_3333Hz = 9,
924   ASM330LHH_XL_ODR_6667Hz = 10,
925 } asm330lhh_odr_xl_t;
926 int32_t asm330lhh_xl_data_rate_set(stmdev_ctx_t *ctx,
927                                    asm330lhh_odr_xl_t val);
928 int32_t asm330lhh_xl_data_rate_get(stmdev_ctx_t *ctx,
929                                    asm330lhh_odr_xl_t *val);
930 
931 typedef enum
932 {
933   ASM330LHH_125dps = 2,
934   ASM330LHH_250dps = 0,
935   ASM330LHH_500dps = 4,
936   ASM330LHH_1000dps = 8,
937   ASM330LHH_2000dps = 12,
938   ASM330LHH_4000dps = 1,
939 } asm330lhh_fs_g_t;
940 int32_t asm330lhh_gy_full_scale_set(stmdev_ctx_t *ctx,
941                                     asm330lhh_fs_g_t val);
942 int32_t asm330lhh_gy_full_scale_get(stmdev_ctx_t *ctx,
943                                     asm330lhh_fs_g_t *val);
944 
945 typedef enum
946 {
947   ASM330LHH_GY_ODR_OFF    = 0,
948   ASM330LHH_GY_ODR_12Hz5  = 1,
949   ASM330LHH_GY_ODR_26Hz   = 2,
950   ASM330LHH_GY_ODR_52Hz   = 3,
951   ASM330LHH_GY_ODR_104Hz  = 4,
952   ASM330LHH_GY_ODR_208Hz  = 5,
953   ASM330LHH_GY_ODR_417Hz  = 6,
954   ASM330LHH_GY_ODR_833Hz  = 7,
955   ASM330LHH_GY_ODR_1667Hz = 8,
956   ASM330LHH_GY_ODR_3333Hz = 9,
957   ASM330LHH_GY_ODR_6667Hz = 10,
958 } asm330lhh_odr_g_t;
959 int32_t asm330lhh_gy_data_rate_set(stmdev_ctx_t *ctx,
960                                    asm330lhh_odr_g_t val);
961 int32_t asm330lhh_gy_data_rate_get(stmdev_ctx_t *ctx,
962                                    asm330lhh_odr_g_t *val);
963 
964 int32_t asm330lhh_block_data_update_set(stmdev_ctx_t *ctx,
965                                         uint8_t val);
966 int32_t asm330lhh_block_data_update_get(stmdev_ctx_t *ctx,
967                                         uint8_t *val);
968 
969 typedef enum
970 {
971   ASM330LHH_LSb_1mg  = 0,
972   ASM330LHH_LSb_16mg = 1,
973 } asm330lhh_usr_off_w_t;
974 int32_t asm330lhh_xl_offset_weight_set(stmdev_ctx_t *ctx,
975                                        asm330lhh_usr_off_w_t val);
976 int32_t asm330lhh_xl_offset_weight_get(stmdev_ctx_t *ctx,
977                                        asm330lhh_usr_off_w_t *val);
978 
979 typedef struct
980 {
981   asm330lhh_all_int_src_t       all_int_src;
982   asm330lhh_wake_up_src_t       wake_up_src;
983   asm330lhh_d6d_src_t           d6d_src;
984   asm330lhh_status_reg_t        status_reg;
985 } asm330lhh_all_sources_t;
986 int32_t asm330lhh_all_sources_get(stmdev_ctx_t *ctx,
987                                   asm330lhh_all_sources_t *val);
988 
989 int32_t asm330lhh_status_reg_get(stmdev_ctx_t *ctx,
990                                  asm330lhh_status_reg_t *val);
991 
992 int32_t asm330lhh_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
993                                          uint8_t *val);
994 
995 int32_t asm330lhh_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
996                                          uint8_t *val);
997 
998 int32_t asm330lhh_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
999                                            uint8_t *val);
1000 
1001 int32_t asm330lhh_xl_usr_offset_x_set(stmdev_ctx_t *ctx,
1002                                       uint8_t *buff);
1003 int32_t asm330lhh_xl_usr_offset_x_get(stmdev_ctx_t *ctx,
1004                                       uint8_t *buff);
1005 
1006 int32_t asm330lhh_xl_usr_offset_y_set(stmdev_ctx_t *ctx,
1007                                       uint8_t *buff);
1008 int32_t asm330lhh_xl_usr_offset_y_get(stmdev_ctx_t *ctx,
1009                                       uint8_t *buff);
1010 
1011 int32_t asm330lhh_xl_usr_offset_z_set(stmdev_ctx_t *ctx,
1012                                       uint8_t *buff);
1013 int32_t asm330lhh_xl_usr_offset_z_get(stmdev_ctx_t *ctx,
1014                                       uint8_t *buff);
1015 
1016 int32_t asm330lhh_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val);
1017 int32_t asm330lhh_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val);
1018 
1019 int32_t asm330lhh_timestamp_rst(stmdev_ctx_t *ctx);
1020 
1021 int32_t asm330lhh_timestamp_set(stmdev_ctx_t *ctx, uint8_t val);
1022 int32_t asm330lhh_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val);
1023 
1024 int32_t asm330lhh_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val);
1025 
1026 typedef enum
1027 {
1028   ASM330LHH_NO_ROUND      = 0,
1029   ASM330LHH_ROUND_XL      = 1,
1030   ASM330LHH_ROUND_GY      = 2,
1031   ASM330LHH_ROUND_GY_XL   = 3,
1032 } asm330lhh_rounding_t;
1033 int32_t asm330lhh_rounding_mode_set(stmdev_ctx_t *ctx,
1034                                     asm330lhh_rounding_t val);
1035 int32_t asm330lhh_rounding_mode_get(stmdev_ctx_t *ctx,
1036                                     asm330lhh_rounding_t *val);
1037 
1038 int32_t asm330lhh_temperature_raw_get(stmdev_ctx_t *ctx,
1039                                       int16_t *val);
1040 
1041 int32_t asm330lhh_angular_rate_raw_get(stmdev_ctx_t *ctx,
1042                                        int16_t *val);
1043 
1044 int32_t asm330lhh_acceleration_raw_get(stmdev_ctx_t *ctx,
1045                                        int16_t *val);
1046 
1047 int32_t asm330lhh_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *val);
1048 
1049 int32_t asm330lhh_device_conf_set(stmdev_ctx_t *ctx, uint8_t val);
1050 int32_t asm330lhh_device_conf_get(stmdev_ctx_t *ctx, uint8_t *val);
1051 
1052 int32_t asm330lhh_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val);
1053 int32_t asm330lhh_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val);
1054 
1055 typedef enum
1056 {
1057   ASM330LHH_DRDY_LATCHED = 0,
1058   ASM330LHH_DRDY_PULSED  = 1,
1059 } asm330lhh_dataready_pulsed_t;
1060 int32_t asm330lhh_data_ready_mode_set(stmdev_ctx_t *ctx,
1061                                       asm330lhh_dataready_pulsed_t val);
1062 int32_t asm330lhh_data_ready_mode_get(stmdev_ctx_t *ctx,
1063                                       asm330lhh_dataready_pulsed_t *val);
1064 
1065 int32_t asm330lhh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
1066 
1067 int32_t asm330lhh_reset_set(stmdev_ctx_t *ctx, uint8_t val);
1068 int32_t asm330lhh_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
1069 
1070 int32_t asm330lhh_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val);
1071 int32_t asm330lhh_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
1072 
1073 int32_t asm330lhh_boot_set(stmdev_ctx_t *ctx, uint8_t val);
1074 int32_t asm330lhh_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
1075 
1076 typedef enum
1077 {
1078   ASM330LHH_XL_ST_DISABLE  = 0,
1079   ASM330LHH_XL_ST_POSITIVE = 1,
1080   ASM330LHH_XL_ST_NEGATIVE = 2,
1081 } asm330lhh_st_xl_t;
1082 int32_t asm330lhh_xl_self_test_set(stmdev_ctx_t *ctx,
1083                                    asm330lhh_st_xl_t val);
1084 int32_t asm330lhh_xl_self_test_get(stmdev_ctx_t *ctx,
1085                                    asm330lhh_st_xl_t *val);
1086 
1087 typedef enum
1088 {
1089   ASM330LHH_GY_ST_DISABLE  = 0,
1090   ASM330LHH_GY_ST_POSITIVE = 1,
1091   ASM330LHH_GY_ST_NEGATIVE = 3,
1092 } asm330lhh_st_g_t;
1093 int32_t asm330lhh_gy_self_test_set(stmdev_ctx_t *ctx,
1094                                    asm330lhh_st_g_t val);
1095 int32_t asm330lhh_gy_self_test_get(stmdev_ctx_t *ctx,
1096                                    asm330lhh_st_g_t *val);
1097 
1098 int32_t asm330lhh_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val);
1099 int32_t asm330lhh_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val);
1100 
1101 int32_t asm330lhh_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val);
1102 int32_t asm330lhh_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val);
1103 
1104 int32_t asm330lhh_filter_settling_mask_set(stmdev_ctx_t *ctx,
1105                                            uint8_t val);
1106 int32_t asm330lhh_filter_settling_mask_get(stmdev_ctx_t *ctx,
1107                                            uint8_t *val);
1108 
1109 typedef enum
1110 {
1111   ASM330LHH_ULTRA_LIGHT  = 0,
1112   ASM330LHH_VERY_LIGHT   = 1,
1113   ASM330LHH_LIGHT        = 2,
1114   ASM330LHH_MEDIUM       = 3,
1115   ASM330LHH_STRONG       = 4,
1116   ASM330LHH_VERY_STRONG  = 5,
1117   ASM330LHH_AGGRESSIVE   = 6,
1118   ASM330LHH_XTREME       = 7,
1119 } asm330lhh_ftype_t;
1120 int32_t asm330lhh_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
1121                                        asm330lhh_ftype_t val);
1122 int32_t asm330lhh_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
1123                                        asm330lhh_ftype_t *val);
1124 
1125 int32_t asm330lhh_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val);
1126 int32_t asm330lhh_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val);
1127 
1128 typedef enum
1129 {
1130   ASM330LHH_HP_PATH_DISABLE_ON_OUT    = 0x00,
1131   ASM330LHH_SLOPE_ODR_DIV_4           = 0x10,
1132   ASM330LHH_HP_ODR_DIV_10             = 0x11,
1133   ASM330LHH_HP_ODR_DIV_20             = 0x12,
1134   ASM330LHH_HP_ODR_DIV_45             = 0x13,
1135   ASM330LHH_HP_ODR_DIV_100            = 0x14,
1136   ASM330LHH_HP_ODR_DIV_200            = 0x15,
1137   ASM330LHH_HP_ODR_DIV_400            = 0x16,
1138   ASM330LHH_HP_ODR_DIV_800            = 0x17,
1139   ASM330LHH_HP_REF_MD_ODR_DIV_10      = 0x31,
1140   ASM330LHH_HP_REF_MD_ODR_DIV_20      = 0x32,
1141   ASM330LHH_HP_REF_MD_ODR_DIV_45      = 0x33,
1142   ASM330LHH_HP_REF_MD_ODR_DIV_100     = 0x34,
1143   ASM330LHH_HP_REF_MD_ODR_DIV_200     = 0x35,
1144   ASM330LHH_HP_REF_MD_ODR_DIV_400     = 0x36,
1145   ASM330LHH_HP_REF_MD_ODR_DIV_800     = 0x37,
1146   ASM330LHH_LP_ODR_DIV_10             = 0x01,
1147   ASM330LHH_LP_ODR_DIV_20             = 0x02,
1148   ASM330LHH_LP_ODR_DIV_45             = 0x03,
1149   ASM330LHH_LP_ODR_DIV_100            = 0x04,
1150   ASM330LHH_LP_ODR_DIV_200            = 0x05,
1151   ASM330LHH_LP_ODR_DIV_400            = 0x06,
1152   ASM330LHH_LP_ODR_DIV_800            = 0x07,
1153 } asm330lhh_hp_slope_xl_en_t;
1154 int32_t asm330lhh_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
1155                                         asm330lhh_hp_slope_xl_en_t val);
1156 int32_t asm330lhh_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
1157                                         asm330lhh_hp_slope_xl_en_t *val);
1158 
1159 int32_t asm330lhh_xl_fast_settling_set(stmdev_ctx_t *ctx,
1160                                        uint8_t val);
1161 int32_t asm330lhh_xl_fast_settling_get(stmdev_ctx_t *ctx,
1162                                        uint8_t *val);
1163 
1164 typedef enum
1165 {
1166   ASM330LHH_USE_SLOPE = 0,
1167   ASM330LHH_USE_HPF   = 1,
1168 } asm330lhh_slope_fds_t;
1169 int32_t asm330lhh_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
1170                                           asm330lhh_slope_fds_t val);
1171 int32_t asm330lhh_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
1172                                           asm330lhh_slope_fds_t *val);
1173 
1174 typedef enum
1175 {
1176   ASM330LHH_HP_FILTER_NONE     = 0x00,
1177   ASM330LHH_HP_FILTER_16mHz    = 0x80,
1178   ASM330LHH_HP_FILTER_65mHz    = 0x81,
1179   ASM330LHH_HP_FILTER_260mHz   = 0x82,
1180   ASM330LHH_HP_FILTER_1Hz04    = 0x83,
1181 } asm330lhh_hpm_g_t;
1182 int32_t asm330lhh_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
1183                                           asm330lhh_hpm_g_t val);
1184 int32_t asm330lhh_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
1185                                           asm330lhh_hpm_g_t *val);
1186 
1187 typedef enum
1188 {
1189   ASM330LHH_PULL_UP_DISC       = 0,
1190   ASM330LHH_PULL_UP_CONNECT    = 1,
1191 } asm330lhh_sdo_pu_en_t;
1192 int32_t asm330lhh_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
1193                                    asm330lhh_sdo_pu_en_t val);
1194 int32_t asm330lhh_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
1195                                    asm330lhh_sdo_pu_en_t *val);
1196 
1197 typedef enum
1198 {
1199   ASM330LHH_SPI_4_WIRE = 0,
1200   ASM330LHH_SPI_3_WIRE = 1,
1201 } asm330lhh_sim_t;
1202 int32_t asm330lhh_spi_mode_set(stmdev_ctx_t *ctx,
1203                                asm330lhh_sim_t val);
1204 int32_t asm330lhh_spi_mode_get(stmdev_ctx_t *ctx,
1205                                asm330lhh_sim_t *val);
1206 
1207 typedef enum
1208 {
1209   ASM330LHH_I2C_ENABLE  = 0,
1210   ASM330LHH_I2C_DISABLE = 1,
1211 } asm330lhh_i2c_disable_t;
1212 int32_t asm330lhh_i2c_interface_set(stmdev_ctx_t *ctx,
1213                                     asm330lhh_i2c_disable_t val);
1214 int32_t asm330lhh_i2c_interface_get(stmdev_ctx_t *ctx,
1215                                     asm330lhh_i2c_disable_t *val);
1216 
1217 typedef struct
1218 {
1219   asm330lhh_int1_ctrl_t          int1_ctrl;
1220   asm330lhh_md1_cfg_t            md1_cfg;
1221 } asm330lhh_pin_int1_route_t;
1222 int32_t asm330lhh_pin_int1_route_set(stmdev_ctx_t *ctx,
1223                                      asm330lhh_pin_int1_route_t *val);
1224 int32_t asm330lhh_pin_int1_route_get(stmdev_ctx_t *ctx,
1225                                      asm330lhh_pin_int1_route_t *val);
1226 
1227 typedef struct
1228 {
1229   asm330lhh_int2_ctrl_t          int2_ctrl;
1230   asm330lhh_md2_cfg_t            md2_cfg;
1231 } asm330lhh_pin_int2_route_t;
1232 int32_t asm330lhh_pin_int2_route_set(stmdev_ctx_t *ctx,
1233                                      asm330lhh_pin_int2_route_t *val);
1234 int32_t asm330lhh_pin_int2_route_get(stmdev_ctx_t *ctx,
1235                                      asm330lhh_pin_int2_route_t *val);
1236 
1237 typedef enum
1238 {
1239   ASM330LHH_PUSH_PULL   = 0,
1240   ASM330LHH_OPEN_DRAIN  = 1,
1241 } asm330lhh_pp_od_t;
1242 int32_t asm330lhh_pin_mode_set(stmdev_ctx_t *ctx,
1243                                asm330lhh_pp_od_t val);
1244 int32_t asm330lhh_pin_mode_get(stmdev_ctx_t *ctx,
1245                                asm330lhh_pp_od_t *val);
1246 
1247 typedef enum
1248 {
1249   ASM330LHH_ACTIVE_HIGH = 0,
1250   ASM330LHH_ACTIVE_LOW  = 1,
1251 } asm330lhh_h_lactive_t;
1252 int32_t asm330lhh_pin_polarity_set(stmdev_ctx_t *ctx,
1253                                    asm330lhh_h_lactive_t val);
1254 int32_t asm330lhh_pin_polarity_get(stmdev_ctx_t *ctx,
1255                                    asm330lhh_h_lactive_t *val);
1256 
1257 int32_t asm330lhh_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
1258 int32_t asm330lhh_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
1259 
1260 typedef enum
1261 {
1262   ASM330LHH_ALL_INT_PULSED            = 0,
1263   ASM330LHH_ALL_INT_LATCHED           = 3,
1264 } asm330lhh_lir_t;
1265 int32_t asm330lhh_int_notification_set(stmdev_ctx_t *ctx,
1266                                        asm330lhh_lir_t val);
1267 int32_t asm330lhh_int_notification_get(stmdev_ctx_t *ctx,
1268                                        asm330lhh_lir_t *val);
1269 
1270 typedef enum
1271 {
1272   ASM330LHH_LSb_FS_DIV_64       = 0,
1273   ASM330LHH_LSb_FS_DIV_256      = 1,
1274 } asm330lhh_wake_ths_w_t;
1275 int32_t asm330lhh_wkup_ths_weight_set(stmdev_ctx_t *ctx,
1276                                       asm330lhh_wake_ths_w_t val);
1277 int32_t asm330lhh_wkup_ths_weight_get(stmdev_ctx_t *ctx,
1278                                       asm330lhh_wake_ths_w_t *val);
1279 
1280 int32_t asm330lhh_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
1281 int32_t asm330lhh_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
1282 
1283 int32_t asm330lhh_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
1284                                             uint8_t val);
1285 int32_t asm330lhh_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
1286                                             uint8_t *val);
1287 
1288 int32_t asm330lhh_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val);
1289 int32_t asm330lhh_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
1290 
1291 int32_t asm330lhh_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val);
1292 int32_t asm330lhh_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
1293 
1294 typedef enum
1295 {
1296   ASM330LHH_DRIVE_SLEEP_CHG_EVENT = 0,
1297   ASM330LHH_DRIVE_SLEEP_STATUS    = 1,
1298 } asm330lhh_sleep_status_on_int_t;
1299 int32_t asm330lhh_act_pin_notification_set(stmdev_ctx_t *ctx,
1300                                            asm330lhh_sleep_status_on_int_t val);
1301 int32_t asm330lhh_act_pin_notification_get(stmdev_ctx_t *ctx,
1302                                            asm330lhh_sleep_status_on_int_t *val);
1303 
1304 typedef enum
1305 {
1306   ASM330LHH_XL_AND_GY_NOT_AFFECTED      = 0,
1307   ASM330LHH_XL_12Hz5_GY_NOT_AFFECTED    = 1,
1308   ASM330LHH_XL_12Hz5_GY_SLEEP           = 2,
1309   ASM330LHH_XL_12Hz5_GY_PD              = 3,
1310 } asm330lhh_inact_en_t;
1311 int32_t asm330lhh_act_mode_set(stmdev_ctx_t *ctx,
1312                                asm330lhh_inact_en_t val);
1313 int32_t asm330lhh_act_mode_get(stmdev_ctx_t *ctx,
1314                                asm330lhh_inact_en_t *val);
1315 
1316 int32_t asm330lhh_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val);
1317 int32_t asm330lhh_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
1318 
1319 typedef enum
1320 {
1321   ASM330LHH_DEG_80  = 0,
1322   ASM330LHH_DEG_70  = 1,
1323   ASM330LHH_DEG_60  = 2,
1324   ASM330LHH_DEG_50  = 3,
1325 } asm330lhh_sixd_ths_t;
1326 int32_t asm330lhh_6d_threshold_set(stmdev_ctx_t *ctx,
1327                                    asm330lhh_sixd_ths_t val);
1328 int32_t asm330lhh_6d_threshold_get(stmdev_ctx_t *ctx,
1329                                    asm330lhh_sixd_ths_t *val);
1330 
1331 int32_t asm330lhh_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val);
1332 int32_t asm330lhh_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
1333 
1334 typedef enum
1335 {
1336   ASM330LHH_FF_TSH_156mg = 0,
1337   ASM330LHH_FF_TSH_219mg = 1,
1338   ASM330LHH_FF_TSH_250mg = 2,
1339   ASM330LHH_FF_TSH_312mg = 3,
1340   ASM330LHH_FF_TSH_344mg = 4,
1341   ASM330LHH_FF_TSH_406mg = 5,
1342   ASM330LHH_FF_TSH_469mg = 6,
1343   ASM330LHH_FF_TSH_500mg = 7,
1344 } asm330lhh_ff_ths_t;
1345 int32_t asm330lhh_ff_threshold_set(stmdev_ctx_t *ctx,
1346                                    asm330lhh_ff_ths_t val);
1347 int32_t asm330lhh_ff_threshold_get(stmdev_ctx_t *ctx,
1348                                    asm330lhh_ff_ths_t *val);
1349 
1350 int32_t asm330lhh_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val);
1351 int32_t asm330lhh_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
1352 
1353 int32_t asm330lhh_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val);
1354 int32_t asm330lhh_fifo_watermark_get(stmdev_ctx_t *ctx,
1355                                      uint16_t *val);
1356 
1357 int32_t asm330lhh_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
1358                                                 uint8_t val);
1359 int32_t asm330lhh_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
1360                                                 uint8_t *val);
1361 
1362 int32_t asm330lhh_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx,
1363                                        uint8_t val);
1364 int32_t asm330lhh_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx,
1365                                        uint8_t *val);
1366 
1367 typedef enum
1368 {
1369   ASM330LHH_XL_NOT_BATCHED        =  0,
1370   ASM330LHH_XL_BATCHED_AT_12Hz5   =  1,
1371   ASM330LHH_XL_BATCHED_AT_26Hz    =  2,
1372   ASM330LHH_XL_BATCHED_AT_52Hz    =  3,
1373   ASM330LHH_XL_BATCHED_AT_104Hz   =  4,
1374   ASM330LHH_XL_BATCHED_AT_208Hz   =  5,
1375   ASM330LHH_XL_BATCHED_AT_417Hz   =  6,
1376   ASM330LHH_XL_BATCHED_AT_833Hz   =  7,
1377   ASM330LHH_XL_BATCHED_AT_1667Hz  =  8,
1378   ASM330LHH_XL_BATCHED_AT_3333Hz  =  9,
1379   ASM330LHH_XL_BATCHED_AT_6667Hz  = 10,
1380   ASM330LHH_XL_BATCHED_AT_6Hz5    = 11,
1381 } asm330lhh_bdr_xl_t;
1382 int32_t asm330lhh_fifo_xl_batch_set(stmdev_ctx_t *ctx,
1383                                     asm330lhh_bdr_xl_t val);
1384 int32_t asm330lhh_fifo_xl_batch_get(stmdev_ctx_t *ctx,
1385                                     asm330lhh_bdr_xl_t *val);
1386 
1387 typedef enum
1388 {
1389   ASM330LHH_GY_NOT_BATCHED         = 0,
1390   ASM330LHH_GY_BATCHED_AT_12Hz5    = 1,
1391   ASM330LHH_GY_BATCHED_AT_26Hz     = 2,
1392   ASM330LHH_GY_BATCHED_AT_52Hz     = 3,
1393   ASM330LHH_GY_BATCHED_AT_104Hz    = 4,
1394   ASM330LHH_GY_BATCHED_AT_208Hz    = 5,
1395   ASM330LHH_GY_BATCHED_AT_417Hz    = 6,
1396   ASM330LHH_GY_BATCHED_AT_833Hz    = 7,
1397   ASM330LHH_GY_BATCHED_AT_1667Hz   = 8,
1398   ASM330LHH_GY_BATCHED_AT_3333Hz   = 9,
1399   ASM330LHH_GY_BATCHED_AT_6667Hz   = 10,
1400   ASM330LHH_GY_BATCHED_AT_6Hz5     = 11,
1401 } asm330lhh_bdr_gy_t;
1402 int32_t asm330lhh_fifo_gy_batch_set(stmdev_ctx_t *ctx,
1403                                     asm330lhh_bdr_gy_t val);
1404 int32_t asm330lhh_fifo_gy_batch_get(stmdev_ctx_t *ctx,
1405                                     asm330lhh_bdr_gy_t *val);
1406 
1407 typedef enum
1408 {
1409   ASM330LHH_BYPASS_MODE             = 0,
1410   ASM330LHH_FIFO_MODE               = 1,
1411   ASM330LHH_STREAM_TO_FIFO_MODE     = 3,
1412   ASM330LHH_BYPASS_TO_STREAM_MODE   = 4,
1413   ASM330LHH_STREAM_MODE             = 6,
1414   ASM330LHH_BYPASS_TO_FIFO_MODE     = 7,
1415 } asm330lhh_fifo_mode_t;
1416 int32_t asm330lhh_fifo_mode_set(stmdev_ctx_t *ctx,
1417                                 asm330lhh_fifo_mode_t val);
1418 int32_t asm330lhh_fifo_mode_get(stmdev_ctx_t *ctx,
1419                                 asm330lhh_fifo_mode_t *val);
1420 
1421 typedef enum
1422 {
1423   ASM330LHH_TEMP_NOT_BATCHED        = 0,
1424   ASM330LHH_TEMP_BATCHED_AT_52Hz    = 1,
1425   ASM330LHH_TEMP_BATCHED_AT_12Hz5   = 2,
1426   ASM330LHH_TEMP_BATCHED_AT_1Hz6    = 3,
1427 } asm330lhh_odr_t_batch_t;
1428 int32_t asm330lhh_fifo_temp_batch_set(stmdev_ctx_t *ctx,
1429                                       asm330lhh_odr_t_batch_t val);
1430 int32_t asm330lhh_fifo_temp_batch_get(stmdev_ctx_t *ctx,
1431                                       asm330lhh_odr_t_batch_t *val);
1432 
1433 typedef enum
1434 {
1435   ASM330LHH_NO_DECIMATION = 0,
1436   ASM330LHH_DEC_1         = 1,
1437   ASM330LHH_DEC_8         = 2,
1438   ASM330LHH_DEC_32        = 3,
1439 } asm330lhh_odr_ts_batch_t;
1440 int32_t asm330lhh_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
1441                                                 asm330lhh_odr_ts_batch_t val);
1442 int32_t asm330lhh_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
1443                                                 asm330lhh_odr_ts_batch_t *val);
1444 
1445 typedef enum
1446 {
1447   ASM330LHH_XL_BATCH_EVENT   = 0,
1448   ASM330LHH_GYRO_BATCH_EVENT = 1,
1449 } asm330lhh_trig_counter_bdr_t;
1450 int32_t asm330lhh_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
1451                                            asm330lhh_trig_counter_bdr_t val);
1452 int32_t asm330lhh_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
1453                                            asm330lhh_trig_counter_bdr_t *val);
1454 
1455 int32_t asm330lhh_rst_batch_counter_set(stmdev_ctx_t *ctx,
1456                                         uint8_t val);
1457 int32_t asm330lhh_rst_batch_counter_get(stmdev_ctx_t *ctx,
1458                                         uint8_t *val);
1459 
1460 int32_t asm330lhh_batch_counter_threshold_set(stmdev_ctx_t *ctx,
1461                                               uint16_t val);
1462 int32_t asm330lhh_batch_counter_threshold_get(stmdev_ctx_t *ctx,
1463                                               uint16_t *val);
1464 
1465 int32_t asm330lhh_fifo_data_level_get(stmdev_ctx_t *ctx,
1466                                       uint16_t *val);
1467 
1468 int32_t asm330lhh_fifo_status_get(stmdev_ctx_t *ctx,
1469                                   asm330lhh_fifo_status2_t *val);
1470 
1471 int32_t asm330lhh_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
1472 
1473 int32_t asm330lhh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
1474 
1475 int32_t asm330lhh_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
1476 
1477 typedef enum
1478 {
1479   ASM330LHH_GYRO_NC_TAG    = 1,
1480   ASM330LHH_XL_NC_TAG,
1481   ASM330LHH_TEMPERATURE_TAG,
1482   ASM330LHH_TIMESTAMP_TAG,
1483   ASM330LHH_CFG_CHANGE_TAG,
1484 } asm330lhh_fifo_tag_t;
1485 int32_t asm330lhh_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
1486                                       asm330lhh_fifo_tag_t *val);
1487 
1488 typedef enum
1489 {
1490   ASM330LHH_DEN_DISABLE    = 0,
1491   ASM330LHH_LEVEL_FIFO     = 6,
1492   ASM330LHH_LEVEL_LETCHED  = 3,
1493   ASM330LHH_LEVEL_TRIGGER  = 2,
1494   ASM330LHH_EDGE_TRIGGER   = 4,
1495 } asm330lhh_den_mode_t;
1496 int32_t asm330lhh_den_mode_set(stmdev_ctx_t *ctx,
1497                                asm330lhh_den_mode_t val);
1498 int32_t asm330lhh_den_mode_get(stmdev_ctx_t *ctx,
1499                                asm330lhh_den_mode_t *val);
1500 
1501 typedef enum
1502 {
1503   ASM330LHH_DEN_ACT_LOW  = 0,
1504   ASM330LHH_DEN_ACT_HIGH = 1,
1505 } asm330lhh_den_lh_t;
1506 int32_t asm330lhh_den_polarity_set(stmdev_ctx_t *ctx,
1507                                    asm330lhh_den_lh_t val);
1508 int32_t asm330lhh_den_polarity_get(stmdev_ctx_t *ctx,
1509                                    asm330lhh_den_lh_t *val);
1510 
1511 typedef enum
1512 {
1513   ASM330LHH_STAMP_IN_GY_DATA     = 0,
1514   ASM330LHH_STAMP_IN_XL_DATA     = 1,
1515   ASM330LHH_STAMP_IN_GY_XL_DATA  = 2,
1516 } asm330lhh_den_xl_g_t;
1517 int32_t asm330lhh_den_enable_set(stmdev_ctx_t *ctx,
1518                                  asm330lhh_den_xl_g_t val);
1519 int32_t asm330lhh_den_enable_get(stmdev_ctx_t *ctx,
1520                                  asm330lhh_den_xl_g_t *val);
1521 
1522 int32_t asm330lhh_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val);
1523 int32_t asm330lhh_den_mark_axis_x_get(stmdev_ctx_t *ctx,
1524                                       uint8_t *val);
1525 
1526 int32_t asm330lhh_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val);
1527 int32_t asm330lhh_den_mark_axis_y_get(stmdev_ctx_t *ctx,
1528                                       uint8_t *val);
1529 
1530 int32_t asm330lhh_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val);
1531 int32_t asm330lhh_den_mark_axis_z_get(stmdev_ctx_t *ctx,
1532                                       uint8_t *val);
1533 
1534 /**
1535   *@}
1536   *
1537   */
1538 
1539 #ifdef __cplusplus
1540 }
1541 #endif
1542 
1543 #endif /* ASM330LHH_REGS_H */
1544 
1545 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1546