1 /* 2 ****************************************************************************** 3 * @file asm330lhhxg1_reg.h 4 * @author Sensor Solutions Software Team 5 * @brief This file contains all the functions prototypes for the 6 * asm330lhhxg1_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2020 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef ASM330LHHXG1_REGS_H 23 #define ASM330LHHXG1_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup ASM330LHHXG1 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup ASM330LHHXG1 Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 172 #define ASM330LHHXG1_I2C_ADD_L 0xD5U 173 #define ASM330LHHXG1_I2C_ADD_H 0xD7U 174 175 /** Device Identification (Who am I) **/ 176 #define ASM330LHHXG1_ID 0x6BU 177 178 /** 179 * @} 180 * 181 */ 182 183 #define ASM330LHHXG1_FUNC_CFG_ACCESS 0x01U 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t not_used_01 : 6; 188 uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ 189 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 190 uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ 191 uint8_t not_used_01 : 6; 192 #endif /* DRV_BYTE_ORDER */ 193 } asm330lhhxg1_func_cfg_access_t; 194 195 #define ASM330LHHXG1_PIN_CTRL 0x02U 196 typedef struct 197 { 198 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 199 uint8_t not_used_01 : 6; 200 uint8_t sdo_pu_en : 1; 201 uint8_t not_used_02 : 1; 202 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 203 uint8_t not_used_02 : 1; 204 uint8_t sdo_pu_en : 1; 205 uint8_t not_used_01 : 6; 206 #endif /* DRV_BYTE_ORDER */ 207 } asm330lhhxg1_pin_ctrl_t; 208 209 #define ASM330LHHXG1_FIFO_CTRL1 0x07U 210 typedef struct 211 { 212 uint8_t wtm : 8; 213 } asm330lhhxg1_fifo_ctrl1_t; 214 215 #define ASM330LHHXG1_FIFO_CTRL2 0x08U 216 typedef struct 217 { 218 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 219 uint8_t wtm : 1; 220 uint8_t not_used_01 : 3; 221 uint8_t odrchg_en : 1; 222 uint8_t not_used_02 : 2; 223 uint8_t stop_on_wtm : 1; 224 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 225 uint8_t stop_on_wtm : 1; 226 uint8_t not_used_02 : 2; 227 uint8_t odrchg_en : 1; 228 uint8_t not_used_01 : 3; 229 uint8_t wtm : 1; 230 #endif /* DRV_BYTE_ORDER */ 231 } asm330lhhxg1_fifo_ctrl2_t; 232 233 #define ASM330LHHXG1_FIFO_CTRL3 0x09U 234 typedef struct 235 { 236 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 237 uint8_t bdr_xl : 4; 238 uint8_t bdr_gy : 4; 239 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 240 uint8_t bdr_gy : 4; 241 uint8_t bdr_xl : 4; 242 #endif /* DRV_BYTE_ORDER */ 243 } asm330lhhxg1_fifo_ctrl3_t; 244 245 #define ASM330LHHXG1_FIFO_CTRL4 0x0AU 246 typedef struct 247 { 248 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 249 uint8_t fifo_mode : 3; 250 uint8_t not_used_01 : 1; 251 uint8_t odr_t_batch : 2; 252 uint8_t dec_ts_batch : 2; 253 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 254 uint8_t dec_ts_batch : 2; 255 uint8_t odr_t_batch : 2; 256 uint8_t not_used_01 : 1; 257 uint8_t fifo_mode : 3; 258 #endif /* DRV_BYTE_ORDER */ 259 } asm330lhhxg1_fifo_ctrl4_t; 260 261 #define ASM330LHHXG1_COUNTER_BDR_REG1 0x0BU 262 typedef struct 263 { 264 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 265 uint8_t cnt_bdr_th : 3; 266 uint8_t not_used_01 : 2; 267 uint8_t trig_counter_bdr : 1; 268 uint8_t rst_counter_bdr : 1; 269 uint8_t dataready_pulsed : 1; 270 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 271 uint8_t dataready_pulsed : 1; 272 uint8_t rst_counter_bdr : 1; 273 uint8_t trig_counter_bdr : 1; 274 uint8_t not_used_01 : 2; 275 uint8_t cnt_bdr_th : 3; 276 #endif /* DRV_BYTE_ORDER */ 277 } asm330lhhxg1_counter_bdr_reg1_t; 278 279 #define ASM330LHHXG1_COUNTER_BDR_REG2 0x0CU 280 typedef struct 281 { 282 uint8_t cnt_bdr_th : 8; 283 } asm330lhhxg1_counter_bdr_reg2_t; 284 285 #define ASM330LHHXG1_INT1_CTRL 0x0DU 286 typedef struct 287 { 288 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 289 uint8_t int1_drdy_xl : 1; 290 uint8_t int1_drdy_g : 1; 291 uint8_t int1_boot : 1; 292 uint8_t int1_fifo_th : 1; 293 uint8_t int1_fifo_ovr : 1; 294 uint8_t int1_fifo_full : 1; 295 uint8_t int1_cnt_bdr : 1; 296 uint8_t den_drdy_flag : 1; 297 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 298 uint8_t den_drdy_flag : 1; 299 uint8_t int1_cnt_bdr : 1; 300 uint8_t int1_fifo_full : 1; 301 uint8_t int1_fifo_ovr : 1; 302 uint8_t int1_fifo_th : 1; 303 uint8_t int1_boot : 1; 304 uint8_t int1_drdy_g : 1; 305 uint8_t int1_drdy_xl : 1; 306 #endif /* DRV_BYTE_ORDER */ 307 } asm330lhhxg1_int1_ctrl_t; 308 309 #define ASM330LHHXG1_INT2_CTRL 0x0EU 310 typedef struct 311 { 312 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 313 uint8_t int2_drdy_xl : 1; 314 uint8_t int2_drdy_g : 1; 315 uint8_t int2_drdy_temp : 1; 316 uint8_t int2_fifo_th : 1; 317 uint8_t int2_fifo_ovr : 1; 318 uint8_t int2_fifo_full : 1; 319 uint8_t int2_cnt_bdr : 1; 320 uint8_t not_used_01 : 1; 321 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 322 uint8_t not_used_01 : 1; 323 uint8_t int2_cnt_bdr : 1; 324 uint8_t int2_fifo_full : 1; 325 uint8_t int2_fifo_ovr : 1; 326 uint8_t int2_fifo_th : 1; 327 uint8_t int2_drdy_temp : 1; 328 uint8_t int2_drdy_g : 1; 329 uint8_t int2_drdy_xl : 1; 330 #endif /* DRV_BYTE_ORDER */ 331 } asm330lhhxg1_int2_ctrl_t; 332 333 #define ASM330LHHXG1_WHO_AM_I 0x0FU 334 335 #define ASM330LHHXG1_CTRL1_XL 0x10U 336 typedef struct 337 { 338 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 339 uint8_t not_used_01 : 1; 340 uint8_t lpf2_xl_en : 1; 341 uint8_t fs_xl : 2; 342 uint8_t odr_xl : 4; 343 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 344 uint8_t odr_xl : 4; 345 uint8_t fs_xl : 2; 346 uint8_t lpf2_xl_en : 1; 347 uint8_t not_used_01 : 1; 348 #endif /* DRV_BYTE_ORDER */ 349 } asm330lhhxg1_ctrl1_xl_t; 350 351 #define ASM330LHHXG1_CTRL2_G 0x11U 352 typedef struct 353 { 354 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 355 uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */ 356 uint8_t odr_g : 4; 357 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 358 uint8_t odr_g : 4; 359 uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */ 360 #endif /* DRV_BYTE_ORDER */ 361 } asm330lhhxg1_ctrl2_g_t; 362 363 #define ASM330LHHXG1_CTRL3_C 0x12U 364 typedef struct 365 { 366 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 367 uint8_t sw_reset : 1; 368 uint8_t not_used_01 : 1; 369 uint8_t if_inc : 1; 370 uint8_t sim : 1; 371 uint8_t pp_od : 1; 372 uint8_t h_lactive : 1; 373 uint8_t bdu : 1; 374 uint8_t boot : 1; 375 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 376 uint8_t boot : 1; 377 uint8_t bdu : 1; 378 uint8_t h_lactive : 1; 379 uint8_t pp_od : 1; 380 uint8_t sim : 1; 381 uint8_t if_inc : 1; 382 uint8_t not_used_01 : 1; 383 uint8_t sw_reset : 1; 384 #endif /* DRV_BYTE_ORDER */ 385 } asm330lhhxg1_ctrl3_c_t; 386 387 #define ASM330LHHXG1_CTRL4_C 0x13U 388 typedef struct 389 { 390 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 391 uint8_t not_used_01 : 1; 392 uint8_t lpf1_sel_g : 1; 393 uint8_t i2c_disable : 1; 394 uint8_t drdy_mask : 1; 395 uint8_t not_used_02 : 1; 396 uint8_t int2_on_int1 : 1; 397 uint8_t sleep_g : 1; 398 uint8_t not_used_03 : 1; 399 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 400 uint8_t not_used_03 : 1; 401 uint8_t sleep_g : 1; 402 uint8_t int2_on_int1 : 1; 403 uint8_t not_used_02 : 1; 404 uint8_t drdy_mask : 1; 405 uint8_t i2c_disable : 1; 406 uint8_t lpf1_sel_g : 1; 407 uint8_t not_used_01 : 1; 408 #endif /* DRV_BYTE_ORDER */ 409 } asm330lhhxg1_ctrl4_c_t; 410 411 #define ASM330LHHXG1_CTRL5_C 0x14U 412 typedef struct 413 { 414 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 415 uint8_t st_xl : 2; 416 uint8_t st_g : 2; 417 uint8_t not_used_01 : 1; 418 uint8_t rounding : 2; 419 uint8_t not_used_02 : 1; 420 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 421 uint8_t not_used_02 : 1; 422 uint8_t rounding : 2; 423 uint8_t not_used_01 : 1; 424 uint8_t st_g : 2; 425 uint8_t st_xl : 2; 426 #endif /* DRV_BYTE_ORDER */ 427 } asm330lhhxg1_ctrl5_c_t; 428 429 #define ASM330LHHXG1_CTRL6_C 0x15U 430 typedef struct 431 { 432 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 433 uint8_t ftype : 3; 434 uint8_t usr_off_w : 1; 435 uint8_t xl_hm_mode : 1; 436 uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ 437 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 438 uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ 439 uint8_t xl_hm_mode : 1; 440 uint8_t usr_off_w : 1; 441 uint8_t ftype : 3; 442 #endif /* DRV_BYTE_ORDER */ 443 } asm330lhhxg1_ctrl6_c_t; 444 445 #define ASM330LHHXG1_CTRL7_G 0x16U 446 typedef struct 447 { 448 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 449 uint8_t not_used_00 : 1; 450 uint8_t usr_off_on_out : 1; 451 uint8_t not_used_01 : 2; 452 uint8_t hpm_g : 2; 453 uint8_t hp_en_g : 1; 454 uint8_t g_hm_mode : 1; 455 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 456 uint8_t g_hm_mode : 1; 457 uint8_t hp_en_g : 1; 458 uint8_t hpm_g : 2; 459 uint8_t not_used_01 : 2; 460 uint8_t usr_off_on_out : 1; 461 uint8_t not_used_00 : 1; 462 #endif /* DRV_BYTE_ORDER */ 463 } asm330lhhxg1_ctrl7_g_t; 464 465 #define ASM330LHHXG1_CTRL8_XL 0x17U 466 typedef struct 467 { 468 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 469 uint8_t low_pass_on_6d : 1; 470 uint8_t not_used_01 : 1; 471 uint8_t hp_slope_xl_en : 1; 472 uint8_t fastsettl_mode_xl : 1; 473 uint8_t hp_ref_mode_xl : 1; 474 uint8_t hpcf_xl : 3; 475 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 476 uint8_t hpcf_xl : 3; 477 uint8_t hp_ref_mode_xl : 1; 478 uint8_t fastsettl_mode_xl : 1; 479 uint8_t hp_slope_xl_en : 1; 480 uint8_t not_used_01 : 1; 481 uint8_t low_pass_on_6d : 1; 482 #endif /* DRV_BYTE_ORDER */ 483 } asm330lhhxg1_ctrl8_xl_t; 484 485 #define ASM330LHHXG1_CTRL9_XL 0x18U 486 typedef struct 487 { 488 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 489 uint8_t not_used_01 : 1; 490 uint8_t i3c_disable : 1; 491 uint8_t den_lh : 1; 492 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 493 uint8_t den_z : 1; 494 uint8_t den_y : 1; 495 uint8_t den_x : 1; 496 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 497 uint8_t den_x : 1; 498 uint8_t den_y : 1; 499 uint8_t den_z : 1; 500 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 501 uint8_t den_lh : 1; 502 uint8_t i3c_disable : 1; 503 uint8_t not_used_01 : 1; 504 #endif /* DRV_BYTE_ORDER */ 505 } asm330lhhxg1_ctrl9_xl_t; 506 507 #define ASM330LHHXG1_CTRL10_C 0x19U 508 typedef struct 509 { 510 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 511 uint8_t not_used_01 : 5; 512 uint8_t timestamp_en : 1; 513 uint8_t not_used_02 : 2; 514 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 515 uint8_t not_used_02 : 2; 516 uint8_t timestamp_en : 1; 517 uint8_t not_used_01 : 5; 518 #endif /* DRV_BYTE_ORDER */ 519 } asm330lhhxg1_ctrl10_c_t; 520 521 #define ASM330LHHXG1_ALL_INT_SRC 0x1AU 522 typedef struct 523 { 524 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 525 uint8_t ff_ia : 1; 526 uint8_t wu_ia : 1; 527 uint8_t not_used_00 : 2; 528 uint8_t d6d_ia : 1; 529 uint8_t sleep_change_ia : 1; 530 uint8_t not_used_01 : 1; 531 uint8_t timestamp_endcount : 1; 532 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 533 uint8_t timestamp_endcount : 1; 534 uint8_t not_used_01 : 1; 535 uint8_t sleep_change_ia : 1; 536 uint8_t d6d_ia : 1; 537 uint8_t not_used_00 : 2; 538 uint8_t wu_ia : 1; 539 uint8_t ff_ia : 1; 540 #endif /* DRV_BYTE_ORDER */ 541 } asm330lhhxg1_all_int_src_t; 542 543 #define ASM330LHHXG1_WAKE_UP_SRC 0x1BU 544 typedef struct 545 { 546 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 547 uint8_t z_wu : 1; 548 uint8_t y_wu : 1; 549 uint8_t x_wu : 1; 550 uint8_t wu_ia : 1; 551 uint8_t sleep_state : 1; 552 uint8_t ff_ia : 1; 553 uint8_t sleep_change_ia : 1; 554 uint8_t not_used_01 : 1; 555 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 556 uint8_t not_used_01 : 1; 557 uint8_t sleep_change_ia : 1; 558 uint8_t ff_ia : 1; 559 uint8_t sleep_state : 1; 560 uint8_t wu_ia : 1; 561 uint8_t x_wu : 1; 562 uint8_t y_wu : 1; 563 uint8_t z_wu : 1; 564 #endif /* DRV_BYTE_ORDER */ 565 } asm330lhhxg1_wake_up_src_t; 566 567 #define ASM330LHHXG1_D6D_SRC 0x1DU 568 typedef struct 569 { 570 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 571 uint8_t xl : 1; 572 uint8_t xh : 1; 573 uint8_t yl : 1; 574 uint8_t yh : 1; 575 uint8_t zl : 1; 576 uint8_t zh : 1; 577 uint8_t d6d_ia : 1; 578 uint8_t den_drdy : 1; 579 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 580 uint8_t den_drdy : 1; 581 uint8_t d6d_ia : 1; 582 uint8_t zh : 1; 583 uint8_t zl : 1; 584 uint8_t yh : 1; 585 uint8_t yl : 1; 586 uint8_t xh : 1; 587 uint8_t xl : 1; 588 #endif /* DRV_BYTE_ORDER */ 589 } asm330lhhxg1_d6d_src_t; 590 591 #define ASM330LHHXG1_STATUS_REG 0x1EU 592 typedef struct 593 { 594 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 595 uint8_t xlda : 1; 596 uint8_t gda : 1; 597 uint8_t tda : 1; 598 uint8_t not_used_01 : 5; 599 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 600 uint8_t not_used_01 : 5; 601 uint8_t tda : 1; 602 uint8_t gda : 1; 603 uint8_t xlda : 1; 604 #endif /* DRV_BYTE_ORDER */ 605 } asm330lhhxg1_status_reg_t; 606 607 #define ASM330LHHXG1_OUT_TEMP_L 0x20U 608 #define ASM330LHHXG1_OUT_TEMP_H 0x21U 609 #define ASM330LHHXG1_OUTX_L_G 0x22U 610 #define ASM330LHHXG1_OUTX_H_G 0x23U 611 #define ASM330LHHXG1_OUTY_L_G 0x24U 612 #define ASM330LHHXG1_OUTY_H_G 0x25U 613 #define ASM330LHHXG1_OUTZ_L_G 0x26U 614 #define ASM330LHHXG1_OUTZ_H_G 0x27U 615 #define ASM330LHHXG1_OUTX_L_A 0x28U 616 #define ASM330LHHXG1_OUTX_H_A 0x29U 617 #define ASM330LHHXG1_OUTY_L_A 0x2AU 618 #define ASM330LHHXG1_OUTY_H_A 0x2BU 619 #define ASM330LHHXG1_OUTZ_L_A 0x2CU 620 #define ASM330LHHXG1_OUTZ_H_A 0x2DU 621 #define ASM330LHHXG1_EMB_FUNC_STATUS_MAINPAGE 0x35U 622 typedef struct 623 { 624 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 625 uint8_t not_used_01 : 7; 626 uint8_t is_fsm_lc : 1; 627 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 628 uint8_t is_fsm_lc : 1; 629 uint8_t not_used_01 : 7; 630 #endif /* DRV_BYTE_ORDER */ 631 } asm330lhhxg1_emb_func_status_mainpage_t; 632 633 #define ASM330LHHXG1_FSM_STATUS_A_MAINPAGE 0x36U 634 typedef struct 635 { 636 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 637 uint8_t is_fsm1 : 1; 638 uint8_t is_fsm2 : 1; 639 uint8_t is_fsm3 : 1; 640 uint8_t is_fsm4 : 1; 641 uint8_t is_fsm5 : 1; 642 uint8_t is_fsm6 : 1; 643 uint8_t is_fsm7 : 1; 644 uint8_t is_fsm8 : 1; 645 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 646 uint8_t is_fsm8 : 1; 647 uint8_t is_fsm7 : 1; 648 uint8_t is_fsm6 : 1; 649 uint8_t is_fsm5 : 1; 650 uint8_t is_fsm4 : 1; 651 uint8_t is_fsm3 : 1; 652 uint8_t is_fsm2 : 1; 653 uint8_t is_fsm1 : 1; 654 #endif /* DRV_BYTE_ORDER */ 655 } asm330lhhxg1_fsm_status_a_mainpage_t; 656 657 #define ASM330LHHXG1_FSM_STATUS_B_MAINPAGE 0x37U 658 typedef struct 659 { 660 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 661 uint8_t is_fsm9 : 1; 662 uint8_t is_fsm10 : 1; 663 uint8_t is_fsm11 : 1; 664 uint8_t is_fsm12 : 1; 665 uint8_t is_fsm13 : 1; 666 uint8_t is_fsm14 : 1; 667 uint8_t is_fsm15 : 1; 668 uint8_t is_fsm16 : 1; 669 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 670 uint8_t is_fsm16 : 1; 671 uint8_t is_fsm15 : 1; 672 uint8_t is_fsm14 : 1; 673 uint8_t is_fsm13 : 1; 674 uint8_t is_fsm12 : 1; 675 uint8_t is_fsm11 : 1; 676 uint8_t is_fsm10 : 1; 677 uint8_t is_fsm9 : 1; 678 #endif /* DRV_BYTE_ORDER */ 679 } asm330lhhxg1_fsm_status_b_mainpage_t; 680 681 #define ASM330LHHXG1_MLC_STATUS_MAINPAGE 0x38U 682 typedef struct 683 { 684 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 685 uint8_t is_mlc1 : 1; 686 uint8_t is_mlc2 : 1; 687 uint8_t is_mlc3 : 1; 688 uint8_t is_mlc4 : 1; 689 uint8_t is_mlc5 : 1; 690 uint8_t is_mlc6 : 1; 691 uint8_t is_mlc7 : 1; 692 uint8_t is_mlc8 : 1; 693 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 694 uint8_t is_mlc8 : 1; 695 uint8_t is_mlc7 : 1; 696 uint8_t is_mlc6 : 1; 697 uint8_t is_mlc5 : 1; 698 uint8_t is_mlc4 : 1; 699 uint8_t is_mlc3 : 1; 700 uint8_t is_mlc2 : 1; 701 uint8_t is_mlc1 : 1; 702 #endif /* DRV_BYTE_ORDER */ 703 } asm330lhhxg1_mlc_status_mainpage_t; 704 705 #define ASM330LHHXG1_STATUS_MASTER_MAINPAGE 0x39U 706 typedef struct 707 { 708 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 709 uint8_t sens_hub_endop : 1; 710 uint8_t not_used_01 : 2; 711 uint8_t slave0_nack : 1; 712 uint8_t slave1_nack : 1; 713 uint8_t slave2_nack : 1; 714 uint8_t slave3_nack : 1; 715 uint8_t wr_once_done : 1; 716 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 717 uint8_t wr_once_done : 1; 718 uint8_t slave3_nack : 1; 719 uint8_t slave2_nack : 1; 720 uint8_t slave1_nack : 1; 721 uint8_t slave0_nack : 1; 722 uint8_t not_used_01 : 2; 723 uint8_t sens_hub_endop : 1; 724 #endif /* DRV_BYTE_ORDER */ 725 } asm330lhhxg1_status_master_mainpage_t; 726 727 #define ASM330LHHXG1_FIFO_STATUS1 0x3AU 728 typedef struct 729 { 730 uint8_t diff_fifo : 8; 731 } asm330lhhxg1_fifo_status1_t; 732 733 #define ASM330LHHXG1_FIFO_STATUS2 0x3BU 734 typedef struct 735 { 736 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 737 uint8_t diff_fifo : 2; 738 uint8_t not_used_01 : 1; 739 uint8_t over_run_latched : 1; 740 uint8_t counter_bdr_ia : 1; 741 uint8_t fifo_full_ia : 1; 742 uint8_t fifo_ovr_ia : 1; 743 uint8_t fifo_wtm_ia : 1; 744 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 745 uint8_t fifo_wtm_ia : 1; 746 uint8_t fifo_ovr_ia : 1; 747 uint8_t fifo_full_ia : 1; 748 uint8_t counter_bdr_ia : 1; 749 uint8_t over_run_latched : 1; 750 uint8_t not_used_01 : 1; 751 uint8_t diff_fifo : 2; 752 #endif /* DRV_BYTE_ORDER */ 753 } asm330lhhxg1_fifo_status2_t; 754 755 #define ASM330LHHXG1_TIMESTAMP0 0x40U 756 #define ASM330LHHXG1_TIMESTAMP1 0x41U 757 #define ASM330LHHXG1_TIMESTAMP2 0x42U 758 #define ASM330LHHXG1_TIMESTAMP3 0x43U 759 #define ASM330LHHXG1_INT_CFG0 0x56U 760 typedef struct 761 { 762 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 763 uint8_t lir : 1; 764 uint8_t not_used_01 : 3; 765 uint8_t slope_fds : 1; 766 uint8_t sleep_status_on_int : 1; 767 uint8_t int_clr_on_read : 1; 768 uint8_t not_used_02 : 1; 769 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 770 uint8_t not_used_02 : 1; 771 uint8_t int_clr_on_read : 1; 772 uint8_t sleep_status_on_int : 1; 773 uint8_t slope_fds : 1; 774 uint8_t not_used_01 : 3; 775 uint8_t lir : 1; 776 #endif /* DRV_BYTE_ORDER */ 777 } asm330lhhxg1_int_cfg0_t; 778 779 #define ASM330LHHXG1_INT_CFG1 0x58U 780 typedef struct 781 { 782 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 783 uint8_t not_used_01 : 5; 784 uint8_t inact_en : 2; 785 uint8_t interrupts_enable : 1; 786 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 787 uint8_t interrupts_enable : 1; 788 uint8_t inact_en : 2; 789 uint8_t not_used_01 : 5; 790 #endif /* DRV_BYTE_ORDER */ 791 } asm330lhhxg1_int_cfg1_t; 792 793 #define ASM330LHHXG1_THS_6D 0x59U 794 typedef struct 795 { 796 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 797 uint8_t not_used_01 : 5; 798 uint8_t sixd_ths : 2; 799 uint8_t d4d_en : 1; 800 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 801 uint8_t d4d_en : 1; 802 uint8_t sixd_ths : 2; 803 uint8_t not_used_01 : 5; 804 #endif /* DRV_BYTE_ORDER */ 805 } asm330lhhxg1_ths_6d_t; 806 807 #define ASM330LHHXG1_WAKE_UP_THS 0x5BU 808 typedef struct 809 { 810 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 811 uint8_t wk_ths : 6; 812 uint8_t usr_off_on_wu : 1; 813 uint8_t not_used_01 : 1; 814 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 815 uint8_t not_used_01 : 1; 816 uint8_t usr_off_on_wu : 1; 817 uint8_t wk_ths : 6; 818 #endif /* DRV_BYTE_ORDER */ 819 } asm330lhhxg1_wake_up_ths_t; 820 821 #define ASM330LHHXG1_WAKE_UP_DUR 0x5CU 822 typedef struct 823 { 824 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 825 uint8_t sleep_dur : 4; 826 uint8_t wake_ths_w : 1; 827 uint8_t wake_dur : 2; 828 uint8_t ff_dur : 1; 829 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 830 uint8_t ff_dur : 1; 831 uint8_t wake_dur : 2; 832 uint8_t wake_ths_w : 1; 833 uint8_t sleep_dur : 4; 834 #endif /* DRV_BYTE_ORDER */ 835 } asm330lhhxg1_wake_up_dur_t; 836 837 #define ASM330LHHXG1_FREE_FALL 0x5DU 838 typedef struct 839 { 840 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 841 uint8_t ff_ths : 3; 842 uint8_t ff_dur : 5; 843 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 844 uint8_t ff_dur : 5; 845 uint8_t ff_ths : 3; 846 #endif /* DRV_BYTE_ORDER */ 847 } asm330lhhxg1_free_fall_t; 848 849 #define ASM330LHHXG1_MD1_CFG 0x5EU 850 typedef struct 851 { 852 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 853 uint8_t int1_shub : 1; 854 uint8_t int1_emb_func : 1; 855 uint8_t int1_6d : 1; 856 uint8_t not_used_01 : 1; 857 uint8_t int1_ff : 1; 858 uint8_t int1_wu : 1; 859 uint8_t not_used_02 : 1; 860 uint8_t int1_sleep_change : 1; 861 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 862 uint8_t int1_sleep_change : 1; 863 uint8_t not_used_02 : 1; 864 uint8_t int1_wu : 1; 865 uint8_t int1_ff : 1; 866 uint8_t not_used_01 : 1; 867 uint8_t int1_6d : 1; 868 uint8_t int1_emb_func : 1; 869 uint8_t int1_shub : 1; 870 #endif /* DRV_BYTE_ORDER */ 871 } asm330lhhxg1_md1_cfg_t; 872 873 #define ASM330LHHXG1_MD2_CFG 0x5FU 874 typedef struct 875 { 876 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 877 uint8_t int2_timestamp : 1; 878 uint8_t int2_emb_func : 1; 879 uint8_t int2_6d : 1; 880 uint8_t not_used_01 : 1; 881 uint8_t int2_ff : 1; 882 uint8_t int2_wu : 1; 883 uint8_t not_used_02 : 1; 884 uint8_t int2_sleep_change : 1; 885 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 886 uint8_t int2_sleep_change : 1; 887 uint8_t not_used_02 : 1; 888 uint8_t int2_wu : 1; 889 uint8_t int2_ff : 1; 890 uint8_t not_used_01 : 1; 891 uint8_t int2_6d : 1; 892 uint8_t int2_emb_func : 1; 893 uint8_t int2_timestamp : 1; 894 #endif /* DRV_BYTE_ORDER */ 895 } asm330lhhxg1_md2_cfg_t; 896 897 #define ASM330LHHXG1_I3C_BUS_AVB 0x62U 898 typedef struct 899 { 900 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 901 uint8_t pd_dis_int1 : 1; 902 uint8_t not_used_01 : 2; 903 uint8_t i3c_bus_avb_sel : 2; 904 uint8_t not_used_02 : 3; 905 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 906 uint8_t not_used_02 : 3; 907 uint8_t i3c_bus_avb_sel : 2; 908 uint8_t not_used_01 : 2; 909 uint8_t pd_dis_int1 : 1; 910 #endif /* DRV_BYTE_ORDER */ 911 } asm330lhhxg1_i3c_bus_avb_t; 912 913 #define ASM330LHHXG1_INTERNAL_FREQ_FINE 0x63U 914 typedef struct 915 { 916 uint8_t freq_fine : 8; 917 } asm330lhhxg1_internal_freq_fine_t; 918 919 #define ASM330LHHXG1_X_OFS_USR 0x73U 920 #define ASM330LHHXG1_Y_OFS_USR 0x74U 921 #define ASM330LHHXG1_Z_OFS_USR 0x75U 922 #define ASM330LHHXG1_FIFO_DATA_OUT_TAG 0x78U 923 typedef struct 924 { 925 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 926 uint8_t tag_parity : 1; 927 uint8_t tag_cnt : 2; 928 uint8_t tag_sensor : 5; 929 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 930 uint8_t tag_sensor : 5; 931 uint8_t tag_cnt : 2; 932 uint8_t tag_parity : 1; 933 #endif /* DRV_BYTE_ORDER */ 934 } asm330lhhxg1_fifo_data_out_tag_t; 935 936 #define ASM330LHHXG1_FIFO_DATA_OUT_X_L 0x79U 937 #define ASM330LHHXG1_FIFO_DATA_OUT_X_H 0x7AU 938 #define ASM330LHHXG1_FIFO_DATA_OUT_Y_L 0x7BU 939 #define ASM330LHHXG1_FIFO_DATA_OUT_Y_H 0x7CU 940 #define ASM330LHHXG1_FIFO_DATA_OUT_Z_L 0x7DU 941 #define ASM330LHHXG1_FIFO_DATA_OUT_Z_H 0x7EU 942 943 #define ASM330LHHXG1_PAGE_SEL 0x02U 944 typedef struct 945 { 946 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 947 uint8_t not_used_01 : 1; 948 uint8_t emb_func_clk_dis : 1; 949 uint8_t not_used_02 : 2; 950 uint8_t page_sel : 4; 951 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 952 uint8_t page_sel : 4; 953 uint8_t not_used_02 : 2; 954 uint8_t emb_func_clk_dis : 1; 955 uint8_t not_used_01 : 1; 956 #endif /* DRV_BYTE_ORDER */ 957 } asm330lhhxg1_page_sel_t; 958 959 #define ASM330LHHXG1_EMB_FUNC_EN_B 0x05U 960 typedef struct 961 { 962 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 963 uint8_t fsm_en : 1; 964 uint8_t not_used_01 : 3; 965 uint8_t mlc_en : 1; 966 uint8_t not_used_02 : 3; 967 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 968 uint8_t not_used_02 : 3; 969 uint8_t mlc_en : 1; 970 uint8_t not_used_01 : 3; 971 uint8_t fsm_en : 1; 972 #endif /* DRV_BYTE_ORDER */ 973 } asm330lhhxg1_emb_func_en_b_t; 974 975 #define ASM330LHHXG1_PAGE_ADDRESS 0x08U 976 typedef struct 977 { 978 uint8_t page_addr : 8; 979 } asm330lhhxg1_page_address_t; 980 981 #define ASM330LHHXG1_PAGE_VALUE 0x09U 982 typedef struct 983 { 984 uint8_t page_value : 8; 985 } asm330lhhxg1_page_value_t; 986 987 #define ASM330LHHXG1_EMB_FUNC_INT1 0x0AU 988 typedef struct 989 { 990 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 991 uint8_t not_used_01 : 7; 992 uint8_t int1_fsm_lc : 1; 993 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 994 uint8_t int1_fsm_lc : 1; 995 uint8_t not_used_01 : 7; 996 #endif /* DRV_BYTE_ORDER */ 997 } asm330lhhxg1_emb_func_int1_t; 998 999 #define ASM330LHHXG1_FSM_INT1_A 0x0BU 1000 typedef struct 1001 { 1002 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1003 uint8_t int1_fsm1 : 1; 1004 uint8_t int1_fsm2 : 1; 1005 uint8_t int1_fsm3 : 1; 1006 uint8_t int1_fsm4 : 1; 1007 uint8_t int1_fsm5 : 1; 1008 uint8_t int1_fsm6 : 1; 1009 uint8_t int1_fsm7 : 1; 1010 uint8_t int1_fsm8 : 1; 1011 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1012 uint8_t int1_fsm8 : 1; 1013 uint8_t int1_fsm7 : 1; 1014 uint8_t int1_fsm6 : 1; 1015 uint8_t int1_fsm5 : 1; 1016 uint8_t int1_fsm4 : 1; 1017 uint8_t int1_fsm3 : 1; 1018 uint8_t int1_fsm2 : 1; 1019 uint8_t int1_fsm1 : 1; 1020 #endif /* DRV_BYTE_ORDER */ 1021 } asm330lhhxg1_fsm_int1_a_t; 1022 1023 #define ASM330LHHXG1_FSM_INT1_B 0x0CU 1024 typedef struct 1025 { 1026 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1027 uint8_t int1_fsm9 : 1; 1028 uint8_t int1_fsm10 : 1; 1029 uint8_t int1_fsm11 : 1; 1030 uint8_t int1_fsm12 : 1; 1031 uint8_t int1_fsm13 : 1; 1032 uint8_t int1_fsm14 : 1; 1033 uint8_t int1_fsm15 : 1; 1034 uint8_t int1_fsm16 : 1; 1035 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1036 uint8_t int1_fsm16 : 1; 1037 uint8_t int1_fsm15 : 1; 1038 uint8_t int1_fsm14 : 1; 1039 uint8_t int1_fsm13 : 1; 1040 uint8_t int1_fsm12 : 1; 1041 uint8_t int1_fsm11 : 1; 1042 uint8_t int1_fsm10 : 1; 1043 uint8_t int1_fsm9 : 1; 1044 #endif /* DRV_BYTE_ORDER */ 1045 } asm330lhhxg1_fsm_int1_b_t; 1046 1047 #define ASM330LHHXG1_MLC_INT1 0x0DU 1048 typedef struct 1049 { 1050 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1051 uint8_t int1_mlc1 : 1; 1052 uint8_t int1_mlc2 : 1; 1053 uint8_t int1_mlc3 : 1; 1054 uint8_t int1_mlc4 : 1; 1055 uint8_t int1_mlc5 : 1; 1056 uint8_t int1_mlc6 : 1; 1057 uint8_t int1_mlc7 : 1; 1058 uint8_t int1_mlc8 : 1; 1059 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1060 uint8_t int1_mlc8 : 1; 1061 uint8_t int1_mlc7 : 1; 1062 uint8_t int1_mlc6 : 1; 1063 uint8_t int1_mlc5 : 1; 1064 uint8_t int1_mlc4 : 1; 1065 uint8_t int1_mlc3 : 1; 1066 uint8_t int1_mlc2 : 1; 1067 uint8_t int1_mlc1 : 1; 1068 #endif /* DRV_BYTE_ORDER */ 1069 } asm330lhhxg1_mlc_int1_t; 1070 1071 #define ASM330LHHXG1_EMB_FUNC_INT2 0x0EU 1072 typedef struct 1073 { 1074 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1075 uint8_t not_used_01 : 7; 1076 uint8_t int2_fsm_lc : 1; 1077 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1078 uint8_t int2_fsm_lc : 1; 1079 uint8_t not_used_01 : 7; 1080 #endif /* DRV_BYTE_ORDER */ 1081 } asm330lhhxg1_emb_func_int2_t; 1082 1083 #define ASM330LHHXG1_FSM_INT2_A 0x0FU 1084 typedef struct 1085 { 1086 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1087 uint8_t int2_fsm1 : 1; 1088 uint8_t int2_fsm2 : 1; 1089 uint8_t int2_fsm3 : 1; 1090 uint8_t int2_fsm4 : 1; 1091 uint8_t int2_fsm5 : 1; 1092 uint8_t int2_fsm6 : 1; 1093 uint8_t int2_fsm7 : 1; 1094 uint8_t int2_fsm8 : 1; 1095 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1096 uint8_t int2_fsm8 : 1; 1097 uint8_t int2_fsm7 : 1; 1098 uint8_t int2_fsm6 : 1; 1099 uint8_t int2_fsm5 : 1; 1100 uint8_t int2_fsm4 : 1; 1101 uint8_t int2_fsm3 : 1; 1102 uint8_t int2_fsm2 : 1; 1103 uint8_t int2_fsm1 : 1; 1104 #endif /* DRV_BYTE_ORDER */ 1105 } asm330lhhxg1_fsm_int2_a_t; 1106 1107 #define ASM330LHHXG1_FSM_INT2_B 0x10U 1108 typedef struct 1109 { 1110 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1111 uint8_t int2_fsm9 : 1; 1112 uint8_t int2_fsm10 : 1; 1113 uint8_t int2_fsm11 : 1; 1114 uint8_t int2_fsm12 : 1; 1115 uint8_t int2_fsm13 : 1; 1116 uint8_t int2_fsm14 : 1; 1117 uint8_t int2_fsm15 : 1; 1118 uint8_t int2_fsm16 : 1; 1119 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1120 uint8_t int2_fsm16 : 1; 1121 uint8_t int2_fsm15 : 1; 1122 uint8_t int2_fsm14 : 1; 1123 uint8_t int2_fsm13 : 1; 1124 uint8_t int2_fsm12 : 1; 1125 uint8_t int2_fsm11 : 1; 1126 uint8_t int2_fsm10 : 1; 1127 uint8_t int2_fsm9 : 1; 1128 #endif /* DRV_BYTE_ORDER */ 1129 } asm330lhhxg1_fsm_int2_b_t; 1130 1131 #define ASM330LHHXG1_MLC_INT2 0x11U 1132 typedef struct 1133 { 1134 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1135 uint8_t int2_mlc1 : 1; 1136 uint8_t int2_mlc2 : 1; 1137 uint8_t int2_mlc3 : 1; 1138 uint8_t int2_mlc4 : 1; 1139 uint8_t int2_mlc5 : 1; 1140 uint8_t int2_mlc6 : 1; 1141 uint8_t int2_mlc7 : 1; 1142 uint8_t int2_mlc8 : 1; 1143 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1144 uint8_t int2_mlc8 : 1; 1145 uint8_t int2_mlc7 : 1; 1146 uint8_t int2_mlc6 : 1; 1147 uint8_t int2_mlc5 : 1; 1148 uint8_t int2_mlc4 : 1; 1149 uint8_t int2_mlc3 : 1; 1150 uint8_t int2_mlc2 : 1; 1151 uint8_t int2_mlc1 : 1; 1152 #endif /* DRV_BYTE_ORDER */ 1153 } asm330lhhxg1_mlc_int2_t; 1154 1155 #define ASM330LHHXG1_EMB_FUNC_STATUS 0x12U 1156 typedef struct 1157 { 1158 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1159 uint8_t not_used_01 : 7; 1160 uint8_t is_fsm_lc : 1; 1161 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1162 uint8_t is_fsm_lc : 1; 1163 uint8_t not_used_01 : 7; 1164 #endif /* DRV_BYTE_ORDER */ 1165 } asm330lhhxg1_emb_func_status_t; 1166 1167 #define ASM330LHHXG1_FSM_STATUS_A 0x13U 1168 typedef struct 1169 { 1170 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1171 uint8_t is_fsm1 : 1; 1172 uint8_t is_fsm2 : 1; 1173 uint8_t is_fsm3 : 1; 1174 uint8_t is_fsm4 : 1; 1175 uint8_t is_fsm5 : 1; 1176 uint8_t is_fsm6 : 1; 1177 uint8_t is_fsm7 : 1; 1178 uint8_t is_fsm8 : 1; 1179 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1180 uint8_t is_fsm8 : 1; 1181 uint8_t is_fsm7 : 1; 1182 uint8_t is_fsm6 : 1; 1183 uint8_t is_fsm5 : 1; 1184 uint8_t is_fsm4 : 1; 1185 uint8_t is_fsm3 : 1; 1186 uint8_t is_fsm2 : 1; 1187 uint8_t is_fsm1 : 1; 1188 #endif /* DRV_BYTE_ORDER */ 1189 } asm330lhhxg1_fsm_status_a_t; 1190 1191 #define ASM330LHHXG1_FSM_STATUS_B 0x14U 1192 typedef struct 1193 { 1194 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1195 uint8_t is_fsm9 : 1; 1196 uint8_t is_fsm10 : 1; 1197 uint8_t is_fsm11 : 1; 1198 uint8_t is_fsm12 : 1; 1199 uint8_t is_fsm13 : 1; 1200 uint8_t is_fsm14 : 1; 1201 uint8_t is_fsm15 : 1; 1202 uint8_t is_fsm16 : 1; 1203 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1204 uint8_t is_fsm16 : 1; 1205 uint8_t is_fsm15 : 1; 1206 uint8_t is_fsm14 : 1; 1207 uint8_t is_fsm13 : 1; 1208 uint8_t is_fsm12 : 1; 1209 uint8_t is_fsm11 : 1; 1210 uint8_t is_fsm10 : 1; 1211 uint8_t is_fsm9 : 1; 1212 #endif /* DRV_BYTE_ORDER */ 1213 } asm330lhhxg1_fsm_status_b_t; 1214 1215 #define ASM330LHHXG1_MLC_STATUS 0x15U 1216 typedef struct 1217 { 1218 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1219 uint8_t is_mlc1 : 1; 1220 uint8_t is_mlc2 : 1; 1221 uint8_t is_mlc3 : 1; 1222 uint8_t is_mlc4 : 1; 1223 uint8_t is_mlc5 : 1; 1224 uint8_t is_mlc6 : 1; 1225 uint8_t is_mlc7 : 1; 1226 uint8_t is_mlc8 : 1; 1227 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1228 uint8_t is_mlc8 : 1; 1229 uint8_t is_mlc7 : 1; 1230 uint8_t is_mlc6 : 1; 1231 uint8_t is_mlc5 : 1; 1232 uint8_t is_mlc4 : 1; 1233 uint8_t is_mlc3 : 1; 1234 uint8_t is_mlc2 : 1; 1235 uint8_t is_mlc1 : 1; 1236 #endif /* DRV_BYTE_ORDER */ 1237 } asm330lhhxg1_mlc_status_t; 1238 1239 #define ASM330LHHXG1_PAGE_RW 0x17U 1240 typedef struct 1241 { 1242 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1243 uint8_t not_used_01 : 5; 1244 uint8_t page_rw : 2; /* page_write + page_read */ 1245 uint8_t emb_func_lir : 1; 1246 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1247 uint8_t emb_func_lir : 1; 1248 uint8_t page_rw : 2; /* page_write + page_read */ 1249 uint8_t not_used_01 : 5; 1250 #endif /* DRV_BYTE_ORDER */ 1251 } asm330lhhxg1_page_rw_t; 1252 1253 #define ASM330LHHXG1_FSM_ENABLE_A 0x46U 1254 typedef struct 1255 { 1256 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1257 uint8_t fsm1_en : 1; 1258 uint8_t fsm2_en : 1; 1259 uint8_t fsm3_en : 1; 1260 uint8_t fsm4_en : 1; 1261 uint8_t fsm5_en : 1; 1262 uint8_t fsm6_en : 1; 1263 uint8_t fsm7_en : 1; 1264 uint8_t fsm8_en : 1; 1265 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1266 uint8_t fsm8_en : 1; 1267 uint8_t fsm7_en : 1; 1268 uint8_t fsm6_en : 1; 1269 uint8_t fsm5_en : 1; 1270 uint8_t fsm4_en : 1; 1271 uint8_t fsm3_en : 1; 1272 uint8_t fsm2_en : 1; 1273 uint8_t fsm1_en : 1; 1274 #endif /* DRV_BYTE_ORDER */ 1275 } asm330lhhxg1_fsm_enable_a_t; 1276 1277 #define ASM330LHHXG1_FSM_ENABLE_B 0x47U 1278 typedef struct 1279 { 1280 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1281 uint8_t fsm9_en : 1; 1282 uint8_t fsm10_en : 1; 1283 uint8_t fsm11_en : 1; 1284 uint8_t fsm12_en : 1; 1285 uint8_t fsm13_en : 1; 1286 uint8_t fsm14_en : 1; 1287 uint8_t fsm15_en : 1; 1288 uint8_t fsm16_en : 1; 1289 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1290 uint8_t fsm16_en : 1; 1291 uint8_t fsm15_en : 1; 1292 uint8_t fsm14_en : 1; 1293 uint8_t fsm13_en : 1; 1294 uint8_t fsm12_en : 1; 1295 uint8_t fsm11_en : 1; 1296 uint8_t fsm10_en : 1; 1297 uint8_t fsm9_en : 1; 1298 #endif /* DRV_BYTE_ORDER */ 1299 } asm330lhhxg1_fsm_enable_b_t; 1300 1301 #define ASM330LHHXG1_FSM_LONG_COUNTER_L 0x48U 1302 #define ASM330LHHXG1_FSM_LONG_COUNTER_H 0x49U 1303 #define ASM330LHHXG1_FSM_LONG_COUNTER_CLEAR 0x4AU 1304 typedef struct 1305 { 1306 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1307 uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ 1308 uint8_t not_used_01 : 6; 1309 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1310 uint8_t not_used_01 : 6; 1311 uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ 1312 #endif /* DRV_BYTE_ORDER */ 1313 } asm330lhhxg1_fsm_long_counter_clear_t; 1314 1315 #define ASM330LHHXG1_FSM_OUTS1 0x4CU 1316 typedef struct 1317 { 1318 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1319 uint8_t n_v : 1; 1320 uint8_t p_v : 1; 1321 uint8_t n_z : 1; 1322 uint8_t p_z : 1; 1323 uint8_t n_y : 1; 1324 uint8_t p_y : 1; 1325 uint8_t n_x : 1; 1326 uint8_t p_x : 1; 1327 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1328 uint8_t p_x : 1; 1329 uint8_t n_x : 1; 1330 uint8_t p_y : 1; 1331 uint8_t n_y : 1; 1332 uint8_t p_z : 1; 1333 uint8_t n_z : 1; 1334 uint8_t p_v : 1; 1335 uint8_t n_v : 1; 1336 #endif /* DRV_BYTE_ORDER */ 1337 } asm330lhhxg1_fsm_outs1_t; 1338 1339 #define ASM330LHHXG1_FSM_OUTS2 0x4DU 1340 typedef struct 1341 { 1342 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1343 uint8_t n_v : 1; 1344 uint8_t p_v : 1; 1345 uint8_t n_z : 1; 1346 uint8_t p_z : 1; 1347 uint8_t n_y : 1; 1348 uint8_t p_y : 1; 1349 uint8_t n_x : 1; 1350 uint8_t p_x : 1; 1351 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1352 uint8_t p_x : 1; 1353 uint8_t n_x : 1; 1354 uint8_t p_y : 1; 1355 uint8_t n_y : 1; 1356 uint8_t p_z : 1; 1357 uint8_t n_z : 1; 1358 uint8_t p_v : 1; 1359 uint8_t n_v : 1; 1360 #endif /* DRV_BYTE_ORDER */ 1361 } asm330lhhxg1_fsm_outs2_t; 1362 1363 #define ASM330LHHXG1_FSM_OUTS3 0x4EU 1364 typedef struct 1365 { 1366 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1367 uint8_t n_v : 1; 1368 uint8_t p_v : 1; 1369 uint8_t n_z : 1; 1370 uint8_t p_z : 1; 1371 uint8_t n_y : 1; 1372 uint8_t p_y : 1; 1373 uint8_t n_x : 1; 1374 uint8_t p_x : 1; 1375 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1376 uint8_t p_x : 1; 1377 uint8_t n_x : 1; 1378 uint8_t p_y : 1; 1379 uint8_t n_y : 1; 1380 uint8_t p_z : 1; 1381 uint8_t n_z : 1; 1382 uint8_t p_v : 1; 1383 uint8_t n_v : 1; 1384 #endif /* DRV_BYTE_ORDER */ 1385 } asm330lhhxg1_fsm_outs3_t; 1386 1387 #define ASM330LHHXG1_FSM_OUTS4 0x4FU 1388 typedef struct 1389 { 1390 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1391 uint8_t n_v : 1; 1392 uint8_t p_v : 1; 1393 uint8_t n_z : 1; 1394 uint8_t p_z : 1; 1395 uint8_t n_y : 1; 1396 uint8_t p_y : 1; 1397 uint8_t n_x : 1; 1398 uint8_t p_x : 1; 1399 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1400 uint8_t p_x : 1; 1401 uint8_t n_x : 1; 1402 uint8_t p_y : 1; 1403 uint8_t n_y : 1; 1404 uint8_t p_z : 1; 1405 uint8_t n_z : 1; 1406 uint8_t p_v : 1; 1407 uint8_t n_v : 1; 1408 #endif /* DRV_BYTE_ORDER */ 1409 } asm330lhhxg1_fsm_outs4_t; 1410 1411 #define ASM330LHHXG1_FSM_OUTS5 0x50U 1412 typedef struct 1413 { 1414 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1415 uint8_t n_v : 1; 1416 uint8_t p_v : 1; 1417 uint8_t n_z : 1; 1418 uint8_t p_z : 1; 1419 uint8_t n_y : 1; 1420 uint8_t p_y : 1; 1421 uint8_t n_x : 1; 1422 uint8_t p_x : 1; 1423 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1424 uint8_t p_x : 1; 1425 uint8_t n_x : 1; 1426 uint8_t p_y : 1; 1427 uint8_t n_y : 1; 1428 uint8_t p_z : 1; 1429 uint8_t n_z : 1; 1430 uint8_t p_v : 1; 1431 uint8_t n_v : 1; 1432 #endif /* DRV_BYTE_ORDER */ 1433 } asm330lhhxg1_fsm_outs5_t; 1434 1435 #define ASM330LHHXG1_FSM_OUTS6 0x51U 1436 typedef struct 1437 { 1438 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1439 uint8_t n_v : 1; 1440 uint8_t p_v : 1; 1441 uint8_t n_z : 1; 1442 uint8_t p_z : 1; 1443 uint8_t n_y : 1; 1444 uint8_t p_y : 1; 1445 uint8_t n_x : 1; 1446 uint8_t p_x : 1; 1447 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1448 uint8_t p_x : 1; 1449 uint8_t n_x : 1; 1450 uint8_t p_y : 1; 1451 uint8_t n_y : 1; 1452 uint8_t p_z : 1; 1453 uint8_t n_z : 1; 1454 uint8_t p_v : 1; 1455 uint8_t n_v : 1; 1456 #endif /* DRV_BYTE_ORDER */ 1457 } asm330lhhxg1_fsm_outs6_t; 1458 1459 #define ASM330LHHXG1_FSM_OUTS7 0x52U 1460 typedef struct 1461 { 1462 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1463 uint8_t n_v : 1; 1464 uint8_t p_v : 1; 1465 uint8_t n_z : 1; 1466 uint8_t p_z : 1; 1467 uint8_t n_y : 1; 1468 uint8_t p_y : 1; 1469 uint8_t n_x : 1; 1470 uint8_t p_x : 1; 1471 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1472 uint8_t p_x : 1; 1473 uint8_t n_x : 1; 1474 uint8_t p_y : 1; 1475 uint8_t n_y : 1; 1476 uint8_t p_z : 1; 1477 uint8_t n_z : 1; 1478 uint8_t p_v : 1; 1479 uint8_t n_v : 1; 1480 #endif /* DRV_BYTE_ORDER */ 1481 } asm330lhhxg1_fsm_outs7_t; 1482 1483 #define ASM330LHHXG1_FSM_OUTS8 0x53U 1484 typedef struct 1485 { 1486 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1487 uint8_t n_v : 1; 1488 uint8_t p_v : 1; 1489 uint8_t n_z : 1; 1490 uint8_t p_z : 1; 1491 uint8_t n_y : 1; 1492 uint8_t p_y : 1; 1493 uint8_t n_x : 1; 1494 uint8_t p_x : 1; 1495 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1496 uint8_t p_x : 1; 1497 uint8_t n_x : 1; 1498 uint8_t p_y : 1; 1499 uint8_t n_y : 1; 1500 uint8_t p_z : 1; 1501 uint8_t n_z : 1; 1502 uint8_t p_v : 1; 1503 uint8_t n_v : 1; 1504 #endif /* DRV_BYTE_ORDER */ 1505 } asm330lhhxg1_fsm_outs8_t; 1506 1507 #define ASM330LHHXG1_FSM_OUTS9 0x54U 1508 typedef struct 1509 { 1510 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1511 uint8_t n_v : 1; 1512 uint8_t p_v : 1; 1513 uint8_t n_z : 1; 1514 uint8_t p_z : 1; 1515 uint8_t n_y : 1; 1516 uint8_t p_y : 1; 1517 uint8_t n_x : 1; 1518 uint8_t p_x : 1; 1519 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1520 uint8_t p_x : 1; 1521 uint8_t n_x : 1; 1522 uint8_t p_y : 1; 1523 uint8_t n_y : 1; 1524 uint8_t p_z : 1; 1525 uint8_t n_z : 1; 1526 uint8_t p_v : 1; 1527 uint8_t n_v : 1; 1528 #endif /* DRV_BYTE_ORDER */ 1529 } asm330lhhxg1_fsm_outs9_t; 1530 1531 #define ASM330LHHXG1_FSM_OUTS10 0x55U 1532 typedef struct 1533 { 1534 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1535 uint8_t n_v : 1; 1536 uint8_t p_v : 1; 1537 uint8_t n_z : 1; 1538 uint8_t p_z : 1; 1539 uint8_t n_y : 1; 1540 uint8_t p_y : 1; 1541 uint8_t n_x : 1; 1542 uint8_t p_x : 1; 1543 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1544 uint8_t p_x : 1; 1545 uint8_t n_x : 1; 1546 uint8_t p_y : 1; 1547 uint8_t n_y : 1; 1548 uint8_t p_z : 1; 1549 uint8_t n_z : 1; 1550 uint8_t p_v : 1; 1551 uint8_t n_v : 1; 1552 #endif /* DRV_BYTE_ORDER */ 1553 } asm330lhhxg1_fsm_outs10_t; 1554 1555 #define ASM330LHHXG1_FSM_OUTS11 0x56U 1556 typedef struct 1557 { 1558 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1559 uint8_t n_v : 1; 1560 uint8_t p_v : 1; 1561 uint8_t n_z : 1; 1562 uint8_t p_z : 1; 1563 uint8_t n_y : 1; 1564 uint8_t p_y : 1; 1565 uint8_t n_x : 1; 1566 uint8_t p_x : 1; 1567 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1568 uint8_t p_x : 1; 1569 uint8_t n_x : 1; 1570 uint8_t p_y : 1; 1571 uint8_t n_y : 1; 1572 uint8_t p_z : 1; 1573 uint8_t n_z : 1; 1574 uint8_t p_v : 1; 1575 uint8_t n_v : 1; 1576 #endif /* DRV_BYTE_ORDER */ 1577 } asm330lhhxg1_fsm_outs11_t; 1578 1579 #define ASM330LHHXG1_FSM_OUTS12 0x57U 1580 typedef struct 1581 { 1582 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1583 uint8_t n_v : 1; 1584 uint8_t p_v : 1; 1585 uint8_t n_z : 1; 1586 uint8_t p_z : 1; 1587 uint8_t n_y : 1; 1588 uint8_t p_y : 1; 1589 uint8_t n_x : 1; 1590 uint8_t p_x : 1; 1591 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1592 uint8_t p_x : 1; 1593 uint8_t n_x : 1; 1594 uint8_t p_y : 1; 1595 uint8_t n_y : 1; 1596 uint8_t p_z : 1; 1597 uint8_t n_z : 1; 1598 uint8_t p_v : 1; 1599 uint8_t n_v : 1; 1600 #endif /* DRV_BYTE_ORDER */ 1601 } asm330lhhxg1_fsm_outs12_t; 1602 1603 #define ASM330LHHXG1_FSM_OUTS13 0x58U 1604 typedef struct 1605 { 1606 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1607 uint8_t n_v : 1; 1608 uint8_t p_v : 1; 1609 uint8_t n_z : 1; 1610 uint8_t p_z : 1; 1611 uint8_t n_y : 1; 1612 uint8_t p_y : 1; 1613 uint8_t n_x : 1; 1614 uint8_t p_x : 1; 1615 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1616 uint8_t p_x : 1; 1617 uint8_t n_x : 1; 1618 uint8_t p_y : 1; 1619 uint8_t n_y : 1; 1620 uint8_t p_z : 1; 1621 uint8_t n_z : 1; 1622 uint8_t p_v : 1; 1623 uint8_t n_v : 1; 1624 #endif /* DRV_BYTE_ORDER */ 1625 } asm330lhhxg1_fsm_outs13_t; 1626 1627 #define ASM330LHHXG1_FSM_OUTS14 0x59U 1628 typedef struct 1629 { 1630 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1631 uint8_t n_v : 1; 1632 uint8_t p_v : 1; 1633 uint8_t n_z : 1; 1634 uint8_t p_z : 1; 1635 uint8_t n_y : 1; 1636 uint8_t p_y : 1; 1637 uint8_t n_x : 1; 1638 uint8_t p_x : 1; 1639 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1640 uint8_t p_x : 1; 1641 uint8_t n_x : 1; 1642 uint8_t p_y : 1; 1643 uint8_t n_y : 1; 1644 uint8_t p_z : 1; 1645 uint8_t n_z : 1; 1646 uint8_t p_v : 1; 1647 uint8_t n_v : 1; 1648 #endif /* DRV_BYTE_ORDER */ 1649 } asm330lhhxg1_fsm_outs14_t; 1650 1651 #define ASM330LHHXG1_FSM_OUTS15 0x5AU 1652 typedef struct 1653 { 1654 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1655 uint8_t n_v : 1; 1656 uint8_t p_v : 1; 1657 uint8_t n_z : 1; 1658 uint8_t p_z : 1; 1659 uint8_t n_y : 1; 1660 uint8_t p_y : 1; 1661 uint8_t n_x : 1; 1662 uint8_t p_x : 1; 1663 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1664 uint8_t p_x : 1; 1665 uint8_t n_x : 1; 1666 uint8_t p_y : 1; 1667 uint8_t n_y : 1; 1668 uint8_t p_z : 1; 1669 uint8_t n_z : 1; 1670 uint8_t p_v : 1; 1671 uint8_t n_v : 1; 1672 #endif /* DRV_BYTE_ORDER */ 1673 } asm330lhhxg1_fsm_outs15_t; 1674 1675 #define ASM330LHHXG1_FSM_OUTS16 0x5BU 1676 typedef struct 1677 { 1678 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1679 uint8_t n_v : 1; 1680 uint8_t p_v : 1; 1681 uint8_t n_z : 1; 1682 uint8_t p_z : 1; 1683 uint8_t n_y : 1; 1684 uint8_t p_y : 1; 1685 uint8_t n_x : 1; 1686 uint8_t p_x : 1; 1687 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1688 uint8_t p_x : 1; 1689 uint8_t n_x : 1; 1690 uint8_t p_y : 1; 1691 uint8_t n_y : 1; 1692 uint8_t p_z : 1; 1693 uint8_t n_z : 1; 1694 uint8_t p_v : 1; 1695 uint8_t n_v : 1; 1696 #endif /* DRV_BYTE_ORDER */ 1697 } asm330lhhxg1_fsm_outs16_t; 1698 1699 #define ASM330LHHXG1_EMB_FUNC_ODR_CFG_B 0x5FU 1700 typedef struct 1701 { 1702 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1703 uint8_t not_used_01 : 3; 1704 uint8_t fsm_odr : 2; 1705 uint8_t not_used_02 : 3; 1706 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1707 uint8_t not_used_02 : 3; 1708 uint8_t fsm_odr : 2; 1709 uint8_t not_used_01 : 3; 1710 #endif /* DRV_BYTE_ORDER */ 1711 } asm330lhhxg1_emb_func_odr_cfg_b_t; 1712 1713 #define ASM330LHHXG1_EMB_FUNC_ODR_CFG_C 0x60U 1714 typedef struct 1715 { 1716 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1717 uint8_t not_used_01 : 4; 1718 uint8_t mlc_odr : 2; 1719 uint8_t not_used_02 : 2; 1720 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1721 uint8_t not_used_02 : 2; 1722 uint8_t mlc_odr : 2; 1723 uint8_t not_used_01 : 4; 1724 #endif /* DRV_BYTE_ORDER */ 1725 } asm330lhhxg1_emb_func_odr_cfg_c_t; 1726 1727 #define ASM330LHHXG1_EMB_FUNC_INIT_B 0x67U 1728 typedef struct 1729 { 1730 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1731 uint8_t fsm_init : 1; 1732 uint8_t not_used_01 : 3; 1733 uint8_t mlc_init : 1; 1734 uint8_t not_used_02 : 3; 1735 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1736 uint8_t not_used_02 : 3; 1737 uint8_t mlc_init : 1; 1738 uint8_t not_used_01 : 3; 1739 uint8_t fsm_init : 1; 1740 #endif /* DRV_BYTE_ORDER */ 1741 } asm330lhhxg1_emb_func_init_b_t; 1742 1743 #define ASM330LHHXG1_MLC0_SRC 0x70U 1744 #define ASM330LHHXG1_MLC1_SRC 0x71U 1745 #define ASM330LHHXG1_MLC2_SRC 0x72U 1746 #define ASM330LHHXG1_MLC3_SRC 0x73U 1747 #define ASM330LHHXG1_MLC4_SRC 0x74U 1748 #define ASM330LHHXG1_MLC5_SRC 0x75U 1749 #define ASM330LHHXG1_MLC6_SRC 0x76U 1750 #define ASM330LHHXG1_MLC7_SRC 0x77U 1751 1752 #define ASM330LHHXG1_MAG_SENSITIVITY_L 0xBAU 1753 #define ASM330LHHXG1_MAG_SENSITIVITY_H 0xBBU 1754 #define ASM330LHHXG1_MAG_OFFX_L 0xC0U 1755 #define ASM330LHHXG1_MAG_OFFX_H 0xC1U 1756 #define ASM330LHHXG1_MAG_OFFY_L 0xC2U 1757 #define ASM330LHHXG1_MAG_OFFY_H 0xC3U 1758 #define ASM330LHHXG1_MAG_OFFZ_L 0xC4U 1759 #define ASM330LHHXG1_MAG_OFFZ_H 0xC5U 1760 #define ASM330LHHXG1_MAG_SI_XX_L 0xC6U 1761 #define ASM330LHHXG1_MAG_SI_XX_H 0xC7U 1762 #define ASM330LHHXG1_MAG_SI_XY_L 0xC8U 1763 #define ASM330LHHXG1_MAG_SI_XY_H 0xC9U 1764 #define ASM330LHHXG1_MAG_SI_XZ_L 0xCAU 1765 #define ASM330LHHXG1_MAG_SI_XZ_H 0xCBU 1766 #define ASM330LHHXG1_MAG_SI_YY_L 0xCCU 1767 #define ASM330LHHXG1_MAG_SI_YY_H 0xCDU 1768 #define ASM330LHHXG1_MAG_SI_YZ_L 0xCEU 1769 #define ASM330LHHXG1_MAG_SI_YZ_H 0xCFU 1770 #define ASM330LHHXG1_MAG_SI_ZZ_L 0xD0U 1771 #define ASM330LHHXG1_MAG_SI_ZZ_H 0xD1U 1772 #define ASM330LHHXG1_MAG_CFG_A 0xD4U 1773 typedef struct 1774 { 1775 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1776 uint8_t mag_z_axis : 3; 1777 uint8_t not_used_01 : 1; 1778 uint8_t mag_y_axis : 3; 1779 uint8_t not_used_02 : 1; 1780 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1781 uint8_t not_used_02 : 1; 1782 uint8_t mag_y_axis : 3; 1783 uint8_t not_used_01 : 1; 1784 uint8_t mag_z_axis : 3; 1785 #endif /* DRV_BYTE_ORDER */ 1786 } asm330lhhxg1_mag_cfg_a_t; 1787 1788 #define ASM330LHHXG1_MAG_CFG_B 0xD5U 1789 typedef struct 1790 { 1791 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1792 uint8_t mag_x_axis : 3; 1793 uint8_t not_used_01 : 5; 1794 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1795 uint8_t not_used_01 : 5; 1796 uint8_t mag_x_axis : 3; 1797 #endif /* DRV_BYTE_ORDER */ 1798 } asm330lhhxg1_mag_cfg_b_t; 1799 1800 #define ASM330LHHXG1_FSM_LC_TIMEOUT_L 0x17AU 1801 #define ASM330LHHXG1_FSM_LC_TIMEOUT_H 0x17BU 1802 #define ASM330LHHXG1_FSM_PROGRAMS 0x17CU 1803 #define ASM330LHHXG1_FSM_START_ADD_L 0x17EU 1804 #define ASM330LHHXG1_FSM_START_ADD_H 0x17FU 1805 1806 #define ASM330LHHXG1_MLC_MAG_SENSITIVITY_L 0x1E8U 1807 #define ASM330LHHXG1_MLC_MAG_SENSITIVITY_H 0x1E9U 1808 1809 #define ASM330LHHXG1_SENSOR_HUB_1 0x02U 1810 typedef struct 1811 { 1812 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1813 uint8_t bit0 : 1; 1814 uint8_t bit1 : 1; 1815 uint8_t bit2 : 1; 1816 uint8_t bit3 : 1; 1817 uint8_t bit4 : 1; 1818 uint8_t bit5 : 1; 1819 uint8_t bit6 : 1; 1820 uint8_t bit7 : 1; 1821 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1822 uint8_t bit7 : 1; 1823 uint8_t bit6 : 1; 1824 uint8_t bit5 : 1; 1825 uint8_t bit4 : 1; 1826 uint8_t bit3 : 1; 1827 uint8_t bit2 : 1; 1828 uint8_t bit1 : 1; 1829 uint8_t bit0 : 1; 1830 #endif /* DRV_BYTE_ORDER */ 1831 } asm330lhhxg1_sensor_hub_1_t; 1832 1833 #define ASM330LHHXG1_SENSOR_HUB_2 0x03U 1834 typedef struct 1835 { 1836 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1837 uint8_t bit0 : 1; 1838 uint8_t bit1 : 1; 1839 uint8_t bit2 : 1; 1840 uint8_t bit3 : 1; 1841 uint8_t bit4 : 1; 1842 uint8_t bit5 : 1; 1843 uint8_t bit6 : 1; 1844 uint8_t bit7 : 1; 1845 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1846 uint8_t bit7 : 1; 1847 uint8_t bit6 : 1; 1848 uint8_t bit5 : 1; 1849 uint8_t bit4 : 1; 1850 uint8_t bit3 : 1; 1851 uint8_t bit2 : 1; 1852 uint8_t bit1 : 1; 1853 uint8_t bit0 : 1; 1854 #endif /* DRV_BYTE_ORDER */ 1855 } asm330lhhxg1_sensor_hub_2_t; 1856 1857 #define ASM330LHHXG1_SENSOR_HUB_3 0x04U 1858 typedef struct 1859 { 1860 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1861 uint8_t bit0 : 1; 1862 uint8_t bit1 : 1; 1863 uint8_t bit2 : 1; 1864 uint8_t bit3 : 1; 1865 uint8_t bit4 : 1; 1866 uint8_t bit5 : 1; 1867 uint8_t bit6 : 1; 1868 uint8_t bit7 : 1; 1869 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1870 uint8_t bit7 : 1; 1871 uint8_t bit6 : 1; 1872 uint8_t bit5 : 1; 1873 uint8_t bit4 : 1; 1874 uint8_t bit3 : 1; 1875 uint8_t bit2 : 1; 1876 uint8_t bit1 : 1; 1877 uint8_t bit0 : 1; 1878 #endif /* DRV_BYTE_ORDER */ 1879 } asm330lhhxg1_sensor_hub_3_t; 1880 1881 #define ASM330LHHXG1_SENSOR_HUB_4 0x05U 1882 typedef struct 1883 { 1884 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1885 uint8_t bit0 : 1; 1886 uint8_t bit1 : 1; 1887 uint8_t bit2 : 1; 1888 uint8_t bit3 : 1; 1889 uint8_t bit4 : 1; 1890 uint8_t bit5 : 1; 1891 uint8_t bit6 : 1; 1892 uint8_t bit7 : 1; 1893 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1894 uint8_t bit7 : 1; 1895 uint8_t bit6 : 1; 1896 uint8_t bit5 : 1; 1897 uint8_t bit4 : 1; 1898 uint8_t bit3 : 1; 1899 uint8_t bit2 : 1; 1900 uint8_t bit1 : 1; 1901 uint8_t bit0 : 1; 1902 #endif /* DRV_BYTE_ORDER */ 1903 } asm330lhhxg1_sensor_hub_4_t; 1904 1905 #define ASM330LHHXG1_SENSOR_HUB_5 0x06U 1906 typedef struct 1907 { 1908 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1909 uint8_t bit0 : 1; 1910 uint8_t bit1 : 1; 1911 uint8_t bit2 : 1; 1912 uint8_t bit3 : 1; 1913 uint8_t bit4 : 1; 1914 uint8_t bit5 : 1; 1915 uint8_t bit6 : 1; 1916 uint8_t bit7 : 1; 1917 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1918 uint8_t bit7 : 1; 1919 uint8_t bit6 : 1; 1920 uint8_t bit5 : 1; 1921 uint8_t bit4 : 1; 1922 uint8_t bit3 : 1; 1923 uint8_t bit2 : 1; 1924 uint8_t bit1 : 1; 1925 uint8_t bit0 : 1; 1926 #endif /* DRV_BYTE_ORDER */ 1927 } asm330lhhxg1_sensor_hub_5_t; 1928 1929 #define ASM330LHHXG1_SENSOR_HUB_6 0x07U 1930 typedef struct 1931 { 1932 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1933 uint8_t bit0 : 1; 1934 uint8_t bit1 : 1; 1935 uint8_t bit2 : 1; 1936 uint8_t bit3 : 1; 1937 uint8_t bit4 : 1; 1938 uint8_t bit5 : 1; 1939 uint8_t bit6 : 1; 1940 uint8_t bit7 : 1; 1941 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1942 uint8_t bit7 : 1; 1943 uint8_t bit6 : 1; 1944 uint8_t bit5 : 1; 1945 uint8_t bit4 : 1; 1946 uint8_t bit3 : 1; 1947 uint8_t bit2 : 1; 1948 uint8_t bit1 : 1; 1949 uint8_t bit0 : 1; 1950 #endif /* DRV_BYTE_ORDER */ 1951 } asm330lhhxg1_sensor_hub_6_t; 1952 1953 #define ASM330LHHXG1_SENSOR_HUB_7 0x08U 1954 typedef struct 1955 { 1956 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1957 uint8_t bit0 : 1; 1958 uint8_t bit1 : 1; 1959 uint8_t bit2 : 1; 1960 uint8_t bit3 : 1; 1961 uint8_t bit4 : 1; 1962 uint8_t bit5 : 1; 1963 uint8_t bit6 : 1; 1964 uint8_t bit7 : 1; 1965 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1966 uint8_t bit7 : 1; 1967 uint8_t bit6 : 1; 1968 uint8_t bit5 : 1; 1969 uint8_t bit4 : 1; 1970 uint8_t bit3 : 1; 1971 uint8_t bit2 : 1; 1972 uint8_t bit1 : 1; 1973 uint8_t bit0 : 1; 1974 #endif /* DRV_BYTE_ORDER */ 1975 } asm330lhhxg1_sensor_hub_7_t; 1976 1977 #define ASM330LHHXG1_SENSOR_HUB_8 0x09U 1978 typedef struct 1979 { 1980 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1981 uint8_t bit0 : 1; 1982 uint8_t bit1 : 1; 1983 uint8_t bit2 : 1; 1984 uint8_t bit3 : 1; 1985 uint8_t bit4 : 1; 1986 uint8_t bit5 : 1; 1987 uint8_t bit6 : 1; 1988 uint8_t bit7 : 1; 1989 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1990 uint8_t bit7 : 1; 1991 uint8_t bit6 : 1; 1992 uint8_t bit5 : 1; 1993 uint8_t bit4 : 1; 1994 uint8_t bit3 : 1; 1995 uint8_t bit2 : 1; 1996 uint8_t bit1 : 1; 1997 uint8_t bit0 : 1; 1998 #endif /* DRV_BYTE_ORDER */ 1999 } asm330lhhxg1_sensor_hub_8_t; 2000 2001 #define ASM330LHHXG1_SENSOR_HUB_9 0x0AU 2002 typedef struct 2003 { 2004 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2005 uint8_t bit0 : 1; 2006 uint8_t bit1 : 1; 2007 uint8_t bit2 : 1; 2008 uint8_t bit3 : 1; 2009 uint8_t bit4 : 1; 2010 uint8_t bit5 : 1; 2011 uint8_t bit6 : 1; 2012 uint8_t bit7 : 1; 2013 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2014 uint8_t bit7 : 1; 2015 uint8_t bit6 : 1; 2016 uint8_t bit5 : 1; 2017 uint8_t bit4 : 1; 2018 uint8_t bit3 : 1; 2019 uint8_t bit2 : 1; 2020 uint8_t bit1 : 1; 2021 uint8_t bit0 : 1; 2022 #endif /* DRV_BYTE_ORDER */ 2023 } asm330lhhxg1_sensor_hub_9_t; 2024 2025 #define ASM330LHHXG1_SENSOR_HUB_10 0x0BU 2026 typedef struct 2027 { 2028 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2029 uint8_t bit0 : 1; 2030 uint8_t bit1 : 1; 2031 uint8_t bit2 : 1; 2032 uint8_t bit3 : 1; 2033 uint8_t bit4 : 1; 2034 uint8_t bit5 : 1; 2035 uint8_t bit6 : 1; 2036 uint8_t bit7 : 1; 2037 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2038 uint8_t bit7 : 1; 2039 uint8_t bit6 : 1; 2040 uint8_t bit5 : 1; 2041 uint8_t bit4 : 1; 2042 uint8_t bit3 : 1; 2043 uint8_t bit2 : 1; 2044 uint8_t bit1 : 1; 2045 uint8_t bit0 : 1; 2046 #endif /* DRV_BYTE_ORDER */ 2047 } asm330lhhxg1_sensor_hub_10_t; 2048 2049 #define ASM330LHHXG1_SENSOR_HUB_11 0x0CU 2050 typedef struct 2051 { 2052 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2053 uint8_t bit0 : 1; 2054 uint8_t bit1 : 1; 2055 uint8_t bit2 : 1; 2056 uint8_t bit3 : 1; 2057 uint8_t bit4 : 1; 2058 uint8_t bit5 : 1; 2059 uint8_t bit6 : 1; 2060 uint8_t bit7 : 1; 2061 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2062 uint8_t bit7 : 1; 2063 uint8_t bit6 : 1; 2064 uint8_t bit5 : 1; 2065 uint8_t bit4 : 1; 2066 uint8_t bit3 : 1; 2067 uint8_t bit2 : 1; 2068 uint8_t bit1 : 1; 2069 uint8_t bit0 : 1; 2070 #endif /* DRV_BYTE_ORDER */ 2071 } asm330lhhxg1_sensor_hub_11_t; 2072 2073 #define ASM330LHHXG1_SENSOR_HUB_12 0x0DU 2074 typedef struct 2075 { 2076 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2077 uint8_t bit0 : 1; 2078 uint8_t bit1 : 1; 2079 uint8_t bit2 : 1; 2080 uint8_t bit3 : 1; 2081 uint8_t bit4 : 1; 2082 uint8_t bit5 : 1; 2083 uint8_t bit6 : 1; 2084 uint8_t bit7 : 1; 2085 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2086 uint8_t bit7 : 1; 2087 uint8_t bit6 : 1; 2088 uint8_t bit5 : 1; 2089 uint8_t bit4 : 1; 2090 uint8_t bit3 : 1; 2091 uint8_t bit2 : 1; 2092 uint8_t bit1 : 1; 2093 uint8_t bit0 : 1; 2094 #endif /* DRV_BYTE_ORDER */ 2095 } asm330lhhxg1_sensor_hub_12_t; 2096 2097 #define ASM330LHHXG1_SENSOR_HUB_13 0x0EU 2098 typedef struct 2099 { 2100 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2101 uint8_t bit0 : 1; 2102 uint8_t bit1 : 1; 2103 uint8_t bit2 : 1; 2104 uint8_t bit3 : 1; 2105 uint8_t bit4 : 1; 2106 uint8_t bit5 : 1; 2107 uint8_t bit6 : 1; 2108 uint8_t bit7 : 1; 2109 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2110 uint8_t bit7 : 1; 2111 uint8_t bit6 : 1; 2112 uint8_t bit5 : 1; 2113 uint8_t bit4 : 1; 2114 uint8_t bit3 : 1; 2115 uint8_t bit2 : 1; 2116 uint8_t bit1 : 1; 2117 uint8_t bit0 : 1; 2118 #endif /* DRV_BYTE_ORDER */ 2119 } asm330lhhxg1_sensor_hub_13_t; 2120 2121 #define ASM330LHHXG1_SENSOR_HUB_14 0x0FU 2122 typedef struct 2123 { 2124 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2125 uint8_t bit0 : 1; 2126 uint8_t bit1 : 1; 2127 uint8_t bit2 : 1; 2128 uint8_t bit3 : 1; 2129 uint8_t bit4 : 1; 2130 uint8_t bit5 : 1; 2131 uint8_t bit6 : 1; 2132 uint8_t bit7 : 1; 2133 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2134 uint8_t bit7 : 1; 2135 uint8_t bit6 : 1; 2136 uint8_t bit5 : 1; 2137 uint8_t bit4 : 1; 2138 uint8_t bit3 : 1; 2139 uint8_t bit2 : 1; 2140 uint8_t bit1 : 1; 2141 uint8_t bit0 : 1; 2142 #endif /* DRV_BYTE_ORDER */ 2143 } asm330lhhxg1_sensor_hub_14_t; 2144 2145 #define ASM330LHHXG1_SENSOR_HUB_15 0x10U 2146 typedef struct 2147 { 2148 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2149 uint8_t bit0 : 1; 2150 uint8_t bit1 : 1; 2151 uint8_t bit2 : 1; 2152 uint8_t bit3 : 1; 2153 uint8_t bit4 : 1; 2154 uint8_t bit5 : 1; 2155 uint8_t bit6 : 1; 2156 uint8_t bit7 : 1; 2157 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2158 uint8_t bit7 : 1; 2159 uint8_t bit6 : 1; 2160 uint8_t bit5 : 1; 2161 uint8_t bit4 : 1; 2162 uint8_t bit3 : 1; 2163 uint8_t bit2 : 1; 2164 uint8_t bit1 : 1; 2165 uint8_t bit0 : 1; 2166 #endif /* DRV_BYTE_ORDER */ 2167 } asm330lhhxg1_sensor_hub_15_t; 2168 2169 #define ASM330LHHXG1_SENSOR_HUB_16 0x11U 2170 typedef struct 2171 { 2172 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2173 uint8_t bit0 : 1; 2174 uint8_t bit1 : 1; 2175 uint8_t bit2 : 1; 2176 uint8_t bit3 : 1; 2177 uint8_t bit4 : 1; 2178 uint8_t bit5 : 1; 2179 uint8_t bit6 : 1; 2180 uint8_t bit7 : 1; 2181 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2182 uint8_t bit7 : 1; 2183 uint8_t bit6 : 1; 2184 uint8_t bit5 : 1; 2185 uint8_t bit4 : 1; 2186 uint8_t bit3 : 1; 2187 uint8_t bit2 : 1; 2188 uint8_t bit1 : 1; 2189 uint8_t bit0 : 1; 2190 #endif /* DRV_BYTE_ORDER */ 2191 } asm330lhhxg1_sensor_hub_16_t; 2192 2193 #define ASM330LHHXG1_SENSOR_HUB_17 0x12U 2194 typedef struct 2195 { 2196 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2197 uint8_t bit0 : 1; 2198 uint8_t bit1 : 1; 2199 uint8_t bit2 : 1; 2200 uint8_t bit3 : 1; 2201 uint8_t bit4 : 1; 2202 uint8_t bit5 : 1; 2203 uint8_t bit6 : 1; 2204 uint8_t bit7 : 1; 2205 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2206 uint8_t bit7 : 1; 2207 uint8_t bit6 : 1; 2208 uint8_t bit5 : 1; 2209 uint8_t bit4 : 1; 2210 uint8_t bit3 : 1; 2211 uint8_t bit2 : 1; 2212 uint8_t bit1 : 1; 2213 uint8_t bit0 : 1; 2214 #endif /* DRV_BYTE_ORDER */ 2215 } asm330lhhxg1_sensor_hub_17_t; 2216 2217 #define ASM330LHHXG1_SENSOR_HUB_18 0x13U 2218 typedef struct 2219 { 2220 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2221 uint8_t bit0 : 1; 2222 uint8_t bit1 : 1; 2223 uint8_t bit2 : 1; 2224 uint8_t bit3 : 1; 2225 uint8_t bit4 : 1; 2226 uint8_t bit5 : 1; 2227 uint8_t bit6 : 1; 2228 uint8_t bit7 : 1; 2229 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2230 uint8_t bit7 : 1; 2231 uint8_t bit6 : 1; 2232 uint8_t bit5 : 1; 2233 uint8_t bit4 : 1; 2234 uint8_t bit3 : 1; 2235 uint8_t bit2 : 1; 2236 uint8_t bit1 : 1; 2237 uint8_t bit0 : 1; 2238 #endif /* DRV_BYTE_ORDER */ 2239 } asm330lhhxg1_sensor_hub_18_t; 2240 2241 #define ASM330LHHXG1_MASTER_CONFIG 0x14U 2242 typedef struct 2243 { 2244 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2245 uint8_t aux_sens_on : 2; 2246 uint8_t master_on : 1; 2247 uint8_t shub_pu_en : 1; 2248 uint8_t pass_through_mode : 1; 2249 uint8_t start_config : 1; 2250 uint8_t write_once : 1; 2251 uint8_t rst_master_regs : 1; 2252 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2253 uint8_t rst_master_regs : 1; 2254 uint8_t write_once : 1; 2255 uint8_t start_config : 1; 2256 uint8_t pass_through_mode : 1; 2257 uint8_t shub_pu_en : 1; 2258 uint8_t master_on : 1; 2259 uint8_t aux_sens_on : 2; 2260 #endif /* DRV_BYTE_ORDER */ 2261 } asm330lhhxg1_master_config_t; 2262 2263 #define ASM330LHHXG1_SLV0_ADD 0x15U 2264 typedef struct 2265 { 2266 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2267 uint8_t rw_0 : 1; 2268 uint8_t slave0 : 7; 2269 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2270 uint8_t slave0 : 7; 2271 uint8_t rw_0 : 1; 2272 #endif /* DRV_BYTE_ORDER */ 2273 } asm330lhhxg1_slv0_add_t; 2274 2275 #define ASM330LHHXG1_SLV0_SUBADD 0x16U 2276 typedef struct 2277 { 2278 uint8_t slave0_reg : 8; 2279 } asm330lhhxg1_slv0_subadd_t; 2280 2281 #define ASM330LHHXG1_SLV0_CONFIG 0x17U 2282 typedef struct 2283 { 2284 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2285 uint8_t slave0_numop : 3; 2286 uint8_t batch_ext_sens_0_en : 1; 2287 uint8_t not_used_01 : 2; 2288 uint8_t shub_odr : 2; 2289 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2290 uint8_t shub_odr : 2; 2291 uint8_t not_used_01 : 2; 2292 uint8_t batch_ext_sens_0_en : 1; 2293 uint8_t slave0_numop : 3; 2294 #endif /* DRV_BYTE_ORDER */ 2295 } asm330lhhxg1_slv0_config_t; 2296 2297 #define ASM330LHHXG1_SLV1_ADD 0x18U 2298 typedef struct 2299 { 2300 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2301 uint8_t r_1 : 1; 2302 uint8_t slave1_add : 7; 2303 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2304 uint8_t slave1_add : 7; 2305 uint8_t r_1 : 1; 2306 #endif /* DRV_BYTE_ORDER */ 2307 } asm330lhhxg1_slv1_add_t; 2308 2309 #define ASM330LHHXG1_SLV1_SUBADD 0x19U 2310 typedef struct 2311 { 2312 uint8_t slave1_reg : 8; 2313 } asm330lhhxg1_slv1_subadd_t; 2314 2315 #define ASM330LHHXG1_SLV1_CONFIG 0x1AU 2316 typedef struct 2317 { 2318 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2319 uint8_t slave1_numop : 3; 2320 uint8_t batch_ext_sens_1_en : 1; 2321 uint8_t not_used_01 : 4; 2322 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2323 uint8_t not_used_01 : 4; 2324 uint8_t batch_ext_sens_1_en : 1; 2325 uint8_t slave1_numop : 3; 2326 #endif /* DRV_BYTE_ORDER */ 2327 } asm330lhhxg1_slv1_config_t; 2328 2329 #define ASM330LHHXG1_SLV2_ADD 0x1BU 2330 typedef struct 2331 { 2332 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2333 uint8_t r_2 : 1; 2334 uint8_t slave2_add : 7; 2335 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2336 uint8_t slave2_add : 7; 2337 uint8_t r_2 : 1; 2338 #endif /* DRV_BYTE_ORDER */ 2339 } asm330lhhxg1_slv2_add_t; 2340 2341 #define ASM330LHHXG1_SLV2_SUBADD 0x1CU 2342 typedef struct 2343 { 2344 uint8_t slave2_reg : 8; 2345 } asm330lhhxg1_slv2_subadd_t; 2346 2347 #define ASM330LHHXG1_SLV2_CONFIG 0x1DU 2348 typedef struct 2349 { 2350 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2351 uint8_t slave2_numop : 3; 2352 uint8_t batch_ext_sens_2_en : 1; 2353 uint8_t not_used_01 : 4; 2354 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2355 uint8_t not_used_01 : 4; 2356 uint8_t batch_ext_sens_2_en : 1; 2357 uint8_t slave2_numop : 3; 2358 #endif /* DRV_BYTE_ORDER */ 2359 } asm330lhhxg1_slv2_config_t; 2360 2361 #define ASM330LHHXG1_SLV3_ADD 0x1EU 2362 typedef struct 2363 { 2364 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2365 uint8_t r_3 : 1; 2366 uint8_t slave3_add : 7; 2367 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2368 uint8_t slave3_add : 7; 2369 uint8_t r_3 : 1; 2370 #endif /* DRV_BYTE_ORDER */ 2371 } asm330lhhxg1_slv3_add_t; 2372 2373 #define ASM330LHHXG1_SLV3_SUBADD 0x1FU 2374 typedef struct 2375 { 2376 uint8_t slave3_reg : 8; 2377 } asm330lhhxg1_slv3_subadd_t; 2378 2379 #define ASM330LHHXG1_SLV3_CONFIG 0x20U 2380 typedef struct 2381 { 2382 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2383 uint8_t slave3_numop : 3; 2384 uint8_t batch_ext_sens_3_en : 1; 2385 uint8_t not_used_01 : 4; 2386 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2387 uint8_t not_used_01 : 4; 2388 uint8_t batch_ext_sens_3_en : 1; 2389 uint8_t slave3_numop : 3; 2390 #endif /* DRV_BYTE_ORDER */ 2391 } asm330lhhxg1_slv3_config_t; 2392 2393 #define ASM330LHHXG1_DATAWRITE_SLV0 0x21U 2394 typedef struct 2395 { 2396 uint8_t slave0_dataw : 8; 2397 } asm330lhhxg1_datawrite_slv0_t; 2398 2399 #define ASM330LHHXG1_STATUS_MASTER 0x22U 2400 typedef struct 2401 { 2402 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2403 uint8_t sens_hub_endop : 1; 2404 uint8_t not_used_01 : 2; 2405 uint8_t slave0_nack : 1; 2406 uint8_t slave1_nack : 1; 2407 uint8_t slave2_nack : 1; 2408 uint8_t slave3_nack : 1; 2409 uint8_t wr_once_done : 1; 2410 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2411 uint8_t wr_once_done : 1; 2412 uint8_t slave3_nack : 1; 2413 uint8_t slave2_nack : 1; 2414 uint8_t slave1_nack : 1; 2415 uint8_t slave0_nack : 1; 2416 uint8_t not_used_01 : 2; 2417 uint8_t sens_hub_endop : 1; 2418 #endif /* DRV_BYTE_ORDER */ 2419 } asm330lhhxg1_status_master_t; 2420 2421 /** 2422 * @defgroup ASM330LHHXG1_Register_Union 2423 * @brief This union group all the registers that has a bit-field 2424 * description. 2425 * This union is useful but not need by the driver. 2426 * 2427 * REMOVING this union you are compliant with: 2428 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 2429 * 2430 * @{ 2431 * 2432 */ 2433 typedef union 2434 { 2435 asm330lhhxg1_func_cfg_access_t func_cfg_access; 2436 asm330lhhxg1_pin_ctrl_t pin_ctrl; 2437 asm330lhhxg1_fifo_ctrl1_t fifo_ctrl1; 2438 asm330lhhxg1_fifo_ctrl2_t fifo_ctrl2; 2439 asm330lhhxg1_fifo_ctrl3_t fifo_ctrl3; 2440 asm330lhhxg1_fifo_ctrl4_t fifo_ctrl4; 2441 asm330lhhxg1_counter_bdr_reg1_t counter_bdr_reg1; 2442 asm330lhhxg1_counter_bdr_reg2_t counter_bdr_reg2; 2443 asm330lhhxg1_int1_ctrl_t int1_ctrl; 2444 asm330lhhxg1_int2_ctrl_t int2_ctrl; 2445 asm330lhhxg1_ctrl1_xl_t ctrl1_xl; 2446 asm330lhhxg1_ctrl2_g_t ctrl2_g; 2447 asm330lhhxg1_ctrl3_c_t ctrl3_c; 2448 asm330lhhxg1_ctrl4_c_t ctrl4_c; 2449 asm330lhhxg1_ctrl5_c_t ctrl5_c; 2450 asm330lhhxg1_ctrl6_c_t ctrl6_c; 2451 asm330lhhxg1_ctrl7_g_t ctrl7_g; 2452 asm330lhhxg1_ctrl8_xl_t ctrl8_xl; 2453 asm330lhhxg1_ctrl9_xl_t ctrl9_xl; 2454 asm330lhhxg1_ctrl10_c_t ctrl10_c; 2455 asm330lhhxg1_all_int_src_t all_int_src; 2456 asm330lhhxg1_wake_up_src_t wake_up_src; 2457 asm330lhhxg1_d6d_src_t d6d_src; 2458 asm330lhhxg1_status_reg_t status_reg; 2459 asm330lhhxg1_fifo_status1_t fifo_status1; 2460 asm330lhhxg1_fifo_status2_t fifo_status2; 2461 asm330lhhxg1_int_cfg0_t int_cfg0; 2462 asm330lhhxg1_int_cfg1_t int_cfg1; 2463 asm330lhhxg1_ths_6d_t ths_6d; 2464 asm330lhhxg1_wake_up_ths_t wake_up_ths; 2465 asm330lhhxg1_wake_up_dur_t wake_up_dur; 2466 asm330lhhxg1_free_fall_t free_fall; 2467 asm330lhhxg1_md1_cfg_t md1_cfg; 2468 asm330lhhxg1_md2_cfg_t md2_cfg; 2469 asm330lhhxg1_i3c_bus_avb_t i3c_bus_avb; 2470 asm330lhhxg1_internal_freq_fine_t internal_freq_fine; 2471 asm330lhhxg1_fifo_data_out_tag_t fifo_data_out_tag; 2472 asm330lhhxg1_page_sel_t page_sel; 2473 asm330lhhxg1_emb_func_en_b_t emb_func_en_b; 2474 asm330lhhxg1_page_address_t page_address; 2475 asm330lhhxg1_page_value_t page_value; 2476 asm330lhhxg1_emb_func_int1_t emb_func_int1; 2477 asm330lhhxg1_fsm_int1_a_t fsm_int1_a; 2478 asm330lhhxg1_fsm_int1_b_t fsm_int1_b; 2479 asm330lhhxg1_mlc_int1_t mlc_int1; 2480 asm330lhhxg1_emb_func_int2_t emb_func_int2; 2481 asm330lhhxg1_fsm_int2_a_t fsm_int2_a; 2482 asm330lhhxg1_fsm_int2_b_t fsm_int2_b; 2483 asm330lhhxg1_mlc_int2_t mlc_int2; 2484 asm330lhhxg1_emb_func_status_t emb_func_status; 2485 asm330lhhxg1_fsm_status_a_t fsm_status_a; 2486 asm330lhhxg1_fsm_status_b_t fsm_status_b; 2487 asm330lhhxg1_mlc_status_mainpage_t mlc_status_mainpage; 2488 asm330lhhxg1_emb_func_odr_cfg_c_t emb_func_odr_cfg_c; 2489 asm330lhhxg1_page_rw_t page_rw; 2490 asm330lhhxg1_fsm_enable_a_t fsm_enable_a; 2491 asm330lhhxg1_fsm_enable_b_t fsm_enable_b; 2492 asm330lhhxg1_fsm_long_counter_clear_t fsm_long_counter_clear; 2493 asm330lhhxg1_fsm_outs1_t fsm_outs1; 2494 asm330lhhxg1_fsm_outs2_t fsm_outs2; 2495 asm330lhhxg1_fsm_outs3_t fsm_outs3; 2496 asm330lhhxg1_fsm_outs4_t fsm_outs4; 2497 asm330lhhxg1_fsm_outs5_t fsm_outs5; 2498 asm330lhhxg1_fsm_outs6_t fsm_outs6; 2499 asm330lhhxg1_fsm_outs7_t fsm_outs7; 2500 asm330lhhxg1_fsm_outs8_t fsm_outs8; 2501 asm330lhhxg1_fsm_outs9_t fsm_outs9; 2502 asm330lhhxg1_fsm_outs10_t fsm_outs10; 2503 asm330lhhxg1_fsm_outs11_t fsm_outs11; 2504 asm330lhhxg1_fsm_outs12_t fsm_outs12; 2505 asm330lhhxg1_fsm_outs13_t fsm_outs13; 2506 asm330lhhxg1_fsm_outs14_t fsm_outs14; 2507 asm330lhhxg1_fsm_outs15_t fsm_outs15; 2508 asm330lhhxg1_fsm_outs16_t fsm_outs16; 2509 asm330lhhxg1_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; 2510 asm330lhhxg1_emb_func_init_b_t emb_func_init_b; 2511 asm330lhhxg1_mag_cfg_a_t mag_cfg_a; 2512 asm330lhhxg1_mag_cfg_b_t mag_cfg_b; 2513 asm330lhhxg1_sensor_hub_1_t sensor_hub_1; 2514 asm330lhhxg1_sensor_hub_2_t sensor_hub_2; 2515 asm330lhhxg1_sensor_hub_3_t sensor_hub_3; 2516 asm330lhhxg1_sensor_hub_4_t sensor_hub_4; 2517 asm330lhhxg1_sensor_hub_5_t sensor_hub_5; 2518 asm330lhhxg1_sensor_hub_6_t sensor_hub_6; 2519 asm330lhhxg1_sensor_hub_7_t sensor_hub_7; 2520 asm330lhhxg1_sensor_hub_8_t sensor_hub_8; 2521 asm330lhhxg1_sensor_hub_9_t sensor_hub_9; 2522 asm330lhhxg1_sensor_hub_10_t sensor_hub_10; 2523 asm330lhhxg1_sensor_hub_11_t sensor_hub_11; 2524 asm330lhhxg1_sensor_hub_12_t sensor_hub_12; 2525 asm330lhhxg1_sensor_hub_13_t sensor_hub_13; 2526 asm330lhhxg1_sensor_hub_14_t sensor_hub_14; 2527 asm330lhhxg1_sensor_hub_15_t sensor_hub_15; 2528 asm330lhhxg1_sensor_hub_16_t sensor_hub_16; 2529 asm330lhhxg1_sensor_hub_17_t sensor_hub_17; 2530 asm330lhhxg1_sensor_hub_18_t sensor_hub_18; 2531 asm330lhhxg1_master_config_t master_config; 2532 asm330lhhxg1_slv0_add_t slv0_add; 2533 asm330lhhxg1_slv0_subadd_t slv0_subadd; 2534 asm330lhhxg1_slv0_config_t slv0_config; 2535 asm330lhhxg1_slv1_add_t slv1_add; 2536 asm330lhhxg1_slv1_subadd_t slv1_subadd; 2537 asm330lhhxg1_slv1_config_t slv1_config; 2538 asm330lhhxg1_slv2_add_t slv2_add; 2539 asm330lhhxg1_slv2_subadd_t slv2_subadd; 2540 asm330lhhxg1_slv2_config_t slv2_config; 2541 asm330lhhxg1_slv3_add_t slv3_add; 2542 asm330lhhxg1_slv3_subadd_t slv3_subadd; 2543 asm330lhhxg1_slv3_config_t slv3_config; 2544 asm330lhhxg1_datawrite_slv0_t datawrite_slv0; 2545 asm330lhhxg1_status_master_t status_master; 2546 bitwise_t bitwise; 2547 uint8_t byte; 2548 } asm330lhhxg1_reg_t; 2549 2550 /** 2551 * @} 2552 * 2553 */ 2554 2555 #ifndef __weak 2556 #define __weak __attribute__((weak)) 2557 #endif /* __weak */ 2558 2559 /* 2560 * These are the basic platform dependent I/O routines to read 2561 * and write device registers connected on a standard bus. 2562 * The driver keeps offering a default implementation based on function 2563 * pointers to read/write routines for backward compatibility. 2564 * The __weak directive allows the final application to overwrite 2565 * them with a custom implementation. 2566 */ 2567 2568 int32_t asm330lhhxg1_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, 2569 uint16_t len); 2570 int32_t asm330lhhxg1_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, 2571 uint16_t len); 2572 2573 float_t asm330lhhxg1_from_fs2g_to_mg(int16_t lsb); 2574 float_t asm330lhhxg1_from_fs4g_to_mg(int16_t lsb); 2575 float_t asm330lhhxg1_from_fs8g_to_mg(int16_t lsb); 2576 float_t asm330lhhxg1_from_fs16g_to_mg(int16_t lsb); 2577 float_t asm330lhhxg1_from_fs125dps_to_mdps(int16_t lsb); 2578 float_t asm330lhhxg1_from_fs250dps_to_mdps(int16_t lsb); 2579 float_t asm330lhhxg1_from_fs500dps_to_mdps(int16_t lsb); 2580 float_t asm330lhhxg1_from_fs1000dps_to_mdps(int16_t lsb); 2581 float_t asm330lhhxg1_from_fs2000dps_to_mdps(int16_t lsb); 2582 float_t asm330lhhxg1_from_fs4000dps_to_mdps(int16_t lsb); 2583 float_t asm330lhhxg1_from_lsb_to_celsius(int16_t lsb); 2584 float_t asm330lhhxg1_from_lsb_to_nsec(int32_t lsb); 2585 2586 typedef enum 2587 { 2588 ASM330LHHXG1_2g = 0, 2589 ASM330LHHXG1_16g = 1, /* if XL_FS_MODE = '1' -> ASM330LHHXG1_2g */ 2590 ASM330LHHXG1_4g = 2, 2591 ASM330LHHXG1_8g = 3, 2592 } asm330lhhxg1_fs_xl_t; 2593 int32_t asm330lhhxg1_xl_full_scale_set(const stmdev_ctx_t *ctx, asm330lhhxg1_fs_xl_t val); 2594 int32_t asm330lhhxg1_xl_full_scale_get(const stmdev_ctx_t *ctx, 2595 asm330lhhxg1_fs_xl_t *val); 2596 2597 typedef enum 2598 { 2599 ASM330LHHXG1_XL_ODR_OFF = 0, 2600 ASM330LHHXG1_XL_ODR_12Hz5 = 1, 2601 ASM330LHHXG1_XL_ODR_26Hz = 2, 2602 ASM330LHHXG1_XL_ODR_52Hz = 3, 2603 ASM330LHHXG1_XL_ODR_104Hz = 4, 2604 ASM330LHHXG1_XL_ODR_208Hz = 5, 2605 ASM330LHHXG1_XL_ODR_417Hz = 6, 2606 ASM330LHHXG1_XL_ODR_833Hz = 7, 2607 ASM330LHHXG1_XL_ODR_1667Hz = 8, 2608 ASM330LHHXG1_XL_ODR_3333Hz = 9, 2609 ASM330LHHXG1_XL_ODR_6667Hz = 10, 2610 ASM330LHHXG1_XL_ODR_1Hz6 = 11, /* (low power only) */ 2611 } asm330lhhxg1_odr_xl_t; 2612 int32_t asm330lhhxg1_xl_data_rate_set(const stmdev_ctx_t *ctx, asm330lhhxg1_odr_xl_t val); 2613 int32_t asm330lhhxg1_xl_data_rate_get(const stmdev_ctx_t *ctx, 2614 asm330lhhxg1_odr_xl_t *val); 2615 2616 typedef enum 2617 { 2618 ASM330LHHXG1_125dps = 2, 2619 ASM330LHHXG1_250dps = 0, 2620 ASM330LHHXG1_500dps = 4, 2621 ASM330LHHXG1_1000dps = 8, 2622 ASM330LHHXG1_2000dps = 12, 2623 ASM330LHHXG1_4000dps = 1, 2624 } asm330lhhxg1_fs_g_t; 2625 int32_t asm330lhhxg1_gy_full_scale_set(const stmdev_ctx_t *ctx, asm330lhhxg1_fs_g_t val); 2626 int32_t asm330lhhxg1_gy_full_scale_get(const stmdev_ctx_t *ctx, asm330lhhxg1_fs_g_t *val); 2627 2628 typedef enum 2629 { 2630 ASM330LHHXG1_GY_ODR_OFF = 0, 2631 ASM330LHHXG1_GY_ODR_12Hz5 = 1, 2632 ASM330LHHXG1_GY_ODR_26Hz = 2, 2633 ASM330LHHXG1_GY_ODR_52Hz = 3, 2634 ASM330LHHXG1_GY_ODR_104Hz = 4, 2635 ASM330LHHXG1_GY_ODR_208Hz = 5, 2636 ASM330LHHXG1_GY_ODR_417Hz = 6, 2637 ASM330LHHXG1_GY_ODR_833Hz = 7, 2638 ASM330LHHXG1_GY_ODR_1667Hz = 8, 2639 ASM330LHHXG1_GY_ODR_3333Hz = 9, 2640 ASM330LHHXG1_GY_ODR_6667Hz = 10, 2641 } asm330lhhxg1_odr_g_t; 2642 int32_t asm330lhhxg1_gy_data_rate_set(const stmdev_ctx_t *ctx, 2643 asm330lhhxg1_odr_g_t val); 2644 int32_t asm330lhhxg1_gy_data_rate_get(const stmdev_ctx_t *ctx, 2645 asm330lhhxg1_odr_g_t *val); 2646 2647 int32_t asm330lhhxg1_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); 2648 int32_t asm330lhhxg1_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); 2649 2650 typedef enum 2651 { 2652 ASM330LHHXG1_LSb_1mg = 0, 2653 ASM330LHHXG1_LSb_16mg = 1, 2654 } asm330lhhxg1_usr_off_w_t; 2655 int32_t asm330lhhxg1_xl_offset_weight_set(const stmdev_ctx_t *ctx, 2656 asm330lhhxg1_usr_off_w_t val); 2657 int32_t asm330lhhxg1_xl_offset_weight_get(const stmdev_ctx_t *ctx, 2658 asm330lhhxg1_usr_off_w_t *val); 2659 2660 typedef enum 2661 { 2662 ASM330LHHXG1_HIGH_PERFORMANCE_MD = 0, 2663 ASM330LHHXG1_LOW_NORMAL_POWER_MD = 1, 2664 } asm330lhhxg1_xl_hm_mode_t; 2665 int32_t asm330lhhxg1_xl_power_mode_set(const stmdev_ctx_t *ctx, 2666 asm330lhhxg1_xl_hm_mode_t val); 2667 int32_t asm330lhhxg1_xl_power_mode_get(const stmdev_ctx_t *ctx, 2668 asm330lhhxg1_xl_hm_mode_t *val); 2669 2670 typedef enum 2671 { 2672 ASM330LHHXG1_GY_HIGH_PERFORMANCE = 0, 2673 ASM330LHHXG1_GY_NORMAL = 1, 2674 } asm330lhhxg1_g_hm_mode_t; 2675 int32_t asm330lhhxg1_gy_power_mode_set(const stmdev_ctx_t *ctx, 2676 asm330lhhxg1_g_hm_mode_t val); 2677 int32_t asm330lhhxg1_gy_power_mode_get(const stmdev_ctx_t *ctx, 2678 asm330lhhxg1_g_hm_mode_t *val); 2679 2680 typedef struct 2681 { 2682 asm330lhhxg1_all_int_src_t all_int_src; 2683 asm330lhhxg1_wake_up_src_t wake_up_src; 2684 asm330lhhxg1_d6d_src_t d6d_src; 2685 asm330lhhxg1_status_reg_t status_reg; 2686 asm330lhhxg1_emb_func_status_t emb_func_status; 2687 asm330lhhxg1_fsm_status_a_t fsm_status_a; 2688 asm330lhhxg1_fsm_status_b_t fsm_status_b; 2689 asm330lhhxg1_mlc_status_mainpage_t mlc_status; 2690 } asm330lhhxg1_all_sources_t; 2691 int32_t asm330lhhxg1_all_sources_get(const stmdev_ctx_t *ctx, 2692 asm330lhhxg1_all_sources_t *val); 2693 2694 int32_t asm330lhhxg1_status_reg_get(const stmdev_ctx_t *ctx, 2695 asm330lhhxg1_status_reg_t *val); 2696 2697 int32_t asm330lhhxg1_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 2698 2699 int32_t asm330lhhxg1_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 2700 2701 int32_t asm330lhhxg1_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 2702 2703 int32_t asm330lhhxg1_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff); 2704 int32_t asm330lhhxg1_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff); 2705 2706 int32_t asm330lhhxg1_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff); 2707 int32_t asm330lhhxg1_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff); 2708 2709 int32_t asm330lhhxg1_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff); 2710 int32_t asm330lhhxg1_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff); 2711 2712 int32_t asm330lhhxg1_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val); 2713 int32_t asm330lhhxg1_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val); 2714 2715 int32_t asm330lhhxg1_timestamp_rst(const stmdev_ctx_t *ctx); 2716 2717 int32_t asm330lhhxg1_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); 2718 int32_t asm330lhhxg1_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); 2719 2720 int32_t asm330lhhxg1_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); 2721 2722 typedef enum 2723 { 2724 ASM330LHHXG1_NO_ROUND = 0, 2725 ASM330LHHXG1_ROUND_XL = 1, 2726 ASM330LHHXG1_ROUND_GY = 2, 2727 ASM330LHHXG1_ROUND_GY_XL = 3, 2728 } asm330lhhxg1_rounding_t; 2729 int32_t asm330lhhxg1_rounding_mode_set(const stmdev_ctx_t *ctx, 2730 asm330lhhxg1_rounding_t val); 2731 int32_t asm330lhhxg1_rounding_mode_get(const stmdev_ctx_t *ctx, 2732 asm330lhhxg1_rounding_t *val); 2733 2734 int32_t asm330lhhxg1_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 2735 2736 int32_t asm330lhhxg1_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 2737 2738 int32_t asm330lhhxg1_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 2739 2740 int32_t asm330lhhxg1_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *val); 2741 2742 int32_t asm330lhhxg1_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); 2743 int32_t asm330lhhxg1_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); 2744 2745 typedef enum 2746 { 2747 ASM330LHHXG1_USER_BANK = 0, 2748 ASM330LHHXG1_SENSOR_HUB_BANK = 1, 2749 ASM330LHHXG1_EMBEDDED_FUNC_BANK = 2, 2750 } asm330lhhxg1_reg_access_t; 2751 int32_t asm330lhhxg1_mem_bank_set(const stmdev_ctx_t *ctx, asm330lhhxg1_reg_access_t val); 2752 int32_t asm330lhhxg1_mem_bank_get(const stmdev_ctx_t *ctx, 2753 asm330lhhxg1_reg_access_t *val); 2754 2755 int32_t asm330lhhxg1_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t address, 2756 uint8_t *val); 2757 int32_t asm330lhhxg1_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, 2758 uint8_t *buf, uint8_t len); 2759 int32_t asm330lhhxg1_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, 2760 uint8_t *val); 2761 int32_t asm330lhhxg1_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, 2762 uint8_t *val); 2763 2764 typedef enum 2765 { 2766 ASM330LHHXG1_DRDY_LATCHED = 0, 2767 ASM330LHHXG1_DRDY_PULSED = 1, 2768 } asm330lhhxg1_dataready_pulsed_t; 2769 int32_t asm330lhhxg1_data_ready_mode_set(const stmdev_ctx_t *ctx, 2770 asm330lhhxg1_dataready_pulsed_t val); 2771 int32_t asm330lhhxg1_data_ready_mode_get(const stmdev_ctx_t *ctx, 2772 asm330lhhxg1_dataready_pulsed_t *val); 2773 2774 int32_t asm330lhhxg1_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 2775 2776 int32_t asm330lhhxg1_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 2777 int32_t asm330lhhxg1_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 2778 2779 int32_t asm330lhhxg1_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); 2780 int32_t asm330lhhxg1_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); 2781 2782 int32_t asm330lhhxg1_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 2783 int32_t asm330lhhxg1_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 2784 2785 typedef enum 2786 { 2787 ASM330LHHXG1_XL_ST_DISABLE = 0, 2788 ASM330LHHXG1_XL_ST_POSITIVE = 1, 2789 ASM330LHHXG1_XL_ST_NEGATIVE = 2, 2790 } asm330lhhxg1_st_xl_t; 2791 int32_t asm330lhhxg1_xl_self_test_set(const stmdev_ctx_t *ctx, asm330lhhxg1_st_xl_t val); 2792 int32_t asm330lhhxg1_xl_self_test_get(const stmdev_ctx_t *ctx, asm330lhhxg1_st_xl_t *val); 2793 2794 typedef enum 2795 { 2796 ASM330LHHXG1_GY_ST_DISABLE = 0, 2797 ASM330LHHXG1_GY_ST_POSITIVE = 1, 2798 ASM330LHHXG1_GY_ST_NEGATIVE = 3, 2799 } asm330lhhxg1_st_g_t; 2800 int32_t asm330lhhxg1_gy_self_test_set(const stmdev_ctx_t *ctx, asm330lhhxg1_st_g_t val); 2801 int32_t asm330lhhxg1_gy_self_test_get(const stmdev_ctx_t *ctx, asm330lhhxg1_st_g_t *val); 2802 2803 int32_t asm330lhhxg1_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); 2804 int32_t asm330lhhxg1_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); 2805 2806 int32_t asm330lhhxg1_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); 2807 int32_t asm330lhhxg1_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); 2808 2809 int32_t asm330lhhxg1_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); 2810 int32_t asm330lhhxg1_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); 2811 2812 typedef enum 2813 { 2814 ASM330LHHXG1_ULTRA_LIGHT = 0, 2815 ASM330LHHXG1_VERY_LIGHT = 1, 2816 ASM330LHHXG1_LIGHT = 2, 2817 ASM330LHHXG1_MEDIUM = 3, 2818 ASM330LHHXG1_STRONG = 4, 2819 ASM330LHHXG1_VERY_STRONG = 5, 2820 ASM330LHHXG1_AGGRESSIVE = 6, 2821 ASM330LHHXG1_XTREME = 7, 2822 } asm330lhhxg1_ftype_t; 2823 int32_t asm330lhhxg1_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, 2824 asm330lhhxg1_ftype_t val); 2825 int32_t asm330lhhxg1_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, 2826 asm330lhhxg1_ftype_t *val); 2827 2828 int32_t asm330lhhxg1_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val); 2829 int32_t asm330lhhxg1_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val); 2830 2831 typedef enum 2832 { 2833 ASM330LHHXG1_HP_PATH_DISABLE_ON_OUT = 0x00, 2834 ASM330LHHXG1_SLOPE_ODR_DIV_4 = 0x10, 2835 ASM330LHHXG1_HP_ODR_DIV_10 = 0x11, 2836 ASM330LHHXG1_HP_ODR_DIV_20 = 0x12, 2837 ASM330LHHXG1_HP_ODR_DIV_45 = 0x13, 2838 ASM330LHHXG1_HP_ODR_DIV_100 = 0x14, 2839 ASM330LHHXG1_HP_ODR_DIV_200 = 0x15, 2840 ASM330LHHXG1_HP_ODR_DIV_400 = 0x16, 2841 ASM330LHHXG1_HP_ODR_DIV_800 = 0x17, 2842 ASM330LHHXG1_HP_REF_MD_ODR_DIV_10 = 0x31, 2843 ASM330LHHXG1_HP_REF_MD_ODR_DIV_20 = 0x32, 2844 ASM330LHHXG1_HP_REF_MD_ODR_DIV_45 = 0x33, 2845 ASM330LHHXG1_HP_REF_MD_ODR_DIV_100 = 0x34, 2846 ASM330LHHXG1_HP_REF_MD_ODR_DIV_200 = 0x35, 2847 ASM330LHHXG1_HP_REF_MD_ODR_DIV_400 = 0x36, 2848 ASM330LHHXG1_HP_REF_MD_ODR_DIV_800 = 0x37, 2849 ASM330LHHXG1_LP_ODR_DIV_10 = 0x01, 2850 ASM330LHHXG1_LP_ODR_DIV_20 = 0x02, 2851 ASM330LHHXG1_LP_ODR_DIV_45 = 0x03, 2852 ASM330LHHXG1_LP_ODR_DIV_100 = 0x04, 2853 ASM330LHHXG1_LP_ODR_DIV_200 = 0x05, 2854 ASM330LHHXG1_LP_ODR_DIV_400 = 0x06, 2855 ASM330LHHXG1_LP_ODR_DIV_800 = 0x07, 2856 } asm330lhhxg1_hp_slope_xl_en_t; 2857 int32_t asm330lhhxg1_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, 2858 asm330lhhxg1_hp_slope_xl_en_t val); 2859 int32_t asm330lhhxg1_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, 2860 asm330lhhxg1_hp_slope_xl_en_t *val); 2861 2862 int32_t asm330lhhxg1_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); 2863 int32_t asm330lhhxg1_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); 2864 2865 typedef enum 2866 { 2867 ASM330LHHXG1_USE_SLOPE = 0, 2868 ASM330LHHXG1_USE_HPF = 1, 2869 } asm330lhhxg1_slope_fds_t; 2870 int32_t asm330lhhxg1_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, 2871 asm330lhhxg1_slope_fds_t val); 2872 int32_t asm330lhhxg1_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, 2873 asm330lhhxg1_slope_fds_t *val); 2874 2875 typedef enum 2876 { 2877 ASM330LHHXG1_HP_FILTER_NONE = 0x00, 2878 ASM330LHHXG1_HP_FILTER_16mHz = 0x80, 2879 ASM330LHHXG1_HP_FILTER_65mHz = 0x81, 2880 ASM330LHHXG1_HP_FILTER_260mHz = 0x82, 2881 ASM330LHHXG1_HP_FILTER_1Hz04 = 0x83, 2882 } asm330lhhxg1_hpm_g_t; 2883 int32_t asm330lhhxg1_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, 2884 asm330lhhxg1_hpm_g_t val); 2885 int32_t asm330lhhxg1_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, 2886 asm330lhhxg1_hpm_g_t *val); 2887 2888 typedef enum 2889 { 2890 ASM330LHHXG1_PULL_UP_DISC = 0, 2891 ASM330LHHXG1_PULL_UP_CONNECT = 1, 2892 } asm330lhhxg1_sdo_pu_en_t; 2893 int32_t asm330lhhxg1_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, 2894 asm330lhhxg1_sdo_pu_en_t val); 2895 int32_t asm330lhhxg1_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, 2896 asm330lhhxg1_sdo_pu_en_t *val); 2897 2898 typedef enum 2899 { 2900 ASM330LHHXG1_PULL_DOWN_CONNECT = 0, 2901 ASM330LHHXG1_PULL_DOWN_DISC = 1, 2902 } asm330lhhxg1_pd_dis_int1_t; 2903 int32_t asm330lhhxg1_int1_mode_set(const stmdev_ctx_t *ctx, 2904 asm330lhhxg1_pd_dis_int1_t val); 2905 int32_t asm330lhhxg1_int1_mode_get(const stmdev_ctx_t *ctx, 2906 asm330lhhxg1_pd_dis_int1_t *val); 2907 2908 typedef enum 2909 { 2910 ASM330LHHXG1_SPI_4_WIRE = 0, 2911 ASM330LHHXG1_SPI_3_WIRE = 1, 2912 } asm330lhhxg1_sim_t; 2913 int32_t asm330lhhxg1_spi_mode_set(const stmdev_ctx_t *ctx, asm330lhhxg1_sim_t val); 2914 int32_t asm330lhhxg1_spi_mode_get(const stmdev_ctx_t *ctx, asm330lhhxg1_sim_t *val); 2915 2916 typedef enum 2917 { 2918 ASM330LHHXG1_I2C_ENABLE = 0, 2919 ASM330LHHXG1_I2C_DISABLE = 1, 2920 } asm330lhhxg1_i2c_disable_t; 2921 int32_t asm330lhhxg1_i2c_interface_set(const stmdev_ctx_t *ctx, 2922 asm330lhhxg1_i2c_disable_t val); 2923 int32_t asm330lhhxg1_i2c_interface_get(const stmdev_ctx_t *ctx, 2924 asm330lhhxg1_i2c_disable_t *val); 2925 2926 typedef enum 2927 { 2928 ASM330LHHXG1_I3C_DISABLE = 0x80, 2929 ASM330LHHXG1_I3C_ENABLE_T_50us = 0x00, 2930 ASM330LHHXG1_I3C_ENABLE_T_2us = 0x01, 2931 ASM330LHHXG1_I3C_ENABLE_T_1ms = 0x02, 2932 ASM330LHHXG1_I3C_ENABLE_T_25ms = 0x03, 2933 } asm330lhhxg1_i3c_disable_t; 2934 int32_t asm330lhhxg1_i3c_disable_set(const stmdev_ctx_t *ctx, 2935 asm330lhhxg1_i3c_disable_t val); 2936 int32_t asm330lhhxg1_i3c_disable_get(const stmdev_ctx_t *ctx, 2937 asm330lhhxg1_i3c_disable_t *val); 2938 2939 typedef struct 2940 { 2941 asm330lhhxg1_int1_ctrl_t int1_ctrl; 2942 asm330lhhxg1_md1_cfg_t md1_cfg; 2943 asm330lhhxg1_emb_func_int1_t emb_func_int1; 2944 asm330lhhxg1_fsm_int1_a_t fsm_int1_a; 2945 asm330lhhxg1_fsm_int1_b_t fsm_int1_b; 2946 asm330lhhxg1_mlc_int1_t mlc_int1; 2947 } asm330lhhxg1_pin_int1_route_t; 2948 int32_t asm330lhhxg1_pin_int1_route_set(const stmdev_ctx_t *ctx, 2949 asm330lhhxg1_pin_int1_route_t *val); 2950 int32_t asm330lhhxg1_pin_int1_route_get(const stmdev_ctx_t *ctx, 2951 asm330lhhxg1_pin_int1_route_t *val); 2952 2953 typedef struct 2954 { 2955 asm330lhhxg1_int2_ctrl_t int2_ctrl; 2956 asm330lhhxg1_md2_cfg_t md2_cfg; 2957 asm330lhhxg1_emb_func_int2_t emb_func_int2; 2958 asm330lhhxg1_fsm_int2_a_t fsm_int2_a; 2959 asm330lhhxg1_fsm_int2_b_t fsm_int2_b; 2960 asm330lhhxg1_mlc_int2_t mlc_int2; 2961 } asm330lhhxg1_pin_int2_route_t; 2962 int32_t asm330lhhxg1_pin_int2_route_set(const stmdev_ctx_t *ctx, 2963 asm330lhhxg1_pin_int2_route_t *val); 2964 int32_t asm330lhhxg1_pin_int2_route_get(const stmdev_ctx_t *ctx, 2965 asm330lhhxg1_pin_int2_route_t *val); 2966 2967 typedef enum 2968 { 2969 ASM330LHHXG1_PUSH_PULL = 0, 2970 ASM330LHHXG1_OPEN_DRAIN = 1, 2971 } asm330lhhxg1_pp_od_t; 2972 int32_t asm330lhhxg1_pin_mode_set(const stmdev_ctx_t *ctx, asm330lhhxg1_pp_od_t val); 2973 int32_t asm330lhhxg1_pin_mode_get(const stmdev_ctx_t *ctx, asm330lhhxg1_pp_od_t *val); 2974 2975 typedef enum 2976 { 2977 ASM330LHHXG1_ACTIVE_HIGH = 0, 2978 ASM330LHHXG1_ACTIVE_LOW = 1, 2979 } asm330lhhxg1_h_lactive_t; 2980 int32_t asm330lhhxg1_pin_polarity_set(const stmdev_ctx_t *ctx, 2981 asm330lhhxg1_h_lactive_t val); 2982 int32_t asm330lhhxg1_pin_polarity_get(const stmdev_ctx_t *ctx, 2983 asm330lhhxg1_h_lactive_t *val); 2984 2985 int32_t asm330lhhxg1_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); 2986 int32_t asm330lhhxg1_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); 2987 2988 typedef enum 2989 { 2990 ASM330LHHXG1_ALL_INT_PULSED = 0, 2991 ASM330LHHXG1_BASE_LATCHED_EMB_PULSED = 1, 2992 ASM330LHHXG1_BASE_PULSED_EMB_LATCHED = 2, 2993 ASM330LHHXG1_ALL_INT_LATCHED = 3, 2994 } asm330lhhxg1_lir_t; 2995 int32_t asm330lhhxg1_int_notification_set(const stmdev_ctx_t *ctx, 2996 asm330lhhxg1_lir_t val); 2997 int32_t asm330lhhxg1_int_notification_get(const stmdev_ctx_t *ctx, 2998 asm330lhhxg1_lir_t *val); 2999 3000 typedef enum 3001 { 3002 ASM330LHHXG1_LSb_FS_DIV_64 = 0, 3003 ASM330LHHXG1_LSb_FS_DIV_256 = 1, 3004 } asm330lhhxg1_wake_ths_w_t; 3005 int32_t asm330lhhxg1_wkup_ths_weight_set(const stmdev_ctx_t *ctx, 3006 asm330lhhxg1_wake_ths_w_t val); 3007 int32_t asm330lhhxg1_wkup_ths_weight_get(const stmdev_ctx_t *ctx, 3008 asm330lhhxg1_wake_ths_w_t *val); 3009 3010 int32_t asm330lhhxg1_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 3011 int32_t asm330lhhxg1_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 3012 3013 int32_t asm330lhhxg1_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, 3014 uint8_t val); 3015 int32_t asm330lhhxg1_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, 3016 uint8_t *val); 3017 3018 int32_t asm330lhhxg1_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 3019 int32_t asm330lhhxg1_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 3020 3021 int32_t asm330lhhxg1_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 3022 int32_t asm330lhhxg1_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 3023 3024 typedef enum 3025 { 3026 ASM330LHHXG1_DRIVE_SLEEP_CHG_EVENT = 0, 3027 ASM330LHHXG1_DRIVE_SLEEP_STATUS = 1, 3028 } asm330lhhxg1_sleep_status_on_int_t; 3029 int32_t asm330lhhxg1_act_pin_notification_set(const stmdev_ctx_t *ctx, 3030 asm330lhhxg1_sleep_status_on_int_t val); 3031 int32_t asm330lhhxg1_act_pin_notification_get(const stmdev_ctx_t *ctx, 3032 asm330lhhxg1_sleep_status_on_int_t *val); 3033 3034 typedef enum 3035 { 3036 ASM330LHHXG1_XL_AND_GY_NOT_AFFECTED = 0, 3037 ASM330LHHXG1_XL_12Hz5_GY_NOT_AFFECTED = 1, 3038 ASM330LHHXG1_XL_12Hz5_GY_SLEEP = 2, 3039 ASM330LHHXG1_XL_12Hz5_GY_PD = 3, 3040 } asm330lhhxg1_inact_en_t; 3041 int32_t asm330lhhxg1_act_mode_set(const stmdev_ctx_t *ctx, 3042 asm330lhhxg1_inact_en_t val); 3043 int32_t asm330lhhxg1_act_mode_get(const stmdev_ctx_t *ctx, 3044 asm330lhhxg1_inact_en_t *val); 3045 3046 int32_t asm330lhhxg1_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 3047 int32_t asm330lhhxg1_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 3048 3049 typedef enum 3050 { 3051 ASM330LHHXG1_DEG_80 = 0, 3052 ASM330LHHXG1_DEG_70 = 1, 3053 ASM330LHHXG1_DEG_60 = 2, 3054 ASM330LHHXG1_DEG_50 = 3, 3055 } asm330lhhxg1_sixd_ths_t; 3056 int32_t asm330lhhxg1_6d_threshold_set(const stmdev_ctx_t *ctx, 3057 asm330lhhxg1_sixd_ths_t val); 3058 int32_t asm330lhhxg1_6d_threshold_get(const stmdev_ctx_t *ctx, 3059 asm330lhhxg1_sixd_ths_t *val); 3060 3061 int32_t asm330lhhxg1_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 3062 int32_t asm330lhhxg1_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 3063 3064 typedef enum 3065 { 3066 ASM330LHHXG1_FF_TSH_156mg = 0, 3067 ASM330LHHXG1_FF_TSH_219mg = 1, 3068 ASM330LHHXG1_FF_TSH_250mg = 2, 3069 ASM330LHHXG1_FF_TSH_312mg = 3, 3070 ASM330LHHXG1_FF_TSH_344mg = 4, 3071 ASM330LHHXG1_FF_TSH_406mg = 5, 3072 ASM330LHHXG1_FF_TSH_469mg = 6, 3073 ASM330LHHXG1_FF_TSH_500mg = 7, 3074 } asm330lhhxg1_ff_ths_t; 3075 int32_t asm330lhhxg1_ff_threshold_set(const stmdev_ctx_t *ctx, 3076 asm330lhhxg1_ff_ths_t val); 3077 int32_t asm330lhhxg1_ff_threshold_get(const stmdev_ctx_t *ctx, 3078 asm330lhhxg1_ff_ths_t *val); 3079 3080 int32_t asm330lhhxg1_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 3081 int32_t asm330lhhxg1_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 3082 3083 int32_t asm330lhhxg1_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val); 3084 int32_t asm330lhhxg1_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val); 3085 3086 int32_t asm330lhhxg1_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, 3087 uint8_t val); 3088 int32_t asm330lhhxg1_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, 3089 uint8_t *val); 3090 3091 int32_t asm330lhhxg1_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); 3092 int32_t asm330lhhxg1_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); 3093 3094 typedef enum 3095 { 3096 ASM330LHHXG1_XL_NOT_BATCHED = 0, 3097 ASM330LHHXG1_XL_BATCHED_AT_12Hz5 = 1, 3098 ASM330LHHXG1_XL_BATCHED_AT_26Hz = 2, 3099 ASM330LHHXG1_XL_BATCHED_AT_52Hz = 3, 3100 ASM330LHHXG1_XL_BATCHED_AT_104Hz = 4, 3101 ASM330LHHXG1_XL_BATCHED_AT_208Hz = 5, 3102 ASM330LHHXG1_XL_BATCHED_AT_417Hz = 6, 3103 ASM330LHHXG1_XL_BATCHED_AT_833Hz = 7, 3104 ASM330LHHXG1_XL_BATCHED_AT_1667Hz = 8, 3105 ASM330LHHXG1_XL_BATCHED_AT_3333Hz = 9, 3106 ASM330LHHXG1_XL_BATCHED_AT_6667Hz = 10, 3107 ASM330LHHXG1_XL_BATCHED_AT_1Hz6 = 11, 3108 } asm330lhhxg1_bdr_xl_t; 3109 int32_t asm330lhhxg1_fifo_xl_batch_set(const stmdev_ctx_t *ctx, 3110 asm330lhhxg1_bdr_xl_t val); 3111 int32_t asm330lhhxg1_fifo_xl_batch_get(const stmdev_ctx_t *ctx, 3112 asm330lhhxg1_bdr_xl_t *val); 3113 3114 typedef enum 3115 { 3116 ASM330LHHXG1_GY_NOT_BATCHED = 0, 3117 ASM330LHHXG1_GY_BATCHED_AT_12Hz5 = 1, 3118 ASM330LHHXG1_GY_BATCHED_AT_26Hz = 2, 3119 ASM330LHHXG1_GY_BATCHED_AT_52Hz = 3, 3120 ASM330LHHXG1_GY_BATCHED_AT_104Hz = 4, 3121 ASM330LHHXG1_GY_BATCHED_AT_208Hz = 5, 3122 ASM330LHHXG1_GY_BATCHED_AT_417Hz = 6, 3123 ASM330LHHXG1_GY_BATCHED_AT_833Hz = 7, 3124 ASM330LHHXG1_GY_BATCHED_AT_1667Hz = 8, 3125 ASM330LHHXG1_GY_BATCHED_AT_3333Hz = 9, 3126 ASM330LHHXG1_GY_BATCHED_AT_6667Hz = 10, 3127 ASM330LHHXG1_GY_BATCHED_AT_6Hz5 = 11, 3128 } asm330lhhxg1_bdr_gy_t; 3129 int32_t asm330lhhxg1_fifo_gy_batch_set(const stmdev_ctx_t *ctx, 3130 asm330lhhxg1_bdr_gy_t val); 3131 int32_t asm330lhhxg1_fifo_gy_batch_get(const stmdev_ctx_t *ctx, 3132 asm330lhhxg1_bdr_gy_t *val); 3133 3134 typedef enum 3135 { 3136 ASM330LHHXG1_BYPASS_MODE = 0, 3137 ASM330LHHXG1_FIFO_MODE = 1, 3138 ASM330LHHXG1_STREAM_TO_FIFO_MODE = 3, 3139 ASM330LHHXG1_BYPASS_TO_STREAM_MODE = 4, 3140 ASM330LHHXG1_STREAM_MODE = 6, 3141 ASM330LHHXG1_BYPASS_TO_FIFO_MODE = 7, 3142 } asm330lhhxg1_fifo_mode_t; 3143 int32_t asm330lhhxg1_fifo_mode_set(const stmdev_ctx_t *ctx, asm330lhhxg1_fifo_mode_t val); 3144 int32_t asm330lhhxg1_fifo_mode_get(const stmdev_ctx_t *ctx, 3145 asm330lhhxg1_fifo_mode_t *val); 3146 3147 typedef enum 3148 { 3149 ASM330LHHXG1_TEMP_NOT_BATCHED = 0, 3150 ASM330LHHXG1_TEMP_BATCHED_AT_52Hz = 1, 3151 ASM330LHHXG1_TEMP_BATCHED_AT_12Hz5 = 2, 3152 ASM330LHHXG1_TEMP_BATCHED_AT_1Hz6 = 3, 3153 } asm330lhhxg1_odr_t_batch_t; 3154 int32_t asm330lhhxg1_fifo_temp_batch_set(const stmdev_ctx_t *ctx, 3155 asm330lhhxg1_odr_t_batch_t val); 3156 int32_t asm330lhhxg1_fifo_temp_batch_get(const stmdev_ctx_t *ctx, 3157 asm330lhhxg1_odr_t_batch_t *val); 3158 3159 typedef enum 3160 { 3161 ASM330LHHXG1_NO_DECIMATION = 0, 3162 ASM330LHHXG1_DEC_1 = 1, 3163 ASM330LHHXG1_DEC_8 = 2, 3164 ASM330LHHXG1_DEC_32 = 3, 3165 } asm330lhhxg1_dec_ts_batch_t; 3166 int32_t asm330lhhxg1_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, 3167 asm330lhhxg1_dec_ts_batch_t val); 3168 int32_t asm330lhhxg1_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, 3169 asm330lhhxg1_dec_ts_batch_t *val); 3170 3171 typedef enum 3172 { 3173 ASM330LHHXG1_XL_BATCH_EVENT = 0, 3174 ASM330LHHXG1_GYRO_BATCH_EVENT = 1, 3175 } asm330lhhxg1_trig_counter_bdr_t; 3176 int32_t asm330lhhxg1_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, 3177 asm330lhhxg1_trig_counter_bdr_t val); 3178 int32_t asm330lhhxg1_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, 3179 asm330lhhxg1_trig_counter_bdr_t *val); 3180 3181 int32_t asm330lhhxg1_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val); 3182 int32_t asm330lhhxg1_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val); 3183 3184 int32_t asm330lhhxg1_batch_counter_threshold_set(const stmdev_ctx_t *ctx, 3185 uint16_t val); 3186 int32_t asm330lhhxg1_batch_counter_threshold_get(const stmdev_ctx_t *ctx, 3187 uint16_t *val); 3188 3189 int32_t asm330lhhxg1_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); 3190 3191 int32_t asm330lhhxg1_fifo_status_get(const stmdev_ctx_t *ctx, 3192 asm330lhhxg1_fifo_status2_t *val); 3193 3194 int32_t asm330lhhxg1_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 3195 3196 int32_t asm330lhhxg1_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 3197 3198 int32_t asm330lhhxg1_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 3199 3200 typedef enum 3201 { 3202 ASM330LHHXG1_GYRO_NC_TAG = 0x01, 3203 ASM330LHHXG1_XL_NC_TAG = 0x02, 3204 ASM330LHHXG1_TEMPERATURE_TAG = 0x03, 3205 ASM330LHHXG1_TIMESTAMP_TAG = 0x04, 3206 ASM330LHHXG1_CFG_CHANGE_TAG = 0x05, 3207 ASM330LHHXG1_SENSORHUB_SLAVE0_TAG = 0x0E, 3208 ASM330LHHXG1_SENSORHUB_SLAVE1_TAG = 0x0F, 3209 ASM330LHHXG1_SENSORHUB_SLAVE2_TAG = 0x10, 3210 ASM330LHHXG1_SENSORHUB_SLAVE3_TAG = 0x11, 3211 ASM330LHHXG1_SENSORHUB_NACK_TAG = 0x19, 3212 } asm330lhhxg1_fifo_tag_t; 3213 int32_t asm330lhhxg1_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, 3214 asm330lhhxg1_fifo_tag_t *val); 3215 3216 int32_t asm330lhhxg1_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val); 3217 int32_t asm330lhhxg1_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, uint8_t *val); 3218 3219 int32_t asm330lhhxg1_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val); 3220 int32_t asm330lhhxg1_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, uint8_t *val); 3221 3222 int32_t asm330lhhxg1_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val); 3223 int32_t asm330lhhxg1_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, uint8_t *val); 3224 3225 int32_t asm330lhhxg1_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val); 3226 int32_t asm330lhhxg1_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, uint8_t *val); 3227 3228 typedef enum 3229 { 3230 ASM330LHHXG1_DEN_DISABLE = 0, 3231 ASM330LHHXG1_LEVEL_FIFO = 6, 3232 ASM330LHHXG1_LEVEL_LETCHED = 3, 3233 ASM330LHHXG1_LEVEL_TRIGGER = 2, 3234 ASM330LHHXG1_EDGE_TRIGGER = 4, 3235 } asm330lhhxg1_den_mode_t; 3236 int32_t asm330lhhxg1_den_mode_set(const stmdev_ctx_t *ctx, 3237 asm330lhhxg1_den_mode_t val); 3238 int32_t asm330lhhxg1_den_mode_get(const stmdev_ctx_t *ctx, 3239 asm330lhhxg1_den_mode_t *val); 3240 3241 typedef enum 3242 { 3243 ASM330LHHXG1_DEN_ACT_LOW = 0, 3244 ASM330LHHXG1_DEN_ACT_HIGH = 1, 3245 } asm330lhhxg1_den_lh_t; 3246 int32_t asm330lhhxg1_den_polarity_set(const stmdev_ctx_t *ctx, 3247 asm330lhhxg1_den_lh_t val); 3248 int32_t asm330lhhxg1_den_polarity_get(const stmdev_ctx_t *ctx, 3249 asm330lhhxg1_den_lh_t *val); 3250 3251 typedef enum 3252 { 3253 ASM330LHHXG1_STAMP_IN_GY_DATA = 0, 3254 ASM330LHHXG1_STAMP_IN_XL_DATA = 1, 3255 ASM330LHHXG1_STAMP_IN_GY_XL_DATA = 2, 3256 } asm330lhhxg1_den_xl_g_t; 3257 int32_t asm330lhhxg1_den_enable_set(const stmdev_ctx_t *ctx, 3258 asm330lhhxg1_den_xl_g_t val); 3259 int32_t asm330lhhxg1_den_enable_get(const stmdev_ctx_t *ctx, 3260 asm330lhhxg1_den_xl_g_t *val); 3261 3262 int32_t asm330lhhxg1_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val); 3263 int32_t asm330lhhxg1_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val); 3264 3265 int32_t asm330lhhxg1_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val); 3266 int32_t asm330lhhxg1_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val); 3267 3268 int32_t asm330lhhxg1_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val); 3269 int32_t asm330lhhxg1_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val); 3270 3271 int32_t asm330lhhxg1_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); 3272 int32_t asm330lhhxg1_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); 3273 3274 int32_t asm330lhhxg1_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); 3275 int32_t asm330lhhxg1_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); 3276 3277 int32_t asm330lhhxg1_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint16_t *val); 3278 int32_t asm330lhhxg1_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val); 3279 3280 typedef enum 3281 { 3282 ASM330LHHXG1_Z_EQ_Y = 0, 3283 ASM330LHHXG1_Z_EQ_MIN_Y = 1, 3284 ASM330LHHXG1_Z_EQ_X = 2, 3285 ASM330LHHXG1_Z_EQ_MIN_X = 3, 3286 ASM330LHHXG1_Z_EQ_MIN_Z = 4, 3287 ASM330LHHXG1_Z_EQ_Z = 5, 3288 } asm330lhhxg1_mag_z_axis_t; 3289 int32_t asm330lhhxg1_mag_z_orient_set(const stmdev_ctx_t *ctx, 3290 asm330lhhxg1_mag_z_axis_t val); 3291 int32_t asm330lhhxg1_mag_z_orient_get(const stmdev_ctx_t *ctx, 3292 asm330lhhxg1_mag_z_axis_t *val); 3293 3294 typedef enum 3295 { 3296 ASM330LHHXG1_Y_EQ_Y = 0, 3297 ASM330LHHXG1_Y_EQ_MIN_Y = 1, 3298 ASM330LHHXG1_Y_EQ_X = 2, 3299 ASM330LHHXG1_Y_EQ_MIN_X = 3, 3300 ASM330LHHXG1_Y_EQ_MIN_Z = 4, 3301 ASM330LHHXG1_Y_EQ_Z = 5, 3302 } asm330lhhxg1_mag_y_axis_t; 3303 int32_t asm330lhhxg1_mag_y_orient_set(const stmdev_ctx_t *ctx, 3304 asm330lhhxg1_mag_y_axis_t val); 3305 int32_t asm330lhhxg1_mag_y_orient_get(const stmdev_ctx_t *ctx, 3306 asm330lhhxg1_mag_y_axis_t *val); 3307 3308 typedef enum 3309 { 3310 ASM330LHHXG1_X_EQ_Y = 0, 3311 ASM330LHHXG1_X_EQ_MIN_Y = 1, 3312 ASM330LHHXG1_X_EQ_X = 2, 3313 ASM330LHHXG1_X_EQ_MIN_X = 3, 3314 ASM330LHHXG1_X_EQ_MIN_Z = 4, 3315 ASM330LHHXG1_X_EQ_Z = 5, 3316 } asm330lhhxg1_mag_x_axis_t; 3317 int32_t asm330lhhxg1_mag_x_orient_set(const stmdev_ctx_t *ctx, 3318 asm330lhhxg1_mag_x_axis_t val); 3319 int32_t asm330lhhxg1_mag_x_orient_get(const stmdev_ctx_t *ctx, 3320 asm330lhhxg1_mag_x_axis_t *val); 3321 3322 typedef struct 3323 { 3324 uint16_t fsm1 : 1; 3325 uint16_t fsm2 : 1; 3326 uint16_t fsm3 : 1; 3327 uint16_t fsm4 : 1; 3328 uint16_t fsm5 : 1; 3329 uint16_t fsm6 : 1; 3330 uint16_t fsm7 : 1; 3331 uint16_t fsm8 : 1; 3332 uint16_t fsm9 : 1; 3333 uint16_t fsm10 : 1; 3334 uint16_t fsm11 : 1; 3335 uint16_t fsm12 : 1; 3336 uint16_t fsm13 : 1; 3337 uint16_t fsm14 : 1; 3338 uint16_t fsm15 : 1; 3339 uint16_t fsm16 : 1; 3340 } asm330lhhxg1_fsm_status_t; 3341 int32_t asm330lhhxg1_fsm_status_get(const stmdev_ctx_t *ctx, 3342 asm330lhhxg1_fsm_status_t *val); 3343 int32_t asm330lhhxg1_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); 3344 3345 int32_t asm330lhhxg1_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, 3346 uint8_t *val); 3347 3348 int32_t asm330lhhxg1_emb_func_clk_dis_set(const stmdev_ctx_t *ctx, uint8_t val); 3349 int32_t asm330lhhxg1_emb_func_clk_dis_get(const stmdev_ctx_t *ctx, uint8_t *val); 3350 3351 int32_t asm330lhhxg1_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val); 3352 int32_t asm330lhhxg1_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val); 3353 3354 typedef struct 3355 { 3356 asm330lhhxg1_fsm_enable_a_t fsm_enable_a; 3357 asm330lhhxg1_fsm_enable_b_t fsm_enable_b; 3358 } asm330lhhxg1_emb_fsm_enable_t; 3359 int32_t asm330lhhxg1_fsm_enable_set(const stmdev_ctx_t *ctx, 3360 asm330lhhxg1_emb_fsm_enable_t *val); 3361 int32_t asm330lhhxg1_fsm_enable_get(const stmdev_ctx_t *ctx, 3362 asm330lhhxg1_emb_fsm_enable_t *val); 3363 3364 int32_t asm330lhhxg1_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); 3365 int32_t asm330lhhxg1_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); 3366 3367 typedef enum 3368 { 3369 ASM330LHHXG1_LC_NORMAL = 0, 3370 ASM330LHHXG1_LC_CLEAR = 1, 3371 ASM330LHHXG1_LC_CLEAR_DONE = 2, 3372 } asm330lhhxg1_fsm_lc_clr_t; 3373 int32_t asm330lhhxg1_long_clr_set(const stmdev_ctx_t *ctx, 3374 asm330lhhxg1_fsm_lc_clr_t val); 3375 int32_t asm330lhhxg1_long_clr_get(const stmdev_ctx_t *ctx, 3376 asm330lhhxg1_fsm_lc_clr_t *val); 3377 3378 typedef enum 3379 { 3380 ASM330LHHXG1_ODR_FSM_12Hz5 = 0, 3381 ASM330LHHXG1_ODR_FSM_26Hz = 1, 3382 ASM330LHHXG1_ODR_FSM_52Hz = 2, 3383 ASM330LHHXG1_ODR_FSM_104Hz = 3, 3384 } asm330lhhxg1_fsm_odr_t; 3385 int32_t asm330lhhxg1_fsm_data_rate_set(const stmdev_ctx_t *ctx, 3386 asm330lhhxg1_fsm_odr_t val); 3387 int32_t asm330lhhxg1_fsm_data_rate_get(const stmdev_ctx_t *ctx, 3388 asm330lhhxg1_fsm_odr_t *val); 3389 3390 int32_t asm330lhhxg1_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val); 3391 int32_t asm330lhhxg1_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val); 3392 3393 int32_t asm330lhhxg1_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val); 3394 int32_t asm330lhhxg1_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val); 3395 3396 int32_t asm330lhhxg1_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, 3397 uint8_t *buff); 3398 int32_t asm330lhhxg1_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, 3399 uint8_t *buff); 3400 3401 int32_t asm330lhhxg1_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); 3402 int32_t asm330lhhxg1_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); 3403 3404 int32_t asm330lhhxg1_mlc_set(const stmdev_ctx_t *ctx, uint8_t val); 3405 int32_t asm330lhhxg1_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val); 3406 3407 int32_t asm330lhhxg1_mlc_status_get(const stmdev_ctx_t *ctx, 3408 asm330lhhxg1_mlc_status_mainpage_t *val); 3409 3410 typedef enum 3411 { 3412 ASM330LHHXG1_ODR_PRGS_12Hz5 = 0, 3413 ASM330LHHXG1_ODR_PRGS_26Hz = 1, 3414 ASM330LHHXG1_ODR_PRGS_52Hz = 2, 3415 ASM330LHHXG1_ODR_PRGS_104Hz = 3, 3416 } asm330lhhxg1_mlc_odr_t; 3417 int32_t asm330lhhxg1_mlc_data_rate_set(const stmdev_ctx_t *ctx, 3418 asm330lhhxg1_mlc_odr_t val); 3419 int32_t asm330lhhxg1_mlc_data_rate_get(const stmdev_ctx_t *ctx, 3420 asm330lhhxg1_mlc_odr_t *val); 3421 3422 int32_t asm330lhhxg1_mlc_init_set(const stmdev_ctx_t *ctx, uint8_t val); 3423 int32_t asm330lhhxg1_mlc_init_get(const stmdev_ctx_t *ctx, uint8_t *val); 3424 3425 int32_t asm330lhhxg1_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); 3426 3427 int32_t asm330lhhxg1_mlc_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); 3428 int32_t asm330lhhxg1_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); 3429 3430 typedef struct 3431 { 3432 asm330lhhxg1_sensor_hub_1_t sh_byte_1; 3433 asm330lhhxg1_sensor_hub_2_t sh_byte_2; 3434 asm330lhhxg1_sensor_hub_3_t sh_byte_3; 3435 asm330lhhxg1_sensor_hub_4_t sh_byte_4; 3436 asm330lhhxg1_sensor_hub_5_t sh_byte_5; 3437 asm330lhhxg1_sensor_hub_6_t sh_byte_6; 3438 asm330lhhxg1_sensor_hub_7_t sh_byte_7; 3439 asm330lhhxg1_sensor_hub_8_t sh_byte_8; 3440 asm330lhhxg1_sensor_hub_9_t sh_byte_9; 3441 asm330lhhxg1_sensor_hub_10_t sh_byte_10; 3442 asm330lhhxg1_sensor_hub_11_t sh_byte_11; 3443 asm330lhhxg1_sensor_hub_12_t sh_byte_12; 3444 asm330lhhxg1_sensor_hub_13_t sh_byte_13; 3445 asm330lhhxg1_sensor_hub_14_t sh_byte_14; 3446 asm330lhhxg1_sensor_hub_15_t sh_byte_15; 3447 asm330lhhxg1_sensor_hub_16_t sh_byte_16; 3448 asm330lhhxg1_sensor_hub_17_t sh_byte_17; 3449 asm330lhhxg1_sensor_hub_18_t sh_byte_18; 3450 } asm330lhhxg1_emb_sh_read_t; 3451 int32_t asm330lhhxg1_sh_read_data_raw_get(const stmdev_ctx_t *ctx, 3452 asm330lhhxg1_emb_sh_read_t *val); 3453 3454 typedef enum 3455 { 3456 ASM330LHHXG1_SLV_0 = 0, 3457 ASM330LHHXG1_SLV_0_1 = 1, 3458 ASM330LHHXG1_SLV_0_1_2 = 2, 3459 ASM330LHHXG1_SLV_0_1_2_3 = 3, 3460 } asm330lhhxg1_aux_sens_on_t; 3461 int32_t asm330lhhxg1_sh_slave_connected_set(const stmdev_ctx_t *ctx, 3462 asm330lhhxg1_aux_sens_on_t val); 3463 int32_t asm330lhhxg1_sh_slave_connected_get(const stmdev_ctx_t *ctx, 3464 asm330lhhxg1_aux_sens_on_t *val); 3465 3466 int32_t asm330lhhxg1_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); 3467 int32_t asm330lhhxg1_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); 3468 3469 typedef enum 3470 { 3471 ASM330LHHXG1_EXT_PULL_UP = 0, 3472 ASM330LHHXG1_INTERNAL_PULL_UP = 1, 3473 } asm330lhhxg1_shub_pu_en_t; 3474 int32_t asm330lhhxg1_sh_pin_mode_set(const stmdev_ctx_t *ctx, 3475 asm330lhhxg1_shub_pu_en_t val); 3476 int32_t asm330lhhxg1_sh_pin_mode_get(const stmdev_ctx_t *ctx, 3477 asm330lhhxg1_shub_pu_en_t *val); 3478 3479 int32_t asm330lhhxg1_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val); 3480 int32_t asm330lhhxg1_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val); 3481 3482 typedef enum 3483 { 3484 ASM330LHHXG1_EXT_ON_INT2_PIN = 0, 3485 ASM330LHHXG1_XL_GY_DRDY = 1, 3486 } asm330lhhxg1_start_config_t; 3487 int32_t asm330lhhxg1_sh_syncro_mode_set(const stmdev_ctx_t *ctx, 3488 asm330lhhxg1_start_config_t val); 3489 int32_t asm330lhhxg1_sh_syncro_mode_get(const stmdev_ctx_t *ctx, 3490 asm330lhhxg1_start_config_t *val); 3491 3492 typedef enum 3493 { 3494 ASM330LHHXG1_EACH_SH_CYCLE = 0, 3495 ASM330LHHXG1_ONLY_FIRST_CYCLE = 1, 3496 } asm330lhhxg1_write_once_t; 3497 int32_t asm330lhhxg1_sh_write_mode_set(const stmdev_ctx_t *ctx, 3498 asm330lhhxg1_write_once_t val); 3499 int32_t asm330lhhxg1_sh_write_mode_get(const stmdev_ctx_t *ctx, 3500 asm330lhhxg1_write_once_t *val); 3501 3502 int32_t asm330lhhxg1_sh_reset_set(const stmdev_ctx_t *ctx); 3503 int32_t asm330lhhxg1_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 3504 3505 typedef enum 3506 { 3507 ASM330LHHXG1_SH_ODR_104Hz = 0, 3508 ASM330LHHXG1_SH_ODR_52Hz = 1, 3509 ASM330LHHXG1_SH_ODR_26Hz = 2, 3510 ASM330LHHXG1_SH_ODR_13Hz = 3, 3511 } asm330lhhxg1_shub_odr_t; 3512 int32_t asm330lhhxg1_sh_data_rate_set(const stmdev_ctx_t *ctx, 3513 asm330lhhxg1_shub_odr_t val); 3514 int32_t asm330lhhxg1_sh_data_rate_get(const stmdev_ctx_t *ctx, 3515 asm330lhhxg1_shub_odr_t *val); 3516 3517 typedef struct 3518 { 3519 uint8_t slv0_add; 3520 uint8_t slv0_subadd; 3521 uint8_t slv0_data; 3522 } asm330lhhxg1_sh_cfg_write_t; 3523 int32_t asm330lhhxg1_sh_cfg_write(const stmdev_ctx_t *ctx, 3524 asm330lhhxg1_sh_cfg_write_t *val); 3525 3526 typedef struct 3527 { 3528 uint8_t slv_add; 3529 uint8_t slv_subadd; 3530 uint8_t slv_len; 3531 } asm330lhhxg1_sh_cfg_read_t; 3532 int32_t asm330lhhxg1_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, 3533 asm330lhhxg1_sh_cfg_read_t *val); 3534 int32_t asm330lhhxg1_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, 3535 asm330lhhxg1_sh_cfg_read_t *val); 3536 int32_t asm330lhhxg1_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, 3537 asm330lhhxg1_sh_cfg_read_t *val); 3538 int32_t asm330lhhxg1_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, 3539 asm330lhhxg1_sh_cfg_read_t *val); 3540 3541 int32_t asm330lhhxg1_sh_status_get(const stmdev_ctx_t *ctx, 3542 asm330lhhxg1_status_master_t *val); 3543 3544 /** 3545 *@} 3546 * 3547 */ 3548 3549 #ifdef __cplusplus 3550 } 3551 #endif 3552 3553 #endif /* ASM330LHHXG1_REGS_H */ 3554 3555 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 3556
