1 /*
2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /***********************************************************************************************************************
8 * Includes <System Includes> , "Project Includes"
9 **********************************************************************************************************************/
10 #include <stdio.h>
11 #include "bsp_api.h"
12
13 #if (BSP_FEATURE_DDR_SUPPORTED)
14 #if (1 == BSP_CFG_DDR_INIT_ENABLE)
15 #include "bsp_ddr.h"
16 #include "bsp_ddr_fw_param.h"
17
18 #if (1 == BSP_CFG_BOARD_RZN2H_EVB)
19 #include "../../../../../board/rzn2h_evb/board_ddr_param.h"
20 #elif (1 == BSP_CFG_BOARD_CUSTOM)
21 #include "../../../../../board/custom/board_ddr_param.h"
22 #endif
23
24 /***********************************************************************************************************************
25 * Typedef definitions
26 **********************************************************************************************************************/
27 #define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
28
29 /***********************************************************************************************************************
30 * Exported global variables (to be accessed by other files)
31 **********************************************************************************************************************/
32
33 /***********************************************************************************************************************
34 * Private global variables and functions
35 **********************************************************************************************************************/
36 static void bsp_prv_ddr_reg_init(void);
37 static void bsp_prv_ddr_phyinit_c(void);
38 static void bsp_prv_ddr_phyinit_d2h_1d(void);
39 static void bsp_prv_ddr_phyinit_d2h_2d(void);
40 static void bsp_prv_ddr_phyinit_mc(void);
41 static void bsp_prv_ddr_phyinit_i(void);
42 static void bsp_prv_ddr_phyinit_j(void);
43
44 #if (1 == BSP_CFG_DDR_ZERO_INITIALIZED_ENABLE)
45 static void bsp_prv_ddr_prog_all0(uint64_t start_addr, uint32_t addr_space);
46
47 #endif
48
49 static int8_t bsp_prv_dwc_ddrphy_cdd_int(uint8_t val);
50 static int8_t bsp_prv_dwc_ddrphy_cdd_abs(uint8_t val);
51
52 static uint32_t bsp_get_mail(uint8_t mode_32bits);
53 static void bsp_prv_dwc_ddrphy_phyinit_userCustom_G_waitDone(uint8_t sel_train);
54 static void bsp_prv_ddr_setup_mc(void);
55 static void bsp_prv_ddr_update_mc(void);
56
57 static void bsp_prv_ddr_phyinit_configuration(void);
58 static void bsp_prv_ddr_phyinit_pin_swizzling(void);
59 static void bsp_prv_ddr_phyinit_load_1d_image(void);
60 static void bsp_prv_ddr_phyinit_exec_1d_image(void);
61 static void bsp_prv_ddr_phyinit_load_2d_image(void);
62 static void bsp_prv_ddr_phyinit_exec_2d_image(void);
63 static void bsp_prv_ddr_phyinit_load_eng_image(void);
64
65 const uint32_t param_phyinit_c_size = ARRAY_SIZE(param_phyinit_c);
66 const uint32_t param_phyinit_i_size = ARRAY_SIZE(param_phyinit_i);
67 const uint32_t param_phyinit_f_1d_0_size = ARRAY_SIZE(param_phyinit_f_1d_0);
68 const uint32_t param_phyinit_f_2d_0_size = ARRAY_SIZE(param_phyinit_f_2d_0);
69 const uint32_t param_phyinit_swizzle_size = ARRAY_SIZE(param_phyinit_swizzle);
70 const uint32_t param_mcinit_size = ARRAY_SIZE(param_mcinit);
71
72 /*******************************************************************************************************************//**
73 * Executes bsp_prv_ddr_reg_init
74 **********************************************************************************************************************/
bsp_prv_ddr_reg_init(void)75 static void bsp_prv_ddr_reg_init (void)
76 {
77 R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
78
79 R_BSP_MODULE_START(FSP_IP_DDRSS, 0);
80
81 R_BSP_ModuleResetDisable(BSP_MODULE_RESET_DDRSS_RST_N);
82 R_BSP_ModuleResetDisable(BSP_MODULE_RESET_DDRSS_RST_PWROKLN);
83 R_BSP_ModuleResetDisable(BSP_MODULE_RESET_DDRSS_RESET);
84 R_BSP_ModuleResetDisable(BSP_MODULE_RESET_DDRSS_AXI0_ARESETN);
85 R_BSP_ModuleResetDisable(BSP_MODULE_RESET_DDRSS_AXI1_ARESETN);
86 R_BSP_ModuleResetDisable(BSP_MODULE_RESET_DDRSS_AXI2_ARESETN);
87 R_BSP_ModuleResetDisable(BSP_MODULE_RESET_DDRSS_AXI3_ARESETN);
88 R_BSP_ModuleResetDisable(BSP_MODULE_RESET_DDRSS_AXI4_ARESETN);
89 R_BSP_ModuleResetDisable(BSP_MODULE_RESET_DDRSS_MC_PRESETN);
90 R_BSP_ModuleResetDisable(BSP_MODULE_RESET_DDRSS_PHY_PRESETN);
91
92 R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
93 }
94
95 /*******************************************************************************************************************//**
96 * Executes bsp_ddr_init
97 **********************************************************************************************************************/
bsp_ddr_init(void)98 void bsp_ddr_init (void)
99 {
100 R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SYSTEM);
101
102 R_BSP_SlaveStopRelease(BSP_BUS_SLAVE_DDRSS_A0_IF);
103 R_BSP_SlaveStopRelease(BSP_BUS_SLAVE_DDRSS_A1_IF);
104 R_BSP_SlaveStopRelease(BSP_BUS_SLAVE_DDRSS_R2_IF);
105 R_BSP_SlaveStopRelease(BSP_BUS_SLAVE_DDRSS_R3_IF);
106 R_BSP_SlaveStopRelease(BSP_BUS_SLAVE_DDRSS_A4_IF);
107 R_SSC->SSTPCR4_b.DDRAPB = 0;
108
109 R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SYSTEM);
110
111 bsp_prv_ddr_reg_init();
112
113 bsp_prv_ddr_setup_mc();
114
115 bsp_prv_ddr_phyinit_c();
116 bsp_prv_ddr_phyinit_d2h_1d();
117 bsp_prv_ddr_phyinit_d2h_2d();
118
119 bsp_prv_ddr_phyinit_mc();
120
121 bsp_prv_ddr_phyinit_i();
122 bsp_prv_ddr_phyinit_j();
123
124 #if (1 == BSP_CFG_DDR_ZERO_INITIALIZED_ENABLE)
125 uint32_t val;
126 uint32_t addr_space, end_addr17;
127
128 val = R_DDRSS->DDR_MEMC_DENALI_CTL_312_b.CS_MAP;
129 if (val == 0x01)
130 {
131 end_addr17 = R_DDRSS->DDR_MEMC_DENALI_CTL_304_b.CS_VAL_UPPER_0;
132 }
133 else
134 {
135 end_addr17 = R_DDRSS->DDR_MEMC_DENALI_CTL_306_b.CS_VAL_UPPER_1;
136 }
137
138 if (end_addr17 == 0xdfff)
139 {
140 addr_space = 33;
141 }
142 else if (end_addr17 == 0x6fff)
143 {
144 addr_space = 32;
145 }
146 else if (end_addr17 == 0x37ff)
147 {
148 addr_space = 31;
149 }
150 else if (end_addr17 == 0x1bff)
151 {
152 addr_space = 30;
153 }
154 else if (end_addr17 == 0x0dff)
155 {
156 addr_space = 29;
157 }
158 else
159 {
160 addr_space = 33;
161 }
162 bsp_prv_ddr_prog_all0(BPS_DDR_BASE_ADDR, addr_space);
163 #endif
164
165 bsp_prv_ddr_update_mc();
166 }
167
168 /*******************************************************************************************************************//**
169 * Executes bsp_prv_ddr_phyinit_c
170 **********************************************************************************************************************/
bsp_prv_ddr_phyinit_c(void)171 static void bsp_prv_ddr_phyinit_c (void)
172 {
173 bsp_prv_ddr_phyinit_configuration();
174 bsp_prv_ddr_phyinit_pin_swizzling();
175 }
176
177 /*******************************************************************************************************************//**
178 * Executes bsp_prv_ddr_phyinit_d2h_1d
179 **********************************************************************************************************************/
bsp_prv_ddr_phyinit_d2h_1d(void)180 static void bsp_prv_ddr_phyinit_d2h_1d (void)
181 {
182 bsp_prv_ddr_phyinit_load_1d_image();
183 bsp_prv_ddr_phyinit_exec_1d_image();
184 }
185
186 /*******************************************************************************************************************//**
187 * Executes bsp_prv_ddr_phyinit_d2h_2d
188 **********************************************************************************************************************/
bsp_prv_ddr_phyinit_d2h_2d(void)189 static void bsp_prv_ddr_phyinit_d2h_2d (void)
190 {
191 bsp_prv_ddr_phyinit_load_2d_image();
192 bsp_prv_ddr_phyinit_exec_2d_image();
193 }
194
195 /*******************************************************************************************************************//**
196 * Executes bsp_prv_ddr_phyinit_i
197 **********************************************************************************************************************/
bsp_prv_ddr_phyinit_i(void)198 static void bsp_prv_ddr_phyinit_i (void)
199 {
200 bsp_prv_ddr_phyinit_load_eng_image();
201 }
202
203 /*******************************************************************************************************************//**
204 * Executes bsp_prv_ddr_phyinit_j
205 **********************************************************************************************************************/
bsp_prv_ddr_phyinit_j(void)206 static void bsp_prv_ddr_phyinit_j (void)
207 {
208 R_DDRSS->DDR_MEMC_DENALI_CTL_00_b.start = 1;
209 FSP_HARDWARE_REGISTER_WAIT((R_DDRSS->DDR_MEMC_DENALI_CTL_335_b.INT_STATUS_INIT & 0x02), 0x02);
210 }
211
212 /*******************************************************************************************************************//**
213 * Executes bsp_prv_ddr_phyinit_mc
214 **********************************************************************************************************************/
bsp_prv_ddr_phyinit_mc(void)215 static void bsp_prv_ddr_phyinit_mc (void)
216 {
217 uint32_t val, num_rank, num_byte, tctrl_delay, bl, x, tx_dqs_dly;
218
219 bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x0);
220
221 val = R_DDRSS->DDR_MEMC_DENALI_CTL_312_b.CS_MAP;
222 num_rank = (val == 3) ? 2 : 1;
223
224 val = R_DDRSS->DDR_MEMC_DENALI_CTL_313_b.MEM_DP_REDUCTION;
225
226 num_byte = (val == 1) ? 2 : 4;
227 val = bsp_dwc_ddrphy_apb_rd(0x02002e);
228 tctrl_delay = ((val >> 1) + (val & 1)) + 8;
229
230 val = R_DDRSS->DDR_MEMC_DENALI_CTL_64_b.BSTLEN;
231 bl = (1 << val);
232
233 x = 0;
234 if (num_byte > 0)
235 {
236 val = bsp_dwc_ddrphy_apb_rd(0x010020);
237 x = (val > x) ? val : x;
238 }
239
240 if (num_byte > 1)
241 {
242 val = bsp_dwc_ddrphy_apb_rd(0x011020);
243 x = (val > x) ? val : x;
244 }
245
246 if (num_byte > 2)
247 {
248 val = bsp_dwc_ddrphy_apb_rd(0x012020); x = (val > x) ? val : x;
249 }
250
251 if (num_byte > 3)
252 {
253 val = bsp_dwc_ddrphy_apb_rd(0x013020); x = (val > x) ? val : x;
254 }
255
256 val = 16 + tctrl_delay + (2 * x);
257 R_DDRSS->DDR_MEMC_DENALI_CTL_732_b.TDFI_PHY_RDLAT_F0 = (val & 0x7F);
258
259 x = 0;
260 if ((num_rank > 0) && (num_byte > 0))
261 {
262 val = bsp_dwc_ddrphy_apb_rd(0x0100d0);
263 x = (val > x) ? val : x;
264 val = bsp_dwc_ddrphy_apb_rd(0x0101d0);
265 x = (val > x) ? val : x;
266 }
267
268 if ((num_rank > 0) && (num_byte > 1))
269 {
270 val = bsp_dwc_ddrphy_apb_rd(0x0110d0);
271 x = (val > x) ? val : x;
272 val = bsp_dwc_ddrphy_apb_rd(0x0111d0);
273 x = (val > x) ? val : x;
274 }
275
276 if ((num_rank > 0) && (num_byte > 2))
277 {
278 val = bsp_dwc_ddrphy_apb_rd(0x0120d0);
279 x = (val > x) ? val : x;
280 val = bsp_dwc_ddrphy_apb_rd(0x0121d0);
281 x = (val > x) ? val : x;
282 }
283
284 if ((num_rank > 0) && (num_byte > 3))
285 {
286 val = bsp_dwc_ddrphy_apb_rd(0x0130d0);
287 x = (val > x) ? val : x;
288 val = bsp_dwc_ddrphy_apb_rd(0x0131d0);
289 x = (val > x) ? val : x;
290 }
291
292 if ((num_rank > 1) && (num_byte > 0))
293 {
294 val = bsp_dwc_ddrphy_apb_rd(0x0100d1);
295 x = (val > x) ? val : x;
296 val = bsp_dwc_ddrphy_apb_rd(0x0101d1);
297 x = (val > x) ? val : x;
298 }
299
300 if ((num_rank > 1) && (num_byte > 1))
301 {
302 val = bsp_dwc_ddrphy_apb_rd(0x0110d1);
303 x = (val > x) ? val : x;
304 val = bsp_dwc_ddrphy_apb_rd(0x0111d1);
305 x = (val > x) ? val : x;
306 }
307
308 if ((num_rank > 1) && (num_byte > 2))
309 {
310 val = bsp_dwc_ddrphy_apb_rd(0x0120d1);
311 x = (val > x) ? val : x;
312 val = bsp_dwc_ddrphy_apb_rd(0x0121d1);
313 x = (val > x) ? val : x;
314 }
315
316 if ((num_rank > 1) && (num_byte > 3))
317 {
318 val = bsp_dwc_ddrphy_apb_rd(0x0130d1);
319 x = (val > x) ? val : x;
320 val = bsp_dwc_ddrphy_apb_rd(0x0131d1);
321 x = (val > x) ? val : x;
322 }
323
324 tx_dqs_dly = ((x >> 6) & 0xf) + (((x >> 4) & 0x01) + ((x >> 3) & 0x1));
325 val = tctrl_delay + (6 + (bl / 2)) + tx_dqs_dly;
326 R_DDRSS->DDR_MEMC_DENALI_CTL_761_b.TDFI_WRDATA = (val & 0xff);
327
328 bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x1);
329 }
330
331 #if (1 == BSP_CFG_DDR_ZERO_INITIALIZED_ENABLE)
332
333 /*******************************************************************************************************************//**
334 * Executes bsp_prv_ddr_prog_all0
335 *
336 * @param[in] start_addr First argument
337 * @param[in] addr_space Second argument
338 **********************************************************************************************************************/
bsp_prv_ddr_prog_all0(uint64_t start_addr,uint32_t addr_space)339 static void bsp_prv_ddr_prog_all0 (uint64_t start_addr, uint32_t addr_space)
340 {
341 uint32_t bak_lp_auto_entry_en;
342
343 R_DDRSS->DDR_MEMC_DENALI_CTL_232_b.ECC_DISABLE_W_UC_ERR = 1;
344
345 bak_lp_auto_entry_en = R_DDRSS->DDR_MEMC_DENALI_CTL_160_b.LP_AUTO_ENTRY_EN;
346
347 R_DDRSS->DDR_MEMC_DENALI_CTL_160_b.LP_AUTO_ENTRY_EN = 0x0;
348
349 R_DDRSS->DDR_MEMC_DENALI_CTL_221_b.BIST_START_ADDRESS = (start_addr & 0xffffffff);
350 R_DDRSS->DDR_MEMC_DENALI_CTL_222_b.BIST_START_ADDRESS32 = ((start_addr >> 32) & 0x00000001);
351 R_DDRSS->DDR_MEMC_DENALI_CTL_219_b.ADDR_SPACE = (addr_space & 0x3F);
352 R_DDRSS->DDR_MEMC_DENALI_CTL_220_b.BIST_DATA_CHECK = 1;
353 R_DDRSS->DDR_MEMC_DENALI_CTL_225_b.BIST_TEST_MODE = 0b100;
354 R_DDRSS->DDR_MEMC_DENALI_CTL_226_b.BIST_DATA_PATTERN0 = 0x00000000;
355 R_DDRSS->DDR_MEMC_DENALI_CTL_227_b.BIST_DATA_PATTERN1 = 0x00000000;
356 R_DDRSS->DDR_MEMC_DENALI_CTL_228_b.BIST_DATA_PATTERN2 = 0x00000000;
357 R_DDRSS->DDR_MEMC_DENALI_CTL_229_b.BIST_DATA_PATTERN3 = 0x00000000;
358
359 R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MICROSECONDS);
360
361 R_DDRSS->DDR_MEMC_DENALI_CTL_219_b.BIST_GO = 1;
362 FSP_HARDWARE_REGISTER_WAIT((R_DDRSS->DDR_MEMC_DENALI_CTL_334_b.INT_STATUS_BIST & 0x01), 0x01);
363
364 R_DDRSS->DDR_MEMC_DENALI_CTL_219_b.BIST_GO = 0;
365 R_DDRSS->DDR_MEMC_DENALI_CTL_343_b.INT_ACK_BIST = 1;
366 R_DDRSS->DDR_MEMC_DENALI_CTL_338_b.INT_ACK_ECC = 0x000001CF;
367
368 FSP_HARDWARE_REGISTER_WAIT(R_DDRSS->DDR_MEMC_DENALI_CTL_334_b.INT_STATUS_BIST, 0);
369 FSP_HARDWARE_REGISTER_WAIT(R_DDRSS->DDR_MEMC_DENALI_CTL_329_b.INT_STATUS_ECC, 0);
370
371 R_DDRSS->DDR_MEMC_DENALI_CTL_160_b.LP_AUTO_ENTRY_EN = (bak_lp_auto_entry_en & 0xf);
372 R_DDRSS->DDR_MEMC_DENALI_CTL_232_b.ECC_DISABLE_W_UC_ERR = 0;
373
374 R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MICROSECONDS);
375 }
376
377 #endif
378
379 /*******************************************************************************************************************//**
380 * Executes bsp_prv_dwc_ddrphy_phyinit_userCustom_G_waitDone
381 *
382 * @param[in] sel_train First argument
383 **********************************************************************************************************************/
bsp_prv_dwc_ddrphy_phyinit_userCustom_G_waitDone(uint8_t sel_train)384 void bsp_prv_dwc_ddrphy_phyinit_userCustom_G_waitDone (uint8_t sel_train)
385 {
386 volatile uint32_t train_done = 0;
387 volatile uint32_t mail = 0;
388 volatile uint32_t data = 0;
389
390 while (train_done == 0)
391 {
392 data = bsp_dwc_ddrphy_apb_rd(0x0d0004);
393
394 if ((data & 0x1) == 0)
395 {
396 mail = bsp_get_mail(0);
397 if ((mail == 0xff) || (mail == 0x07))
398 {
399 train_done = 1;
400 }
401 }
402 }
403
404 FSP_PARAMETER_NOT_USED(sel_train);
405 }
406
407 /*******************************************************************************************************************//**
408 * Executes bsp_get_mail
409 *
410 * @param[in] mode_32bits First argument
411 *
412 * @retval Returns the value of uint32_t
413 **********************************************************************************************************************/
bsp_get_mail(uint8_t mode_32bits)414 uint32_t bsp_get_mail (uint8_t mode_32bits)
415 {
416 uint32_t mail = 0;
417
418 while ((bsp_dwc_ddrphy_apb_rd(0x0d0004) & 0x1) != 0)
419 {
420 ;
421 }
422
423 mail = bsp_dwc_ddrphy_apb_rd(0x0d0032);
424
425 if (mode_32bits != 0)
426 {
427 mail = (bsp_dwc_ddrphy_apb_rd(0x0d0034) << 16) | mail;
428 }
429
430 bsp_dwc_ddrphy_apb_wr(0x0d0031, 0x0000);
431
432 while ((bsp_dwc_ddrphy_apb_rd(0x0d0004) & 0x1) == 0)
433 {
434 ;
435 }
436
437 bsp_dwc_ddrphy_apb_wr(0x0d0031, 0x0001);
438
439 return mail;
440 }
441
442 /*******************************************************************************************************************//**
443 * Executes bsp_prv_dwc_ddrphy_cdd_int
444 *
445 * @param[in] val First argument
446 *
447 * @return Returns the value of uint8_t
448 **********************************************************************************************************************/
bsp_prv_dwc_ddrphy_cdd_int(uint8_t val)449 static int8_t bsp_prv_dwc_ddrphy_cdd_int (uint8_t val)
450 {
451 return (int8_t) ((((val >> 7) & 0x1) == 1) ? -((0x7f ^ ((val >> 0) & 0x7f)) + 1) : ((val >> 0) & 0x7f));
452 }
453
454 /*******************************************************************************************************************//**
455 * Executes bsp_prv_dwc_ddrphy_cdd_abs
456 *
457 * @param[in] val First argument
458 *
459 * @return Returns the value of uint8_t
460 **********************************************************************************************************************/
bsp_prv_dwc_ddrphy_cdd_abs(uint8_t val)461 static int8_t bsp_prv_dwc_ddrphy_cdd_abs (uint8_t val)
462 {
463 return (uint8_t) ((((val >> 7) & 0x1) == 1) ? ((0x7f ^ ((val >> 0) & 0x7f)) + 1) : ((val >> 0) & 0x7f));
464 }
465
466 /*******************************************************************************************************************//**
467 * Executes bsp_prv_ddr_setup_mc
468 **********************************************************************************************************************/
bsp_prv_ddr_setup_mc(void)469 void bsp_prv_ddr_setup_mc (void)
470 {
471 uint32_t i;
472
473 for (i = 0; i < param_mcinit_size; i++)
474 {
475 bsp_ddrtop_mc_apb_wr(param_mcinit[i][0], param_mcinit[i][1]);
476 }
477 }
478
479 /*******************************************************************************************************************//**
480 * Executes bsp_prv_ddr_phyinit_configuration
481 **********************************************************************************************************************/
bsp_prv_ddr_phyinit_configuration(void)482 static void bsp_prv_ddr_phyinit_configuration (void)
483 {
484 uint32_t i;
485
486 for (i = 0; i < param_phyinit_c_size; i++)
487 {
488 bsp_dwc_ddrphy_apb_wr(param_phyinit_c[i][0], param_phyinit_c[i][1]);
489 }
490 }
491
492 /*******************************************************************************************************************//**
493 * Executes bsp_prv_ddr_phyinit_pin_swizzling
494 **********************************************************************************************************************/
bsp_prv_ddr_phyinit_pin_swizzling(void)495 static void bsp_prv_ddr_phyinit_pin_swizzling (void)
496 {
497 uint32_t i;
498
499 for (i = 0; i < param_phyinit_swizzle_size; i++)
500 {
501 bsp_dwc_ddrphy_apb_wr(param_phyinit_swizzle[i][0], param_phyinit_swizzle[i][1]);
502 }
503 }
504
505 /*******************************************************************************************************************//**
506 * Executes bsp_prv_ddr_phyinit_load_1d_image
507 **********************************************************************************************************************/
bsp_prv_ddr_phyinit_load_1d_image(void)508 static void bsp_prv_ddr_phyinit_load_1d_image (void)
509 {
510 uint32_t i;
511
512 bsp_dwc_ddrphy_apb_wr(0x020060, 0x2);
513 bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x0);
514
515 for (i = 0x0; i <= 0x3fff; i++)
516 {
517 bsp_dwc_ddrphy_apb_wr((uint32_t) (0x50000 + i), (uint32_t) (phyinit_fw_1d[i]));
518 }
519
520 bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x1);
521
522 for (i = 0; i < param_phyinit_f_1d_0_size; i++)
523 {
524 bsp_dwc_ddrphy_apb_wr(param_phyinit_f_1d_0[i][0], param_phyinit_f_1d_0[i][1]);
525 }
526 }
527
528 /*******************************************************************************************************************//**
529 * Executes bsp_prv_ddr_phyinit_exec_1d_image
530 **********************************************************************************************************************/
bsp_prv_ddr_phyinit_exec_1d_image(void)531 static void bsp_prv_ddr_phyinit_exec_1d_image (void)
532 {
533 uint8_t sel_train;
534 uint32_t val;
535
536 bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x0);
537 val = bsp_dwc_ddrphy_apb_rd(0x01005f);
538 sel_train = ((val & 0x700) == 0x100) ? 0 : 2;
539 bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x1);
540
541 bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x1);
542 bsp_dwc_ddrphy_apb_wr(0x0d0099, 0x9);
543 bsp_dwc_ddrphy_apb_wr(0x0d0099, 0x1);
544 bsp_dwc_ddrphy_apb_wr(0x0d0099, 0x0);
545 bsp_prv_dwc_ddrphy_phyinit_userCustom_G_waitDone(sel_train);
546 bsp_dwc_ddrphy_apb_wr(0x0d0099, 0x1);
547
548 bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x0);
549
550 uint32_t num_rank;
551 val = R_DDRSS->DDR_MEMC_DENALI_CTL_312_b.CS_MAP;
552 num_rank = (val == 3) ? 2 : 1;
553
554 int8_t val0;
555 int8_t val1;
556 int8_t cdd_rr;
557 int8_t cdd_rw_abs;
558 int8_t cdd_ww;
559 int8_t cdd_ww_abs;
560
561 if (num_rank > 1)
562 {
563 val = bsp_dwc_ddrphy_apb_rd(0x54013);
564 val0 = bsp_prv_dwc_ddrphy_cdd_int((val >> 0) & 0xff);
565 val1 = bsp_prv_dwc_ddrphy_cdd_int((val >> 8) & 0xff);
566 cdd_rr = val0;
567 cdd_rr = (val1 > cdd_rr) ? val1 : cdd_rr;
568
569 val = bsp_dwc_ddrphy_apb_rd(0x54014);
570 val0 = bsp_prv_dwc_ddrphy_cdd_abs((val >> 0) & 0xff);
571 val1 = bsp_prv_dwc_ddrphy_cdd_abs((val >> 8) & 0xff);
572 cdd_rw_abs = val0;
573 cdd_rw_abs = (val1 > cdd_rw_abs) ? val1 : cdd_rw_abs;
574
575 val = bsp_dwc_ddrphy_apb_rd(0x54015);
576 val0 = bsp_prv_dwc_ddrphy_cdd_abs((val >> 0) & 0xff);
577 val1 = bsp_prv_dwc_ddrphy_cdd_abs((val >> 8) & 0xff);
578 cdd_rw_abs = (val0 > cdd_rw_abs) ? val0 : cdd_rw_abs;
579 cdd_rw_abs = (val1 > cdd_rw_abs) ? val1 : cdd_rw_abs;
580
581 val = bsp_dwc_ddrphy_apb_rd(0x54018);
582 val0 = bsp_prv_dwc_ddrphy_cdd_int((val >> 0) & 0xff);
583 val1 = bsp_prv_dwc_ddrphy_cdd_int((val >> 8) & 0xff);
584 cdd_ww = val0;
585 cdd_ww = (val1 > cdd_ww) ? val1 : cdd_ww;
586 val0 = bsp_prv_dwc_ddrphy_cdd_abs((val >> 0) & 0xff);
587 val1 = bsp_prv_dwc_ddrphy_cdd_abs((val >> 8) & 0xff);
588 cdd_ww_abs = val0;
589 cdd_ww_abs = (val1 > cdd_ww_abs) ? val1 : cdd_ww_abs;
590
591 val = bsp_dwc_ddrphy_apb_rd(0x5402c);
592 val1 = bsp_prv_dwc_ddrphy_cdd_int((val >> 8) & 0xff);
593 cdd_rr = (val1 > cdd_rr) ? val1 : cdd_rr;
594
595 val = bsp_dwc_ddrphy_apb_rd(0x5402d);
596 val0 = bsp_prv_dwc_ddrphy_cdd_int((val >> 0) & 0xff);
597 cdd_rr = (val0 > cdd_rr) ? val0 : cdd_rr;
598 val1 = bsp_prv_dwc_ddrphy_cdd_abs((val >> 8) & 0xff);
599 cdd_rw_abs = (val1 > cdd_rw_abs) ? val1 : cdd_rw_abs;
600
601 val = bsp_dwc_ddrphy_apb_rd(0x5402e);
602 val0 = bsp_prv_dwc_ddrphy_cdd_abs((val >> 0) & 0xff);
603 val1 = bsp_prv_dwc_ddrphy_cdd_abs((val >> 8) & 0xff);
604 cdd_rw_abs = (val0 > cdd_rw_abs) ? val0 : cdd_rw_abs;
605 cdd_rw_abs = (val1 > cdd_rw_abs) ? val1 : cdd_rw_abs;
606
607 val = bsp_dwc_ddrphy_apb_rd(0x5402f);
608 val0 = bsp_prv_dwc_ddrphy_cdd_abs((val >> 0) & 0xff);
609 cdd_rw_abs = (val0 > cdd_rw_abs) ? val0 : cdd_rw_abs;
610
611 val = bsp_dwc_ddrphy_apb_rd(0x54031);
612 val1 = bsp_prv_dwc_ddrphy_cdd_int((val >> 8) & 0xff);
613 cdd_ww = (val1 > cdd_ww) ? val1 : cdd_ww;
614 val1 = bsp_prv_dwc_ddrphy_cdd_abs((val >> 8) & 0xff);
615 cdd_ww_abs = (val1 > cdd_ww_abs) ? val1 : cdd_ww_abs;
616
617 val = bsp_dwc_ddrphy_apb_rd(0x54032);
618 val0 = bsp_prv_dwc_ddrphy_cdd_int((val >> 0) & 0xff);
619 cdd_ww = (val0 > cdd_ww) ? val0 : cdd_ww;
620 val0 = bsp_prv_dwc_ddrphy_cdd_abs((val >> 0) & 0xff);
621 cdd_ww_abs = (val0 > cdd_ww_abs) ? val0 : cdd_ww_abs;
622
623 if (cdd_rr > 0)
624 {
625 val = R_DDRSS->DDR_MEMC_DENALI_CTL_376_b.R2R_DIFFCS_DLY_F0;
626 val += (uint32_t) ((uint8_t) cdd_rr);
627 R_DDRSS->DDR_MEMC_DENALI_CTL_376_b.R2R_DIFFCS_DLY_F0 = (val & 0x1F);
628 }
629
630 if (cdd_ww > 0)
631 {
632 val = R_DDRSS->DDR_MEMC_DENALI_CTL_377_b.W2W_DIFFCS_DLY_F0;
633 val += (uint32_t) ((uint8_t) cdd_ww);
634 R_DDRSS->DDR_MEMC_DENALI_CTL_377_b.W2W_DIFFCS_DLY_F0 = (val & 0x1F);
635 }
636
637 val = R_DDRSS->DDR_MEMC_DENALI_CTL_376_b.R2W_DIFFCS_DLY_F0;
638 val += (uint32_t) ((uint8_t) cdd_rw_abs);
639 R_DDRSS->DDR_MEMC_DENALI_CTL_376_b.R2W_DIFFCS_DLY_F0 = (val & 0x1F);
640
641 val = R_DDRSS->DDR_MEMC_DENALI_CTL_377_b.W2R_DIFFCS_DLY_F0;
642 val += (uint32_t) ((uint8_t) cdd_ww_abs);
643 R_DDRSS->DDR_MEMC_DENALI_CTL_377_b.W2R_DIFFCS_DLY_F0 = (val & 0x1F);
644 }
645
646 bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x1);
647 }
648
649 /*******************************************************************************************************************//**
650 * Executes bsp_prv_ddr_phyinit_load_2d_image
651 **********************************************************************************************************************/
bsp_prv_ddr_phyinit_load_2d_image(void)652 void bsp_prv_ddr_phyinit_load_2d_image (void)
653 {
654 uint32_t i;
655
656 bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x0);
657 for (i = 0x0; i <= 0x3fff; i++)
658 {
659 bsp_dwc_ddrphy_apb_wr((uint32_t) (0x50000 + i), (uint32_t) (phyinit_fw_2d[i]));
660 }
661
662 bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x1);
663
664 for (i = 0; i < param_phyinit_f_2d_0_size; i++)
665 {
666 bsp_dwc_ddrphy_apb_wr(param_phyinit_f_2d_0[i][0], param_phyinit_f_2d_0[i][1]);
667 }
668 }
669
670 /*******************************************************************************************************************//**
671 * Executes bsp_prv_ddr_phyinit_exec_2d_image
672 **********************************************************************************************************************/
bsp_prv_ddr_phyinit_exec_2d_image(void)673 void bsp_prv_ddr_phyinit_exec_2d_image (void)
674 {
675 uint8_t sel_train;
676 uint32_t val;
677
678 bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x0);
679 val = bsp_dwc_ddrphy_apb_rd(0x01005f);
680 sel_train = ((val & 0x700) == 0x100) ? 1 : 3;
681 bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x1);
682 bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x1);
683 bsp_dwc_ddrphy_apb_wr(0x0d0099, 0x9);
684 bsp_dwc_ddrphy_apb_wr(0x0d0099, 0x1);
685 bsp_dwc_ddrphy_apb_wr(0x0d0099, 0x0);
686 bsp_prv_dwc_ddrphy_phyinit_userCustom_G_waitDone(sel_train);
687 bsp_dwc_ddrphy_apb_wr(0x0d0099, 0x1);
688
689 bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x0);
690 bsp_dwc_ddrphy_apb_wr(0x0d0000, 0x1);
691 }
692
693 /*******************************************************************************************************************//**
694 * Executes bsp_prv_ddr_phyinit_load_eng_image
695 **********************************************************************************************************************/
bsp_prv_ddr_phyinit_load_eng_image(void)696 void bsp_prv_ddr_phyinit_load_eng_image (void)
697 {
698 uint32_t i;
699
700 for (i = 0; i < param_phyinit_i_size; i++)
701 {
702 bsp_dwc_ddrphy_apb_wr(param_phyinit_i[i][0], param_phyinit_i[i][1]);
703 }
704 }
705
706 /*******************************************************************************************************************//**
707 * Executes bsp_prv_ddr_update_mc
708 **********************************************************************************************************************/
bsp_prv_ddr_update_mc(void)709 void bsp_prv_ddr_update_mc (void)
710 {
711 uint32_t val;
712
713 R_DDRSS->DDR_MEMC_DENALI_CTL_327_b.INT_MASK_MASTER = 0;
714
715 val = R_DDRSS->DDR_MEMC_DENALI_CTL_167_b.PCPCS_PD_EN;
716 if (val == 1)
717 {
718 R_DDRSS->DDR_MEMC_DENALI_CTL_158_b.LPI_WAKEUP_EN = 0x1E;
719 }
720 else
721 {
722 R_DDRSS->DDR_MEMC_DENALI_CTL_158_b.LPI_WAKEUP_EN = 0x1F;
723 }
724 }
725
726 #endif
727 #endif
728
