1 /* 2 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef PLAT_ARM_H 7 #define PLAT_ARM_H 8 9 #include <stdbool.h> 10 #include <stdint.h> 11 12 #include <drivers/arm/tzc_common.h> 13 #include <lib/bakery_lock.h> 14 #include <lib/cassert.h> 15 #include <lib/el3_runtime/cpu_data.h> 16 #include <lib/spinlock.h> 17 #include <lib/utils_def.h> 18 #include <lib/xlat_tables/xlat_tables_compat.h> 19 20 /******************************************************************************* 21 * Forward declarations 22 ******************************************************************************/ 23 struct meminfo; 24 struct image_info; 25 struct bl_params; 26 27 typedef struct arm_tzc_regions_info { 28 unsigned long long base; 29 unsigned long long end; 30 unsigned int sec_attr; 31 unsigned int nsaid_permissions; 32 } arm_tzc_regions_info_t; 33 34 /******************************************************************************* 35 * Default mapping definition of the TrustZone Controller for ARM standard 36 * platforms. 37 * Configure: 38 * - Region 0 with no access; 39 * - Region 1 with secure access only; 40 * - the remaining DRAM regions access from the given Non-Secure masters. 41 ******************************************************************************/ 42 43 #if ENABLE_RME 44 #define ARM_TZC_RME_REGIONS_DEF \ 45 {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\ 46 {ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \ 47 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 48 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 49 /* Realm and Shared area share the same PAS */ \ 50 {ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 51 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 52 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 53 PLAT_ARM_TZC_NS_DEV_ACCESS} 54 #endif 55 56 #if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) 57 #define ARM_TZC_REGIONS_DEF \ 58 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ 59 TZC_REGION_S_RDWR, 0}, \ 60 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 61 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 62 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 63 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 64 {PLAT_SP_IMAGE_NS_BUF_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE + \ 65 PLAT_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \ 66 PLAT_ARM_TZC_NS_DEV_ACCESS} 67 68 #elif ENABLE_RME 69 #if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 70 MEASURED_BOOT 71 #define ARM_TZC_REGIONS_DEF \ 72 ARM_TZC_RME_REGIONS_DEF, \ 73 {ARM_EVENT_LOG_DRAM1_BASE, ARM_EVENT_LOG_DRAM1_END, \ 74 TZC_REGION_S_RDWR, 0} 75 #else 76 #define ARM_TZC_REGIONS_DEF \ 77 ARM_TZC_RME_REGIONS_DEF 78 #endif 79 80 #else 81 #define ARM_TZC_REGIONS_DEF \ 82 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ 83 TZC_REGION_S_RDWR, 0}, \ 84 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 85 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 86 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 87 PLAT_ARM_TZC_NS_DEV_ACCESS} 88 #endif 89 90 #define ARM_CASSERT_MMAP \ 91 CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \ 92 assert_plat_arm_mmap_mismatch); \ 93 CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \ 94 <= MAX_MMAP_REGIONS, \ 95 assert_max_mmap_regions); 96 97 void arm_setup_romlib(void); 98 99 #if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) 100 /* 101 * Use this macro to instantiate lock before it is used in below 102 * arm_lock_xxx() macros 103 */ 104 #define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock) 105 #define ARM_LOCK_GET_INSTANCE (&arm_lock) 106 107 #if !HW_ASSISTED_COHERENCY 108 #define ARM_SCMI_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_scmi_lock) 109 #else 110 #define ARM_SCMI_INSTANTIATE_LOCK spinlock_t arm_scmi_lock 111 #endif 112 #define ARM_SCMI_LOCK_GET_INSTANCE (&arm_scmi_lock) 113 114 /* 115 * These are wrapper macros to the Coherent Memory Bakery Lock API. 116 */ 117 #define arm_lock_init() bakery_lock_init(&arm_lock) 118 #define arm_lock_get() bakery_lock_get(&arm_lock) 119 #define arm_lock_release() bakery_lock_release(&arm_lock) 120 121 #else 122 123 /* 124 * Empty macros for all other BL stages other than BL31 and BL32 125 */ 126 #define ARM_INSTANTIATE_LOCK static int arm_lock __unused 127 #define ARM_LOCK_GET_INSTANCE 0 128 #define arm_lock_init() 129 #define arm_lock_get() 130 #define arm_lock_release() 131 132 #endif /* defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) */ 133 134 #if ARM_RECOM_STATE_ID_ENC 135 /* 136 * Macros used to parse state information from State-ID if it is using the 137 * recommended encoding for State-ID. 138 */ 139 #define ARM_LOCAL_PSTATE_WIDTH 4 140 #define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) 141 142 #if PSCI_OS_INIT_MODE 143 #define ARM_LAST_AT_PLVL_MASK (ARM_LOCAL_PSTATE_MASK << \ 144 (ARM_LOCAL_PSTATE_WIDTH * \ 145 (PLAT_MAX_PWR_LVL + 1))) 146 #endif /* __PSCI_OS_INIT_MODE__ */ 147 148 /* Macros to construct the composite power state */ 149 150 /* Make composite power state parameter till power level 0 */ 151 #if PSCI_EXTENDED_STATE_ID 152 153 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 154 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) 155 #else 156 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 157 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 158 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ 159 ((type) << PSTATE_TYPE_SHIFT)) 160 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 161 162 /* Make composite power state parameter till power level 1 */ 163 #define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ 164 (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \ 165 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) 166 167 /* Make composite power state parameter till power level 2 */ 168 #define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ 169 (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \ 170 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) 171 172 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 173 174 /* ARM State switch error codes */ 175 #define STATE_SW_E_PARAM (-2) 176 #define STATE_SW_E_DENIED (-3) 177 178 /* plat_get_rotpk_info() flags */ 179 #define ARM_ROTPK_REGS_ID 1 180 #define ARM_ROTPK_DEVEL_RSA_ID 2 181 #define ARM_ROTPK_DEVEL_ECDSA_ID 3 182 #define ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID 4 183 #define ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID 5 184 185 #define ARM_USE_DEVEL_ROTPK \ 186 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) || \ 187 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_ECDSA_ID) || \ 188 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID) || \ 189 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID) 190 191 /* IO storage utility functions */ 192 int arm_io_setup(void); 193 194 /* Set image specification in IO block policy */ 195 int arm_set_image_source(unsigned int image_id, const char *part_name, 196 uintptr_t *dev_handle, uintptr_t *image_spec); 197 void arm_set_fip_addr(uint32_t active_fw_bank_idx); 198 199 /* Security utility functions */ 200 void arm_tzc400_setup(uintptr_t tzc_base, 201 const arm_tzc_regions_info_t *tzc_regions); 202 struct tzc_dmc500_driver_data; 203 void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data, 204 const arm_tzc_regions_info_t *tzc_regions); 205 206 /* Console utility functions */ 207 void arm_console_boot_init(void); 208 void arm_console_boot_end(void); 209 void arm_console_runtime_init(void); 210 void arm_console_runtime_end(void); 211 212 /* Systimer utility function */ 213 void arm_configure_sys_timer(void); 214 215 /* PM utility functions */ 216 int arm_validate_power_state(unsigned int power_state, 217 psci_power_state_t *req_state); 218 int arm_validate_psci_entrypoint(uintptr_t entrypoint); 219 int arm_validate_ns_entrypoint(uintptr_t entrypoint); 220 void arm_system_pwr_domain_save(void); 221 void arm_system_pwr_domain_resume(void); 222 int arm_psci_read_mem_protect(int *enabled); 223 int arm_nor_psci_write_mem_protect(int val); 224 void arm_nor_psci_do_static_mem_protect(void); 225 void arm_nor_psci_do_dyn_mem_protect(void); 226 int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length); 227 228 /* Topology utility function */ 229 int arm_check_mpidr(u_register_t mpidr); 230 231 /* BL1 utility functions */ 232 void arm_bl1_early_platform_setup(void); 233 void arm_bl1_platform_setup(void); 234 void arm_bl1_plat_arch_setup(void); 235 236 /* BL2 utility functions */ 237 void arm_bl2_early_platform_setup(uintptr_t fw_config, struct meminfo *mem_layout); 238 void arm_bl2_platform_setup(void); 239 void arm_bl2_plat_arch_setup(void); 240 uint32_t arm_get_spsr_for_bl32_entry(void); 241 uint32_t arm_get_spsr_for_bl33_entry(void); 242 int arm_bl2_plat_handle_post_image_load(unsigned int image_id); 243 int arm_bl2_handle_post_image_load(unsigned int image_id); 244 struct bl_params *arm_get_next_bl_params(void); 245 246 /* BL2 at EL3 functions */ 247 void arm_bl2_el3_early_platform_setup(void); 248 void arm_bl2_el3_plat_arch_setup(void); 249 250 /* BL2U utility functions */ 251 void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, 252 void *plat_info); 253 void arm_bl2u_platform_setup(void); 254 void arm_bl2u_plat_arch_setup(void); 255 256 /* BL31 utility functions */ 257 void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 258 uintptr_t hw_config, void *plat_params_from_bl2); 259 void arm_bl31_platform_setup(void); 260 void arm_bl31_plat_runtime_setup(void); 261 void arm_bl31_plat_arch_setup(void); 262 263 /* TSP utility functions */ 264 void arm_tsp_early_platform_setup(void); 265 266 /* SP_MIN utility functions */ 267 void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, 268 uintptr_t hw_config, void *plat_params_from_bl2); 269 void arm_sp_min_plat_runtime_setup(void); 270 void arm_sp_min_plat_arch_setup(void); 271 272 /* FIP TOC validity check */ 273 bool arm_io_is_toc_valid(void); 274 275 /* Utility functions for Dynamic Config */ 276 void arm_bl2_dyn_cfg_init(void); 277 void arm_bl1_set_mbedtls_heap(void); 278 int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size); 279 280 #if MEASURED_BOOT 281 int arm_set_tos_fw_info(uintptr_t log_addr, size_t log_size); 282 int arm_set_nt_fw_info( 283 /* 284 * Currently OP-TEE does not support reading DTBs from Secure memory 285 * and this option should be removed when feature is supported. 286 */ 287 #ifdef SPD_opteed 288 uintptr_t log_addr, 289 #endif 290 size_t log_size, uintptr_t *ns_log_addr); 291 int arm_set_tb_fw_info(uintptr_t log_addr, size_t log_size, 292 size_t log_max_size); 293 int arm_get_tb_fw_info(uint64_t *log_addr, size_t *log_size, 294 size_t *log_max_size); 295 #endif /* MEASURED_BOOT */ 296 297 /* 298 * Free the memory storing initialization code only used during an images boot 299 * time so it can be reclaimed for runtime data 300 */ 301 void arm_free_init_memory(void); 302 303 /* 304 * Make the higher level translation tables read-only 305 */ 306 void arm_xlat_make_tables_readonly(void); 307 308 /* 309 * Mandatory functions required in ARM standard platforms 310 */ 311 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr); 312 void plat_arm_gic_driver_init(void); 313 void plat_arm_gic_init(void); 314 void plat_arm_gic_cpuif_enable(void); 315 void plat_arm_gic_cpuif_disable(void); 316 void plat_arm_gic_redistif_on(void); 317 void plat_arm_gic_redistif_off(void); 318 void plat_arm_gic_pcpu_init(void); 319 void plat_arm_gic_save(void); 320 void plat_arm_gic_resume(void); 321 void plat_arm_security_setup(void); 322 void plat_arm_pwrc_setup(void); 323 void plat_arm_interconnect_init(void); 324 void plat_arm_interconnect_enter_coherency(void); 325 void plat_arm_interconnect_exit_coherency(void); 326 void plat_arm_program_trusted_mailbox(uintptr_t address); 327 bool plat_arm_bl1_fwu_needed(void); 328 __dead2 void plat_arm_error_handler(int err); 329 __dead2 void plat_arm_system_reset(void); 330 331 /* 332 * Optional functions in ARM standard platforms 333 */ 334 void plat_arm_override_gicr_frames(const uintptr_t *plat_gicr_frames); 335 int arm_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, 336 unsigned int *flags); 337 int arm_get_rotpk_info_regs(void **key_ptr, unsigned int *key_len, 338 unsigned int *flags); 339 int arm_get_rotpk_info_cc(void **key_ptr, unsigned int *key_len, 340 unsigned int *flags); 341 int arm_get_rotpk_info_dev(void **key_ptr, unsigned int *key_len, 342 unsigned int *flags); 343 344 #if ARM_PLAT_MT 345 unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr); 346 #endif 347 348 /* 349 * This function is called after loading SCP_BL2 image and it is used to perform 350 * any platform-specific actions required to handle the SCP firmware. 351 */ 352 int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info); 353 354 /* 355 * Optional functions required in ARM standard platforms 356 */ 357 void plat_arm_io_setup(void); 358 int plat_arm_get_alt_image_source( 359 unsigned int image_id, 360 uintptr_t *dev_handle, 361 uintptr_t *image_spec); 362 unsigned int plat_arm_calc_core_pos(u_register_t mpidr); 363 const mmap_region_t *plat_arm_get_mmap(void); 364 365 /* Allow platform to override psci_pm_ops during runtime */ 366 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops); 367 368 /* Execution state switch in ARM platforms */ 369 int arm_execution_state_switch(unsigned int smc_fid, 370 uint32_t pc_hi, 371 uint32_t pc_lo, 372 uint32_t cookie_hi, 373 uint32_t cookie_lo, 374 void *handle); 375 376 /* Optional functions for SP_MIN */ 377 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 378 u_register_t arg2, u_register_t arg3); 379 380 /* global variables */ 381 extern plat_psci_ops_t plat_arm_psci_pm_ops; 382 extern const mmap_region_t plat_arm_mmap[]; 383 extern const unsigned int arm_pm_idle_states[]; 384 385 /* secure watchdog */ 386 void plat_arm_secure_wdt_start(void); 387 void plat_arm_secure_wdt_stop(void); 388 void plat_arm_secure_wdt_refresh(void); 389 390 /* Get SOC-ID of ARM platform */ 391 uint32_t plat_arm_get_soc_id(void); 392 393 #endif /* PLAT_ARM_H */ 394
