1 /*
2 * Copyright (c) 2017-2022 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /*
20 * CMSIS-Core(M) MPU API for Armv8-M and Armv8.1-M MPU
21 */
22
23 #ifndef ARM_MPU_ARMV8_H
24 #define ARM_MPU_ARMV8_H
25
26 #if defined ( __ICCARM__ )
27 #pragma system_include /* treat file as system include file for MISRA check */
28 #elif defined (__clang__)
29 #pragma clang system_header /* treat file as system include file */
30 #endif
31
32 /** \brief Attribute for device memory (outer only) */
33 #define ARM_MPU_ATTR_DEVICE ( 0U )
34
35 /** \brief Attribute for non-cacheable, normal memory */
36 #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
37
38 /** \brief Attribute for Normal memory, Outer and Inner cacheability.
39 * \param NT Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data.
40 * \param WB Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy.
41 * \param RA Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss.
42 * \param WA Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss.
43 */
44 #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
45 ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
46
47 /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
48 #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
49
50 /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
51 #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
52
53 /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
54 #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
55
56 /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
57 #define ARM_MPU_ATTR_DEVICE_GRE (3U)
58
59 /** \brief Normal memory outer-cacheable and inner-cacheable attributes
60 * WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate
61 */
62 #define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE (0b0100)
63 #define MPU_ATTR_NORMAL_OUTER_WT_TR_RA (0b0010)
64 #define MPU_ATTR_NORMAL_OUTER_WT_TR_WA (0b0001)
65 #define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA (0b0011)
66 #define MPU_ATTR_NORMAL_OUTER_WT_RA (0b1010)
67 #define MPU_ATTR_NORMAL_OUTER_WT_WA (0b1001)
68 #define MPU_ATTR_NORMAL_OUTER_WT_RA_WA (0b1011)
69 #define MPU_ATTR_NORMAL_OUTER_WB_TR_RA (0b0101)
70 #define MPU_ATTR_NORMAL_OUTER_WB_TR_WA (0b0110)
71 #define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA (0b0111)
72 #define MPU_ATTR_NORMAL_OUTER_WB_RA (0b1101)
73 #define MPU_ATTR_NORMAL_OUTER_WB_WA (0b1110)
74 #define MPU_ATTR_NORMAL_OUTER_WB_RA_WA (0b1111)
75 #define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE (0b0100)
76 #define MPU_ATTR_NORMAL_INNER_WT_TR_RA (0b0010)
77 #define MPU_ATTR_NORMAL_INNER_WT_TR_WA (0b0001)
78 #define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA (0b0011)
79 #define MPU_ATTR_NORMAL_INNER_WT_RA (0b1010)
80 #define MPU_ATTR_NORMAL_INNER_WT_WA (0b1001)
81 #define MPU_ATTR_NORMAL_INNER_WT_RA_WA (0b1011)
82 #define MPU_ATTR_NORMAL_INNER_WB_TR_RA (0b0101)
83 #define MPU_ATTR_NORMAL_INNER_WB_TR_WA (0b0110)
84 #define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA (0b0111)
85 #define MPU_ATTR_NORMAL_INNER_WB_RA (0b1101)
86 #define MPU_ATTR_NORMAL_INNER_WB_WA (0b1110)
87 #define MPU_ATTR_NORMAL_INNER_WB_RA_WA (0b1111)
88
89 /** \brief Memory Attribute
90 * \param O Outer memory attributes
91 * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
92 */
93 #define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
94
95 /* \brief Specifies MAIR_ATTR number */
96 #define MAIR_ATTR(x) ((x > 7 || x < 0) ? 0 : x)
97
98 /**
99 * Shareability
100 */
101 /** \brief Normal memory, non-shareable */
102 #define ARM_MPU_SH_NON (0U)
103
104 /** \brief Normal memory, outer shareable */
105 #define ARM_MPU_SH_OUTER (2U)
106
107 /** \brief Normal memory, inner shareable */
108 #define ARM_MPU_SH_INNER (3U)
109
110 /**
111 * Access permissions
112 * AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only
113 */
114 /** \brief Normal memory, read/write */
115 #define ARM_MPU_AP_RW (0U)
116
117 /** \brief Normal memory, read-only */
118 #define ARM_MPU_AP_RO (1U)
119
120 /** \brief Normal memory, any privilege level */
121 #define ARM_MPU_AP_NP (1U)
122
123 /** \brief Normal memory, privileged access only */
124 #define ARM_MPU_AP_PO (0U)
125
126 /*
127 * Execute-never
128 * XN = Execute-never, EX = Executable
129 */
130 /** \brief Normal memory, Execution only permitted if read permitted */
131 #define ARM_MPU_XN (1U)
132
133 /** \brief Normal memory, Execution only permitted if read permitted */
134 #define ARM_MPU_EX (0U)
135
136 /** \brief Memory access permissions
137 * \param RO Read-Only: Set to 1 for read-only memory. Set to 0 for a read/write memory.
138 * \param NP Non-Privileged: Set to 1 for non-privileged memory. Set to 0 for privileged memory.
139 */
140 #define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
141
142 /** \brief Region Base Address Register value
143 * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
144 * \param SH Defines the Shareability domain for this memory region.
145 * \param RO Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region.
146 * \param NP Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region.
147 * \param XN eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region.
148 */
149 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
150 (((BASE) & MPU_RBAR_BASE_Msk) | \
151 (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
152 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
153 (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
154
155 /** \brief Region Limit Address Register value
156 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
157 * \param IDX The attribute index to be associated with this memory region.
158 */
159 #define ARM_MPU_RLAR(LIMIT, IDX) \
160 (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
161 (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
162 (MPU_RLAR_EN_Msk))
163
164 #if defined(MPU_RLAR_PXN_Pos)
165
166 /** \brief Region Limit Address Register with PXN value
167 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
168 * \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
169 * \param IDX The attribute index to be associated with this memory region.
170 */
171 #define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
172 (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
173 (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
174 (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
175 (MPU_RLAR_EN_Msk))
176
177 #endif
178
179 /**
180 * Struct for a single MPU Region
181 */
182 typedef struct {
183 uint32_t RBAR; /*!< Region Base Address Register value */
184 uint32_t RLAR; /*!< Region Limit Address Register value */
185 } ARM_MPU_Region_t;
186
187 /**
188 \brief Read MPU Type Register
189 \return Number of MPU regions
190 */
ARM_MPU_TYPE()191 __STATIC_INLINE uint32_t ARM_MPU_TYPE()
192 {
193 return ((MPU->TYPE) >> 8);
194 }
195
196 /** Enable the MPU.
197 * \param MPU_Control Default access permissions for unconfigured regions.
198 */
ARM_MPU_Enable(uint32_t MPU_Control)199 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
200 {
201 __DMB();
202 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
203 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
204 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
205 #endif
206 __DSB();
207 __ISB();
208 }
209
210 /** Disable the MPU.
211 */
ARM_MPU_Disable(void)212 __STATIC_INLINE void ARM_MPU_Disable(void)
213 {
214 __DMB();
215 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
216 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
217 #endif
218 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
219 __DSB();
220 __ISB();
221 }
222
223 #ifdef MPU_NS
224 /** Enable the Non-secure MPU.
225 * \param MPU_Control Default access permissions for unconfigured regions.
226 */
ARM_MPU_Enable_NS(uint32_t MPU_Control)227 __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
228 {
229 __DMB();
230 MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
231 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
232 SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
233 #endif
234 __DSB();
235 __ISB();
236 }
237
238 /** Disable the Non-secure MPU.
239 */
ARM_MPU_Disable_NS(void)240 __STATIC_INLINE void ARM_MPU_Disable_NS(void)
241 {
242 __DMB();
243 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
244 SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
245 #endif
246 MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
247 __DSB();
248 __ISB();
249 }
250 #endif
251
252 /** Set the memory attribute encoding to the given MPU.
253 * \param mpu Pointer to the MPU to be configured.
254 * \param idx The attribute index to be set [0-7]
255 * \param attr The attribute value to be set.
256 */
ARM_MPU_SetMemAttrEx(MPU_Type * mpu,uint8_t idx,uint8_t attr)257 __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
258 {
259 const uint8_t reg = idx / 4U;
260 const uint32_t pos = ((idx % 4U) * 8U);
261 const uint32_t mask = 0xFFU << pos;
262
263 if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
264 return; // invalid index
265 }
266
267 mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
268 }
269
270 /** Set the memory attribute encoding.
271 * \param idx The attribute index to be set [0-7]
272 * \param attr The attribute value to be set.
273 */
ARM_MPU_SetMemAttr(uint8_t idx,uint8_t attr)274 __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
275 {
276 ARM_MPU_SetMemAttrEx(MPU, idx, attr);
277 }
278
279 #ifdef MPU_NS
280 /** Set the memory attribute encoding to the Non-secure MPU.
281 * \param idx The attribute index to be set [0-7]
282 * \param attr The attribute value to be set.
283 */
ARM_MPU_SetMemAttr_NS(uint8_t idx,uint8_t attr)284 __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
285 {
286 ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
287 }
288 #endif
289
290 /** Clear and disable the given MPU region of the given MPU.
291 * \param mpu Pointer to MPU to be used.
292 * \param rnr Region number to be cleared.
293 */
ARM_MPU_ClrRegionEx(MPU_Type * mpu,uint32_t rnr)294 __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
295 {
296 mpu->RNR = rnr;
297 mpu->RLAR = 0U;
298 }
299
300 /** Clear and disable the given MPU region.
301 * \param rnr Region number to be cleared.
302 */
ARM_MPU_ClrRegion(uint32_t rnr)303 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
304 {
305 ARM_MPU_ClrRegionEx(MPU, rnr);
306 }
307
308 #ifdef MPU_NS
309 /** Clear and disable the given Non-secure MPU region.
310 * \param rnr Region number to be cleared.
311 */
ARM_MPU_ClrRegion_NS(uint32_t rnr)312 __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
313 {
314 ARM_MPU_ClrRegionEx(MPU_NS, rnr);
315 }
316 #endif
317
318 /** Configure the given MPU region of the given MPU.
319 * \param mpu Pointer to MPU to be used.
320 * \param rnr Region number to be configured.
321 * \param rbar Value for RBAR register.
322 * \param rlar Value for RLAR register.
323 */
ARM_MPU_SetRegionEx(MPU_Type * mpu,uint32_t rnr,uint32_t rbar,uint32_t rlar)324 __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
325 {
326 mpu->RNR = rnr;
327 mpu->RBAR = rbar;
328 mpu->RLAR = rlar;
329 }
330
331 /** Configure the given MPU region.
332 * \param rnr Region number to be configured.
333 * \param rbar Value for RBAR register.
334 * \param rlar Value for RLAR register.
335 */
ARM_MPU_SetRegion(uint32_t rnr,uint32_t rbar,uint32_t rlar)336 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
337 {
338 ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
339 }
340
341 #ifdef MPU_NS
342 /** Configure the given Non-secure MPU region.
343 * \param rnr Region number to be configured.
344 * \param rbar Value for RBAR register.
345 * \param rlar Value for RLAR register.
346 */
ARM_MPU_SetRegion_NS(uint32_t rnr,uint32_t rbar,uint32_t rlar)347 __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
348 {
349 ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
350 }
351 #endif
352
353 /** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
354 * \param dst Destination data is copied to.
355 * \param src Source data is copied from.
356 * \param len Amount of data words to be copied.
357 */
ARM_MPU_OrderedMemcpy(volatile uint32_t * dst,const uint32_t * __RESTRICT src,uint32_t len)358 __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
359 {
360 uint32_t i;
361 for (i = 0U; i < len; ++i)
362 {
363 dst[i] = src[i];
364 }
365 }
366
367 /** Load the given number of MPU regions from a table to the given MPU.
368 * \param mpu Pointer to the MPU registers to be used.
369 * \param rnr First region number to be configured.
370 * \param table Pointer to the MPU configuration table.
371 * \param cnt Amount of regions to be configured.
372 */
ARM_MPU_LoadEx(MPU_Type * mpu,uint32_t rnr,ARM_MPU_Region_t const * table,uint32_t cnt)373 __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
374 {
375 const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
376 if (cnt == 1U) {
377 mpu->RNR = rnr;
378 ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
379 } else {
380 uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
381 uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
382
383 mpu->RNR = rnrBase;
384 while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
385 uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
386 ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
387 table += c;
388 cnt -= c;
389 rnrOffset = 0U;
390 rnrBase += MPU_TYPE_RALIASES;
391 mpu->RNR = rnrBase;
392 }
393
394 ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
395 }
396 }
397
398 /** Load the given number of MPU regions from a table.
399 * \param rnr First region number to be configured.
400 * \param table Pointer to the MPU configuration table.
401 * \param cnt Amount of regions to be configured.
402 */
ARM_MPU_Load(uint32_t rnr,ARM_MPU_Region_t const * table,uint32_t cnt)403 __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
404 {
405 ARM_MPU_LoadEx(MPU, rnr, table, cnt);
406 }
407
408 #ifdef MPU_NS
409 /** Load the given number of MPU regions from a table to the Non-secure MPU.
410 * \param rnr First region number to be configured.
411 * \param table Pointer to the MPU configuration table.
412 * \param cnt Amount of regions to be configured.
413 */
ARM_MPU_Load_NS(uint32_t rnr,ARM_MPU_Region_t const * table,uint32_t cnt)414 __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
415 {
416 ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
417 }
418 #endif
419
420 #endif
421
422
